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FPGA_LVDS_PROTOCOL_ANALYSER/lvds_monitor.jditmp
2026-06-10 09:32:26 +02:00

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<sld_project_info>
<project>
<hash md5_digest_80b="be30335bc4df29bcee3f"/>
</project>
<file_info>
<file device="EP4CE6E22C8" path="lvds_monitor.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>