Arrive/FPGA_LVDS_PROTOCOL_ANALYSER
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Initial commit: LVDS Protocol Analyser v1.0.0

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David Rice
2026-06-10 09:32:26 +02:00
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{
"permissions": {
"allow": [
"Bash(quartus_sh -t lvds_monitor.tcl)"
]
}
}

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* text=auto
*.v text eol=lf
*.sdc text eol=lf
*.tcl text eol=lf

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# Quartus generated output directories
db/
incremental_db/
output_files/
greybox_tmp/
hc_output/
logging/
# Quartus report and log files
*.rpt
*.smsg
*.summary
*.pin
# Quartus compilation phase outputs
*.fit.*
*.map.*
*.sta.*
*.asm.*
# Compiled database files
*.qdb
*.qarxml
# Timing analysis / back-annotation
*.sdo
*.vho
*.vwo
# Programmer files (keep .sof)
*.pof
*.rbf
*.rpd
*.hexout
*.jam
*.jbc
*.ekp
*.jic
# Simulation
*.vcd
*.wlf
# Quartus workspace
*.qws
# Project files regenerated by TCL script
*.qpf
*.qsf

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# Introduction
FPGA_LVDS_PROTOCOL_ANALYSER - LVDS ANALYSER BASED ON DS90CF386 AND ALTERA CYCLONE-IV FPGA

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--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
--VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC VERSION_END
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources =
SUBDESIGN add_sub_7pc
(
cout : output;
dataa[0..0] : input;
datab[0..0] : input;
result[0..0] : output;
)
VARIABLE
carry_eqn[0..0] : WIRE;
cin_wire : WIRE;
datab_node[0..0] : WIRE;
sum_eqn[0..0] : WIRE;
BEGIN
carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
cin_wire = B"1";
cout = carry_eqn[0..0];
datab_node[] = (! datab[]);
result[] = sum_eqn[];
sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
END;
--VALID FILE

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--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
--VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC VERSION_END
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
--synthesis_resources =
SUBDESIGN add_sub_8pc
(
cout : output;
dataa[1..0] : input;
datab[1..0] : input;
result[1..0] : output;
)
VARIABLE
carry_eqn[1..0] : WIRE;
cin_wire : WIRE;
datab_node[1..0] : WIRE;
sum_eqn[1..0] : WIRE;
BEGIN
carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
cin_wire = B"1";
cout = carry_eqn[1..1];
datab_node[] = (! datab[]);
result[] = sum_eqn[];
sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
END;
--VALID FILE

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--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION sign_div_unsign_qlh (denominator[3..0], numerator[15..0])
RETURNS ( quotient[15..0], remainder[3..0]);
--synthesis_resources = lut 81
SUBDESIGN lpm_divide_2jm
(
denom[3..0] : input;
numer[15..0] : input;
quotient[15..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : sign_div_unsign_qlh;
numer_tmp[15..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

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--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION sign_div_unsign_qlh (denominator[3..0], numerator[15..0])
RETURNS ( quotient[15..0], remainder[3..0]);
--synthesis_resources =
SUBDESIGN lpm_divide_5bm
(
denom[3..0] : input;
numer[15..0] : input;
quotient[15..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : sign_div_unsign_qlh;
numer_tmp[15..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

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--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=7 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION sign_div_unsign_tlh (denominator[6..0], numerator[15..0])
RETURNS ( quotient[15..0], remainder[6..0]);
--synthesis_resources = lut 111
SUBDESIGN lpm_divide_5jm
(
denom[6..0] : input;
numer[15..0] : input;
quotient[15..0] : output;
remain[6..0] : output;
)
VARIABLE
divider : sign_div_unsign_tlh;
numer_tmp[15..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

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--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=10 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-- Copyright (C) 2025 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Altera and sold by Altera or its authorized distributors. Please
-- refer to the Altera Software License Subscription Agreements
-- on the Quartus Prime software download page.
FUNCTION sign_div_unsign_7nh (denominator[9..0], numerator[15..0])
RETURNS ( quotient[15..0], remainder[9..0]);
--synthesis_resources = lut 132
SUBDESIGN lpm_divide_fkm
(
denom[9..0] : input;
numer[15..0] : input;
quotient[15..0] : output;
remain[9..0] : output;
)
VARIABLE
divider : sign_div_unsign_7nh;
numer_tmp[15..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1781075228905 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1781075228905 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 10 09:07:08 2026 " "Processing started: Wed Jun 10 09:07:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1781075228905 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1781075228905 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1781075228905 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1781075229287 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1781075229298 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4744 " "Peak virtual memory: 4744 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075229383 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:09 2026 " "Processing ended: Wed Jun 10 09:07:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075229383 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075229383 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075229383 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1781075229383 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="lvds_monitor">
</PROJECT>
</LOG_ROOT>

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v1
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,7;0;7;0;0;7;7;0;7;7;0;0;0;0;6;0;0;6;0;0;0;0;0;0;0;0;0;7;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;7;0;7;7;0;0;7;0;0;7;7;7;7;1;7;7;1;7;7;7;7;7;7;7;7;7;0;7;7,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,vsync,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,hsync,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,uart_tx_pin,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,clk_50mhz,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,rst_n_pin,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,rx_clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,de,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

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Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Version_Index = 604268800
Creation_Time = Wed Jun 10 08:48:23 2026

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|top
clk_50mhz => clk_uart.IN1
rx_clk => rx_clk.IN1
de => de.IN1
vsync => ~NO_FANOUT~
hsync => ~NO_FANOUT~
rst_n_pin => rst_sync_uart[0].ACLR
rst_n_pin => rst_sync_uart[1].ACLR
rst_n_pin => rst_sync_uart[2].ACLR
rst_n_pin => rst_sync_pix[0].ACLR
rst_n_pin => rst_sync_pix[1].ACLR
rst_n_pin => rst_sync_pix[2].ACLR
uart_tx_pin << uart_tx:u_uart.tx
|top|de_monitor:u_mon
pix_clk => anomaly_o~reg0.CLK
pix_clk => width_o[0]~reg0.CLK
pix_clk => width_o[1]~reg0.CLK
pix_clk => width_o[2]~reg0.CLK
pix_clk => width_o[3]~reg0.CLK
pix_clk => width_o[4]~reg0.CLK
pix_clk => width_o[5]~reg0.CLK
pix_clk => width_o[6]~reg0.CLK
pix_clk => width_o[7]~reg0.CLK
pix_clk => width_o[8]~reg0.CLK
pix_clk => width_o[9]~reg0.CLK
pix_clk => width_o[10]~reg0.CLK
pix_clk => width_o[11]~reg0.CLK
pix_clk => width_o[12]~reg0.CLK
pix_clk => width_o[13]~reg0.CLK
pix_clk => width_o[14]~reg0.CLK
pix_clk => width_o[15]~reg0.CLK
pix_clk => lines_o[0]~reg0.CLK
pix_clk => lines_o[1]~reg0.CLK
pix_clk => lines_o[2]~reg0.CLK
pix_clk => lines_o[3]~reg0.CLK
pix_clk => lines_o[4]~reg0.CLK
pix_clk => lines_o[5]~reg0.CLK
pix_clk => lines_o[6]~reg0.CLK
pix_clk => lines_o[7]~reg0.CLK
pix_clk => lines_o[8]~reg0.CLK
pix_clk => lines_o[9]~reg0.CLK
pix_clk => lines_o[10]~reg0.CLK
pix_clk => lines_o[11]~reg0.CLK
pix_clk => lines_o[12]~reg0.CLK
pix_clk => lines_o[13]~reg0.CLK
pix_clk => lines_o[14]~reg0.CLK
pix_clk => lines_o[15]~reg0.CLK
pix_clk => frame_done~reg0.CLK
pix_clk => frame_active.CLK
pix_clk => gap_count[0].CLK
pix_clk => gap_count[1].CLK
pix_clk => gap_count[2].CLK
pix_clk => gap_count[3].CLK
pix_clk => gap_count[4].CLK
pix_clk => gap_count[5].CLK
pix_clk => gap_count[6].CLK
pix_clk => gap_count[7].CLK
pix_clk => gap_count[8].CLK
pix_clk => gap_count[9].CLK
pix_clk => gap_count[10].CLK
pix_clk => gap_count[11].CLK
pix_clk => gap_count[12].CLK
pix_clk => gap_count[13].CLK
pix_clk => gap_count[14].CLK
pix_clk => gap_count[15].CLK
pix_clk => line_count[0].CLK
pix_clk => line_count[1].CLK
pix_clk => line_count[2].CLK
pix_clk => line_count[3].CLK
pix_clk => line_count[4].CLK
pix_clk => line_count[5].CLK
pix_clk => line_count[6].CLK
pix_clk => line_count[7].CLK
pix_clk => line_count[8].CLK
pix_clk => line_count[9].CLK
pix_clk => line_count[10].CLK
pix_clk => line_count[11].CLK
pix_clk => line_count[12].CLK
pix_clk => line_count[13].CLK
pix_clk => line_count[14].CLK
pix_clk => line_count[15].CLK
pix_clk => any_bad_width.CLK
pix_clk => bad_width[0].CLK
pix_clk => bad_width[1].CLK
pix_clk => bad_width[2].CLK
pix_clk => bad_width[3].CLK
pix_clk => bad_width[4].CLK
pix_clk => bad_width[5].CLK
pix_clk => bad_width[6].CLK
pix_clk => bad_width[7].CLK
pix_clk => bad_width[8].CLK
pix_clk => bad_width[9].CLK
pix_clk => bad_width[10].CLK
pix_clk => bad_width[11].CLK
pix_clk => bad_width[12].CLK
pix_clk => bad_width[13].CLK
pix_clk => bad_width[14].CLK
pix_clk => bad_width[15].CLK
pix_clk => last_width[0].CLK
pix_clk => last_width[1].CLK
pix_clk => last_width[2].CLK
pix_clk => last_width[3].CLK
pix_clk => last_width[4].CLK
pix_clk => last_width[5].CLK
pix_clk => last_width[6].CLK
pix_clk => last_width[7].CLK
pix_clk => last_width[8].CLK
pix_clk => last_width[9].CLK
pix_clk => last_width[10].CLK
pix_clk => last_width[11].CLK
pix_clk => last_width[12].CLK
pix_clk => last_width[13].CLK
pix_clk => last_width[14].CLK
pix_clk => last_width[15].CLK
pix_clk => line_width[0].CLK
pix_clk => line_width[1].CLK
pix_clk => line_width[2].CLK
pix_clk => line_width[3].CLK
pix_clk => line_width[4].CLK
pix_clk => line_width[5].CLK
pix_clk => line_width[6].CLK
pix_clk => line_width[7].CLK
pix_clk => line_width[8].CLK
pix_clk => line_width[9].CLK
pix_clk => line_width[10].CLK
pix_clk => line_width[11].CLK
pix_clk => line_width[12].CLK
pix_clk => line_width[13].CLK
pix_clk => line_width[14].CLK
pix_clk => line_width[15].CLK
pix_clk => de_q.CLK
rst_n => anomaly_o~reg0.ACLR
rst_n => width_o[0]~reg0.ACLR
rst_n => width_o[1]~reg0.ACLR
rst_n => width_o[2]~reg0.ACLR
rst_n => width_o[3]~reg0.ACLR
rst_n => width_o[4]~reg0.ACLR
rst_n => width_o[5]~reg0.ACLR
rst_n => width_o[6]~reg0.ACLR
rst_n => width_o[7]~reg0.ACLR
rst_n => width_o[8]~reg0.ACLR
rst_n => width_o[9]~reg0.ACLR
rst_n => width_o[10]~reg0.ACLR
rst_n => width_o[11]~reg0.ACLR
rst_n => width_o[12]~reg0.ACLR
rst_n => width_o[13]~reg0.ACLR
rst_n => width_o[14]~reg0.ACLR
rst_n => width_o[15]~reg0.ACLR
rst_n => lines_o[0]~reg0.ACLR
rst_n => lines_o[1]~reg0.ACLR
rst_n => lines_o[2]~reg0.ACLR
rst_n => lines_o[3]~reg0.ACLR
rst_n => lines_o[4]~reg0.ACLR
rst_n => lines_o[5]~reg0.ACLR
rst_n => lines_o[6]~reg0.ACLR
rst_n => lines_o[7]~reg0.ACLR
rst_n => lines_o[8]~reg0.ACLR
rst_n => lines_o[9]~reg0.ACLR
rst_n => lines_o[10]~reg0.ACLR
rst_n => lines_o[11]~reg0.ACLR
rst_n => lines_o[12]~reg0.ACLR
rst_n => lines_o[13]~reg0.ACLR
rst_n => lines_o[14]~reg0.ACLR
rst_n => lines_o[15]~reg0.ACLR
rst_n => frame_done~reg0.ACLR
rst_n => frame_active.ACLR
rst_n => gap_count[0].ACLR
rst_n => gap_count[1].ACLR
rst_n => gap_count[2].ACLR
rst_n => gap_count[3].ACLR
rst_n => gap_count[4].ACLR
rst_n => gap_count[5].ACLR
rst_n => gap_count[6].ACLR
rst_n => gap_count[7].ACLR
rst_n => gap_count[8].ACLR
rst_n => gap_count[9].ACLR
rst_n => gap_count[10].ACLR
rst_n => gap_count[11].ACLR
rst_n => gap_count[12].ACLR
rst_n => gap_count[13].ACLR
rst_n => gap_count[14].ACLR
rst_n => gap_count[15].ACLR
rst_n => line_count[0].ACLR
rst_n => line_count[1].ACLR
rst_n => line_count[2].ACLR
rst_n => line_count[3].ACLR
rst_n => line_count[4].ACLR
rst_n => line_count[5].ACLR
rst_n => line_count[6].ACLR
rst_n => line_count[7].ACLR
rst_n => line_count[8].ACLR
rst_n => line_count[9].ACLR
rst_n => line_count[10].ACLR
rst_n => line_count[11].ACLR
rst_n => line_count[12].ACLR
rst_n => line_count[13].ACLR
rst_n => line_count[14].ACLR
rst_n => line_count[15].ACLR
rst_n => any_bad_width.ACLR
rst_n => bad_width[0].ACLR
rst_n => bad_width[1].ACLR
rst_n => bad_width[2].ACLR
rst_n => bad_width[3].ACLR
rst_n => bad_width[4].ACLR
rst_n => bad_width[5].ACLR
rst_n => bad_width[6].ACLR
rst_n => bad_width[7].ACLR
rst_n => bad_width[8].ACLR
rst_n => bad_width[9].ACLR
rst_n => bad_width[10].ACLR
rst_n => bad_width[11].ACLR
rst_n => bad_width[12].ACLR
rst_n => bad_width[13].ACLR
rst_n => bad_width[14].ACLR
rst_n => bad_width[15].ACLR
rst_n => last_width[0].ACLR
rst_n => last_width[1].ACLR
rst_n => last_width[2].ACLR
rst_n => last_width[3].ACLR
rst_n => last_width[4].ACLR
rst_n => last_width[5].ACLR
rst_n => last_width[6].ACLR
rst_n => last_width[7].ACLR
rst_n => last_width[8].ACLR
rst_n => last_width[9].ACLR
rst_n => last_width[10].ACLR
rst_n => last_width[11].ACLR
rst_n => last_width[12].ACLR
rst_n => last_width[13].ACLR
rst_n => last_width[14].ACLR
rst_n => last_width[15].ACLR
rst_n => line_width[0].ACLR
rst_n => line_width[1].ACLR
rst_n => line_width[2].ACLR
rst_n => line_width[3].ACLR
rst_n => line_width[4].ACLR
rst_n => line_width[5].ACLR
rst_n => line_width[6].ACLR
rst_n => line_width[7].ACLR
rst_n => line_width[8].ACLR
rst_n => line_width[9].ACLR
rst_n => line_width[10].ACLR
rst_n => line_width[11].ACLR
rst_n => line_width[12].ACLR
rst_n => line_width[13].ACLR
rst_n => line_width[14].ACLR
rst_n => line_width[15].ACLR
rst_n => de_q.ACLR
de => de_rise.IN1
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => de_q.DATAIN
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => frame_done.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => anomaly_o.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => any_bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => frame_active.OUTPUTSELECT
de => de_fall.IN1
frame_done <= frame_done~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[0] <= lines_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[1] <= lines_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[2] <= lines_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[3] <= lines_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[4] <= lines_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[5] <= lines_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[6] <= lines_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[7] <= lines_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[8] <= lines_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[9] <= lines_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[10] <= lines_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[11] <= lines_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[12] <= lines_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[13] <= lines_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[14] <= lines_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[15] <= lines_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[0] <= width_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[1] <= width_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[2] <= width_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[3] <= width_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[4] <= width_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[5] <= width_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[6] <= width_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[7] <= width_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[8] <= width_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[9] <= width_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[10] <= width_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[11] <= width_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[12] <= width_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[13] <= width_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[14] <= width_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[15] <= width_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
anomaly_o <= anomaly_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|top|uart_tx:u_uart
clk => busy~reg0.CLK
clk => tx~reg0.CLK
clk => shift[0].CLK
clk => shift[1].CLK
clk => shift[2].CLK
clk => shift[3].CLK
clk => shift[4].CLK
clk => shift[5].CLK
clk => shift[6].CLK
clk => shift[7].CLK
clk => tick[0].CLK
clk => tick[1].CLK
clk => tick[2].CLK
clk => tick[3].CLK
clk => tick[4].CLK
clk => tick[5].CLK
clk => tick[6].CLK
clk => tick[7].CLK
clk => tick[8].CLK
clk => state~12.DATAIN
rst_n => busy~reg0.ACLR
rst_n => tx~reg0.PRESET
rst_n => shift[0].ACLR
rst_n => shift[1].ACLR
rst_n => shift[2].ACLR
rst_n => shift[3].ACLR
rst_n => shift[4].ACLR
rst_n => shift[5].ACLR
rst_n => shift[6].ACLR
rst_n => shift[7].ACLR
rst_n => tick[0].ACLR
rst_n => tick[1].ACLR
rst_n => tick[2].ACLR
rst_n => tick[3].ACLR
rst_n => tick[4].ACLR
rst_n => tick[5].ACLR
rst_n => tick[6].ACLR
rst_n => tick[7].ACLR
rst_n => tick[8].ACLR
rst_n => state~14.DATAIN
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => busy.DATAB
start => tx.DATAB
data[0] => shift.DATAB
data[1] => shift.DATAB
data[2] => shift.DATAB
data[3] => shift.DATAB
data[4] => shift.DATAB
data[5] => shift.DATAB
data[6] => shift.DATAB
data[7] => shift.DATAB
tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
busy <= busy~reg0.DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >u_uart</TD>
<TD >11</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_mon</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >34</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; u_uart ; 11 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; u_mon ; 3 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1781075213461 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1781075213462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 10 09:06:53 2026 " "Processing started: Wed Jun 10 09:06:53 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1781075213462 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075213462 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor " "Command: quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075213462 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "14 14 " "Parallel compilation is enabled and will use 14 of the 14 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1781075213684 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de_monitor.v 1 1 " "Found 1 design units, including 1 entities, in source file de_monitor.v" { { "Info" "ISGN_ENTITY_NAME" "1 de_monitor " "Found entity 1: de_monitor" { } { { "de_monitor.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/de_monitor.v" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218864 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218864 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218866 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218867 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1781075218897 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "_unused top.v(33) " "Verilog HDL or VHDL warning at top.v(33): object \"_unused\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 33 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218900 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L0_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L0_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218900 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L1_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L1_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L2_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L2_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L3_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L3_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W0_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W0_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W1_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W1_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W2_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W2_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W3_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W3_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "de_monitor de_monitor:u_mon " "Elaborating entity \"de_monitor\" for hierarchy \"de_monitor:u_mon\"" { } { { "top.v" "u_mon" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart\"" { } { { "top.v" "u_uart" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 359 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075218903 ""}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "uart_tx.v(60) " "Verilog HDL Case Statement information at uart_tx.v(60): all case item expressions in this case statement are onehot" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 60 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1781075218910 "|top|uart_tx:u_uart"}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 18 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1781075219700 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1781075219700 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1781075220414 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1781075222360 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1781075222473 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075222473 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "vsync " "No output dependent on input pin \"vsync\"" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 26 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1781075222547 "|top|vsync"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "hsync " "No output dependent on input pin \"hsync\"" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 27 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1781075222547 "|top|hsync"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1781075222547 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2001 " "Implemented 2001 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1781075222547 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1781075222547 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1994 " "Implemented 1994 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1781075222547 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1781075222547 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4878 " "Peak virtual memory: 4878 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:02 2026 " "Processing ended: Wed Jun 10 09:07:02 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075222558 ""}

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v1

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DONE

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State Machine - |top|fstate
Name fstate.F_WAIT fstate.F_LOAD fstate.F_CONVERT fstate.F_IDLE
fstate.F_IDLE 0 0 0 0
fstate.F_CONVERT 0 0 1 1
fstate.F_LOAD 0 1 0 1
fstate.F_WAIT 1 0 0 1
State Machine - |top|uart_tx:u_uart|state
Name state.S_STOP state.S_D7 state.S_D6 state.S_D5 state.S_D4 state.S_D3 state.S_D2 state.S_D1 state.S_D0 state.S_START state.S_IDLE
state.S_IDLE 0 0 0 0 0 0 0 0 0 0 0
state.S_START 0 0 0 0 0 0 0 0 0 1 1
state.S_D0 0 0 0 0 0 0 0 0 1 0 1
state.S_D1 0 0 0 0 0 0 0 1 0 0 1
state.S_D2 0 0 0 0 0 0 1 0 0 0 1
state.S_D3 0 0 0 0 0 1 0 0 0 0 1
state.S_D4 0 0 0 0 1 0 0 0 0 0 1
state.S_D5 0 0 0 1 0 0 0 0 0 0 1
state.S_D6 0 0 1 0 0 0 0 0 0 0 1
state.S_D7 0 1 0 0 0 0 0 0 0 0 1
state.S_STOP 1 0 0 0 0 0 0 0 0 0 1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1781075230414 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1781075230415 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 10 09:07:10 2026 " "Processing started: Wed Jun 10 09:07:10 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1781075230415 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230415 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lvds_monitor -c lvds_monitor " "Command: quartus_sta lvds_monitor -c lvds_monitor" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230415 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1781075230517 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "14 14 " "Parallel compilation is enabled and will use 14 of the 14 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1781075230601 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1781075230633 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1781075230634 ""}
{ "Info" "ISTA_SDC_FOUND" "lvds_monitor.sdc " "Reading SDC File: 'lvds_monitor.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1781075230777 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Timing Analyzer" 0 -1 1781075230779 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230788 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1781075230789 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1781075230795 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.242 " "Worst-case setup slack is 4.242" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.242 0.000 clk_50mhz " " 4.242 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.059 0.000 rx_clk " " 7.059 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230816 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 clk_50mhz " " 0.452 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 rx_clk " " 0.452 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230821 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 8.730 " "Worst-case recovery slack is 8.730" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.730 0.000 rx_clk " " 8.730 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.869 0.000 clk_50mhz " " 15.869 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230824 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.067 " "Worst-case removal slack is 3.067" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.067 0.000 clk_50mhz " " 3.067 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.061 0.000 rx_clk " " 4.061 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230827 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 6.480 " "Worst-case minimum pulse width slack is 6.480" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.480 0.000 rx_clk " " 6.480 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.735 0.000 clk_50mhz " " 9.735 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230830 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 46 synchronizer chains. " "Report Metastability: Found 46 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 46 " "Number of Synchronizer Chains Found: 46" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.327 ns " "Worst Case Available Settling Time: 12.327 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230879 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1781075230885 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1781075230900 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1781075231132 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231208 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 5.201 " "Worst-case setup slack is 5.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.201 0.000 clk_50mhz " " 5.201 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.569 0.000 rx_clk " " 7.569 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231225 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 clk_50mhz " " 0.401 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 rx_clk " " 0.401 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231231 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 9.063 " "Worst-case recovery slack is 9.063" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.063 0.000 rx_clk " " 9.063 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 16.187 0.000 clk_50mhz " " 16.187 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231238 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.755 " "Worst-case removal slack is 2.755" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.755 0.000 clk_50mhz " " 2.755 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.637 0.000 rx_clk " " 3.637 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231244 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 6.498 " "Worst-case minimum pulse width slack is 6.498" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.498 0.000 rx_clk " " 6.498 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.750 0.000 clk_50mhz " " 9.750 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231247 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 46 synchronizer chains. " "Report Metastability: Found 46 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 46 " "Number of Synchronizer Chains Found: 46" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.424 ns " "Worst Case Available Settling Time: 12.424 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231325 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1781075231331 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231416 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 10.706 " "Worst-case setup slack is 10.706" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.706 0.000 rx_clk " " 10.706 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 13.064 0.000 clk_50mhz " " 13.064 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231425 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 clk_50mhz " " 0.186 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 rx_clk " " 0.186 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231432 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 11.259 " "Worst-case recovery slack is 11.259" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.259 0.000 rx_clk " " 11.259 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 18.082 0.000 clk_50mhz " " 18.082 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231439 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.361 " "Worst-case removal slack is 1.361" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.361 0.000 clk_50mhz " " 1.361 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.805 0.000 rx_clk " " 1.805 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231447 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 6.002 " "Worst-case minimum pulse width slack is 6.002" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.002 0.000 rx_clk " " 6.002 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.262 0.000 clk_50mhz " " 9.262 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231451 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 46 synchronizer chains. " "Report Metastability: Found 46 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 46 " "Number of Synchronizer Chains Found: 46" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.010 ns " "Worst Case Available Settling Time: 13.010 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231530 ""}
{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1781075231746 ""}
{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1781075231746 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4946 " "Peak virtual memory: 4946 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075231805 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:11 2026 " "Processing ended: Wed Jun 10 09:07:11 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075231805 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075231805 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075231805 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1781075231805 ""}

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