Arrive/FPGA_LVDS_PROTOCOL_ANALYSER
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David Rice 6ffca3d97f Initial commit: LVDS Protocol Analyser v1.0.0
2026-06-10 09:32:26 +02:00
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Initial commit: LVDS Protocol Analyser v1.0.0
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db
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de_monitor.v
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lvds_monitor.asm.rpt
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lvds_monitor.done
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lvds_monitor.fit.rpt
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lvds_monitor.fit.smsg
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lvds_monitor.fit.summary
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lvds_monitor.flow.rpt
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lvds_monitor.jdi
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lvds_monitor.jditmp
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lvds_monitor.map.rpt
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lvds_monitor.map.summary
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lvds_monitor.pin
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lvds_monitor.qpf
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lvds_monitor.qsf
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lvds_monitor.sdc
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lvds_monitor.sld
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lvds_monitor.sof
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lvds_monitor.sta.rpt
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lvds_monitor.sta.summary
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lvds_monitor.tcl
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README.md
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top.v
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uart_tx.v
Initial commit: LVDS Protocol Analyser v1.0.0
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README.md

Introduction

FPGA_LVDS_PROTOCOL_ANALYSER - LVDS ANALYSER BASED ON DS90CF386 AND ALTERA CYCLONE-IV FPGA

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Description
LVDS Analyser based on DS90CF386 and Altera Cyclone-IV FPGA
Readme 6.3 MiB
Languages
Verilog 89.8%
Tcl 7%
Python 3.2%