50 lines
25 KiB
Plaintext
50 lines
25 KiB
Plaintext
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "14 14 " "Parallel compilation is enabled and will use 14 of the 14 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1781075223819 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "lvds_monitor EP4CE6E22C8 " "Selected device EP4CE6E22C8 for design \"lvds_monitor\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1781075223828 ""}
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{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1781075223859 ""}
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{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1781075223859 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1781075223932 ""}
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{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1781075223935 ""}
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{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C8 " "Device EP4CE10E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1781075223991 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1781075223991 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1781075223991 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1781075223991 ""}
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{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3188 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3190 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3192 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3194 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1781075223993 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1781075223994 ""}
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{ "Info" "ISTA_SDC_FOUND" "lvds_monitor.sdc " "Reading SDC File: 'lvds_monitor.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1781075224324 ""}
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{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1781075224326 ""}
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{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1781075224335 ""}
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{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1781075224335 ""}
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{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 clk_50mhz " " 20.000 clk_50mhz" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 13.500 rx_clk " " 13.500 rx_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1781075224335 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rx_clk~input (placed in PIN 30 (DIFFIO_L8p, DQS1L/CQ1L#,DPCLK1)) " "Automatically promoted node rx_clk~input (placed in PIN 30 (DIFFIO_L8p, DQS1L/CQ1L#,DPCLK1))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 24 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3184 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_50mhz~input (placed in PIN 24 (CLK2, DIFFCLK_1p)) " "Automatically promoted node clk_50mhz~input (placed in PIN 24 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 23 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3182 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n_pin~input (placed in PIN 88 (CLK7, DIFFCLK_3n)) " "Automatically promoted node rst_n_pin~input (placed in PIN 88 (CLK7, DIFFCLK_3n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 28 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3183 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_sync_pix\[2\] " "Automatically promoted node rst_sync_pix\[2\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 57 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 200 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_sync_uart\[2\] " "Automatically promoted node rst_sync_uart\[2\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 51 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 197 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1781075224604 ""}
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{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1781075224605 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1781075224605 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1781075224606 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1781075224607 ""}
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{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1781075224607 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1781075224608 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1781075224608 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1781075224655 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1781075224655 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1781075224655 ""}
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{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075224675 ""}
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{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1781075224680 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1781075225007 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075225151 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1781075225164 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1781075225798 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075225798 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1781075226066 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1781075226561 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1781075226561 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1781075226671 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1781075226671 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1781075226671 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075226672 ""}
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{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.33 " "Total time spent on timing analysis during the Fitter is 0.33 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1781075226756 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1781075226769 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1781075226945 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1781075226946 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1781075227149 ""}
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{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075227477 ""}
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{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "6 Cyclone IV E " "6 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "vsync 3.3-V LVTTL 32 " "Pin vsync uses I/O standard 3.3-V LVTTL at 32" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { vsync } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "vsync" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 26 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 8 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "hsync 3.3-V LVTTL 33 " "Pin hsync uses I/O standard 3.3-V LVTTL at 33" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { hsync } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "hsync" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 27 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk_50mhz 3.3-V LVTTL 24 " "Pin clk_50mhz uses I/O standard 3.3-V LVTTL at 24" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { clk_50mhz } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_50mhz" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 23 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 5 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n_pin 3.3-V LVTTL 88 " "Pin rst_n_pin uses I/O standard 3.3-V LVTTL at 88" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { rst_n_pin } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n_pin" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 28 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rx_clk 3.3-V LVTTL 30 " "Pin rx_clk uses I/O standard 3.3-V LVTTL at 30" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { rx_clk } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rx_clk" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 24 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 6 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "de 3.3-V LVTTL 31 " "Pin de uses I/O standard 3.3-V LVTTL at 31" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { de } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "de" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 25 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 7 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1781075227622 ""}
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.fit.smsg " "Generated suppressed messages file C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1781075227671 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6367 " "Peak virtual memory: 6367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075227977 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:07 2026 " "Processing ended: Wed Jun 10 09:07:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075227977 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075227977 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075227977 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1781075227977 ""}
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