121 lines
19 KiB
HTML
121 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0303–0332</title>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 1 of 30 display load sessions (3%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0323</td><td>20260415_085420</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.2 ns</td><td>1.015 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0303</td><td>20260415_084704</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0304</td><td>20260415_084726</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0305</td><td>20260415_084748</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260415_084810</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260415_084831</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260415_084853</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260415_084915</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260415_084937</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260415_084958</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260415_085020</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260415_085042</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260415_085104</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260415_085126</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260415_085148</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260415_085209</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260415_085231</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260415_085253</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260415_085315</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260415_085337</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260415_085358</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260415_085420</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260415_085442</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260415_085504</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260415_085525</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260415_085547</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260415_085609</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260415_085630</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260415_085652</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260415_085714</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260415_085735</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-15 09:02:14 |
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<strong>Scope:</strong> Captures 0303–0332 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis Report</p>
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<p>## Batch: Captures 0303–0332 (30 sessions, 1 confirmed flicker event)</p>
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<ul><li></li></ul>
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<p>## 1. Consistent Spec Concerns</p>
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<p>### A. Register Timing — Systemic D-PHY v1.1 Non-Compliance (ALL 30 captures)</p>
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<p>Every capture shows identical register values — the system is running <strong>'Round Best' mode</strong> with <strong>5 persistent D-PHY violations</strong>:</p>
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<p>| Parameter | Programmed | Actual | Spec Min | Deficit |<br>|-----------|-----------|--------|----------|---------|<br>| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns (7.4%)</strong> |<br>| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns (2.6%)</strong> |<br>| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns (7.3%)</strong> |<br>| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns (1.2%)</strong> |<br>| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns (0.9%)</strong> |</p>
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<p><strong>Critical insight:</strong> The THS_PREPARE+THS_ZERO violation (1.5 ns short) directly controls the <strong>data lane SoT sequence</strong>. This is the time the receiver has to detect the HS-0 state before clock edges arrive. At only 0.9% below spec, the SN65DSI83 will *usually* latch it — but with jitter, process variation, and temperature, it will occasionally miss it. This exactly matches the observed bistable behaviour.</p>
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<p>### B. HS Amplitude — Marginal with Sub-140 mV Excursions</p>
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<ul><li><strong>CLK lane:</strong> Mean Vdiff ≈ 165.4 mV — only <strong>18% above the 140 mV floor</strong>. Every capture shows 17–102 settled samples below 140 mV.</li><li><strong>DAT0 lane:</strong> Mean Vdiff ≈ 187–199 mV (healthier), but sub-140 mV sample counts are highly variable: 19 to <strong>8,906</strong> samples per capture. This suggests data-pattern-dependent ISI causing amplitude collapse on certain bit sequences.</li><li><strong>CLK asymmetry:</strong> Consistent +194/−137 mV split (+30 mV common-mode offset) indicates a systematic DC offset in the clock driver or termination mismatch. While Vdiff is within spec, the asymmetry reduces noise margin on the negative swing.</li></ul>
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<p>### C. LP-11 Voltage — Low but In-Spec</p>
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<ul><li>LP-11 voltage: 1.014–1.016 V across all captures (spec 1.0–1.45 V).</li><li>This is at the <strong>bottom 4% of the allowed range</strong>. With VDDIO at 1.766 V, the LP driver VOH should be closer to 1.2–1.3 V. The 1.015 V level suggests either excessive series resistance in the LP path, a weak pull-up, or the probe is loading the LP driver (unlikely at ≥10 kΩ scope input).</li><li><strong>Not causing flicker directly</strong>, but reduced LP-11 level shrinks the receiver's threshold margin for detecting LP-11 → LP-01 transitions.</li></ul>
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<p>### D. LP Exit Duration — Universally Violated</p>
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<ul><li><strong>22 of 29 measurable captures</strong> show LP exit → HS of 2–4 ns (spec ≥ 50 ns).</li><li>Only <strong>6 captures</strong> show 348 ns (passing), and <strong>1 capture</strong> shows 174 ns (passing).</li><li>This is <strong>not a measurement artifact</strong>: the LP-01/LP-00 intermediate states are being driven too briefly (or skipped entirely) at the scope's sample resolution. The 2–4 ns readings indicate the PHY is transitioning from LP-11 directly to HS-0 without adequate dwell time in LP-01 and LP-00.</li></ul>
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<p><strong>Root cause:</strong> THS_PREPARE+THS_ZERO = 166.7 ns (below 168.2 ns spec) combined with the too-short TCLK_PREPARE (37 ns < 38 ns) means the PHY state machine is rushing through the SoT entry states. The Samsung DSIM PHY internally sequences LP-11 → LP-01 → LP-00 → HS-0 using these register values as counters.</p>
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<ul><li></li></ul>
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<p>## 2. Trends Across Captures</p>
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<p>### A. No Drift — Stable Degradation</p>
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<p>| Parameter | Min | Max | Trend |<br>|-----------|-----|-----|-------|<br>| CLK Vdiff | 163.3 mV | 166.6 mV | <strong>Flat</strong> (±1%) |<br>| DAT Vdiff | 175.5 mV | 199.4 mV | <strong>No drift</strong>, high variance |<br>| CLK jitter p-p | 138.2 ps | 170.4 ps | <strong>Flat</strong> (no degradation) |<br>| CLK jitter RMS | 51.4 ps | 54.8 ps | <strong>Flat</strong> |<br>| LP-11 voltage | 1.014 V | 1.016 V | <strong>Flat</strong> |<br>| 1.8 V mean | 1.7645 V | 1.7712 V | <strong>Flat</strong> |<br>| 1.8 V droop | 8.5 mV | 14.0 mV | <strong>Flat</strong> (no worsening) |<br>| LP-low plateau | 0–343 ns | — | <strong>Bimodal</strong> (see §3) |</p>
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<p><strong>Conclusion:</strong> No temporal degradation. The system is thermally and electrically stable. The problem is purely in the SoT timing register configuration.</p>
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<p>### B. LP-Low Plateau — Bimodal Distribution (Key Finding)</p>
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<p>The LP-low plateau values cluster into <strong>three discrete groups</strong>:</p>
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<p>| LP-low plateau | Count | LP exit reported | Flicker? |<br>|----------------|-------|-----------------|----------|<br>| <strong>342–343 ns</strong> | 17 | 2–4 ns (fail) or 348 ns (pass) | No (except 0323) |<br>| <strong>108 ns</strong> | 5 | 2–4 ns (fail) | No |<br>| <strong>169 ns</strong> | 1 | 174 ns (pass) | No |<br>| <strong>0 ns</strong> | 1 (Cap 0323) | 2 ns (fail) | <strong>YES — FLICKER</strong> |</p>
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<p>The 342–343 ns group corresponds to approximately <strong>18.5 byte-clocks</strong> — this is THS_PREPARE+THS_ZERO (9 bc = 166.7 ns) plus additional PHY sequencing. The 108 ns group (≈6 bc) suggests a capture where the scope trigger caught only partial SoT.</p>
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<p><strong>Capture 0323 is the critical outlier:</strong> LP-low = 0 ns means the PHY drove LP-11 → HS-0 with <strong>no detectable LP-low dwell</strong>. The SN65DSI83 never saw LP-01/LP-00 and failed to recognise SoT.</p>
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<ul><li></li></ul>
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<p>## 3. Anomalies</p>
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<p>### A. Flicker Capture 0323 — Detailed Analysis</p>
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<p>| Parameter | Cap 0323 (flicker) | Batch mean (no flicker) |<br>|-----------|-------------------|------------------------|<br>| LP-low plateau | <strong>0 ns</strong> | 108–343 ns |<br>| LP exit → HS | 2 ns | 2–348 ns |<br>| 1.8 V droop | 9.4 mV | 10.2 mV (avg) |<br>| 1.8 V ripple | 5.44 mV | 5.65 mV (avg) |<br>| CLK jitter p-p | 146.0 ps | 152.0 ps (avg) |<br>| LP-11 voltage | 1.015 V | 1.015 V (avg) |</p>
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<p><strong>The supply was actually slightly better than average during the flicker event.</strong> This confirms the flicker is <strong>not supply-related</strong> — it is a timing race condition in the PHY SoT state machine.</p>
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<p>### B. DAT0 HS Signal Anomalies</p>
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<ul><li><strong>Captures 0306, 0315:</strong> sig/dat reports 0.0 mV — HS signal entirely absent in the sig capture window. The scope likely triggered too early or too late relative to the HS burst. Probe contact verified by valid lp/dat data.</li><li><strong>Capture 0321:</strong> proto/dat reports 0.0 mV — data lane was in LP state during the entire proto window. Again a trigger timing issue, not a hardware fault.</li><li><strong>Most sig/dat captures</strong> show only negative swings (Vdiff pos = 0.0 mV). This indicates the scope trigger consistently lands on a data-0 run. Not a hardware concern, but the true DAT0 amplitude is likely slightly higher than reported.</li></ul>
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<p>### C. Capture 0325 — Processing Error</p>
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<p>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP data capture buffer was exactly full with no LP→HS transition found within the window. The DAT0 lane may not have transitioned during this capture's acquisition window. This is a trigger/timing issue, not a hardware fault.</p>
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<p>### D. CLK Lane LP State</p>
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<p>All captures show "CLK LP→HS: NOT DETECTED" — this is <strong>expected and correct</strong>. The i.MX 8M Mini DSIM runs the clock lane in <strong>continuous HS mode</strong> (no LP toggling on CLK during video). The CLK lane only enters LP at display pipeline unload, which these captures don't cover.</p>
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<ul><li></li></ul>
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<p>## 4. Supply Correlation Analysis</p>
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<p>| Metric | Flicker (0323) | Non-flicker (29 caps) | Correlation |<br>|--------|---------------|----------------------|-------------|<br>| 1.8 V mean | 1.7654 V | 1.7645–1.7712 V | <strong>None</strong> |<br>| 1.8 V min | 1.7560 V | 1.7520–1.7600 V | <strong>None</strong> |<br>| Droop depth | 9.4 mV | 8.5–14.0 mV | <strong>None</strong> — droop was average |<br>| Ripple RMS | 5.44 mV | 5.44–6.13 mV | <strong>None</strong> — ripple was minimum |</p>
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<p><strong>Conclusion: The 1.8 V supply is healthy and not a contributing factor.</strong> All readings are comfortably within spec (1.71–1.89 V). The droop of 8.5–14.0 mV (<1% of VDDIO) is excellent. There is no correlation between supply conditions and LP timing anomalies.</p>
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<p>The LP-11 voltage of 1.015 V (~56% of VDDIO) is lower than the expected ~70% (1.26 V) but is within D-PHY spec and does not correlate with the flicker event.</p>
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<ul><li></li></ul>
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<p>## 5. WARNING/ERROR Explanations</p>
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<p>| Warning | Count | Cause | Action |<br>|---------|-------|-------|--------|<br>| `LP exit duration N ns below spec min 50 ns` | 22/29 | THS_PREPARE+THS_ZERO too short (166.7 ns < 168.2 ns); PHY rushes LP→HS transition. Scope sees LP-01/LP-00 as sub-sample-resolution glitch. | <strong>Switch to 'Round Up' register values</strong> |<br>| `settled samples below 140 mV` (CLK) | 30/30 | CLK amplitude (165 mV) only 18% above floor; ISI/jitter pushes occasional eyes below. Termination or impedance mismatch likely. | Check CLK± PCB impedance matching; verify 100Ω differential termination at SN65DSI83 |<br>| `settled samples below 140 mV` (DAT) | 28/30 | Data pattern-dependent ISI; counts vary 19–8906. Higher counts correlate with captures where data pattern has long same-symbol runs. | Will improve with corrected register timing (better-formed SoT → fewer error patterns) |<br>| `Only negative swings in capture window` | 25/30 | Scope trigger consistently catches data-0 bit runs. Amplitude may be slightly underestimated. | Not a hardware concern; for accurate amplitude use pattern generator or longer random window |<br>| `No HS signal detected` (sig/dat) | 2/30 | Trigger landed outside HS burst window on DAT0. | Adjust trigger holdoff or use CLK-edge trigger for sig captures |<br>| `No HS signal detected` (proto/dat) | 1/30 | DAT0 in LP state during entire proto window. | Same trigger adjustment |<br>| `index out of bounds` (0325 lp_dat) | 1/30 | Buffer filled before LP→HS edge appeared — trigger too early or DAT0 transition outside window. | Increase buffer depth or adjust pre-trigger ratio |<br>| `CLK LP→HS: NOT DETECTED` | 30/30 | <strong>Expected.</strong> CLK runs continuous HS. | No action — informational only |</p>
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<ul><li></li></ul>
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<p>## 6. Actionable Recommendations</p>
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<p>### PRIORITY 1 — Switch to 'Round Up' PHY Timing (Fixes Root Cause)</p>
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<p>Patch the samsung-dsim driver or device tree to program the 'Round Up' register values:</p>
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<p>```<br>DSIM_PHYTIMING (0xb4): 0x00000306 (THS_EXIT=6 → 111.1 ns ✓)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04 (TCLK_PREPARE=3 → 55.6 ns ✓, TCLK_ZERO=15, TCLK_TRAIL=4 → 74.1 ns ✓)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706 (THS_ZERO=7, THS_TRAIL=6 → 111.1 ns ✓)<br>```</p>
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<p>This eliminates all 5 D-PHY violations. The critical fix is <strong>THS_PREPARE+THS_ZERO: 10 bc = 185.2 ns</strong> (was 166.7 ns, spec ≥ 168.2 ns) — an increase of <strong>18.5 ns (11%)</strong> giving the SN65DSI83 receiver comfortable margin to detect SoT.</p>
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<p><strong>Implementation options (in order of preference):</strong><br>1. <strong>Driver patch:</strong> Modify the `samsung_dsim_set_phy_timing()` function to use ceiling division instead of round-to-nearest for all timing parameters.<br>2. <strong>Device tree override:</strong> If the driver supports `phy-timing` properties, set them explicitly.<br>3. <strong>Runtime register write:</strong> As a temporary test, write registers via `memtool` after pipeline load (will confirm the fix but won't persist across loads).</p>
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<p>### PRIORITY 2 — Investigate LP-11 Voltage (Low Priority)</p>
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<p>LP-11 at 1.015 V (56% VDDIO) is unusually low. Check:<br>- Series resistance on DAT0+/DAT0− LP paths (ESD protection, ferrite beads, connectors).<br>- Whether the scope probe is loading the LP driver (unlikely but verify with 10× probe).<br>- SN65DSI83 input bias current on MIPI pins — the TI datasheet specifies the input leakage.</p>
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<p>This is not causing flicker but is a signal quality concern that could become problematic at higher bit rates or lower temperatures.</p>
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<p>### PRIORITY 3 — CLK Amplitude Margin Improvement (Medium Priority)</p>
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<p>CLK Vdiff at 165 mV with consistent sub-140 mV excursions suggests:<br>- Verify CLK± trace impedance is 100Ω differential (50Ω single-ended). Any impedance mismatch will reduce amplitude via reflections.<br>- Check for stubs or vias on CLK± traces near the SN65DSI83 input.<br>- The +30 mV common-mode offset on CLK indicates asymmetric termination or driver offset — verify both CLK± termination resistors are matched.</p>
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<p>### PRIORITY 4 — Improve Capture Trigger Reliability (Diagnostic)</p>
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<ul><li>Use CLK-lane HS edge as trigger source for</li></ul>
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<p class="tokens">Tokens: 45085 in / 4096 out</p>
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</body>
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