MIPI D-PHY Analysis Report

Generated: 2026-04-15 09:02:14  |  Scope: Captures 0303–0332  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis Report

## Batch: Captures 0303–0332 (30 sessions, 1 confirmed flicker event)

## 1. Consistent Spec Concerns

### A. Register Timing — Systemic D-PHY v1.1 Non-Compliance (ALL 30 captures)

Every capture shows identical register values — the system is running 'Round Best' mode with 5 persistent D-PHY violations:

| Parameter | Programmed | Actual | Spec Min | Deficit |
|-----------|-----------|--------|----------|---------|
| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns (7.4%) |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns (2.6%) |
| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns (7.3%) |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns (1.2%) |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns (0.9%) |

Critical insight: The THS_PREPARE+THS_ZERO violation (1.5 ns short) directly controls the data lane SoT sequence. This is the time the receiver has to detect the HS-0 state before clock edges arrive. At only 0.9% below spec, the SN65DSI83 will *usually* latch it — but with jitter, process variation, and temperature, it will occasionally miss it. This exactly matches the observed bistable behaviour.

### B. HS Amplitude — Marginal with Sub-140 mV Excursions

• CLK lane: Mean Vdiff ≈ 165.4 mV — only 18% above the 140 mV floor. Every capture shows 17–102 settled samples below 140 mV.
• DAT0 lane: Mean Vdiff ≈ 187–199 mV (healthier), but sub-140 mV sample counts are highly variable: 19 to 8,906 samples per capture. This suggests data-pattern-dependent ISI causing amplitude collapse on certain bit sequences.
• CLK asymmetry: Consistent +194/−137 mV split (+30 mV common-mode offset) indicates a systematic DC offset in the clock driver or termination mismatch. While Vdiff is within spec, the asymmetry reduces noise margin on the negative swing.

### C. LP-11 Voltage — Low but In-Spec

• LP-11 voltage: 1.014–1.016 V across all captures (spec 1.0–1.45 V).
• This is at the bottom 4% of the allowed range. With VDDIO at 1.766 V, the LP driver VOH should be closer to 1.2–1.3 V. The 1.015 V level suggests either excessive series resistance in the LP path, a weak pull-up, or the probe is loading the LP driver (unlikely at ≥10 kΩ scope input).
• Not causing flicker directly, but reduced LP-11 level shrinks the receiver's threshold margin for detecting LP-11 → LP-01 transitions.

### D. LP Exit Duration — Universally Violated

• 22 of 29 measurable captures show LP exit → HS of 2–4 ns (spec ≥ 50 ns).
• Only 6 captures show 348 ns (passing), and 1 capture shows 174 ns (passing).
• This is not a measurement artifact: the LP-01/LP-00 intermediate states are being driven too briefly (or skipped entirely) at the scope's sample resolution. The 2–4 ns readings indicate the PHY is transitioning from LP-11 directly to HS-0 without adequate dwell time in LP-01 and LP-00.

Root cause: THS_PREPARE+THS_ZERO = 166.7 ns (below 168.2 ns spec) combined with the too-short TCLK_PREPARE (37 ns < 38 ns) means the PHY state machine is rushing through the SoT entry states. The Samsung DSIM PHY internally sequences LP-11 → LP-01 → LP-00 → HS-0 using these register values as counters.

## 2. Trends Across Captures

### A. No Drift — Stable Degradation

| Parameter | Min | Max | Trend |
|-----------|-----|-----|-------|
| CLK Vdiff | 163.3 mV | 166.6 mV | Flat (±1%) |
| DAT Vdiff | 175.5 mV | 199.4 mV | No drift, high variance |
| CLK jitter p-p | 138.2 ps | 170.4 ps | Flat (no degradation) |
| CLK jitter RMS | 51.4 ps | 54.8 ps | Flat |
| LP-11 voltage | 1.014 V | 1.016 V | Flat |
| 1.8 V mean | 1.7645 V | 1.7712 V | Flat |
| 1.8 V droop | 8.5 mV | 14.0 mV | Flat (no worsening) |
| LP-low plateau | 0–343 ns | — | Bimodal (see §3) |

Conclusion: No temporal degradation. The system is thermally and electrically stable. The problem is purely in the SoT timing register configuration.

### B. LP-Low Plateau — Bimodal Distribution (Key Finding)

The LP-low plateau values cluster into three discrete groups:

| LP-low plateau | Count | LP exit reported | Flicker? |
|----------------|-------|-----------------|----------|
| 342–343 ns | 17 | 2–4 ns (fail) or 348 ns (pass) | No (except 0323) |
| 108 ns | 5 | 2–4 ns (fail) | No |
| 169 ns | 1 | 174 ns (pass) | No |
| 0 ns | 1 (Cap 0323) | 2 ns (fail) | YES — FLICKER |

The 342–343 ns group corresponds to approximately 18.5 byte-clocks — this is THS_PREPARE+THS_ZERO (9 bc = 166.7 ns) plus additional PHY sequencing. The 108 ns group (≈6 bc) suggests a capture where the scope trigger caught only partial SoT.

Capture 0323 is the critical outlier: LP-low = 0 ns means the PHY drove LP-11 → HS-0 with no detectable LP-low dwell. The SN65DSI83 never saw LP-01/LP-00 and failed to recognise SoT.

## 3. Anomalies

### A. Flicker Capture 0323 — Detailed Analysis

| Parameter | Cap 0323 (flicker) | Batch mean (no flicker) |
|-----------|-------------------|------------------------|
| LP-low plateau | 0 ns | 108–343 ns |
| LP exit → HS | 2 ns | 2–348 ns |
| 1.8 V droop | 9.4 mV | 10.2 mV (avg) |
| 1.8 V ripple | 5.44 mV | 5.65 mV (avg) |
| CLK jitter p-p | 146.0 ps | 152.0 ps (avg) |
| LP-11 voltage | 1.015 V | 1.015 V (avg) |

The supply was actually slightly better than average during the flicker event. This confirms the flicker is not supply-related — it is a timing race condition in the PHY SoT state machine.

### B. DAT0 HS Signal Anomalies

• Captures 0306, 0315: sig/dat reports 0.0 mV — HS signal entirely absent in the sig capture window. The scope likely triggered too early or too late relative to the HS burst. Probe contact verified by valid lp/dat data.
• Capture 0321: proto/dat reports 0.0 mV — data lane was in LP state during the entire proto window. Again a trigger timing issue, not a hardware fault.
• Most sig/dat captures show only negative swings (Vdiff pos = 0.0 mV). This indicates the scope trigger consistently lands on a data-0 run. Not a hardware concern, but the true DAT0 amplitude is likely slightly higher than reported.

### C. Capture 0325 — Processing Error

`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP data capture buffer was exactly full with no LP→HS transition found within the window. The DAT0 lane may not have transitioned during this capture's acquisition window. This is a trigger/timing issue, not a hardware fault.

### D. CLK Lane LP State

All captures show "CLK LP→HS: NOT DETECTED" — this is expected and correct. The i.MX 8M Mini DSIM runs the clock lane in continuous HS mode (no LP toggling on CLK during video). The CLK lane only enters LP at display pipeline unload, which these captures don't cover.

## 4. Supply Correlation Analysis

| Metric | Flicker (0323) | Non-flicker (29 caps) | Correlation |
|--------|---------------|----------------------|-------------|
| 1.8 V mean | 1.7654 V | 1.7645–1.7712 V | None |
| 1.8 V min | 1.7560 V | 1.7520–1.7600 V | None |
| Droop depth | 9.4 mV | 8.5–14.0 mV | None — droop was average |
| Ripple RMS | 5.44 mV | 5.44–6.13 mV | None — ripple was minimum |

Conclusion: The 1.8 V supply is healthy and not a contributing factor. All readings are comfortably within spec (1.71–1.89 V). The droop of 8.5–14.0 mV (<1% of VDDIO) is excellent. There is no correlation between supply conditions and LP timing anomalies.

The LP-11 voltage of 1.015 V (~56% of VDDIO) is lower than the expected ~70% (1.26 V) but is within D-PHY spec and does not correlate with the flicker event.

## 5. WARNING/ERROR Explanations

| Warning | Count | Cause | Action |
|---------|-------|-------|--------|
| `LP exit duration N ns below spec min 50 ns` | 22/29 | THS_PREPARE+THS_ZERO too short (166.7 ns < 168.2 ns); PHY rushes LP→HS transition. Scope sees LP-01/LP-00 as sub-sample-resolution glitch. | Switch to 'Round Up' register values |
| `settled samples below 140 mV` (CLK) | 30/30 | CLK amplitude (165 mV) only 18% above floor; ISI/jitter pushes occasional eyes below. Termination or impedance mismatch likely. | Check CLK± PCB impedance matching; verify 100Ω differential termination at SN65DSI83 |
| `settled samples below 140 mV` (DAT) | 28/30 | Data pattern-dependent ISI; counts vary 19–8906. Higher counts correlate with captures where data pattern has long same-symbol runs. | Will improve with corrected register timing (better-formed SoT → fewer error patterns) |
| `Only negative swings in capture window` | 25/30 | Scope trigger consistently catches data-0 bit runs. Amplitude may be slightly underestimated. | Not a hardware concern; for accurate amplitude use pattern generator or longer random window |
| `No HS signal detected` (sig/dat) | 2/30 | Trigger landed outside HS burst window on DAT0. | Adjust trigger holdoff or use CLK-edge trigger for sig captures |
| `No HS signal detected` (proto/dat) | 1/30 | DAT0 in LP state during entire proto window. | Same trigger adjustment |
| `index out of bounds` (0325 lp_dat) | 1/30 | Buffer filled before LP→HS edge appeared — trigger too early or DAT0 transition outside window. | Increase buffer depth or adjust pre-trigger ratio |
| `CLK LP→HS: NOT DETECTED` | 30/30 | Expected. CLK runs continuous HS. | No action — informational only |

## 6. Actionable Recommendations

### PRIORITY 1 — Switch to 'Round Up' PHY Timing (Fixes Root Cause)

Patch the samsung-dsim driver or device tree to program the 'Round Up' register values:

```
DSIM_PHYTIMING (0xb4): 0x00000306 (THS_EXIT=6 → 111.1 ns ✓)
DSIM_PHYTIMING1 (0xb8): 0x030f0a04 (TCLK_PREPARE=3 → 55.6 ns ✓, TCLK_ZERO=15, TCLK_TRAIL=4 → 74.1 ns ✓)
DSIM_PHYTIMING2 (0xbc): 0x00030706 (THS_ZERO=7, THS_TRAIL=6 → 111.1 ns ✓)
```

This eliminates all 5 D-PHY violations. The critical fix is THS_PREPARE+THS_ZERO: 10 bc = 185.2 ns (was 166.7 ns, spec ≥ 168.2 ns) — an increase of 18.5 ns (11%) giving the SN65DSI83 receiver comfortable margin to detect SoT.

Implementation options (in order of preference):
1. Driver patch: Modify the `samsung_dsim_set_phy_timing()` function to use ceiling division instead of round-to-nearest for all timing parameters.
2. Device tree override: If the driver supports `phy-timing` properties, set them explicitly.
3. Runtime register write: As a temporary test, write registers via `memtool` after pipeline load (will confirm the fix but won't persist across loads).

### PRIORITY 2 — Investigate LP-11 Voltage (Low Priority)

LP-11 at 1.015 V (56% VDDIO) is unusually low. Check:
- Series resistance on DAT0+/DAT0− LP paths (ESD protection, ferrite beads, connectors).
- Whether the scope probe is loading the LP driver (unlikely but verify with 10× probe).
- SN65DSI83 input bias current on MIPI pins — the TI datasheet specifies the input leakage.

This is not causing flicker but is a signal quality concern that could become problematic at higher bit rates or lower temperatures.

### PRIORITY 3 — CLK Amplitude Margin Improvement (Medium Priority)

CLK Vdiff at 165 mV with consistent sub-140 mV excursions suggests:
- Verify CLK± trace impedance is 100Ω differential (50Ω single-ended). Any impedance mismatch will reduce amplitude via reflections.
- Check for stubs or vias on CLK± traces near the SN65DSI83 input.
- The +30 mV common-mode offset on CLK indicates asymmetric termination or driver offset — verify both CLK± termination resistors are matched.

### PRIORITY 4 — Improve Capture Trigger Reliability (Diagnostic)

• Use CLK-lane HS edge as trigger source for

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