Initial commit: LVDS Protocol Analyser v1.0.0

lvds_monitor.sdc

@@ -0,0 +1,26 @@
+# lvds_monitor.sdc
+# Timing constraints for the LVDS FlatLink monitor.
+
+# ---- primary clocks ----
+create_clock -name clk_50mhz -period 20.000 [get_ports {clk_50mhz}]
+# DS90CF386 RxCLKOUT for the Ampire 1280x800 panel: ~71.5 MHz typical.
+# Use 13.500 ns (74 MHz) to give a small worst-case margin.
+create_clock -name rx_clk    -period 13.500 [get_ports {rx_clk}]
+
+derive_clock_uncertainty
+
+# ---- async clock domain crossing ----
+# req_tog and the latched data registers in the pix domain are sampled
+# by 2-FF synchronisers on the UART domain. Treat the two clocks as
+# fully asynchronous; per-path false_path on the individual register
+# crossings is more precise, but set_clock_groups suffices here.
+set_clock_groups -asynchronous \
+    -group [get_clocks {rx_clk}] \
+    -group [get_clocks {clk_50mhz}]
+
+# ---- inputs (asynchronous to internal logic; tell TimeQuest to skip) ----
+set_false_path -from [get_ports {de vsync hsync rst_n_pin}] -to [all_registers]
+
+# ---- output ----
+# UART TX is asynchronous from the receiver's standpoint; don't constrain it.
+set_false_path -from [all_registers] -to [get_ports {uart_tx_pin}]