Arrive/FPGA_LVDS_PROTOCOL_ANALYSER
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Initial commit: LVDS Protocol Analyser v1.0.0

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David Rice
2026-06-10 09:32:26 +02:00
commit 6ffca3d97f
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lvds_monitor.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2025 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Altera and sold by Altera or its authorized distributors. Please
# refer to the Altera Software License Subscription Agreements
# on the Quartus Prime software download page.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
# Date created = 08:48:23 June 10, 2026
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# lvds_monitor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:48:23 JUNE 10, 2026"
set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
set_global_assignment -name VERILOG_FILE de_monitor.v
set_global_assignment -name VERILOG_FILE uart_tx.v
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name SDC_FILE lvds_monitor.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_24 -to clk_50mhz
set_location_assignment PIN_10 -to uart_tx_pin
set_location_assignment PIN_88 -to rst_n_pin
set_location_assignment PIN_30 -to rx_clk
set_location_assignment PIN_31 -to de
set_location_assignment PIN_32 -to vsync
set_location_assignment PIN_33 -to hsync
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50mhz
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_tx_pin
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pin
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rx_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to de
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vsync
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hsync