Initial commit: LVDS Protocol Analyser v1.0.0
This commit is contained in:
David Rice
450
lvds_monitor.map.rpt
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450
lvds_monitor.map.rpt
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Analysis & Synthesis report for lvds_monitor
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Wed Jun 10 09:07:02 2026
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Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. State Machine - |top|fstate
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9. State Machine - |top|uart_tx:u_uart|state
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10. Registers Removed During Synthesis
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11. Removed Registers Triggering Further Register Optimizations
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12. General Register Statistics
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13. Inverted Register Statistics
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14. Multiplexer Restructuring Statistics (Restructuring Performed)
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15. Parameter Settings for User Entity Instance: de_monitor:u_mon
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16. Parameter Settings for User Entity Instance: uart_tx:u_uart
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17. Post-Synthesis Netlist Statistics for Top Partition
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18. Elapsed Time Per Partition
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19. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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||||
----------------
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Copyright (C) 2025 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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||||
(including device programming or simulation files), and any
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||||
associated documentation or information are expressly subject
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||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
the Altera IP License Agreement, or other applicable license
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||||
agreement, including, without limitation, that your use is for
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||||
the sole purpose of programming logic devices manufactured by
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Altera and sold by Altera or its authorized distributors. Please
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||||
refer to the Altera Software License Subscription Agreements
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||||
on the Quartus Prime software download page.
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||||
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||||
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+--------------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+-------------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Wed Jun 10 09:07:02 2026 ;
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; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
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; Revision Name ; lvds_monitor ;
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; Top-level Entity Name ; top ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; 1,990 ;
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; Total combinational functions ; 1,853 ;
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; Dedicated logic registers ; 319 ;
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; Total registers ; 319 ;
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; Total pins ; 7 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Total PLLs ; 0 ;
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+------------------------------------+-------------------------------------------------+
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+------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Device ; EP4CE6E22C8 ; ;
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; Top-level entity name ; top ; lvds_monitor ;
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; Family name ; Cyclone IV E ; Cyclone V ;
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; Maximum processors allowed for parallel compilation ; All ; ;
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; Verilog Version ; SystemVerilog_2005 ; Verilog_2001 ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto RAM Block Balancing ; On ; On ;
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; Auto RAM to Logic Cell Conversion ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 2 ; 2 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
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||||
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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||||
; Resource Aware Inference For Block RAM ; On ; On ;
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+------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 20 ;
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; Maximum allowed ; 14 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 14 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 0.1% ;
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; Processor 3 ; 0.1% ;
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; Processor 4 ; 0.0% ;
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; Processor 5 ; 0.0% ;
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; Processors 6-14 ; 0.0% ;
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+----------------------------+-------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+----------------------------------+-----------------+------------------------+-------------------------------------------------------------+---------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
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+----------------------------------+-----------------+------------------------+-------------------------------------------------------------+---------+
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; de_monitor.v ; yes ; User Verilog HDL File ; C:/Users/DavidRice/Documents/fpga/lvds_monitor/de_monitor.v ; ;
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; uart_tx.v ; yes ; User Verilog HDL File ; C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v ; ;
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; top.v ; yes ; User Verilog HDL File ; C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v ; ;
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+----------------------------------+-----------------+------------------------+-------------------------------------------------------------+---------+
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+------------------------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+---------------------------------------------+--------------+
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; Resource ; Usage ;
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+---------------------------------------------+--------------+
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; Estimated Total logic elements ; 1,990 ;
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; ; ;
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; Total combinational functions ; 1853 ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 855 ;
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; -- 3 input functions ; 149 ;
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; -- <=2 input functions ; 849 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 1128 ;
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; -- arithmetic mode ; 725 ;
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; ; ;
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; Total registers ; 319 ;
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; -- Dedicated logic registers ; 319 ;
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; -- I/O registers ; 0 ;
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; ; ;
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; I/O pins ; 7 ;
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; ; ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; ; ;
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; Maximum fan-out node ; rx_clk~input ;
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; Maximum fan-out ; 162 ;
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; Total fan-out ; 6831 ;
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; Average fan-out ; 3.12 ;
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+---------------------------------------------+--------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
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; |top ; 1853 (1701) ; 319 (173) ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |top ; top ; work ;
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; |de_monitor:u_mon| ; 127 (127) ; 117 (117) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|de_monitor:u_mon ; de_monitor ; work ;
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; |uart_tx:u_uart| ; 25 (25) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|uart_tx:u_uart ; uart_tx ; work ;
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+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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Encoding Type: One-Hot
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+-------------------------------------------------------------------------------------+
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; State Machine - |top|fstate ;
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+------------------+---------------+---------------+------------------+---------------+
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; Name ; fstate.F_WAIT ; fstate.F_LOAD ; fstate.F_CONVERT ; fstate.F_IDLE ;
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+------------------+---------------+---------------+------------------+---------------+
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; fstate.F_IDLE ; 0 ; 0 ; 0 ; 0 ;
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; fstate.F_CONVERT ; 0 ; 0 ; 1 ; 1 ;
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; fstate.F_LOAD ; 0 ; 1 ; 0 ; 1 ;
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; fstate.F_WAIT ; 1 ; 0 ; 0 ; 1 ;
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||||
+------------------+---------------+---------------+------------------+---------------+
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||||
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||||
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Encoding Type: One-Hot
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||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; State Machine - |top|uart_tx:u_uart|state ;
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+---------------+--------------+------------+------------+------------+------------+------------+------------+------------+------------+---------------+--------------+
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; Name ; state.S_STOP ; state.S_D7 ; state.S_D6 ; state.S_D5 ; state.S_D4 ; state.S_D3 ; state.S_D2 ; state.S_D1 ; state.S_D0 ; state.S_START ; state.S_IDLE ;
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+---------------+--------------+------------+------------+------------+------------+------------+------------+------------+------------+---------------+--------------+
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||||
; state.S_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
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; state.S_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
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; state.S_D0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
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; state.S_D1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
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; state.S_D2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
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; state.S_D3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
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; state.S_D4 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
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; state.S_D5 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
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; state.S_D6 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
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; state.S_D7 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
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; state.S_STOP ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
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||||
+---------------+--------------+------------+------------+------------+------------+------------+------------+------------+------------+---------------+--------------+
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+---------------------------------------------------------------------------------+
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; Registers Removed During Synthesis ;
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+----------------------------------------+----------------------------------------+
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; Register name ; Reason for Removal ;
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+----------------------------------------+----------------------------------------+
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||||
; msg_len[2,5] ; Stuck at GND due to stuck port data_in ;
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; tx_byte[7] ; Stuck at GND due to stuck port data_in ;
|
||||
; uart_tx:u_uart|shift[7] ; Stuck at GND due to stuck port data_in ;
|
||||
; msg_len[3,4] ; Merged with is_err_msg ;
|
||||
; fstate~8 ; Lost fanout ;
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; fstate~9 ; Lost fanout ;
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||||
; uart_tx:u_uart|state~15 ; Lost fanout ;
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||||
; uart_tx:u_uart|state~16 ; Lost fanout ;
|
||||
; uart_tx:u_uart|state~17 ; Lost fanout ;
|
||||
; uart_tx:u_uart|state~18 ; Lost fanout ;
|
||||
; req_tog ; Merged with hb_count[0] ;
|
||||
; Total Number of Removed Registers = 13 ; ;
|
||||
+----------------------------------------+----------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------+
|
||||
; Removed Registers Triggering Further Register Optimizations ;
|
||||
+---------------+---------------------------+----------------------------------------+
|
||||
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
|
||||
+---------------+---------------------------+----------------------------------------+
|
||||
; tx_byte[7] ; Stuck at GND ; uart_tx:u_uart|shift[7] ;
|
||||
; ; due to stuck port data_in ; ;
|
||||
+---------------+---------------------------+----------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
; General Register Statistics ;
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 319 ;
|
||||
; Number of registers using Synchronous Clear ; 32 ;
|
||||
; Number of registers using Synchronous Load ; 25 ;
|
||||
; Number of registers using Asynchronous Clear ; 319 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 287 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
||||
+--------------------------------------------------+
|
||||
; Inverted Register Statistics ;
|
||||
+----------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------+---------+
|
||||
; uart_tx:u_uart|tx ; 2 ;
|
||||
; Total number of inverted registers = 1 ; ;
|
||||
+----------------------------------------+---------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
|
||||
; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |top|uart_tx:u_uart|tick[2] ;
|
||||
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |top|de_monitor:u_mon|line_width[0] ;
|
||||
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |top|de_monitor:u_mon|line_count[4] ;
|
||||
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |top|de_monitor:u_mon|bad_width[0] ;
|
||||
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |top|conv_step[1] ;
|
||||
; 5:1 ; 16 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |top|de_monitor:u_mon|gap_count[12] ;
|
||||
; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |top|idx[5] ;
|
||||
; 65:1 ; 4 bits ; 172 LEs ; 80 LEs ; 92 LEs ; Yes ; |top|tx_byte[0] ;
|
||||
; 34:1 ; 10 bits ; 220 LEs ; 180 LEs ; 40 LEs ; Yes ; |top|l_rem[15] ;
|
||||
; 34:1 ; 10 bits ; 220 LEs ; 180 LEs ; 40 LEs ; Yes ; |top|w_rem[12] ;
|
||||
; 3:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |top|uart_tx:u_uart|state ;
|
||||
; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |top|Selector39 ;
|
||||
; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |top|Selector40 ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: de_monitor:u_mon ;
|
||||
+----------------+------------------+---------------------------+
|
||||
; Parameter Name ; Value ; Type ;
|
||||
+----------------+------------------+---------------------------+
|
||||
; EXPECTED_LINES ; 0000001100100000 ; Unsigned Binary ;
|
||||
; EXPECTED_WIDTH ; 0000010100000000 ; Unsigned Binary ;
|
||||
; FRAME_GAP_PIX ; 0000100000000000 ; Unsigned Binary ;
|
||||
+----------------+------------------+---------------------------+
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+-------------------------------------------------------------+
|
||||
; Parameter Settings for User Entity Instance: uart_tx:u_uart ;
|
||||
+----------------+----------+---------------------------------+
|
||||
; Parameter Name ; Value ; Type ;
|
||||
+----------------+----------+---------------------------------+
|
||||
; CLK_HZ ; 50000000 ; Signed Integer ;
|
||||
; BAUD ; 115200 ; Signed Integer ;
|
||||
+----------------+----------+---------------------------------+
|
||||
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
; Post-Synthesis Netlist Statistics for Top Partition ;
|
||||
+-----------------------+-----------------------------+
|
||||
; Type ; Count ;
|
||||
+-----------------------+-----------------------------+
|
||||
; boundary_port ; 7 ;
|
||||
; cycloneiii_ff ; 319 ;
|
||||
; CLR ; 22 ;
|
||||
; CLR SCLR ; 9 ;
|
||||
; CLR SLD ; 1 ;
|
||||
; ENA CLR ; 240 ;
|
||||
; ENA CLR SCLR ; 23 ;
|
||||
; ENA CLR SLD ; 24 ;
|
||||
; cycloneiii_lcell_comb ; 1854 ;
|
||||
; arith ; 725 ;
|
||||
; 2 data inputs ; 725 ;
|
||||
; normal ; 1129 ;
|
||||
; 0 data inputs ; 1 ;
|
||||
; 1 data inputs ; 63 ;
|
||||
; 2 data inputs ; 61 ;
|
||||
; 3 data inputs ; 149 ;
|
||||
; 4 data inputs ; 855 ;
|
||||
; ; ;
|
||||
; Max LUT depth ; 13.00 ;
|
||||
; Average LUT depth ; 7.35 ;
|
||||
+-----------------------+-----------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Elapsed Time Per Partition ;
|
||||
+----------------+--------------+
|
||||
; Partition Name ; Elapsed Time ;
|
||||
+----------------+--------------+
|
||||
; Top ; 00:00:03 ;
|
||||
+----------------+--------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Wed Jun 10 09:06:53 2026
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor
|
||||
Info (20030): Parallel compilation is enabled and will use 14 of the 14 processors detected
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file de_monitor.v
|
||||
Info (12023): Found entity 1: de_monitor File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/de_monitor.v Line: 23
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file uart_tx.v
|
||||
Info (12023): Found entity 1: uart_tx File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v Line: 10
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file top.v
|
||||
Info (12023): Found entity 1: top File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 22
|
||||
Info (12127): Elaborating entity "top" for the top level hierarchy
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(33): object "_unused" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 33
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L0_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L1_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L2_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L3_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W0_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W1_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W2_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
|
||||
Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W3_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
|
||||
Info (12128): Elaborating entity "de_monitor" for hierarchy "de_monitor:u_mon" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 81
|
||||
Info (12128): Elaborating entity "uart_tx" for hierarchy "uart_tx:u_uart" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 359
|
||||
Info (10264): Verilog HDL Case Statement information at uart_tx.v(60): all case item expressions in this case statement are onehot File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v Line: 60
|
||||
Info (13000): Registers with preset signals will power-up high File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v Line: 18
|
||||
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (17049): 6 registers lost all their fanouts during netlist optimizations.
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Warning (21074): Design contains 2 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "vsync" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 26
|
||||
Warning (15610): No output dependent on input pin "hsync" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 27
|
||||
Info (21057): Implemented 2001 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 6 input pins
|
||||
Info (21059): Implemented 1 output pins
|
||||
Info (21061): Implemented 1994 logic cells
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
|
||||
Info: Peak virtual memory: 4878 megabytes
|
||||
Info: Processing ended: Wed Jun 10 09:07:02 2026
|
||||
Info: Elapsed time: 00:00:09
|
||||
Info: Total CPU time (on all processors): 00:00:16
|
||||
|
||||
|
||||
Reference in New Issue
Block a user