Arrive/FPGA_LVDS_PROTOCOL_ANALYSER
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Initial commit: LVDS Protocol Analyser v1.0.0

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David Rice
2026-06-10 09:32:26 +02:00
commit 6ffca3d97f
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Flow report for lvds_monitor
Wed Jun 10 09:07:11 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+--------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Wed Jun 10 09:07:09 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; lvds_monitor ;
; Top-level Entity Name ; top ;
; Family ; Cyclone IV E ;
; Device ; EP4CE6E22C8 ;
; Timing Models ; Final ;
; Total logic elements ; 1,953 / 6,272 ( 31 % ) ;
; Total combinational functions ; 1,856 / 6,272 ( 30 % ) ;
; Dedicated logic registers ; 319 / 6,272 ( 5 % ) ;
; Total registers ; 319 ;
; Total pins ; 7 / 92 ( 8 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 276,480 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+-------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 06/10/2026 09:06:53 ;
; Main task ; Compilation ;
; Revision Name ; lvds_monitor ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------+---------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 266223544113564.178107521313648 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; All ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; top ; lvds_monitor ; -- ; -- ;
; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
+-------------------------+---------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4878 MB ; 00:00:16 ;
; Fitter ; 00:00:04 ; 1.3 ; 6367 MB ; 00:00:08 ;
; Assembler ; 00:00:01 ; 1.0 ; 4743 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:01 ; 1.4 ; 4946 MB ; 00:00:02 ;
; Total ; 00:00:15 ; -- ; -- ; 00:00:27 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor
quartus_fit --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor
quartus_asm --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor
quartus_sta lvds_monitor -c lvds_monitor