Arrive/FPGA_LVDS_PROTOCOL_ANALYSER
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Initial commit: LVDS Protocol Analyser v1.0.0

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David Rice
2026-06-10 09:32:26 +02:00
commit 6ffca3d97f
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Fitter Status : Successful - Wed Jun 10 09:07:07 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : lvds_monitor
Top-level Entity Name : top
Family : Cyclone IV E
Device : EP4CE6E22C8
Timing Models : Final
Total logic elements : 1,953 / 6,272 ( 31 % )
Total combinational functions : 1,856 / 6,272 ( 30 % )
Dedicated logic registers : 319 / 6,272 ( 5 % )
Total registers : 319
Total pins : 7 / 92 ( 8 % )
Total virtual pins : 0
Total memory bits : 0 / 276,480 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 30 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )