Arrive/FPGA_LVDS_PROTOCOL_ANALYSER
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit: LVDS Protocol Analyser v1.0.0

Browse Source
This commit is contained in:
David Rice
2026-06-10 09:32:26 +02:00
commit 6ffca3d97f
146 changed files with 8230 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
db/lvds_monitor.smp_dump.txt Normal file
View File

@@ -0,0 +1,21 @@
State Machine - |top|fstate
Name fstate.F_WAIT fstate.F_LOAD fstate.F_CONVERT fstate.F_IDLE
fstate.F_IDLE 0 0 0 0
fstate.F_CONVERT 0 0 1 1
fstate.F_LOAD 0 1 0 1
fstate.F_WAIT 1 0 0 1
State Machine - |top|uart_tx:u_uart|state
Name state.S_STOP state.S_D7 state.S_D6 state.S_D5 state.S_D4 state.S_D3 state.S_D2 state.S_D1 state.S_D0 state.S_START state.S_IDLE
state.S_IDLE 0 0 0 0 0 0 0 0 0 0 0
state.S_START 0 0 0 0 0 0 0 0 0 1 1
state.S_D0 0 0 0 0 0 0 0 0 1 0 1
state.S_D1 0 0 0 0 0 0 0 1 0 0 1
state.S_D2 0 0 0 0 0 0 1 0 0 0 1
state.S_D3 0 0 0 0 0 1 0 0 0 0 1
state.S_D4 0 0 0 0 1 0 0 0 0 0 1
state.S_D5 0 0 0 1 0 0 0 0 0 0 1
state.S_D6 0 0 1 0 0 0 0 0 0 0 1
state.S_D7 0 1 0 0 0 0 0 0 0 0 1
state.S_STOP 1 0 0 0 0 0 0 0 0 0 1