FPGA_LVDS_PROTOCOL_ANALYSER/db/lvds_monitor_partition_pins.json

{
	"partitions" : [
		{
			"name" : "Top",
			"pins" : [
				{
					"name" : "uart_tx_pin",
					"strict" : false
				},
				{
					"name" : "clk_50mhz",
					"strict" : false
				},
				{
					"name" : "rst_n_pin",
					"strict" : false
				},
				{
					"name" : "rx_clk",
					"strict" : false
				},
				{
					"name" : "de",
					"strict" : false
				}
			]
		}
	]
}