29 lines
12 KiB
Plaintext
29 lines
12 KiB
Plaintext
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1781075213461 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1781075213462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 10 09:06:53 2026 " "Processing started: Wed Jun 10 09:06:53 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1781075213462 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075213462 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor " "Command: quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075213462 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "14 14 " "Parallel compilation is enabled and will use 14 of the 14 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1781075213684 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de_monitor.v 1 1 " "Found 1 design units, including 1 entities, in source file de_monitor.v" { { "Info" "ISGN_ENTITY_NAME" "1 de_monitor " "Found entity 1: de_monitor" { } { { "de_monitor.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/de_monitor.v" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218864 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218864 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218866 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218867 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1781075218897 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "_unused top.v(33) " "Verilog HDL or VHDL warning at top.v(33): object \"_unused\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 33 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218900 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L0_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L0_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218900 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L1_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L1_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L2_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L2_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L3_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L3_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W0_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W0_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W1_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W1_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W2_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W2_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W3_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W3_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "de_monitor de_monitor:u_mon " "Elaborating entity \"de_monitor\" for hierarchy \"de_monitor:u_mon\"" { } { { "top.v" "u_mon" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart\"" { } { { "top.v" "u_uart" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 359 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075218903 ""}
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{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "uart_tx.v(60) " "Verilog HDL Case Statement information at uart_tx.v(60): all case item expressions in this case statement are onehot" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 60 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1781075218910 "|top|uart_tx:u_uart"}
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{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 18 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1781075219700 ""}
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{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1781075219700 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1781075220414 ""}
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{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1781075222360 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1781075222473 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075222473 ""}
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{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "vsync " "No output dependent on input pin \"vsync\"" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 26 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1781075222547 "|top|vsync"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "hsync " "No output dependent on input pin \"hsync\"" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 27 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1781075222547 "|top|hsync"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1781075222547 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "2001 " "Implemented 2001 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1781075222547 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1781075222547 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1994 " "Implemented 1994 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1781075222547 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1781075222547 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4878 " "Peak virtual memory: 4878 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:02 2026 " "Processing ended: Wed Jun 10 09:07:02 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075222558 ""}
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