Files
FPGA_LVDS_PROTOCOL_ANALYSER/db/lvds_monitor.lpc.rdb

5 lines
481 B
Plaintext
Raw Normal View History

<00> oo8Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition<6F>o<00><00>x<01>R<EFBFBD>J<EFBFBD>@<10>Z<EFBFBD>"تǞ<D8AA><13><>4
<EFBFBD>^<<3C>ń<EFBFBD><C584>Ζd<CE96><64><EFBFBD><EFBFBD><37><14><>$3y<33><79>ͼ<EFBFBD>WI <0C><><19>׼0<D7BC>~7<><37><EFBFBD><><D2A9>f<EFBFBD><66><EFBFBD><EFBFBD>w<EFBFBD><77><08><><EFBFBD>u{⣦'<1E>x<> (<28><><EFBFBD>7"V<>H<EFBFBD>6<EFBFBD>L<EFBFBD><4C><EFBFBD>Dh<44><68>B<EFBFBD><42><EFBFBD>'/<2F>:<3A><>!<21>~<03><>B<EFBFBD>ge<>S錷TH<54><12>[<5B><>*<2A><>Te<54><EFBFBD>NV<4E><56><EFBFBD>te<74><65>]<5D><>VȈ?<3F>
\l+<2B>;<3B>h-iGe<47>E<EFBFBD><1E>8<EFBFBD><38><EFBFBD>V<EFBFBD>:<3A><><EFBFBD>@<40>ݘ<EFBFBD><DD98>2<EFBFBD>@z<>+<1F><08>
C <09>s<EFBFBD>z<EFBFBD>h?q<>/<2F><><EFBFBD><EFBFBD><EFBFBD>r y<><79><EFBFBD><7F><00><>xba`d<00><><EFBFBD><1F> @<40><04><>@<1C><><14><><EFBFBD><EFBFBD><EFBFBD><1C><><01><><EFBFBD><EFBFBD>g<1E>)e<10>ʇ8:<3A><>BU13HE<><45><EFBFBD>
<EFBFBD>t<>X<08>A<EFBFBD>@T<><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0(<00>eB<65><42><EFBFBD>i<>a<EFBFBD>@<40>P<12><><EFBFBD>U <00><>