FPGA_LVDS_PROTOCOL_ANALYSER/db/lvds_monitor.hier_info

|top
clk_50mhz => clk_uart.IN1
rx_clk => rx_clk.IN1
de => de.IN1
vsync => ~NO_FANOUT~
hsync => ~NO_FANOUT~
rst_n_pin => rst_sync_uart[0].ACLR
rst_n_pin => rst_sync_uart[1].ACLR
rst_n_pin => rst_sync_uart[2].ACLR
rst_n_pin => rst_sync_pix[0].ACLR
rst_n_pin => rst_sync_pix[1].ACLR
rst_n_pin => rst_sync_pix[2].ACLR
uart_tx_pin << uart_tx:u_uart.tx


|top|de_monitor:u_mon
pix_clk => anomaly_o~reg0.CLK
pix_clk => width_o[0]~reg0.CLK
pix_clk => width_o[1]~reg0.CLK
pix_clk => width_o[2]~reg0.CLK
pix_clk => width_o[3]~reg0.CLK
pix_clk => width_o[4]~reg0.CLK
pix_clk => width_o[5]~reg0.CLK
pix_clk => width_o[6]~reg0.CLK
pix_clk => width_o[7]~reg0.CLK
pix_clk => width_o[8]~reg0.CLK
pix_clk => width_o[9]~reg0.CLK
pix_clk => width_o[10]~reg0.CLK
pix_clk => width_o[11]~reg0.CLK
pix_clk => width_o[12]~reg0.CLK
pix_clk => width_o[13]~reg0.CLK
pix_clk => width_o[14]~reg0.CLK
pix_clk => width_o[15]~reg0.CLK
pix_clk => lines_o[0]~reg0.CLK
pix_clk => lines_o[1]~reg0.CLK
pix_clk => lines_o[2]~reg0.CLK
pix_clk => lines_o[3]~reg0.CLK
pix_clk => lines_o[4]~reg0.CLK
pix_clk => lines_o[5]~reg0.CLK
pix_clk => lines_o[6]~reg0.CLK
pix_clk => lines_o[7]~reg0.CLK
pix_clk => lines_o[8]~reg0.CLK
pix_clk => lines_o[9]~reg0.CLK
pix_clk => lines_o[10]~reg0.CLK
pix_clk => lines_o[11]~reg0.CLK
pix_clk => lines_o[12]~reg0.CLK
pix_clk => lines_o[13]~reg0.CLK
pix_clk => lines_o[14]~reg0.CLK
pix_clk => lines_o[15]~reg0.CLK
pix_clk => frame_done~reg0.CLK
pix_clk => frame_active.CLK
pix_clk => gap_count[0].CLK
pix_clk => gap_count[1].CLK
pix_clk => gap_count[2].CLK
pix_clk => gap_count[3].CLK
pix_clk => gap_count[4].CLK
pix_clk => gap_count[5].CLK
pix_clk => gap_count[6].CLK
pix_clk => gap_count[7].CLK
pix_clk => gap_count[8].CLK
pix_clk => gap_count[9].CLK
pix_clk => gap_count[10].CLK
pix_clk => gap_count[11].CLK
pix_clk => gap_count[12].CLK
pix_clk => gap_count[13].CLK
pix_clk => gap_count[14].CLK
pix_clk => gap_count[15].CLK
pix_clk => line_count[0].CLK
pix_clk => line_count[1].CLK
pix_clk => line_count[2].CLK
pix_clk => line_count[3].CLK
pix_clk => line_count[4].CLK
pix_clk => line_count[5].CLK
pix_clk => line_count[6].CLK
pix_clk => line_count[7].CLK
pix_clk => line_count[8].CLK
pix_clk => line_count[9].CLK
pix_clk => line_count[10].CLK
pix_clk => line_count[11].CLK
pix_clk => line_count[12].CLK
pix_clk => line_count[13].CLK
pix_clk => line_count[14].CLK
pix_clk => line_count[15].CLK
pix_clk => any_bad_width.CLK
pix_clk => bad_width[0].CLK
pix_clk => bad_width[1].CLK
pix_clk => bad_width[2].CLK
pix_clk => bad_width[3].CLK
pix_clk => bad_width[4].CLK
pix_clk => bad_width[5].CLK
pix_clk => bad_width[6].CLK
pix_clk => bad_width[7].CLK
pix_clk => bad_width[8].CLK
pix_clk => bad_width[9].CLK
pix_clk => bad_width[10].CLK
pix_clk => bad_width[11].CLK
pix_clk => bad_width[12].CLK
pix_clk => bad_width[13].CLK
pix_clk => bad_width[14].CLK
pix_clk => bad_width[15].CLK
pix_clk => last_width[0].CLK
pix_clk => last_width[1].CLK
pix_clk => last_width[2].CLK
pix_clk => last_width[3].CLK
pix_clk => last_width[4].CLK
pix_clk => last_width[5].CLK
pix_clk => last_width[6].CLK
pix_clk => last_width[7].CLK
pix_clk => last_width[8].CLK
pix_clk => last_width[9].CLK
pix_clk => last_width[10].CLK
pix_clk => last_width[11].CLK
pix_clk => last_width[12].CLK
pix_clk => last_width[13].CLK
pix_clk => last_width[14].CLK
pix_clk => last_width[15].CLK
pix_clk => line_width[0].CLK
pix_clk => line_width[1].CLK
pix_clk => line_width[2].CLK
pix_clk => line_width[3].CLK
pix_clk => line_width[4].CLK
pix_clk => line_width[5].CLK
pix_clk => line_width[6].CLK
pix_clk => line_width[7].CLK
pix_clk => line_width[8].CLK
pix_clk => line_width[9].CLK
pix_clk => line_width[10].CLK
pix_clk => line_width[11].CLK
pix_clk => line_width[12].CLK
pix_clk => line_width[13].CLK
pix_clk => line_width[14].CLK
pix_clk => line_width[15].CLK
pix_clk => de_q.CLK
rst_n => anomaly_o~reg0.ACLR
rst_n => width_o[0]~reg0.ACLR
rst_n => width_o[1]~reg0.ACLR
rst_n => width_o[2]~reg0.ACLR
rst_n => width_o[3]~reg0.ACLR
rst_n => width_o[4]~reg0.ACLR
rst_n => width_o[5]~reg0.ACLR
rst_n => width_o[6]~reg0.ACLR
rst_n => width_o[7]~reg0.ACLR
rst_n => width_o[8]~reg0.ACLR
rst_n => width_o[9]~reg0.ACLR
rst_n => width_o[10]~reg0.ACLR
rst_n => width_o[11]~reg0.ACLR
rst_n => width_o[12]~reg0.ACLR
rst_n => width_o[13]~reg0.ACLR
rst_n => width_o[14]~reg0.ACLR
rst_n => width_o[15]~reg0.ACLR
rst_n => lines_o[0]~reg0.ACLR
rst_n => lines_o[1]~reg0.ACLR
rst_n => lines_o[2]~reg0.ACLR
rst_n => lines_o[3]~reg0.ACLR
rst_n => lines_o[4]~reg0.ACLR
rst_n => lines_o[5]~reg0.ACLR
rst_n => lines_o[6]~reg0.ACLR
rst_n => lines_o[7]~reg0.ACLR
rst_n => lines_o[8]~reg0.ACLR
rst_n => lines_o[9]~reg0.ACLR
rst_n => lines_o[10]~reg0.ACLR
rst_n => lines_o[11]~reg0.ACLR
rst_n => lines_o[12]~reg0.ACLR
rst_n => lines_o[13]~reg0.ACLR
rst_n => lines_o[14]~reg0.ACLR
rst_n => lines_o[15]~reg0.ACLR
rst_n => frame_done~reg0.ACLR
rst_n => frame_active.ACLR
rst_n => gap_count[0].ACLR
rst_n => gap_count[1].ACLR
rst_n => gap_count[2].ACLR
rst_n => gap_count[3].ACLR
rst_n => gap_count[4].ACLR
rst_n => gap_count[5].ACLR
rst_n => gap_count[6].ACLR
rst_n => gap_count[7].ACLR
rst_n => gap_count[8].ACLR
rst_n => gap_count[9].ACLR
rst_n => gap_count[10].ACLR
rst_n => gap_count[11].ACLR
rst_n => gap_count[12].ACLR
rst_n => gap_count[13].ACLR
rst_n => gap_count[14].ACLR
rst_n => gap_count[15].ACLR
rst_n => line_count[0].ACLR
rst_n => line_count[1].ACLR
rst_n => line_count[2].ACLR
rst_n => line_count[3].ACLR
rst_n => line_count[4].ACLR
rst_n => line_count[5].ACLR
rst_n => line_count[6].ACLR
rst_n => line_count[7].ACLR
rst_n => line_count[8].ACLR
rst_n => line_count[9].ACLR
rst_n => line_count[10].ACLR
rst_n => line_count[11].ACLR
rst_n => line_count[12].ACLR
rst_n => line_count[13].ACLR
rst_n => line_count[14].ACLR
rst_n => line_count[15].ACLR
rst_n => any_bad_width.ACLR
rst_n => bad_width[0].ACLR
rst_n => bad_width[1].ACLR
rst_n => bad_width[2].ACLR
rst_n => bad_width[3].ACLR
rst_n => bad_width[4].ACLR
rst_n => bad_width[5].ACLR
rst_n => bad_width[6].ACLR
rst_n => bad_width[7].ACLR
rst_n => bad_width[8].ACLR
rst_n => bad_width[9].ACLR
rst_n => bad_width[10].ACLR
rst_n => bad_width[11].ACLR
rst_n => bad_width[12].ACLR
rst_n => bad_width[13].ACLR
rst_n => bad_width[14].ACLR
rst_n => bad_width[15].ACLR
rst_n => last_width[0].ACLR
rst_n => last_width[1].ACLR
rst_n => last_width[2].ACLR
rst_n => last_width[3].ACLR
rst_n => last_width[4].ACLR
rst_n => last_width[5].ACLR
rst_n => last_width[6].ACLR
rst_n => last_width[7].ACLR
rst_n => last_width[8].ACLR
rst_n => last_width[9].ACLR
rst_n => last_width[10].ACLR
rst_n => last_width[11].ACLR
rst_n => last_width[12].ACLR
rst_n => last_width[13].ACLR
rst_n => last_width[14].ACLR
rst_n => last_width[15].ACLR
rst_n => line_width[0].ACLR
rst_n => line_width[1].ACLR
rst_n => line_width[2].ACLR
rst_n => line_width[3].ACLR
rst_n => line_width[4].ACLR
rst_n => line_width[5].ACLR
rst_n => line_width[6].ACLR
rst_n => line_width[7].ACLR
rst_n => line_width[8].ACLR
rst_n => line_width[9].ACLR
rst_n => line_width[10].ACLR
rst_n => line_width[11].ACLR
rst_n => line_width[12].ACLR
rst_n => line_width[13].ACLR
rst_n => line_width[14].ACLR
rst_n => line_width[15].ACLR
rst_n => de_q.ACLR
de => de_rise.IN1
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => line_width.OUTPUTSELECT
de => de_q.DATAIN
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => gap_count.OUTPUTSELECT
de => frame_done.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => lines_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => width_o.OUTPUTSELECT
de => anomaly_o.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => line_count.OUTPUTSELECT
de => any_bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => bad_width.OUTPUTSELECT
de => frame_active.OUTPUTSELECT
de => de_fall.IN1
frame_done <= frame_done~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[0] <= lines_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[1] <= lines_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[2] <= lines_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[3] <= lines_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[4] <= lines_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[5] <= lines_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[6] <= lines_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[7] <= lines_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[8] <= lines_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[9] <= lines_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[10] <= lines_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[11] <= lines_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[12] <= lines_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[13] <= lines_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[14] <= lines_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lines_o[15] <= lines_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[0] <= width_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[1] <= width_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[2] <= width_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[3] <= width_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[4] <= width_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[5] <= width_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[6] <= width_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[7] <= width_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[8] <= width_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[9] <= width_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[10] <= width_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[11] <= width_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[12] <= width_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[13] <= width_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[14] <= width_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
width_o[15] <= width_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
anomaly_o <= anomaly_o~reg0.DB_MAX_OUTPUT_PORT_TYPE


|top|uart_tx:u_uart
clk => busy~reg0.CLK
clk => tx~reg0.CLK
clk => shift[0].CLK
clk => shift[1].CLK
clk => shift[2].CLK
clk => shift[3].CLK
clk => shift[4].CLK
clk => shift[5].CLK
clk => shift[6].CLK
clk => shift[7].CLK
clk => tick[0].CLK
clk => tick[1].CLK
clk => tick[2].CLK
clk => tick[3].CLK
clk => tick[4].CLK
clk => tick[5].CLK
clk => tick[6].CLK
clk => tick[7].CLK
clk => tick[8].CLK
clk => state~12.DATAIN
rst_n => busy~reg0.ACLR
rst_n => tx~reg0.PRESET
rst_n => shift[0].ACLR
rst_n => shift[1].ACLR
rst_n => shift[2].ACLR
rst_n => shift[3].ACLR
rst_n => shift[4].ACLR
rst_n => shift[5].ACLR
rst_n => shift[6].ACLR
rst_n => shift[7].ACLR
rst_n => tick[0].ACLR
rst_n => tick[1].ACLR
rst_n => tick[2].ACLR
rst_n => tick[3].ACLR
rst_n => tick[4].ACLR
rst_n => tick[5].ACLR
rst_n => tick[6].ACLR
rst_n => tick[7].ACLR
rst_n => tick[8].ACLR
rst_n => state~14.DATAIN
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => shift.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => busy.DATAB
start => tx.DATAB
data[0] => shift.DATAB
data[1] => shift.DATAB
data[2] => shift.DATAB
data[3] => shift.DATAB
data[4] => shift.DATAB
data[5] => shift.DATAB
data[6] => shift.DATAB
data[7] => shift.DATAB
tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
busy <= busy~reg0.DB_MAX_OUTPUT_PORT_TYPE