Files
FPGA_LVDS_PROTOCOL_ANALYSER/db/lvds_monitor.(13).cnf.hdb

5 lines
906 B
Plaintext
Raw Normal View History

<00> oo8Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition<6F> <00>v<00>x<01>V;O<>0 <0C>%^b<00><>!10s<1C><><EFBFBD>XY*T<1D><07><>-<2D><><EFBFBD><EFBFBD> ;><3E>Ҧn<16><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ű<1D><><EFBFBD> <0C> <0C><53><DC97><EFBFBD><EFBFBD>*<15>:<3A>m} <0B><><EFBFBD><EFBFBD><EFBFBD>0I<30>(<19>i<EFBFBD>
<EFBFBD>I<11><19><><EFBFBD><EFBFBD>k<EFBFBD><6B>Q<EFBFBD><51><EFBFBD><EFBFBD><EFBFBD>x%A<>m<EFBFBD><6D>`<60><><EFBFBD>D<>~<7E><1B>a<EFBFBD>@<40>3<EFBFBD>4<EFBFBD>}<7D><><01>K<EFBFBD><4B><EFBFBD>cM<03><>j.<2E><07>" <0A>i<EFBFBD>e1n<15>4<>&gL=ˍ<0E><><EFBFBD>,K<><4B>ܘ˕|1(8<00>.<2E><><EFBFBD><EFBFBD><EFBFBD>~=g^<5E><><EFBFBD>A8q<11>.™<>p<EFBFBD>"+ŽŕCO1<4F><31>/<1D>/z
@<40>O)<29><><EFBFBD><EFBFBD>(<28><>|<7C>DY<44>S<EFBFBD>[U<>O<EFBFBD>G<0E><10>*<2A>X<10>`B <1F>ӍU<D38D>D<>)s<>K<EFBFBD>7((<28><><EFBFBD>($<<3C><>5<EFBFBD><35>&P<>
ʞm<EFBFBD><EFBFBD><EFBFBD>Ʃ<EFBFBD>l<EFBFBD><EFBFBD><EFBFBD>q<EFBFBD><EFBFBD><EFBFBD>i[m<>BF<42>~<7E>1G6_<36><5F><02><><EFBFBD>9L<04><>ی Ծ<>U<>X <0C><><00><>ڣ4<DAA3><10><><EFBFBD><76><1E>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>7v<><76>t<EFBFBD>0<18>9<13>QL޲|<7C>*<2A>ȬY<C8AC><59> kq<6B><1F><1D>v<17><>.<2E><>`!m<><6D><EFBFBD><EFBFBD>٘%He<48>U<EFBFBD>'<27><>G1vT<76>?Ij;<3B><17>ڣyml,<2C><>se<73>ĝď<C49D>n<EFBFBD><6E><EFBFBD><EFBFBD><EFBFBD><08>C<EFBFBD>-zJ<7A>oc<6F>(1=<1F><><EFBFBD><00><>x<01>d`d<>```8\X<><58><08><><EFBFBD>X<08><><EFBFBD><EFBFBD><EFBFBD>}<7D><>C<<3C><> <0C><>&<01>p<EFBFBD>v<EFBFBD>3} m<><6D><EFBFBD><EFBFBD>58<35><38><EFBFBD>5<EFBFBD><35>/$(<28><>A(<28>3Rk.;<3B><>bQ <06><><1E>U<><02><>~u<>V<EFBFBD>*N <20><><EFBFBD> p
<06>4/>8$<24><><EFBFBD>b4+<2B>P<><50><EFBFBD><EFBFBD>0<EFBFBD>J<01>N<EFBFBD><4E><EFBFBD><11><1E><>A<EFBFBD>A<EFBFBD><1E><><01>A!<21><>~n<>l`<60>U<>H <17><>XY<15>e楳<65>}<7D><><EFBFBD>'<27><>`<1F>i<>`w<>ǃ<EFBFBD>=\}94<><12><><EFBFBD>K@^<07>$ U<18><11><><EFBFBD><13>/<2F><><16>3<EFBFBD><33><EFBFBD>=]<5D>^<5E>t:<00><>