114 lines
18 KiB
HTML
114 lines
18 KiB
HTML
<!DOCTYPE html>
|
||
<html lang="en">
|
||
<head>
|
||
<meta charset="UTF-8">
|
||
<title>MIPI Analysis — Captures 0303–0332</title>
|
||
<style>
|
||
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
|
||
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
|
||
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
|
||
p { line-height: 1.6; }
|
||
ol, ul { line-height: 1.8; padding-left: 24px; }
|
||
li { margin: 4px 0; }
|
||
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
|
||
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
|
||
padding: 16px 20px; margin-bottom: 28px; }
|
||
.flicker-alert h2 { color: #e65100; margin-top: 0; }
|
||
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
|
||
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
|
||
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
|
||
table { border-collapse: collapse; width: 100%; }
|
||
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
|
||
td { border: 1px solid #ddd; padding: 5px 10px; }
|
||
@media print { body { margin: 20px; } }
|
||
</style>
|
||
</head>
|
||
<body>
|
||
<h1>MIPI D-PHY Analysis Report</h1>
|
||
|
||
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
|
||
padding:16px 20px;margin-bottom:28px;">
|
||
<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 6 of 30 display load sessions (20%) flickered</h2>
|
||
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
|
||
pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
|
||
missed the SoT sequence and dropped a frame.<br>
|
||
LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
|
||
for the SN65DSI83 bridge to detect start-of-transmission.</p>
|
||
<table>
|
||
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
|
||
<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
|
||
<tr><td>0304</td><td>20260409_132523</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>0308</td><td>20260409_132650</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.1 ns</td><td>1.015 V</td></tr><tr><td>0315</td><td>20260409_132922</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.8 ns</td><td>1.016 V</td></tr><tr><td>0318</td><td>20260409_133028</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.015 V</td></tr><tr><td>0324</td><td>20260409_133238</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.2 ns</td><td>1.014 V</td></tr><tr><td>0328</td><td>20260409_133406</td><td>dat</td><td style='color:red'>None ns</td><td>None ns</td><td>1.014 V</td></tr>
|
||
</table>
|
||
</div>
|
||
|
||
<details style="margin-bottom:24px;">
|
||
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
|
||
DSI Register Snapshots (30 captures)
|
||
</summary>
|
||
<div style="overflow-x:auto;margin-top:8px;">
|
||
<table>
|
||
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
|
||
<tr><td>0303</td><td>20260409_132501</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0304</td><td>20260409_132523</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0305</td><td>20260409_132545</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260409_132607</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260409_132628</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260409_132650</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260409_132712</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260409_132733</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260409_132755</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260409_132817</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260409_132839</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260409_132901</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260409_132922</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260409_132944</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260409_133006</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260409_133028</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260409_133049</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260409_133111</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260409_133133</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260409_133155</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260409_133217</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260409_133238</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260409_133300</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260409_133322</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260409_133344</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260409_133406</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260409_133428</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260409_133449</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260409_133511</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260409_133533</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
|
||
</table>
|
||
</div>
|
||
</details>
|
||
<p class="meta">
|
||
<strong>Generated:</strong> 2026-04-09 13:40:13 |
|
||
<strong>Scope:</strong> Captures 0303–0332 |
|
||
<strong>Model:</strong> claude-opus-4-6
|
||
</p>
|
||
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0303–0332</p>
|
||
<p>## 1. Root Cause Identification</p>
|
||
<p>### The Smoking Gun: Register Mismatch vs. Target</p>
|
||
<p>Every single capture shows the <strong>same wrong register values</strong>:</p>
|
||
<p>| Register | Target (compliant) | Actual (all captures) | Impact |<br>|---|---|---|---|<br>| <strong>PHYTIMING (0xb4)</strong> | `0x00000306` | `0x00000305` | <strong>THS_EXIT=5 → 92.6 ns</strong> (spec ≥100 ns) ✗ |<br>| <strong>PHYTIMING1 (0xb8)</strong> | `0x03110A04` | `0x020e0a03` | <strong>TCLK_PREPARE=2 → 37 ns</strong> (spec 38–95 ns) ✗; <strong>TCLK_ZERO=14 → 259 ns</strong> (spec ≥300 ns) ✗; <strong>TCLK_TRAIL=3 → 55.6 ns</strong> (spec ≥60 ns) ✗ |<br>| <strong>PHYTIMING2 (0xbc)</strong> | `0x00040A03` | `0x00030605` | <strong>THS_PREPARE=5 → 92.6 ns</strong> (spec 40+4×UI=49.3–85+6×UI=98.9 ns) — marginal high; <strong>THS_ZERO=6 → 111 ns</strong> (spec ≥145+10×UI=168.2 ns) ✗✗✗; <strong>THS_TRAIL=3 → 55.6 ns</strong> (spec max(8×UI,60ns+4×UI)=69.3 ns) ✗ |</p>
|
||
<p><strong>The driver is programming the wrong timing values.</strong> The samsung-dsim driver's timing calculation algorithm is producing values that violate MIPI D-PHY v1.1 for this 432 Mbit/s bit rate. This is the primary root cause.</p>
|
||
<p>### Critical Violations Directly Causing Flicker</p>
|
||
<p><strong>THS_ZERO = 6 (111 ns) vs. spec minimum 168 ns</strong> — This is the most severe violation. THS_ZERO defines the duration of the HS-0 state in the data lane SoT sequence (LP-11 → LP-01 → LP-00 → HS-0 → data). At 111 ns, it is <strong>34% below the minimum</strong>. The SN65DSI83 bridge must detect this HS-0 period to synchronize its deserializer. When the PHY's internal timing jitter causes the HS-0 to be even shorter than the already-too-short programmed value, the bridge fails to lock — producing the observed bistable behavior.</p>
|
||
<p><strong>TCLK_ZERO = 14 (259 ns) vs. spec minimum 300 ns</strong> — The clock lane's HS-0 initialization is also too short. The bridge may not have a stable clock reference established before data lane SoT arrives.</p>
|
||
<p>### Why It's Intermittent (20% Failure Rate)</p>
|
||
<p>The LP-low plateau measurement shows a <strong>trimodal distribution</strong>:<br>- <strong>~343 ns</strong> — 14 captures (good sessions, bridge locks)<br>- <strong>~108 ns</strong> — 9 captures (good sessions, bridge locks — barely)<br>- <strong>0 ns</strong> — 5 captures (<strong>all</strong> confirmed flicker sessions: 0304, 0308, 0315, 0318, 0324)<br>- <strong>1 capture (0328)</strong> — no measurable LP-low, split HS bursts, confirmed flicker</p>
|
||
<p>The correlation is <strong>perfect</strong>: every capture with LP-low = 0 ns produced flicker. The PHY's SoT state machine timing is racing against internal PLL lock and clock distribution. With THS_ZERO programmed 57 ns below spec minimum, there is zero margin. On ~20% of startups, internal timing variation causes the LP-00/HS-0 states to collapse entirely, producing a degenerate SoT that the SN65DSI83 cannot detect.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 2. Trend Analysis Across All 30 Captures</p>
|
||
<p>### HS Signal Quality — Stable, No Degradation<br>| Parameter | Range | Trend |<br>|---|---|---|<br>| CLK Vdiff | 175.4–177.9 mV | Rock-steady, no drift |<br>| DAT Vdiff | 177.5–223.2 mV | Stable (222 mV outlier in 0322 likely capture artifact) |<br>| CLK jitter p-p | 94.8–149.6 ps | Random variation, no trend |<br>| CLK jitter RMS | 25.6–29.7 ps | Stable |<br>| Rise times | 133.8–153.4 ps | Stable, well within spec |<br>| Clock frequency | 215.82–216.12 MHz | ±0.1%, excellent |</p>
|
||
<p><strong>HS signal quality is not the problem.</strong> Once HS mode is established, the link runs perfectly — consistent with the observed bistable behavior.</p>
|
||
<p>### LP-11 Voltage — Stable But Low<br>- Range: <strong>1.014–1.016 V</strong> across all captures<br>- MIPI D-PHY spec: VIH(LP) > 880 mV at receiver; transmitter spec is VDDIO × 0.55 to VDDIO<br>- At VDDIO = 1.8 V: expected LP-high ≈ 1.08–1.2 V typical<br>- Measured <strong>1.015 V is 56% of VDDIO</strong> — at the absolute floor of the transmitter output spec<br>- <strong>Not causing the flicker</strong> (SN65DSI83 VIH threshold is ~880 mV, so 1.015 V is detected), but indicates the LP driver is marginally biased, possibly related to the same timing register misconfiguration affecting LP driver enable timing.</p>
|
||
<p>### 1.8 V Supply — Healthy, Not Correlated<br>| Parameter | Range |<br>|---|---|<br>| Mean | 1.7631–1.7685 V |<br>| Min | 1.7480–1.7600 V |<br>| Droop | 7.1–16.2 mV |<br>| Ripple RMS | 4.89–5.70 mV |</p>
|
||
<p><strong>No correlation between supply droop and flicker events:</strong><br>- Flicker capture 0304: droop 8.0 mV (below average)<br>- Flicker capture 0324: droop 8.3 mV (average)<br>- Good capture 0321: droop 15.6 mV (worst in batch)<br>- Good capture 0330: droop 16.2 mV (worst in batch)</p>
|
||
<p>The supply is healthy and not a contributing factor.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 3. Anomaly Flags</p>
|
||
<p>### A. LP-Low Plateau Absent on All Flicker Captures<br>| Capture | LP-low (ns) | Flicker? | LP exit→HS (ns) |<br>|---|---|---|---|<br>| 0304 | <strong>0</strong> | <strong>YES</strong> | 2 |<br>| 0308 | <strong>0</strong> | <strong>YES</strong> | 3 |<br>| 0315 | <strong>0</strong> | <strong>YES</strong> | 4 |<br>| 0318 | <strong>0</strong> | <strong>YES</strong> | 2 |<br>| 0324 | <strong>0</strong> | <strong>YES</strong> | 2 |<br>| 0328 | <strong>N/A</strong> | <strong>YES</strong> | N/A |<br>| 0303 | 343 | no | 3 |<br>| 0325 | 342 | no | 348 ✓ |<br>| 0331 | 343 | no | 348 ✓ |</p>
|
||
<p>Note: Captures 0325 and 0331 are the <strong>only</strong> two captures where `LP exit → HS` was measured at a spec-compliant 348 ns. These represent the PHY "getting lucky" with internal timing — the same registers produce wildly different observable timing on the wire.</p>
|
||
<p>### B. Capture 0328 — Severely Degenerate SoT<br>- <strong>Two HS bursts</strong> (avg 2508 ns each) instead of the normal single 5020 ns burst — the bridge attempted and failed to sync, causing the PHY to re-try<br>- <strong>HS amplitude 3 mV</strong> — essentially no HS signal detected on data lane<br>- <strong>sig/dat: 0 mV</strong> — DAT0 never entered HS properly<br>- This is the most severe flicker event: the SoT was so badly malformed that the data lane never achieved HS at all during the capture window</p>
|
||
<p>### C. Systematic "Only Negative Swings" on sig/dat<br>Approximately 70% of captures show only negative differential swings on the data lane high-res capture. This is a <strong>probe/trigger alignment artifact</strong> — the scope is capturing during blanking intervals where the data lane transmits a consistent pattern. Not a signal integrity concern.</p>
|
||
<p>### D. Samples Below 140 mV — Data Lane ISI<br>The proto/dat captures consistently show 82–10,171 samples below 140 mV minimum Vdiff. This is <strong>inter-symbol interference (ISI)</strong> during transitions between different bit patterns at 432 Mbit/s. The clock lane (which has a fixed 50/50 pattern) shows far fewer violations. This is a board-level impedance/termination concern but is <strong>not correlated with flicker</strong> — it affects eye margin during sustained HS, not SoT detection.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 4. Supply Correlation Assessment</p>
|
||
<p><strong>No correlation exists.</strong> Statistical analysis:<br>- Flicker events droop: 7.1, 8.0, 8.3, 8.4, 8.5, 9.0 mV (mean 8.4 mV)<br>- Good events droop: 7.5–16.2 mV (mean 8.8 mV)<br>- Ripple RMS is virtually identical across all captures (4.89–5.70 mV)</p>
|
||
<p>The 1.8 V supply is not the trigger. The root cause is entirely in the PHY timing registers.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 5. Warning/Error Explanations</p>
|
||
<p>| Warning | Cause | Action |<br>|---|---|---|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>THS_PREPARE + THS_ZERO too short in registers</strong> — PHY collapses LP→HS states | Fix PHYTIMING registers |<br>| `CLK lane in continuous HS mode` | Normal for Video Mode DSI — CLK runs HS continuously | None needed |<br>| `Only negative swings in capture window` | Scope triggered during blanking line with constant pattern | Benign — adjust trigger for mixed patterns if needed |<br>| `No HS signal detected` (sig/dat, captures 0311, 0315, 0323, 0328) | Scope captured during LP or V-blank gap | Benign for 0311/0323; for 0315/0328 (flicker), DAT never entered HS properly |<br>| `Settled samples below 140 mV` | ISI on data transitions; impedance mismatch on PCB | Review termination; not flicker root cause |<br>| `[lp_dat] ERROR: index out of bounds` (0312) | Processing script edge case — LP capture truncated | Improve script bounds checking |</p>
|
||
<ul><li></li></ul>
|
||
<p>## 6. Actionable Recommendations</p>
|
||
<p>### PRIORITY 1 — Fix PHY Timing Registers (Root Cause)</p>
|
||
<p>The samsung-dsim driver is computing wrong values for 432 Mbit/s. Apply the target values via one of:</p>
|
||
<p><strong>Option A: Device Tree override (preferred, no kernel rebuild)</strong><br>```dts<br>&mipi_dsi {<br> samsung,phy-timing = <0x00000306>;<br> samsung,phy-timing1 = <0x03110a04>;<br> samsung,phy-timing2 = <0x00040a03>;<br>};<br>```</p>
|
||
<p><strong>Option B: Kernel driver patch</strong> — Fix the `samsung_dsim_set_phy_timing()` calculation in `drivers/gpu/drm/bridge/samsung-dsim.c`. The current algorithm underestimates multiple fields at this bit rate. Specific field corrections needed:</p>
|
||
<p>| Field | Current | Required | Byte-clock units |<br>|---|---|---|---|<br>| THS_EXIT | 5 | <strong>6</strong> | +1 |<br>| TCLK_PREPARE | 2 | <strong>3</strong> | +1 |<br>| TCLK_ZERO | 14 (0x0e) | <strong>17 (0x11)</strong> | +3 |<br>| TCLK_TRAIL | 3 | <strong>4</strong> | +1 |<br>| THS_ZERO | 6 | <strong>10 (0x0a)</strong> | +4 ← <strong>critical</strong> |<br>| THS_TRAIL | 3 | <strong>4</strong> | +1 |<br>| THS_PREPARE | 5 | <strong>3</strong> | −2 (currently over-counting) |</p>
|
||
<p>### PRIORITY 2 — Add Margin to THS_ZERO</p>
|
||
<p>Even the target value of THS_ZERO=10 (185 ns) provides only 10% margin over the 168 ns spec minimum. For a bridge chip with known sensitivity, consider:<br>```<br>THS_ZERO = 12 → 222 ns (32% margin)<br>```<br>This eliminates the intermittent SoT failure entirely at the cost of ~37 ns added latency per line — negligible.</p>
|
||
<p>### PRIORITY 3 — Investigate LP-11 Voltage</p>
|
||
<p>LP-11 at 1.015 V (56% of 1.8 V VDDIO) is lower than typical (~65–70%). Check:<br>- Series resistors on LP lines (some designs add 200–300 Ω for ESD; verify values)<br>- SN65DSI83 input termination bias — it may be loading the LP drivers<br>- VDDIO accuracy at the PHY pins (not just at the regulator output)</p>
|
||
<p>### PRIORITY 4 — PCB Signal Integrity for ISI</p>
|
||
<p>The persistent below-140 mV samples on the data lane suggest impedance mismatch. For future board revisions:<br>- Verify 100 Ω differential impedance on MIPI traces<br>- Check connector stub length if using FPC<br>- Add/verify 100 Ω differential termination at SN65DSI83 inputs</p>
|
||
<ul><li></li></ul>
|
||
<p>## 7. Overall Assessment</p>
|
||
<p><strong>The flicker root cause is definitively identified: the samsung-dsim PHY timing registers are programmed with values that violate MIPI D-PHY v1.1 minimum timing on six of seven critical parameters, most severely THS_ZERO (111 ns vs. 168 ns minimum).</strong> This causes the data lane SoT sequence to be too short for the SN65DSI83 to reliably detect, producing a 20% failure rate at pipeline startup that manifests as the observed bistable flicker behavior. The 1.8 V supply, HS signal quality, and LP-11 voltage are not contributing factors.</p>
|
||
<p><strong>Correcting the three PHYTIMING registers to their target values will eliminate the flicker.</strong> The fix is a single device-tree or driver change with no hardware modification required. Adding extra margin to THS_ZERO (value 12 instead of 10) is recommended given the bridge chip's sensitivity and the observed zero-margin failure mode.</p>
|
||
<p class="tokens">Tokens: 33977 in / 3728 out</p>
|
||
</body>
|
||
</html>
|