124 lines
19 KiB
HTML
124 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0472–0501</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert h2 { color: #e65100; margin-top: 0; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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table { border-collapse: collapse; width: 100%; }
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th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 6 of 30 display load sessions (20%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0475</td><td>20260410_095610</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.4 ns</td><td>1.015 V</td></tr><tr><td>0476</td><td>20260410_095632</td><td>dat</td><td style='color:red'>0.2 ns</td><td>1.4 ns</td><td>1.016 V</td></tr><tr><td>0487</td><td>20260410_100030</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.5 ns</td><td>1.017 V</td></tr><tr><td>0489</td><td>20260410_100114</td><td>dat</td><td style='color:red'>0.2 ns</td><td>0.8 ns</td><td>1.016 V</td></tr><tr><td>0490</td><td>20260410_100135</td><td>dat</td><td style='color:red'>0.3 ns</td><td>1.2 ns</td><td>1.016 V</td></tr><tr><td>0501</td><td>20260410_100533</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.1 ns</td><td>1.017 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0472</td><td>20260410_095505</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0473</td><td>20260410_095527</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0474</td><td>20260410_095549</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0475</td><td>20260410_095610</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0476</td><td>20260410_095632</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0477</td><td>20260410_095654</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0478</td><td>20260410_095716</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0479</td><td>20260410_095737</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0480</td><td>20260410_095759</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0481</td><td>20260410_095820</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0482</td><td>20260410_095842</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0483</td><td>20260410_095904</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0484</td><td>20260410_095925</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0485</td><td>20260410_095947</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0486</td><td>20260410_100009</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0487</td><td>20260410_100030</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0488</td><td>20260410_100052</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0489</td><td>20260410_100114</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0490</td><td>20260410_100135</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0491</td><td>20260410_100157</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0492</td><td>20260410_100218</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0493</td><td>20260410_100240</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0494</td><td>20260410_100302</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0495</td><td>20260410_100323</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0496</td><td>20260410_100345</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0497</td><td>20260410_100406</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0498</td><td>20260410_100428</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0499</td><td>20260410_100449</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0500</td><td>20260410_100511</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0501</td><td>20260410_100533</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-10 10:10:15 |
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<strong>Scope:</strong> Captures 0472–0501 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0472–0501</p>
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<ul><li></li></ul>
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<p>## 1. Register Mismatch: The Primary Root Cause</p>
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<p>### Actual vs. Target Registers</p>
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<p>| Register | Target | Actual (all captures) | Impact |<br>|---|---|---|---|<br>| <strong>PHYTIMING (0xb4)</strong> | `0x00000306` | `0x00000305` | <strong>THS_EXIT=5 → 92.6 ns</strong> (spec ≥100 ns) <strong>✗</strong> |<br>| <strong>PHYTIMING1 (0xb8)</strong> | `0x03110A04` | `0x020e0a03` | <strong>TCLK_PREPARE=2→37 ns</strong> (spec 38–95 ns) <strong>✗</strong>, <strong>TCLK_ZERO=14→259 ns</strong> (spec ≥300 ns) <strong>✗</strong>, TCLK_TRAIL=3→55.6 ns (spec ≥60 ns) <strong>✗</strong> |<br>| <strong>PHYTIMING2 (0xbc)</strong> | `0x00040A03` | `0x00030605` | <strong>THS_PREPARE=5→92.6 ns</strong> (spec 40+4×UI=49.3–85+6×UI=98.9 ns) borderline, <strong>THS_ZERO=6→111 ns</strong> (spec ≥145+10×UI=168 ns) <strong>✗ SEVERE</strong>, THS_TRAIL=3→55.6 ns (spec ≥max(8×UI,60ns+4×UI)=69.3 ns) <strong>✗</strong> |</p>
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<p><strong>Every single capture shows the WRONG register values.</strong> The target values (documented as MIPI D-PHY v1.1 compliant) are not being programmed. The samsung-dsim driver is computing its own timing values and overriding the device-tree or platform settings. This is the <strong>systemic defect</strong> underlying the flicker.</p>
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<p>### Critical Field: THS_ZERO = 6 → 111 ns (needs ≥168 ns)</p>
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<p>THS_ZERO controls how long the data lane transmitter holds LP-00 before driving HS-0. At 111 ns, it is <strong>34% below the D-PHY v1.1 minimum of 168 ns</strong>. The SN65DSI83 receiver must detect the LP-00 state to recognise Start-of-Transmission. With THS_ZERO this short, the LP-00 plateau is a <strong>race condition</strong>: some startups catch it, some don't.</p>
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<p>This directly explains:<br>- The <strong>bistable behaviour</strong> (SoT detected → good; SoT missed → stuck bad)<br>- The <strong>~20% failure rate</strong> (the LP-00 window is short enough that receiver sampling jitter and internal delays occasionally miss it)<br>- The <strong>non-correlation with supply, temperature, or ongoing conditions</strong> (it's a one-shot timing race at SoT)</p>
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<ul><li></li></ul>
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<p>## 2. LP Timing Analysis: Flicker vs. Non-Flicker Captures</p>
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<p>### LP-Low Plateau Distribution</p>
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<p>| LP-low plateau | Captures (no flicker) | Captures (FLICKER) |<br>|---|---|---|<br>| <strong>~342–343 ns</strong> | 0472, 0474, 0477, 0479, 0480, 0481, 0488, 0491, 0492, 0493, 0495, 0497, 0498, 0499 | 0487 (reported 0 ns — likely mismeasured) |<br>| <strong>~108 ns</strong> | 0478, 0482, 0483, 0486, 0496, 0500 | — |<br>| <strong>0 ns (absent)</strong> | — | <strong>0475, 0476, 0489, 0490, 0501</strong> |</p>
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<p><strong>Perfect correlation</strong>: All 6 flicker captures show LP-low plateau = 0 ns (absent) or anomalously short. The LP-00 state required for SoT detection is either completely missing or too brief for the SN65DSI83 to sample.</p>
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<p>### Bimodal Plateau Distribution (Non-Flicker)</p>
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<p>The non-flicker captures cluster at two values:<br>- <strong>~342 ns</strong> (~18.5 byte-clocks): Consistent with the PHY executing the programmed THS_ZERO + THS_PREPARE sequence at full duration<br>- <strong>~108 ns</strong> (~5.8 byte-clocks): Consistent with THS_ZERO=6 (111 ns) — the actual programmed value</p>
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<p>The 342 ns group likely reflects additional PHY setup overhead or a different internal state machine path. The 108 ns group matches the (too-short) register value. <strong>Both work only because the SN65DSI83 happens to catch the LP-00 → HS transition. The 0 ns group represents cases where the PHY skipped or collapsed the LP-00 state entirely.</strong></p>
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<p>### LP Exit Duration</p>
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<p><strong>Every capture</strong> (except 0478, 0479, 0482, 0494) shows LP exit → HS of 0–4 ns — far below the 50 ns TLPX minimum. This means the LP-01 intermediate state (required before LP-00) is essentially absent. The PHY is transitioning from LP-11 directly to LP-00/HS-0 without a properly resolved LP-01 step.</p>
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<p>This is consistent with <strong>TLPX=5</strong> in the actual register (0xb4 field), which is 92.6 ns and should be adequate. However, the measurement of "LP exit → HS" at 0–4 ns suggests the <strong>Dp line</strong> is not cleanly stepping through LP-01 before LP-00. This could be:<br>- The probe is on Dn (not Dp), so LP-01 (Dp=high, Dn=low) looks like the start of LP-00<br>- Or the PHY is genuinely collapsing LP-01 due to the short THS_PREPARE/THS_ZERO chain</p>
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<ul><li></li></ul>
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<p>## 3. HS Signal Quality Assessment</p>
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<p>### Consistent Characteristics (Stable Across All Captures)</p>
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<p>| Parameter | CLK Lane | DAT0 Lane | Spec | Status |<br>|---|---|---|---|---|<br>| Vdiff amplitude | 165–167 mV | 186–198 mV | 140–270 mV | ✓ marginal on CLK |<br>| Common mode | +27–30 mV | −6 to +5 mV | ±25 mV (spec varies) | CLK borderline |<br>| Rise time 20-80% | 164–165 ps | 153–185 ps | 150 ps min | ✓ |<br>| Jitter p-p | 141–174 ps | — | <0.35 UI (811 ps) | ✓ |<br>| Jitter RMS | 50–56 ps | — | — | acceptable |</p>
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<p><strong>No amplitude drift or degradation trend</strong> across the 30 captures. HS signal quality is stable and adequate.</p>
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<p>### CLK Lane Asymmetry</p>
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<p>Consistently: Vpos ≈ +194 mV, Vneg ≈ −137 mV. The <strong>30 mV positive common-mode offset</strong> on CLK is near the edge of spec. This is a PCB/termination asymmetry, not a flicker cause, but should be investigated for long-term reliability.</p>
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<p>### Sub-140 mV Samples</p>
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<p>Data lane shows 46–4946 samples below 140 mV across captures. This correlates with <strong>data pattern content</strong> (transitions through zero-crossing), not with flicker. The high counts (2000–5000) appear in captures with certain data patterns. Not a root cause concern at this bit rate.</p>
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<ul><li></li></ul>
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<p>## 4. Supply Rail Correlation</p>
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<p>### 1.8V VDDIO During LP→HS Transition</p>
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<p>| Parameter | Range | Spec | Status |<br>|---|---|---|---|<br>| Mean | 1.7644–1.7706 V | 1.71–1.89 V | ✓ (2% low of nominal) |<br>| Min | 1.7480–1.7600 V | ≥1.71 V | ✓ |<br>| Droop | 8.4–17.8 mV | — | acceptable |<br>| Ripple RMS | 5.49–6.20 mV | — | acceptable |</p>
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<p><strong>No supply correlation with flicker.</strong> Specifically:<br>- Flicker capture 0487: droop 17.8 mV (highest in set) — but non-flicker capture 0484 also shows 17.3 mV droop with no flicker<br>- Flicker captures 0475, 0476, 0490, 0501: droop 9.8–10.5 mV — identical to many non-flicker captures<br>- LP-11 voltage is rock-stable at 1.015–1.017 V across all captures (flicker and non-flicker)</p>
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<p><strong>The supply is not the cause.</strong> The 1.8V rail is clean and stable during the LP→HS transition. The LP driver voltage is well within spec. The failure mechanism is purely timing-based.</p>
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<ul><li></li></ul>
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<p>## 5. ERROR/WARNING Explanation</p>
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<p>| Message | Captures | Cause | Action |<br>|---|---|---|---|<br>| `lp_dat ERROR: index 200000 out of bounds` | 0473, 0484, 0485 | Capture window ended before LP→HS transition completed; trigger timing placed the SoT at the very end of the acquisition buffer | Increase post-trigger depth or shift trigger offset. Not a hardware issue. |<br>| `No HS signal detected` on DAT0 sig | 0485, 0486, 0487, 0489, 0501 | Scope trigger captured a blanking interval or the data lane was in LP-idle during the high-res capture window | Non-actionable — sig captures are short windows and may miss active HS. The proto captures confirm HS is present. |<br>| `Only negative swings in capture window` | Most captures | The high-res sig window caught the DAT0 lane during a run of identical bit values (all-zero data). Normal for short captures on data lanes. | Non-actionable. |<br>| `CLK lane in continuous HS mode` | All captures | CLK is in continuous clock mode (expected for SN65DSI83 which requires continuous clock). LP transitions occur only on data lanes. | Correct behaviour. |<br>| `LP exit duration X ns below spec min 50 ns` | Most captures | THS_PREPARE + TLPX timing too short, or measurement artifact from probe placement (see Section 2). | Fix register values. |</p>
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<ul><li></li></ul>
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<p>## 6. Actionable Recommendations</p>
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<p>### IMMEDIATE FIX — Priority 1: Correct PHY Timing Registers</p>
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<p>The samsung-dsim driver is <strong>not applying the target register values</strong>. Force the correct values:</p>
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<p>```<br>PHYTIMING (0xb4) = 0x00000306 → TLPX=3 (55.6ns), THS_EXIT=6 (111ns)<br>PHYTIMING1 (0xb8) = 0x03110A04 → TCLK_PREPARE=3 (55.6ns), TCLK_ZERO=17 (315ns), <br> TCLK_POST=10 (185ns), TCLK_TRAIL=4 (74ns)<br>PHYTIMING2 (0xbc) = 0x00040A03 → THS_TRAIL=4 (74ns), THS_ZERO=10 (185ns), <br> THS_PREPARE=3 (55.6ns)<br>```</p>
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<p><strong>The single most critical change is THS_ZERO: 6→10</strong> (111 ns → 185 ns). This gives the SN65DSI83 a proper 185 ns LP-00 window to detect SoT, with 17 ns of margin above the 168 ns D-PHY minimum.</p>
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<p><strong>Implementation options</strong> (in order of preference):</p>
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<ol><li><strong>Device tree override</strong>: Use `samsung,phy-timing` property if the samsung-dsim driver supports it. Check `samsung,dsim-phy-timing` or `phy-timing-*` bindings in the driver.</li></ol>
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<ol><li><strong>Driver patch</strong>: In `samsung_dsim_set_phy_timing()` (or equivalent), override the auto-calculated values with hardcoded constants for the 432 Mbit/s operating point. The auto-calculation is clearly producing sub-spec values.</li></ol>
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<ol><li><strong>Runtime memtool workaround</strong> (for validation only):</li><li>```bash</li><li># After DSI init but before display enable:</li><li>memtool mw -l 0x32e100b4=0x00000306</li><li>memtool mw -l 0x32e100b8=0x03110A04</li><li>memtool mw -l 0x32e100bc=0x00040A03</li><li>```</li><li><strong>Warning</strong>: This is fragile — the driver may re-program registers during enable. Use only to confirm the fix works.</li></ol>
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<p>### Priority 2: Investigate Driver Auto-Calculation</p>
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<p>The samsung-dsim driver computes PHY timing from the HS clock rate. At 432 Mbit/s the computation produces:<br>- THS_ZERO=6 instead of 10 (off by 4 byte-clocks = 74 ns)<br>- TCLK_ZERO=14 instead of 17 (off by 3 byte-clocks = 56 ns)<br>- TCLK_PREPARE=2 instead of 3 (off by 1 byte-clock = 18.5 ns)<br>- Multiple trail parameters off by 1</p>
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<p>This suggests the driver formula uses <strong>floor rounding instead of ceiling</strong>, or the base constants are wrong for the D-PHY v1.1 spec. File a bug against the `sec-dsim`/`samsung-dsim` driver with these specific field comparisons.</p>
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<p>### Priority 3: Add Margin Beyond Minimum</p>
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<p>Even the target values have thin margins (THS_ZERO: 185 ns vs 168 ns min = 10% margin). For a production system with the SN65DSI83 (which has known sensitivity to SoT timing), consider:</p>
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<p>```<br>PHYTIMING2 (0xbc) = 0x00040C03 → THS_ZERO=12 (222ns), giving 32% margin<br>```</p>
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<p>This costs negligible bandwidth at 432 Mbit/s video mode and eliminates any remaining race-condition risk.</p>
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<p>### Priority 4: CLK Common-Mode Offset</p>
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<p>The +28–30 mV CLK common-mode offset warrants checking:<br>- CLK lane termination resistor values and matching<br>- PCB trace length matching between CLK_P and CLK_N<br>- Not a flicker cause, but reduces noise margin</p>
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<ul><li></li></ul>
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<p>## 7. Summary</p>
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<p><strong>The flicker is caused by incorrect DSIM PHY timing register values — specifically THS_ZERO programmed at 6 byte-clocks (111 ns) instead of the required 10 (185 ns), leaving the LP-00 SoT state 34% below the D-PHY minimum of 168 ns.</strong> The samsung-dsim driver's auto-calculation is systematically under-programming all timing fields by 1–4 byte-clocks compared to the target values. This creates a non-deterministic SoT detection race at the SN65DSI83 receiver, producing the observed 20% flicker rate at pipeline load. Supply, HS amplitude, jitter, and LP-11 voltage are all nominal and uncorrelated with flicker.</p>
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<p><strong>Fix: Force PHYTIMING registers to the target values (especially THS_ZERO ≥ 10) via driver patch or device-tree override. This should eliminate flicker entirely.</strong> Validate by running ≥100 load/unload cycles and confirming zero LP-low plateau absences.</p>
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<p class="tokens">Tokens: 32465 in / 3851 out</p>
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</body>
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