122 lines
19 KiB
HTML
122 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0137–0166</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert h2 { color: #e65100; margin-top: 0; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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table { border-collapse: collapse; width: 100%; }
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th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 6 of 30 display load sessions (20%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0143</td><td>20260409_122244</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>0148</td><td>20260409_122432</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.4 ns</td><td>1.016 V</td></tr><tr><td>0152</td><td>20260409_122559</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.1 ns</td><td>1.015 V</td></tr><tr><td>0156</td><td>20260409_122725</td><td>dat</td><td style='color:red'>0.2 ns</td><td>0.1 ns</td><td>1.016 V</td></tr><tr><td>0159</td><td>20260409_122830</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.4 ns</td><td>1.015 V</td></tr><tr><td>0166</td><td>20260409_123101</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0137</td><td>20260409_122033</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0138</td><td>20260409_122055</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260409_122117</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260409_122138</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260409_122200</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260409_122222</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260409_122244</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260409_122305</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260409_122327</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260409_122349</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260409_122410</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260409_122432</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260409_122454</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260409_122515</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260409_122537</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260409_122559</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260409_122620</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260409_122642</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260409_122704</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260409_122725</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260409_122747</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260409_122809</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260409_122830</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260409_122852</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260409_122914</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260409_122935</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260409_122957</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260409_123018</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260409_123040</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260409_123101</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-09 12:35:40 |
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<strong>Scope:</strong> Captures 0137–0166 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166</p>
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<ul><li></li></ul>
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<p>## 1. Executive Summary</p>
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<p><strong>The system has a systematic SoT failure mechanism on the data lane.</strong> Every single capture (30/30) shows LP exit → HS timing of 0–4 ns, violating the MIPI D-PHY ≥50 ns TLPX minimum by an order of magnitude. The flicker-correlated captures (6/30, 20%) are distinguished solely by <strong>LP-low plateau = 0 ns</strong> (completely absent LP-00 state), while non-flicker captures show LP-low plateaux of 108–343 ns. The root registers are wrong — the driver is programming `0x00000305` / `0x020e0a03` / `0x00030605` instead of the target values `0x00000306` / `0x03110A04` / `0x00040A03`, resulting in under-specified TLPX, TCLK_PREPARE, TCLK_ZERO, THS_PREPARE, THS_ZERO, and THS_TRAIL durations. The SN65DSI83 bridge is at the edge of its SoT detection window; when the LP-00 state is entirely absent, the bridge fails to lock.</p>
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<ul><li></li></ul>
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<p>## 2. Register Analysis — Root Cause</p>
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<p>### Actual vs. Target Register Values</p>
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<p>| Register | Actual | Target | Status |<br>|---|---|---|---|<br>| PHYTIMING (0xb4) | `0x00000305` | `0x00000306` | <strong>WRONG</strong> |<br>| PHYTIMING1 (0xb8) | `0x020e0a03` | `0x03110A04` | <strong>WRONG</strong> |<br>| PHYTIMING2 (0xbc) | `0x00030605` | `0x00040A03` | <strong>WRONG</strong> |</p>
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<p>### Field-by-Field Decode (all 30 captures identical)</p>
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<p>| Field | Actual (byte-clk) | Actual (ns) | Target (byte-clk) | Target (ns) | D-PHY Spec Min | Verdict |<br>|---|---|---|---|---|---|---|<br>| <strong>TLPX</strong> | 3 | 55.6 ns | 3 | 55.6 ns | 50 ns | ✓ marginal |<br>| <strong>THS_EXIT</strong> | 5 | 92.6 ns | 6 | 111.1 ns | 100 ns | <strong>✗ FAIL</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 | 37.0 ns | 3 | 55.6 ns | 38 ns | <strong>✗ MARGINAL/FAIL</strong> |<br>| <strong>TCLK_ZERO</strong> | 14 (0x0e) | 259.3 ns | 17 (0x11) | 314.8 ns | 300 ns | <strong>✗ FAIL</strong> |<br>| <strong>TCLK_POST</strong> | 10 (0x0a) | 185.2 ns | 10 (0x0a) | 185.2 ns | 180 ns | ✓ marginal |<br>| <strong>TCLK_TRAIL</strong> | 3 | 55.6 ns | 4 | 74.1 ns | 60 ns | <strong>✗ FAIL</strong> |<br>| <strong>THS_PREPARE</strong> | 3 | 55.6 ns | 3 | 55.6 ns | 40+4×UI=49.3 ns | ✓ |<br>| <strong>THS_ZERO</strong> | 6 | 111.1 ns | 10 (0x0a) | 185.2 ns | 145+10×UI=168.2 ns | <strong>✗ FAIL</strong> |<br>| <strong>THS_TRAIL</strong> | 5 | 92.6 ns | 4 | 74.1 ns | max(8×UI,60+4×UI)=69.3 ns | ✓ over-spec |</p>
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<p><strong>Five fields are out of MIPI D-PHY v1.1 spec.</strong> The critical ones for SoT are:</p>
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<ul><li><strong>THS_EXIT = 5 (92.6 ns) < 100 ns spec minimum</strong>: The HS-exit-to-LP transition is too short. This directly controls how long the line dwells in LP states before re-entering HS.</li><li><strong>THS_ZERO = 6 (111.1 ns) < 168 ns spec minimum</strong>: The HS-0 state before the sync sequence is 34% too short. The receiver has less time to acquire the HS common mode and prepare for data.</li><li><strong>TCLK_ZERO = 14 (259 ns) < 300 ns spec minimum</strong>: The clock lane HS-0 preamble is 14% too short.</li><li><strong>TCLK_TRAIL = 3 (55.6 ns) < 60 ns spec minimum</strong>: Clock trail is too short.</li><li><strong>TCLK_PREPARE = 2 (37 ns)</strong>: At the absolute floor of the 38–95 ns window; likely below spec with any layout/probe derating.</li></ul>
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<p>### Why The Driver Is Writing Wrong Values</p>
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<p>The samsung-dsim driver computes PHY timing from the HS bit rate using a formula with integer truncation. At 432 Mbit/s (a relatively low MIPI rate), several fields truncate to values 1 byte-clock below the spec-compliant minimum. <strong>The driver's automatic calculation does not match the target values.</strong> This is a known issue with the samsung-dsim / sec-dsim timing computation at low bit rates — the rounding is not conservative enough.</p>
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<ul><li></li></ul>
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<p>## 3. LP Timing Analysis — Flicker Mechanism</p>
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<p>### LP-Low Plateau Distribution</p>
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<p>| LP-low plateau (ns) | Count | Flicker? |<br>|---|---|---|<br>| <strong>0</strong> (absent) | <strong>6</strong> | <strong>ALL 6 FLICKER</strong> |<br>| 108 | 7 | 0 flicker |<br>| 144 | 1 | 0 flicker |<br>| 342–343 | 16 | 0 flicker |</p>
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<p><strong>Perfect correlation: LP-low plateau = 0 ↔ flicker.</strong> No capture with LP-low ≥ 108 ns produced flicker; every capture with LP-low = 0 ns did.</p>
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<p>### LP Exit Duration</p>
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<p>Every capture shows LP exit → HS of 0–4 ns (spec minimum 50 ns). This is not a measurement artifact — it is a consequence of <strong>THS_EXIT = 5 byte-clocks (92.6 ns)</strong> which is already below the 100 ns minimum, combined with the oscilloscope's single-ended LP measurement resolving the transition as essentially instantaneous.</p>
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<p>### Why LP-Low Is Non-Deterministic</p>
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<p>The LP-low plateau clusters into three values (0, ~108, ~343 ns), suggesting the DSIM IP has a <strong>race condition between the LP state machine and the HS transmitter enable</strong>. The LP-00 state is supposed to persist for THS_PREPARE + THS_ZERO ≈ 167 ns (at target values), but the actual programmed THS_ZERO = 6 (111 ns) is so short that, depending on internal clock-domain synchronization:</p>
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<ul><li><strong>Best case</strong> (~60% of captures): LP-00 holds for ~343 ns (≈ TCLK_ZERO + margin) — the clock lane's longer preparation masks the data lane's short state.</li><li><strong>Middle case</strong> (~27%): LP-00 holds for ~108 ns (≈ THS_ZERO actual + jitter) — data lane barely completes its sequence.</li><li><strong>Worst case</strong> (~20%): LP-00 is <strong>completely skipped</strong> — the HS transmitter fires before the LP driver has asserted the 00 state. The SN65DSI83 never sees a valid SoT and fails to lock.</li></ul>
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<p>This race is exacerbated by:<br>1. <strong>THS_ZERO being 34% below spec</strong> (111 ns vs. 168 ns required)<br>2. <strong>THS_EXIT being below spec</strong> (92.6 ns vs. 100 ns), leaving insufficient LP-11 dwell time before the next SoT<br>3. <strong>TCLK_ZERO being below spec</strong> (259 ns vs. 300 ns), reducing the clock-lane preamble that normally provides timing margin</p>
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<ul><li></li></ul>
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<p>## 4. HS Signal Quality</p>
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<p>### Clock Lane — Stable, Minor Concern<br>- <strong>Amplitude</strong>: 175.4–177.9 mV — consistent, well within 140–270 mV spec<br>- <strong>Asymmetry</strong>: +190 / −163 mV typical — <strong>+27 mV positive bias</strong> (common mode +13–15 mV). Acceptable but indicates slight termination mismatch.<br>- <strong>Rise time</strong>: 135–154 ps (20–80%) — excellent<br>- <strong>Jitter</strong>: 99–138 ps p-p, 26–29 ps RMS — acceptable for 432 Mbit/s<br>- <strong>Sub-140 mV samples</strong>: Present in every proto capture (125–1555 samples). These are transition-region samples, not settled violations. The long-window capture catches more edges. Not a concern at this rate.</p>
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<p>### Data Lane — Measurement Artifact Dominates<br>- <strong>Only-negative-swing warning</strong> appears in 22/30 sig/dat captures: The oscilloscope trigger is catching the same polarity bit pattern consistently. This is a <strong>trigger/capture window artifact</strong>, not a real asymmetry.<br>- <strong>Zero-amplitude sig/dat</strong> in captures 0146, 0148, 0163, 0166: The high-res capture window landed during blanking (LP state or idle). Three of these four are flicker captures — consistent with the bridge not being in HS mode.<br>- <strong>Proto dat sub-140 mV counts vary widely</strong> (62 to 16,096): This reflects different data patterns in the long capture window. Not a degradation indicator.<br>- <strong>Settled amplitude</strong>: 181–224 mV when valid — healthy.</p>
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<p>### No Amplitude Drift<br>No systematic trend in clock or data amplitude across the 30-capture sequence. The signal path is thermally and electrically stable.</p>
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<ul><li></li></ul>
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<p>## 5. Supply Rail Analysis</p>
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<p>### 1.8 V Rail — Acceptable, No Flicker Correlation</p>
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<p>| Metric | Range | Spec | Verdict |<br>|---|---|---|---|<br>| Mean | 1.7633–1.7685 V | 1.71–1.89 V | ✓ |<br>| Min | 1.7480–1.7600 V | ≥1.71 V | ✓ |<br>| Droop | 7.5–17.1 mV | — | Mild |<br>| Ripple RMS | 4.98–5.59 mV | — | Low |</p>
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<p><strong>Droop vs. Flicker Correlation:</strong></p>
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<p>| Capture | Flicker | Droop (mV) |<br>|---|---|---|<br>| 0143 | YES | 7.5 |<br>| 0148 | YES | 12.2 |<br>| 0152 | YES | 12.5 |<br>| 0156 | YES | 11.3 |<br>| 0159 | YES | 8.7 |<br>| 0166 | YES | 11.9 |<br>| <strong>Flicker mean</strong> | | <strong>10.7</strong> |<br>| Non-flicker mean | | <strong>9.5</strong> |</p>
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<p>The difference is negligible (1.2 mV). The largest droop (17.1 mV, capture 0164) did NOT produce flicker. <strong>Supply droop is not the cause.</strong> The LP-11 voltage is rock-solid at 1.015–1.016 V across all captures — the LP driver pull-ups are healthy.</p>
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<ul><li></li></ul>
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<p>## 6. Anomaly Summary</p>
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<p>| Finding | Severity | Captures Affected | Cause |<br>|---|---|---|---|<br>| LP exit 0–4 ns (spec ≥50 ns) | <strong>CRITICAL</strong> | <strong>30/30 (100%)</strong> | THS_EXIT, THS_ZERO under-programmed |<br>| LP-low plateau = 0 ns | <strong>CRITICAL</strong> | 6/30 (flicker events) | Race condition from short THS_ZERO |<br>| THS_EXIT < 100 ns | <strong>SPEC VIOLATION</strong> | 30/30 | Register 0xb4 field wrong |<br>| THS_ZERO < 168 ns | <strong>SPEC VIOLATION</strong> | 30/30 | Register 0xbc field wrong |<br>| TCLK_ZERO < 300 ns | <strong>SPEC VIOLATION</strong> | 30/30 | Register 0xb8 field wrong |<br>| TCLK_TRAIL < 60 ns | <strong>SPEC VIOLATION</strong> | 30/30 | Register 0xb8 field wrong |<br>| TCLK_PREPARE at floor | <strong>MARGINAL</strong> | 30/30 | Register 0xb8 field wrong |<br>| CLK +27 mV amplitude asymmetry | Minor | 30/30 | Termination/layout mismatch |<br>| Sig/dat zero amplitude | Info | 4/30 | Capture during blanking |<br>| Sig/dat only-negative-swing | Info | 22/30 | Trigger alignment artifact |</p>
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<ul><li></li></ul>
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<p>## 7. Actionable Recommendations</p>
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<p>### ① IMMEDIATE — Fix PHY Timing Registers (PRIMARY FIX)</p>
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<p>Override the samsung-dsim driver's automatic timing computation and force the target values:</p>
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<p>```<br>DSIM_PHYTIMING (0x32e100b4) = 0x00000306<br>DSIM_PHYTIMING1 (0x32e100b8) = 0x03110A04<br>DSIM_PHYTIMING2 (0x32e100bc) = 0x00040A03<br>```</p>
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<p><strong>Implementation options (choose one):</strong></p>
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<p><strong>Option A — Device Tree override (preferred):</strong><br>If the samsung-dsim driver supports `samsung,phy-timing` or equivalent DT properties, set all fields explicitly. Check the binding documentation.</p>
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<p><strong>Option B — Driver patch:</strong><br>In `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim`), locate the `samsung_dsim_set_phy_timing()` function and either:<br>- Add a post-computation fixup that clamps each field to the MIPI spec minimum, OR<br>- Replace the automatic computation with a lookup table for 432 Mbit/s</p>
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<p><strong>Option C — Runtime memtool (test only):</strong><br>```bash<br># Write AFTER the driver initializes, BEFORE enabling video output<br>memtool mw -l 0x32e100b4=0x00000306<br>memtool mw -l 0x32e100b8=0x03110A04<br>memtool mw -l 0x32e100bc=0x00040A03<br>```<br>This confirms the fix before committing to a driver change.</p>
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<p>### ② Add Margin Beyond Spec Minimums</p>
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<p>For production robustness, consider adding 1 byte-clock (18.5 ns) of margin to the most critical fields:</p>
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<p>| Field | Target | With Margin | ns |<br>|---|---|---|---|<br>| THS_EXIT | 6 | <strong>7</strong> | 129.6 ns |<br>| THS_ZERO | 10 | <strong>11</strong> | 203.7 ns |<br>| TCLK_ZERO | 17 | <strong>18</strong> | 333.3 ns |</p>
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<p>This eliminates the race condition entirely by ensuring the LP-00 state persists well beyond the SN65DSI83's detection window.</p>
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<p>### ③ Verify All 4 Data Lanes</p>
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<p>These captures only show DAT0. The other three data lanes share the same PHYTIMING2 register, so they have the same violations. However, verify with a scope that all lanes exhibit the fix after the register change.</p>
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<p>### ④ Address Clock Lane Asymmetry (Low Priority)</p>
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<p>The +27 mV positive/negative amplitude mismatch on CLK (e.g., +191 / −163 mV) suggests a ~15% termination imbalance. Check:<br>- 100Ω differential termination resistor tolerance at the SN65DSI83 input<br>- Any asymmetric stubs or vias on CLK_P vs CLK_N traces<br>- This is not causing the flicker but may reduce margin at higher bit rates</p>
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<p>### ⑤ Measurement Setup Improvement (Low Priority)</p>
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<ul><li>The "only negative swings" artifact on sig/dat suggests the trigger is synced to a specific clock edge that always captures the same data polarity. Use random triggering or a longer capture window.</li><li>The zero-amplitude sig/dat captures during blanking are expected in non-continuous-clock data lane measurements, but consider trigg</li></ul>
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<p class="tokens">Tokens: 34006 in / 4096 out</p>
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