114 lines
19 KiB
HTML
114 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0138–0167</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert h2 { color: #e65100; margin-top: 0; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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table { border-collapse: collapse; width: 100%; }
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th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 4 of 30 display load sessions (13%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0143</td><td>20260410_112853</td><td>dat</td><td style='color:red'>0.2 ns</td><td>4.5 ns</td><td>1.016 V</td></tr><tr><td>0148</td><td>20260410_113041</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.015 V</td></tr><tr><td>0152</td><td>20260410_113207</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.9 ns</td><td>1.016 V</td></tr><tr><td>0164</td><td>20260410_113628</td><td>dat</td><td style='color:red'>0.2 ns</td><td>3.2 ns</td><td>1.015 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0138</td><td>20260410_112705</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260410_112727</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260410_112748</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260410_112810</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260410_112831</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260410_112853</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260410_112915</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260410_112936</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260410_112958</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260410_113020</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260410_113041</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260410_113102</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260410_113124</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260410_113146</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260410_113207</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260410_113229</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260410_113251</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260410_113312</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260410_113334</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260410_113356</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260410_113417</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260410_113439</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260410_113501</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260410_113522</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260410_113544</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260410_113606</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260410_113628</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260410_113649</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260410_113711</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0167</td><td>20260410_113733</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-10 11:42:18 |
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<strong>Scope:</strong> Captures 0138–0167 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0138–0167</p>
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<ul><li></li></ul>
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<p>## 1. CRITICAL FINDING: Register Mismatch Is the Root Cause</p>
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<p>### Actual vs. Target Register Values</p>
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<p>| Register | Target | Actual (all captures) | Impact |<br>|---|---|---|---|<br>| <strong>PHYTIMING (0xb4)</strong> | <strong>0x00000306</strong> | <strong>0x00000305</strong> | THS_EXIT=5 → 92.6 ns (spec ≥100 ns) <strong>✗ VIOLATION</strong> |<br>| <strong>PHYTIMING1 (0xb8)</strong> | <strong>0x03110A04</strong> | <strong>0x020e0a03</strong> | TCLK_PREPARE=2 → 37 ns (spec 38–95 ns) <strong>✗ VIOLATION</strong>; TCLK_ZERO=14 → 259 ns (spec ≥300 ns) <strong>✗ VIOLATION</strong>; TCLK_TRAIL=3 → 55.6 ns (spec ≥60 ns) <strong>✗ VIOLATION</strong> |<br>| <strong>PHYTIMING2 (0xbc)</strong> | <strong>0x00040A03</strong> | <strong>0x00030605</strong> | THS_PREPARE=5 → 92.6 ns (spec 40+4×UI=49 ns to 85+6×UI=99 ns) <strong>✗ BORDERLINE/VIOLATION at 93 ns</strong>; THS_ZERO=6 → 111 ns (spec ≥ 145+10×UI=168 ns) <strong>✗ VIOLATION</strong>; THS_TRAIL=3 → 55.6 ns (spec ≥ max(8×UI, 60+4×UI)=69.3 ns) <strong>✗ VIOLATION</strong> |</p>
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<p><strong>Every single DSIM PHY timing register is wrong.</strong> The driver is not applying the target values. All 30 captures show the identical incorrect values, confirming this is a persistent configuration bug — not a transient failure.</p>
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<p>### Decoded Timing Violations (actual register values)</p>
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<p>| Parameter | Field Value | Actual Duration | D-PHY v1.1 Min | Status |<br>|---|---|---|---|---|<br>| TLPX | 3 | 55.6 ns | 50 ns | ✓ marginal |<br>| THS_EXIT | 5 | 92.6 ns | 100 ns | <strong>✗ SHORT by 7.4 ns</strong> |<br>| TCLK_PREPARE | 2 | 37.0 ns | 38 ns | <strong>✗ SHORT by 1 ns</strong> |<br>| TCLK_ZERO | 14 (0x0e) | 259 ns | 300 ns | <strong>✗ SHORT by 41 ns</strong> |<br>| TCLK_POST | 10 (0x0a) | 185 ns | ~180 ns | ✓ barely |<br>| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | <strong>✗ SHORT by 4.4 ns</strong> |<br>| THS_PREPARE | 5 | 92.6 ns | 49–99 ns | ✓ but high-side |<br>| THS_ZERO | 6 | 111 ns | 168 ns | <strong>✗ SHORT by 57 ns</strong> |<br>| THS_TRAIL | 3 | 55.6 ns | 69.3 ns | <strong>✗ SHORT by 13.7 ns</strong> |</p>
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<p><strong>Six of nine timing parameters violate D-PHY v1.1 spec.</strong> The most damaging are:</p>
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<ul><li><strong>THS_ZERO = 111 ns vs. 168 ns required</strong>: The data lane HS-Zero state is 34% too short. This is the interval where the receiver must detect the HS-0 level before the SoT (sync byte 0xB8). When it's too short, the SN65DSI83's CDR has insufficient time to lock before data arrives.</li><li><strong>TCLK_ZERO = 259 ns vs. 300 ns required</strong>: The clock lane HS-Zero is 14% too short, reducing the receiver's window to acquire clock lock.</li><li><strong>THS_EXIT = 92.6 ns vs. 100 ns required</strong>: Exit from HS back to LP is too fast for receivers to reliably detect the transition.</li></ul>
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<ul><li></li></ul>
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<p>## 2. LP-Low Plateau Analysis: The Flicker Mechanism</p>
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<p>### Distribution of LP-low plateau durations across all captures</p>
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<p>| LP-low Plateau | Count | Flicker? | Captures |<br>|---|---|---|---|<br>| <strong>0 ns (absent)</strong> | <strong>4</strong> | <strong>YES — all 4</strong> | 0143, 0148, 0152, 0164 |<br>| ~108 ns | 4 | No | 0139, 0155, 0158, 0160, 0162 |<br>| ~342–348 ns | 20 | No | Remainder |<br>| Missing data | 1 | Unknown | 0141 (processing error) |</p>
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<p><strong>Perfect correlation:</strong> Every flicker event corresponds to LP-low plateau = 0 ns. Every non-flicker event has LP-low ≥ 108 ns. There are no exceptions.</p>
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<p>The LP-low plateau represents the combined duration of the LP-01 → LP-00 sequence that constitutes the data lane SoT entry. When THS_ZERO is programmed at only 111 ns (vs. 168 ns required), the PHY's internal state machine has almost no timing margin. Under normal conditions, the silicon *happens* to produce a recognizable LP-00 state of ~342 ns — well above spec. But intermittently (~13% of startups), a race condition within the PHY causes the LP-01/LP-00 states to be completely swallowed, producing a direct LP-11 → HS transition with no detectable SoT sequence.</p>
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<p><strong>Why it's non-deterministic:</strong> The Samsung DSIM PHY's internal PLL lock time and lane synchronization have cycle-to-cycle jitter. With the programmed THS_ZERO 34% below spec, the internal sequencer's timing margin is negative. Most of the time the PLL locks fast enough that the sequencer still outputs the LP states; occasionally it doesn't, and the SoT is corrupted.</p>
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<p>The "LP exit → HS" metric (1–4 ns across all captures, including non-flicker ones) confirms that the LP-01 state itself is never being held for the required TLPX ≥ 50 ns — even on "good" startups, the LP-01 pulse is undetectably brief. What saves non-flicker sessions is the ~342 ns LP-00 plateau, which gives the SN65DSI83 enough time to detect the HS entry. When even that disappears (flicker cases), the bridge never acquires sync.</p>
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<ul><li></li></ul>
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<p>## 3. HS Signal Quality</p>
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<p>### Consistent observations across all 30 captures:</p>
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<p>| Parameter | CLK | DAT0 | Assessment |<br>|---|---|---|---|<br>| Vdiff amplitude | 165.6–169.1 mV | 177–224 mV | <strong>Marginal-low on CLK</strong> (spec 140–270 mV, only 26 mV above floor) |<br>| Common mode | +26.6 to +32.0 mV | −98 to +5 mV | CLK offset ✓; DAT asymmetric |<br>| Rise time 20–80% | 163.6–165.4 ps | 143.8–219.4 ps | ✓ within spec |<br>| Jitter p-p | 145–177 ps | — | ✓ acceptable |<br>| Samples below 140 mV | 21–153 per capture | 18–7280 per capture | <strong>✗ Persistent sub-spec excursions</strong> |</p>
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<p><strong>Clock amplitude is running at ~167 mV — only 19% above the 140 mV floor.</strong> This provides essentially no margin against supply droop, temperature variation, or aging. The persistent sub-140 mV samples on both clock and data indicate ISI/reflection-induced amplitude dips that regularly breach the minimum.</p>
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<p><strong>DAT0 asymmetry:</strong> Most sig/dat captures show only negative differential swings (Vdiff pos = 0.0 mV), indicating a probe/measurement artifact (likely single-ended measurement of one line only, or trigger position capturing only one data phase). However, proto/dat captures with both polarities show a consistent ~7–10 mV asymmetry between positive and negative swings, suggesting slight impedance mismatch or common-mode offset on the data lane.</p>
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<ul><li></li></ul>
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<p>## 4. 1.8 V Supply Rail Correlation</p>
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<p>### Supply droop statistics:</p>
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<p>| Droop Category | Count | Flicker events in category |<br>|---|---|---|<br>| < 30 mV (healthy) | 7 | <strong>2 flicker</strong> (0143: 31 mV, 0148: 30.7 mV, 0164: 28.4 mV) |<br>| 30–50 mV (marginal) | 8 | 1 flicker (0152: 55.6 mV) |<br>| 50–68 mV (poor, some below 1.71 V) | 12 | 0 flicker |<br>| Below 1.71 V spec minimum | 5 | 0 flicker |</p>
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<p><strong>No correlation between supply droop and flicker.</strong> Three of four flicker events occurred at modest droop (<32 mV), while the deepest droops (66–68 mV, Vmin = 1.700 V) produced no flicker. This confirms the flicker is not supply-induced — it's a timing/sequencing issue.</p>
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<p>However, the supply health is independently concerning:<br>- <strong>5 captures</strong> dropped below the 1.71 V MIPI VDDIO minimum (0142: 1.700 V, 0147: 1.704 V, 0150: 1.700 V, 0151: 1.700 V, 0166: 1.708 V)<br>- Mean droop is ~43 mV; worst case is 67.7 mV<br>- This indicates <strong>insufficient bulk/MLCC decoupling</strong> near the MIPI PHY VDDIO pin</p>
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<ul><li></li></ul>
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<p>## 5. Warning/Error Explanations</p>
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<p>| Warning | Cause | Action |<br>|---|---|---|<br>| "CLK lane is in continuous HS mode" | Normal for video-mode DSI — CLK runs continuously HS; no LP→HS expected on CLK | None needed |<br>| "Only negative swings in capture window" | sig/dat probe capturing during a single data symbol (long run of zeros/ones), or single-ended probe on one line only | Verify differential probe connection; not a device fault |<br>| "No HS signal detected" (sig/dat 0162, 0163; proto/dat 0155) | Trigger caught blanking interval (HFP/HBP) where DAT0 is in LP; CLK continues HS | Trigger refinement; not a device fault |<br>| "LP exit duration X ns below spec min 50 ns" | <strong>Register misconfiguration</strong>: THS_PREPARE (92.6 ns) is correct but the LP-01 state is too brief because the PHY sequencer races through it with the underspecified THS_ZERO | Fix registers |<br>| "index 200000 is out of bounds" (Capture 0141) | Buffer overrun in LP analysis script; the LP→HS edge was at or beyond the end of the capture window | Re-capture with wider window or earlier trigger |<br>| "Supply droops below 1.71 V" | Insufficient decoupling or trace resistance on VDDIO | Add MLCC capacitance |<br>| "Settled samples below 140 mV" | ISI/reflection causing Vdiff dips below 140 mV floor during HS toggling | Improve termination/routing; increase PHY drive strength if available |</p>
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<ul><li></li></ul>
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<p>## 6. Actionable Recommendations</p>
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<p>### PRIORITY 1 — Fix PHY Timing Registers (ROOT CAUSE OF FLICKER)</p>
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<p>The samsung-dsim (sec-dsim) driver is computing or writing incorrect values. Apply the <strong>target</strong> values via device-tree override or driver patch:</p>
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<p>```<br>/* Device tree or driver patch */<br>DSIM_PHYTIMING = 0x00000306 /* TLPX=3, THS_EXIT=6 */<br>DSIM_PHYTIMING1 = 0x03110A04 /* TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4 */<br>DSIM_PHYTIMING2 = 0x00040A03 /* THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3 */<br>```</p>
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<p><strong>Specific fixes and expected impact:</strong></p>
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<p>| Field | Current → Target | Duration Change | Why It Matters |<br>|---|---|---|---|<br>| THS_ZERO | 6 → <strong>10</strong> | 111 → <strong>185 ns</strong> | Gives receiver 74 ns more to detect HS-0 before sync byte. <strong>Primary flicker fix.</strong> |<br>| TCLK_ZERO | 14 → <strong>17</strong> | 259 → <strong>315 ns</strong> | Allows proper clock CDR acquisition. Eliminates clock lock failures. |<br>| THS_EXIT | 5 → <strong>6</strong> | 92.6 → <strong>111 ns</strong> | Meets 100 ns minimum. Prevents LP re-entry confusion. |<br>| TCLK_PREPARE | 2 → <strong>3</strong> | 37 → <strong>55.6 ns</strong> | Meets 38 ns minimum with margin. |<br>| TCLK_TRAIL | 3 → <strong>4</strong> | 55.6 → <strong>74 ns</strong> | Meets 60 ns minimum with margin. |<br>| THS_TRAIL | 3 → <strong>4</strong> | 55.6 → <strong>74 ns</strong> | Meets 69.3 ns minimum with margin. |<br>| THS_PREPARE | 5 → <strong>3</strong> | 92.6 → <strong>55.6 ns</strong> | Moves from 93 ns (borderline over 99 ns max) to comfortable mid-range. |</p>
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<p><strong>Verification:</strong> After applying, read back registers with `memtool md -l 0x32e100b4+0x0c` and confirm the target values. Run 100+ pipeline load/unload cycles to verify zero flicker.</p>
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<p><strong>Driver investigation:</strong> The samsung-dsim driver's `samsung_dsim_set_phy_timing()` function computes timing from the HS clock rate. At 432 Mbit/s the formula may be rounding down. Check:<br>- `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` in NXP BSP)<br>- The timing computation uses integer division that truncates; for low bitrates like 432 Mbps, every byte-clock unit matters<br>- Consider whether the NXP BSP has a known erratum or patch for this</p>
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<p>### PRIORITY 2 — Improve 1.8 V VDDIO Decoupling</p>
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<p>Although not correlated with flicker, the supply is out-of-spec:</p>
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<ol><li><strong>Add 2×4.7 µF + 2×100 nF MLCC</strong> as close as possible to the MIPI PHY VDDIO pins on the SOM carrier board</li><li><strong>Check VDDIO trace impedance</strong> — the 67 mV droop at LP→HS transition (4 lanes switching simultaneously) suggests >100 mΩ path resistance</li><li>Target: droop < 30 mV, Vmin > 1.71 V under all conditions</li></ol>
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<p>### PRIORITY 3 — Clock Amplitude Margin</p>
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<p>CLK differential amplitude at ~167 mV is only 19% above the 140 mV minimum:</p>
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<ol><li>Check for excessive series resistance in AC coupling capacitors (use 0402 or 0201 with low ESR)</li><li>Verify 100 Ω differential termination at receiver (SN65DSI83 has internal, but external may be present and wrong value)</li><li>If the i.MX 8M Mini DPHY has programmable drive strength, increase by one step</li><li>Reduce trace length / improve impedance matching to eliminate the sub-140 mV ISI dips</li></ol>
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<p>### PRIORITY 4 — Add Software Retry as Belt-and-Suspenders</p>
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<p>Even after fixing registers, add a startup verification loop:</p>
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<p>```c<br>/* After DSI pipeline enable, read SN65DSI83 status register 0x0A */<br>/* Bit 0 = PLL lock. If not locked within 50ms, unload and reload pipeline */<br>for (retries = 0</p>
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<p class="tokens">Tokens: 33253 in / 4096 out</p>
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</body>
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</html>
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