127 lines
8.2 KiB
HTML
127 lines
8.2 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Interactive Flicker Test — 2026-04-17 09:29:53</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
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padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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h2 { color: #1a3a5c; margin-top: 32px; }
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h3 { color: #333; }
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.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
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.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
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padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
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.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
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border-radius: 6px; font-size: 1.05em; font-weight: bold; }
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.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
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.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
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.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
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table { border-collapse: collapse; width: 100%; margin-top: 8px; }
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th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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tr:nth-child(even) { background: #fafafa; }
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pre { margin: 0; }
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</style>
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</head>
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<body>
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<h1>MIPI Interactive Flicker Test Report</h1>
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<p class="meta">
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Generated: 2026-04-17 09:29:53 |
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Model: claude-opus-4-6
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</p>
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<div class="stop-box">
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<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
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</div>
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<div>
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<div class="stat s-confirmed">0 confirmed flicker(s)</div>
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<div class="stat s-false">2 false alarm(s)</div>
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<div class="stat s-claude-no">6 Claude said no</div>
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</div>
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<h2>D-PHY Configuration</h2>
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<p>
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Pixel clock: <strong>72.0 MHz</strong> |
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Bit rate: <strong>432.0 Mbit/s per lane</strong> |
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Byte clock: <strong>54.000 MHz</strong>
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(18.519 ns/byte) |
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UI: <strong>2.315 ns</strong>
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</p>
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<table>
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<tr>
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<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
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<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
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</tr>
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<tr><td><code>lpx</code></td><td>≥ 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
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<tr><td><code>hs_prepare</code></td><td>49.3 – 98.9</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
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<tr><td><code>hs_zero</code></td><td>≥ 112.6</td><td>6</td><td>7</td><td>+0</td><td><strong>7</strong></td><td>129.63</td><td>✓</td></tr>
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<tr><td><code>hs_trail</code></td><td>≥ 69.3</td><td>4</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>✓</td></tr>
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<tr><td><code>hs_exit</code></td><td>≥ 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>✓</td></tr>
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<tr><td><code>clk_prepare</code></td><td>38.0 – 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
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<tr><td><code>clk_zero</code></td><td>≥ 244.4</td><td>13</td><td>14</td><td>+0</td><td><strong>14</strong></td><td>259.26</td><td>✓</td></tr>
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<tr><td><code>clk_post</code></td><td>≥ 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>✓</td></tr>
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<tr><td><code>clk_trail</code></td><td>≥ 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>✓</td></tr>
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</table>
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<p style="color:#2e7d32">✓ All D-PHY v1.1 Table 14 constraints satisfied.</p>
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<h3>Samsung DSIM Registers</h3>
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<table>
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<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
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<tr>
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<td>PHY_TIMING</td><td><code>0xb4</code></td>
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<td><code>0x00000306</code></td>
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<td>lpx=3 hs_exit=6</td>
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</tr>
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<tr>
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<td>PHY_TIMING1</td><td><code>0xb8</code></td>
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<td><code>0x030e0a04</code></td>
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<td>clk_prepare=3 clk_zero=14
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clk_post=10 clk_trail=4</td>
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</tr>
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<tr>
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<td>PHY_TIMING2</td><td><code>0xbc</code></td>
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<td><code>0x00030704</code></td>
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<td>hs_prepare=3 hs_zero=7
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hs_trail=4</td>
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</tr>
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</table>
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<h3>u-boot Commands</h3>
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<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
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white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
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#
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# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
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# PHY_TIMING1 (0xb8) = 0x030e0a04 clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
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# PHY_TIMING2 (0xbc) = 0x00030704 hs_prepare=3 hs_zero=7 hs_trail=4
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# Enable Round-Up rounding (dsi-tweak bit 2)
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setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"
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saveenv
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boot</pre>
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<h2>Event Log</h2>
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<table>
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<tr>
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<th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th>
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<th>Claude: flicker?</th><th>Outcome</th>
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</tr>
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<tr><td>0001</td><td>20260417_084455</td><td>dat</td><td>107.8 ns</td><td>112.9 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0005</td><td>20260417_084634</td><td>dat</td><td>53.2 ns</td><td>58.3 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0023</td><td>20260417_085336</td><td>dat</td><td>342.4 ns</td><td>347.7 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0029</td><td>20260417_085602</td><td>dat</td><td>342.6 ns</td><td>347.8 ns</td><td>1.015 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0033</td><td>20260417_085742</td><td>dat</td><td>342.5 ns</td><td>347.5 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0079</td><td>20260417_091529</td><td>dat</td><td style="color:red">12.2 ns</td><td>0.6 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0082</td><td>20260417_091657</td><td>dat</td><td style="color:red">6.8 ns</td><td>0.0 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0085</td><td>20260417_091825</td><td>dat</td><td>342.5 ns</td><td>347.8 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr>
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</table>
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<h2>Claude Assessments</h2><h3>Capture 0079 [20260417_091529] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau of 12.2 ns is far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, at only ~24% of the threshold. The LP exit-to-HS transition of just 0.6–1 ns confirms the LP-01/LP-00 preamble states were essentially skipped, giving the bridge no meaningful window to recognize the start-of-transmission. Despite the HS amplitude (116 mV) and LP-11 voltage (1.015 V) being within normal ranges—indicating the PHY is electrically healthy—the critically truncated LP-low plateau means the SN65DSI83 almost certainly missed this SoT entry, resulting in a lost or corrupted video frame and visible flicker.</pre><h3>Capture 0082 [20260417_091657] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau of 6.8 ns is dramatically below the SN65DSI83's 50 ns minimum requirement for SoT detection — it is only ~14% of the needed duration. The LP exit-to-HS transition time of 0 ns further confirms that the LP-01/LP-00 preamble states were essentially absent or too brief to be resolved, meaning the bridge almost certainly missed the start-of-transmission. The slightly elevated HS amplitude of 131 mV (above the normal 105–122 mV range) suggests the transmitter may have entered HS mode abruptly without proper state progression, consistent with a truncated entry sequence that would cause the SN65DSI83 to lose frame sync and produce visible flicker.</pre>
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</body>
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</html>
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