131 lines
19 KiB
HTML
131 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0138–0167</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert h2 { color: #e65100; margin-top: 0; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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table { border-collapse: collapse; width: 100%; }
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th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 4 of 30 display load sessions (13%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0141</td><td>20260410_074657</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.2 ns</td><td>1.015 V</td></tr><tr><td>0147</td><td>20260410_074906</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.1 ns</td><td>1.016 V</td></tr><tr><td>0152</td><td>20260410_075053</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.2 ns</td><td>1.015 V</td></tr><tr><td>0166</td><td>20260410_075555</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.8 ns</td><td>1.016 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0138</td><td>20260410_074552</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260410_074614</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260410_074635</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260410_074657</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260410_074718</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260410_074740</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260410_074801</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260410_074823</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260410_074844</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260410_074906</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260410_074927</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260410_074949</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260410_075010</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260410_075032</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260410_075053</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260410_075115</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260410_075136</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260410_075158</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260410_075219</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260410_075241</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260410_075303</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260410_075324</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260410_075346</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260410_075407</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260410_075429</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260410_075450</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260410_075512</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260410_075533</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260410_075555</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0167</td><td>20260410_075616</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-10 08:01:00 |
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<strong>Scope:</strong> Captures 0138–0167 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis Report</p>
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<p>## 1. Executive Summary</p>
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<p><strong>The system has a critical SoT (Start-of-Transmission) timing defect that causes intermittent bridge lock failure at ~13% rate.</strong> The root cause is twofold: (a) the DSIM PHY timing registers are programmed with values significantly below your target spec, shortening THS_PREPARE and THS_ZERO to the point where LP-01→LP-00 states are marginally detectable; and (b) a non-deterministic race condition at the PHY level causes the LP-low plateau to occasionally collapse from ~342 ns to 0 ns, eliminating the SoT entry sequence entirely. The SN65DSI83 cannot detect SoT, fails to lock, and the display flickers for the entire session.</p>
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<ul><li></li></ul>
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<p>## 2. Register Analysis — The Smoking Gun</p>
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<p>### Actual vs. Target Register Values</p>
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<p>| Register | Target | Actual | Status |<br>|---|---|---|---|<br>| PHYTIMING (0xb4) | `0x00000306` | `0x00000305` | <strong>WRONG</strong> |<br>| PHYTIMING1 (0xb8) | `0x03110A04` | `0x020e0a03` | <strong>WRONG</strong> |<br>| PHYTIMING2 (0xbc) | `0x00040A03` | `0x00030605` | <strong>WRONG</strong> |</p>
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<p>### Field-by-Field Decode (all 30 captures show identical wrong values)</p>
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<p>| Field | Target (byte-clk) | Target (ns) | Actual (byte-clk) | Actual (ns) | Spec Min (ns) | Status |<br>|---|---|---|---|---|---|---|<br>| <strong>TLPX</strong> | 3 | 55.6 | 3 | 55.6 | 50 | ✓ OK |<br>| <strong>THS_EXIT</strong> | 6 | 111.1 | 5 | 92.6 | 100 | <strong>✗ VIOLATION</strong> |<br>| <strong>TCLK_PREPARE</strong> | 3 | 55.6 | 2 | 37.0 | 38* | <strong>⚠ Marginal</strong> |<br>| <strong>TCLK_ZERO</strong> | 17 (0x11) | 314.8 | 14 (0x0e) | 259.3 | 300 | <strong>✗ VIOLATION</strong> |<br>| <strong>TCLK_POST</strong> | 10 (0x0a) | 185.2 | 10 (0x0a) | 185.2 | 60+52×UI ≈180 | ✓ OK |<br>| <strong>TCLK_TRAIL</strong> | 4 | 74.1 | 3 | 55.6 | 60 | <strong>✗ VIOLATION</strong> |<br>| <strong>THS_PREPARE</strong> | 3 | 55.6 | 5 | 92.6 | 40+4×UI=49.3 / max 85+6×UI=98.9 | <strong>⚠ Near max</strong> |<br>| <strong>THS_ZERO</strong> | 10 (0x0a) | 185.2 | 6 | 111.1 | 145+10×UI=168.2 | <strong>✗ VIOLATION</strong> |<br>| <strong>THS_TRAIL</strong> | 4 | 74.1 | 3 | 55.6 | max(8×UI, 60+4×UI)=69.3 | <strong>✗ VIOLATION</strong> |</p>
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<p><strong>Five timing parameters are out of spec. The driver is not applying your target values.</strong> This is consistent across all 30 captures — the samsung-dsim driver's timing calculation function is overriding your devicetree values with its own computed (incorrect) values, or the devicetree properties are not being parsed.</p>
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<p>### Critical Impact of Wrong Registers on SoT</p>
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<ul><li><strong>THS_ZERO = 6 (111 ns) vs. spec min 168 ns</strong>: This is the duration data lanes hold LP-00 before HS-0. At 111 ns, it's <strong>34% below spec minimum</strong>. The SN65DSI83's SoT detector needs to see LP-00 for at least one full internal sample window. At 111 ns, it's on the edge — sometimes it catches it, sometimes it doesn't.</li></ul>
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<ul><li><strong>TCLK_ZERO = 14 (259 ns) vs. spec min 300 ns</strong>: The clock lane's HS preparation is also short, meaning the clock may not be stable when data SoT arrives.</li></ul>
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<ul><li><strong>THS_EXIT = 5 (92.6 ns) vs. spec min 100 ns</strong>: The exit time from HS back to LP is too short, potentially corrupting the LP-11 idle state before the next SoT.</li></ul>
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<ul><li></li></ul>
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<p>## 3. LP Timing Analysis — SoT Failure Mechanism</p>
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<p>### LP-low Plateau Distribution (30 captures)</p>
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<p>| LP-low plateau | Count | Flicker? |<br>|---|---|---|<br>| ~342-343 ns | 20 | 0/20 (0%) — <strong>all good</strong> |<br>| ~108 ns | 3 | 0/3 (0%) — good but marginal |<br>| 0 ns (absent) | 4 | <strong>4/4 (100%) — all flicker</strong> |<br>| Parse error | 1 | Unknown |</p>
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<p><strong>Perfect 1:1 correlation</strong>: Every capture with LP-low = 0 ns produced flicker. Every capture with LP-low ≥ 108 ns was good. The mechanism is:</p>
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<ol><li><strong>Normal case (~342 ns)</strong>: PHY executes LP-11 → LP-01 → LP-00 (held ~342 ns) → HS-0. The SN65DSI83 detects the SoT sequence, locks, display works.</li></ol>
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<ol><li><strong>Marginal case (~108 ns)</strong>: LP-00 hold is shortened to ~108 ns (roughly 6 byte clocks = actual THS_ZERO value). Still detectable by the bridge, but margin is thin.</li></ol>
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<ol><li><strong>Failure case (0 ns)</strong>: The LP-00 state is entirely skipped — the PHY jumps directly from LP-11 to HS. The bridge cannot detect SoT, never locks, display flickers indefinitely.</li></ol>
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<p>### Why Does LP-low Occasionally Collapse to Zero?</p>
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<p>The 2-3 ns "LP exit → HS" measurement appears in both good and bad captures, suggesting the measurement methodology flags any fast transition. However, the <strong>LP-low plateau</strong> measurement distinguishes the real failures:</p>
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<ul><li>The Samsung DSIM PHY has an internal state machine that sequences LP-11 → LP-01 → LP-00 → HS-0. With THS_ZERO = 6 byte-clocks (111 ns) and THS_PREPARE = 5 byte-clocks (92.6 ns), the total LP-low window is ~200 ns.</li></ul>
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<ul><li>The <strong>non-deterministic failure</strong> (0 ns LP-low) suggests a <strong>clock-domain-crossing race condition</strong> inside the PHY: when the byte-clock and the PHY's internal LP sequencer are not phase-aligned at the exact moment of the first SoT, the LP-00 state can be entirely skipped. With the timers set to minimum values (below spec), the window for this race is widened.</li></ul>
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<ul><li>At your target values (THS_ZERO=10, THS_PREPARE=3), the total LP-low budget would be ~241 ns — enough to reliably survive any clock alignment variation.</li></ul>
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<ul><li></li></ul>
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<p>## 4. HS Signal Quality Assessment</p>
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<p>### Consistent Observations (All 30 Captures)</p>
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<p>| Parameter | CLK Lane | DAT0 Lane | Assessment |<br>|---|---|---|---|<br>| Vdiff amplitude | 165-167 mV | 181-200 mV | ✓ Within 140-270 mV but <strong>low margin on CLK</strong> |<br>| Common mode | +27 to +31 mV | -6 to 0 mV | ✓ Acceptable |<br>| Rise time 20-80% | 164-165 ps | 159-188 ps | ✓ Within spec |<br>| Jitter p-p | 136-171 ps | — | ✓ Acceptable for 432 Mbit/s |<br>| Jitter RMS | 50-54 ps | — | ✓ Within budget |<br>| Clock frequency | 213-219 MHz | — | ⚠ Some variance |</p>
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<p>### Concerns</p>
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<ol><li><strong>CLK amplitude asymmetry</strong>: Positive swing +194 mV, negative swing -137 mV consistently. The ~57 mV imbalance (28 mV common-mode offset) is within spec but suggests slight impedance mismatch on CLK+ vs CLK- or a DC offset in the driver.</li></ol>
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<ol><li><strong>Below-140 mV samples</strong>: Present in virtually every capture on both CLK (7-174 samples) and DAT (19-3488 samples). These are transition-region samples and ISI-induced eye closure. The DAT lane count of 3488 (Capture 0166, a flicker event) is notably high, suggesting the failed SoT may cause the data pattern to degrade.</li></ol>
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<ol><li><strong>DAT0 "only negative swings"</strong>: Many captures show DAT0 with only negative Vdiff in the sig window. This is a <strong>probe alignment/trigger issue</strong> — the oscilloscope window is capturing a run of identical bits. Not a hardware fault.</li></ol>
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<p>4. <strong>DAT0 proto showing 0 mV</strong> (Captures 0149, 0152 sig): These are captures where the data lane was idle or in LP during the proto window, likely because the scope triggered before HS data started. Capture 0152 is a flicker event — the bridge never locked, so data may have been intermittent.</p>
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<ul><li></li></ul>
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<p>## 5. Supply Rail Analysis</p>
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<p>### 1.8 V VDDIO (All 30 Captures)</p>
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<p>| Parameter | Range | Spec | Status |<br>|---|---|---|---|<br>| Mean voltage | 1.7647 – 1.7704 V | 1.71 – 1.89 V | ✓ |<br>| Min voltage | 1.7520 – 1.7600 V | 1.71 V | ✓ |<br>| Droop depth | 8.7 – 13.1 mV | — | ✓ Acceptable |<br>| Ripple RMS | 5.52 – 6.20 mV | — | ✓ Low |</p>
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<p><strong>Supply is NOT correlated with flicker.</strong> The four flicker captures (0141, 0147, 0152, 0166) show droop depths of 10.7, 9.8, 10.1, 10.1 mV respectively — entirely within the normal range of non-flicker captures. Mean voltage and ripple are similarly indistinguishable between good and bad sessions.</p>
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<p>The 1.8 V rail is <strong>clean and stable</strong>. The LP-11 voltage of ~1.015 V (consistently across all captures) is within spec (1.0-1.45 V) but notably at the low end. This is normal for the i.MX 8M Mini PHY LP driver with 1.77 V supply — the LP pull-up impedance divides the voltage.</p>
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<p><strong>Conclusion: Supply is exonerated as a flicker cause.</strong></p>
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<ul><li></li></ul>
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<p>## 6. Trend Analysis</p>
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<p>### No Degradation Over Time</p>
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<p>Across the 30-capture batch spanning ~10 minutes:<br>- CLK amplitude: rock-steady at 166 ±1 mV<br>- DAT amplitude: stable at 187-200 mV<br>- Jitter: no trend (136-171 ps p-p)<br>- Supply: stable ±5 mV<br>- LP-11 voltage: stable at 1.015 ±0.001 V</p>
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<p><strong>No thermal drift, no aging, no progressive degradation.</strong> The flicker events are randomly distributed in time, consistent with a non-deterministic race condition.</p>
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<p>### LP-low Plateau Clustering</p>
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<p>The three distinct LP-low durations observed (0, 108, 342 ns) correspond to:<br>- <strong>342 ns ≈ THS_PREPARE + THS_ZERO = (5+6) × 18.5 ns × ~1.7</strong> — this factor suggests the PHY may be using half-byte-clock granularity or there's additional internal pipeline delay<br>- <strong>108 ns ≈ 6 × 18.5 ns</strong> — exactly THS_ZERO alone (LP-01 phase skipped or merged)<br>- <strong>0 ns</strong> — complete SoT sequence skip</p>
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<p>This trimodal distribution is characteristic of a PHY state machine with multiple failure modes at marginal timing settings.</p>
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<ul><li></li></ul>
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<p>## 7. Warnings and Errors Explained</p>
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<p>| Warning | Captures | Cause | Action |<br>|---|---|---|---|<br>| "LP exit duration 2-4 ns below spec min 50 ns" | 24/28 valid | <strong>Measurement artifact partially, real failure for 0 ns plateau captures.</strong> The LP-11 → LP-01 transition is very fast (~2 ns slew) but the LP-01 → LP-00 → HS-0 sequence follows. The measurement picks up the initial falling edge, not the full LP-low duration. | Use LP-low plateau as the real metric |<br>| "Only negative swings in capture window" | ~20 captures | Scope trigger captures a run of identical data bits (e.g., all-zeros blanking period). | Not a fault. Ignore for amplitude assessment; use proto captures for true amplitude |<br>| "No HS signal detected" on sig/dat | 3 captures | Window captured LP or idle period. Captures 0149, 0152 (flicker), 0163. | Trigger refinement; for 0152 this is evidence of failed data lane activation |<br>| "CLK lane in continuous HS mode" | All captures | Expected — CLK runs continuously in video-mode DSI. No LP states on CLK. | Normal operation |<br>| "[lp_dat] ERROR: index out of bounds" | Capture 0154 | Analysis script buffer overrun — LP→HS transition was at the very edge of the capture window. | Extend capture window or adjust trigger delay |<br>| "29-3488 settled samples below 140 mV" | All captures | ISI (inter-symbol interference) causing eye closure during transitions. Count varies with data pattern. | Not critical at these counts vs. total samples, but CLK's consistent below-140mV samples indicate impedance mismatch worth investigating |</p>
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<ul><li></li></ul>
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<p>## 8. Actionable Recommendations</p>
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<p>### PRIORITY 1 — Fix the PHY Timing Registers (ROOT CAUSE)</p>
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<p>The samsung-dsim driver is computing its own timing values and ignoring your target. You must force the correct values:</p>
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<p><strong>Option A: Patch the driver timing calculation</strong></p>
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<p>In `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` for NXP fork), locate `samsung_dsim_set_phy_timing()`. The driver computes timings from the bit rate using formulas that are known to be incorrect for lower bit rates. Override with:</p>
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<p>```c<br>/* Force compliant timings for 432 Mbit/s */<br>reg = DSIM_PHYTIMING_LPX(3) | DSIM_PHYTIMING_HS_EXIT(6);<br>writel(reg, base + DSIM_PHYTIMING);</p>
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<p>reg = DSIM_PHYTIMING1_CLK_PREPARE(3) | DSIM_PHYTIMING1_CLK_ZERO(17) |<br> DSIM_PHYTIMING1_CLK_POST(10) | DSIM_PHYTIMING1_CLK_TRAIL(4);<br>writel(reg, base + DSIM_PHYTIMING1);</p>
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<p>reg = DSIM_PHYTIMING2_HS_TRAIL(4) | DSIM_PHYTIMING2_HS_ZERO(10) |<br> DSIM_PHYTIMING2_HS_PREPARE(3);<br>writel(reg, base + DSIM_PHYTIMING2);<br>```</p>
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<p><strong>Option B: Post-boot register override (temporary validation)</strong></p>
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<p>```bash<br># After pipeline load, before display enable (if sequencing allows):<br>memtool mw -l 0x32e100b4=0x00000306<br>memtool mw -l 0x32e100b8=0x03110A04<br>memtool mw -l 0x32e100bc=0x00040A03<br>```</p>
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<p>⚠ This may not work if the driver re-programs registers during enable. The driver patch is the reliable fix.</p>
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<p><strong>Option C: Device tree override (if driver supports it)</strong></p>
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<p>Check if the NXP BSP's samsung-dsim binding supports `samsung,phy-timing` properties. If so</p>
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<p class="tokens">Tokens: 32516 in / 4096 out</p>
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</body>
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</html>
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