Arrive/MiPi_TEST
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Updates

Browse Source
This commit is contained in:
david rice
2026-04-13 15:03:47 +01:00
parent 17d393cbd1
commit fa96fef9ea
11 changed files with 724 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
__pycache__/analyze_captures.cpython-312.pyc
View File

Binary file not shown.

BIN
__pycache__/csv_preprocessor.cpython-312.pyc
View File

Binary file not shown.

77
analyze_captures.py
View File

@@ -38,27 +38,31 @@ REPORTS_DIR = Path(__file__).parent / "reports"
# HS bit UI = 1 / 432e6 ≈ 2.315 ns
# Byte clock = 432 / 8 = 54 MHz → 18.518 ns/byte
#
# MIPI D-PHY v1.1 minimum timings at 432 Mbit/s:
# T_LPX ≥ 50 ns
# T_HS-PREPARE 40+4·UI → 85+6·UI = 49.3–98.9 ns
# T_HS-ZERO ≥ 145+10·UI = 168.2 ns
# T_HS-TRAIL ≥ max(8·UI, 60+4·UI) = 69.3 ns
# T_HS-EXIT ≥ 100 ns
# T_CLK-PREPARE 38–95 ns
# T_CLK-ZERO ≥ 300 ns
# T_CLK-POST ≥ 60+52·UI = 180.4 ns
# T_CLK-TRAIL ≥ 60 ns
# MIPI D-PHY v1.1 Table 14 timing constraints at 432 Mbit/s (UI = 2.315 ns):
# T_LPX ≥ 50 ns
# T_HS-PREPARE 40+4·UI → 85+6·UI = 49.3–98.9 ns (individual range)
# T_HS-PREPARE+T_HS-ZERO ≥ 145+10·UI = 168.2 ns (combined minimum; no per-field min on T_HS-ZERO)
# T_HS-TRAIL ≥ max(8·UI, 60+4·UI) = 69.3 ns
# T_HS-EXIT ≥ 100 ns
# T_CLK-PREPARE 38–95 ns (individual range)
# T_CLK-PREPARE+T_CLK-ZERO ≥ 300 ns (combined minimum; no per-field min on T_CLK-ZERO)
# T_CLK-POST ≥ 60+52·UI = 180.4 ns
# T_CLK-TRAIL ≥ 60 ns
#
# In byte-clock units (÷ 18.518 ns, round up):
# TLPX = 3 (55.6 ns)
# THS_PREPARE = 3 (55.6 ns — within 49.3–98.9 ns window)
# THS_ZERO = 10 (185.2 ns ≥ 168.2 ns ✓)
# THS_TRAIL = 4 (74.1 ns ≥ 69.3 ns ✓)
# THS_EXIT = 6 (111.1 ns ≥ 100 ns ✓)
# TCLK_PREPARE = 3 (55.6 ns — within 38–95 ns ✓)
# TCLK_ZERO = 17 (314.8 ns ≥ 300 ns ✓)
# TCLK_POST = 10 (185.2 ns ≥ 180.4 ns ✓)
# TCLK_TRAIL = 4 (74.1 ns ≥ 60 ns ✓)
# Samsung DSIM field mapping (verified against kernel log output):
# PHYTIMING (0xb4): [15:8]=TLPX, [7:0]=THS_EXIT
# PHYTIMING1 (0xb8): [31:24]=TCLK_PREPARE, [23:16]=TCLK_ZERO,
# [15:8]=TCLK_POST, [7:0]=TCLK_TRAIL
# PHYTIMING2 (0xbc): [23:16]=THS_PREPARE, [15:8]=THS_ZERO, [7:0]=THS_TRAIL
#
# Kernel driver computes: clk_zero = 300 − 38 = 262 ns minimum;
# hs_zero = 145 + 10·UI − (40 + 4·UI) = 105 + 6·UI = 118.9 ns minimum
#
# Actual register values programmed by samsung-dsim driver (samsung_dsim_set_phy_ctrl):
# "Round Best" (default): PHY_TIMING=00000305, PHY_TIMING1=020e0a03, PHY_TIMING2=00030605
# → MULTIPLE D-PHY SPEC VIOLATIONS (see dsim_phytiming_round_best below)
# "Round Up": PHY_TIMING=00000306, PHY_TIMING1=030f0a04, PHY_TIMING2=00030706
# → ALL fields spec-compliant
DEVICE_CONFIG = {
"dsi_host": "NXP i.MX 8M Mini (Samsung DSIM IP, sec-dsim/samsung-dsim driver)",
"dsi_bridge": "Texas Instruments SN65DSI83 (MIPI-to-LVDS)",
@@ -75,16 +79,18 @@ DEVICE_CONFIG = {
"byte_clock_mhz": 54, # 432 / 8
"byte_period_ns": 18.518,
"vddio_v": 1.8,
# Samsung DSIM PHY timing field mapping (sec_mipi_dsim.c / samsung-dsim.c):
# PHYTIMING (0xb4): [15:8]=TLPX, [7:0]=THS_EXIT
# PHYTIMING1 (0xb8): [31:24]=TCLK_PREPARE, [23:16]=TCLK_ZERO,
# [15:8]=TCLK_POST, [7:0]=TCLK_TRAIL
# PHYTIMING2 (0xbc): [23:16]=THS_TRAIL, [15:8]=THS_ZERO, [7:0]=THS_PREPARE
# All fields in byte-clock units (÷ 18.518 ns, rounded up) per MIPI D-PHY v1.1:
"dsim_phytiming_target": {
"PHYTIMING (0xb4)": "0x00000306 (TLPX=3→55.6ns ≥50ns ✓, THS_EXIT=6→111ns ≥100ns ✓)",
"PHYTIMING1 (0xb8)": "0x03110A04 (TCLK_PREPARE=3→55.6ns, TCLK_ZERO=17→315ns ≥300ns ✓, TCLK_POST=10→185ns ≥180ns ✓, TCLK_TRAIL=4→74ns ≥60ns ✓)",
"PHYTIMING2 (0xbc)": "0x00040A03 (THS_TRAIL=4→74ns ≥69ns ✓, THS_ZERO=10→185ns ≥168ns ✓, THS_PREPARE=3→56ns within 49-99ns ✓)",
# Actual register values from kernel (samsung_dsim_set_phy_ctrl) — two rounding modes:
"dsim_phytiming_round_best": {
"PHYTIMING (0xb4)": "0x00000305 (TLPX=3→55.6ns ✓, THS_EXIT=5→92.6ns < 100ns ✗)",
"PHYTIMING1 (0xb8)": "0x020e0a03 (TCLK_PREPARE=2→37.0ns < 38ns ✗, TCLK_ZERO=14, PREP+ZERO=16bc→296ns < 300ns ✗, TCLK_POST=10→185ns ✓, TCLK_TRAIL=3→55.6ns < 60ns ✗)",
"PHYTIMING2 (0xbc)": "0x00030605 (THS_PREPARE=3→55.6ns ✓, THS_ZERO=6, PREP+ZERO=9bc→166.7ns < 168.2ns ✗, THS_TRAIL=5→92.6ns ✓)",
"verdict": "NON-COMPLIANT — 5 D-PHY violations; flicker risk at SoT",
},
"dsim_phytiming_round_up": {
"PHYTIMING (0xb4)": "0x00000306 (TLPX=3→55.6ns ✓, THS_EXIT=6→111.1ns ✓)",
"PHYTIMING1 (0xb8)": "0x030f0a04 (TCLK_PREPARE=3→55.6ns ✓, TCLK_ZERO=15, PREP+ZERO=18bc→333ns ✓, TCLK_POST=10→185ns ✓, TCLK_TRAIL=4→74.1ns ✓)",
"PHYTIMING2 (0xbc)": "0x00030706 (THS_PREPARE=3→55.6ns ✓, THS_ZERO=7, PREP+ZERO=10bc→185.2ns ✓, THS_TRAIL=6→111.1ns ✓)",
"verdict": "FULLY COMPLIANT with D-PHY v1.1 Table 14",
},
}
@@ -207,7 +213,8 @@ def process_capture(
def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
flicker_count: int = 0, total_sessions: int = 0) -> str:
cfg = DEVICE_CONFIG
target = cfg["dsim_phytiming_target"]
best = cfg["dsim_phytiming_round_best"]
up = cfg["dsim_phytiming_round_up"]
config_section = (
f"Device under test:\n"
f" DSI host: {cfg['dsi_host']}\n"
@@ -222,8 +229,12 @@ def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
f" HS UI: {cfg['hs_ui_ns']:.3f} ns\n"
f" Byte clock: {cfg['byte_clock_mhz']} MHz ({cfg['byte_period_ns']:.3f} ns/byte)\n"
f" VDDIO: {cfg['vddio_v']} V\n"
f" Target DSIM PHY timing registers (byte-clock units, MIPI D-PHY v1.1 compliant):\n"
+ "\n".join(f" {k}: {v}" for k, v in target.items())
f" DSIM PHY timing — 'Round Best' mode (D-PHY v1.1 non-compliant):\n"
+ "\n".join(f" {k}: {v}" for k, v in best.items())
+ f"\n DSIM PHY timing — 'Round Up' mode (D-PHY v1.1 fully compliant):\n"
+ "\n".join(f" {k}: {v}" for k, v in up.items())
+ f"\n NOTE: Compare captured register values against both modes above. "
f"'Round Best' has 5 spec violations that could cause non-deterministic SoT failures."
)
body = "\n\n".join(all_summaries)

111
csv_preprocessor.py
View File

@@ -425,6 +425,106 @@ def analyze_1v8_file(path: Path) -> "V1V8Metrics":
)
# ---------------------------------------------------------------------------
# DSIM PHY timing register decoder (D-PHY v1.1 Table 14 @ 432 Mbit/s, 54 MHz byte clock)
# ---------------------------------------------------------------------------
# Byte-clock period used to convert register fields (in byte-clock units) to nanoseconds.
# 54 MHz byte clock → 18.518 ns per byte clock.
_DSIM_BYTE_PERIOD_NS = 18.518
# Per-field decode table. Key = lowest 2 hex digits of register address.
# Each entry: (field_name, bit_shift, byte_mask, spec)
# spec = ("min", ns) — field_ns must be ≥ ns
# ("range", lo, hi) — field_ns must be lo ≤ x ≤ hi
# None — not individually checked (part of a combined check only)
_DSIM_PHY_FIELDS: dict[str, list] = {
"b4": [ # PHYTIMING 0x32e100b4
("TLPX", 8, 0xFF, ("min", 50.0)),
("THS_EXIT", 0, 0xFF, ("min", 100.0)),
],
"b8": [ # PHYTIMING1 0x32e100b8
("TCLK_PREPARE", 24, 0xFF, ("range", 38.0, 95.0)),
("TCLK_ZERO", 16, 0xFF, None), # combined with TCLK_PREPARE ≥ 300 ns
("TCLK_POST", 8, 0xFF, ("min", 180.4)),
("TCLK_TRAIL", 0, 0xFF, ("min", 60.0)),
],
"bc": [ # PHYTIMING2 0x32e100bc
# Field order verified against kernel logs (samsung_dsim_set_phy_ctrl):
# [23:16]=THS_PREPARE, [15:8]=THS_ZERO, [7:0]=THS_TRAIL
("THS_PREPARE", 16, 0xFF, ("range", 49.3, 98.9)),
("THS_ZERO", 8, 0xFF, None), # combined with THS_PREPARE ≥ 168.2 ns
("THS_TRAIL", 0, 0xFF, ("min", 69.3)),
],
}
# Combined (sum) checks applied after individual field decoding.
# (field_a, field_b, min_ns, label)
_DSIM_COMBINED_CHECKS = [
("TCLK_PREPARE", "TCLK_ZERO", 300.0, "TCLK_PREPARE+TCLK_ZERO"),
("THS_PREPARE", "THS_ZERO", 168.2, "THS_PREPARE+THS_ZERO"),
]
def _decode_dsim_registers(registers: list) -> list[str]:
"""
Decode DSIM PHY timing registers and return a list of annotated strings,
one per field, with D-PHY v1.1 spec compliance check results.
"""
ok = lambda c: "✓" if c else "✗ VIOLATION"
lines = []
field_ns: dict[str, float] = {}
for reg in registers:
addr_str = reg.get("address", "").lower().lstrip("0x")
val_str = reg.get("value", "0x0").lower()
suffix = addr_str[-2:] if len(addr_str) >= 2 else ""
fields = _DSIM_PHY_FIELDS.get(suffix)
if fields is None:
continue # register not in our decode table
try:
val = int(val_str, 16)
except ValueError:
lines.append(f" {reg.get('address')} : {reg.get('value')} (parse error)")
continue
reg_name = reg.get("name") or f"0x{addr_str}"
lines.append(f" {reg.get('address')} ({reg_name}) = {val_str}")
for (fname, shift, mask, spec) in fields:
raw = (val >> shift) & mask
ns = raw * _DSIM_BYTE_PERIOD_NS
field_ns[fname] = ns
if spec is None:
# shown in combined check only
lines.append(f" {fname:<16s} = {raw:3d} bc → {ns:6.1f} ns (combined check below)")
elif spec[0] == "min":
pass_check = ns >= spec[1]
lines.append(
f" {fname:<16s} = {raw:3d} bc → {ns:6.1f} ns "
f"(spec ≥ {spec[1]:.1f} ns) {ok(pass_check)}"
)
elif spec[0] == "range":
pass_check = spec[1] <= ns <= spec[2]
lines.append(
f" {fname:<16s} = {raw:3d} bc → {ns:6.1f} ns "
f"(spec {spec[1]:.1f}–{spec[2]:.1f} ns) {ok(pass_check)}"
)
# Combined sum checks
for (fa, fb, min_ns, label) in _DSIM_COMBINED_CHECKS:
if fa in field_ns and fb in field_ns:
total = field_ns[fa] + field_ns[fb]
pass_check = total >= min_ns
lines.append(
f" {label:<28s} = {total:6.1f} ns (spec ≥ {min_ns:.1f} ns) {ok(pass_check)}"
)
return lines
@dataclass
class RegDump:
"""DSI controller register snapshot read from device via memtool."""
@@ -443,9 +543,14 @@ class RegDump:
lines.append(" No registers captured")
return "\n".join(lines)
lines.append(f" Commands : {'; '.join(self.commands)}")
for r in self.registers:
name = f" ({r['name']})" if r.get("name") else ""
lines.append(f" {r['address']} : {r['value']}{name}")
decoded = _decode_dsim_registers(self.registers)
if decoded:
lines.extend(decoded)
else:
# Fallback: raw hex dump if no addresses matched decode table
for r in self.registers:
name = f" ({r['name']})" if r.get("name") else ""
lines.append(f" {r['address']} : {r['value']}{name}")
return "\n".join(lines)

2
mipi_test.py
View File

@@ -68,7 +68,7 @@ rigol_scope.connect()
# ---------------------------------------------------------------------------
def setup_scope():
"""Initialises DSO80204B for MIPI DSI signals (~210 MHz)."""
"""Initialises for MIPI DSI signals (~210 MHz)."""
print("CONFIGURING SCOPE...")
cmds = [

106
reports/20260413_095911_analysis.html Normal file
View File

@@ -0,0 +1,106 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Analysis — Captures 0137–0166</title>
<style>
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
p { line-height: 1.6; }
ol, ul { line-height: 1.8; padding-left: 24px; }
li { margin: 4px 0; }
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
padding: 16px 20px; margin-bottom: 28px; }
.flicker-alert h2 { color: #e65100; margin-top: 0; }
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
table { border-collapse: collapse; width: 100%; }
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
@media print { body { margin: 20px; } }
</style>
</head>
<body>
<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 1 of 30 display load sessions (3%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0164</td><td>20260413_095340</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.015 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0137</td><td>20260413_094356</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0138</td><td>20260413_094418</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260413_094439</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260413_094501</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260413_094523</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260413_094544</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260413_094606</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260413_094627</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260413_094649</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260413_094710</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260413_094732</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260413_094754</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260413_094816</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260413_094837</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260413_094859</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260413_094920</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260413_094942</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260413_095003</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260413_095025</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260413_095047</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260413_095108</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260413_095130</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260413_095152</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260413_095213</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260413_095235</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260413_095257</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260413_095318</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260413_095340</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260413_095402</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260413_095423</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-13 09:59:11 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0137–0166 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166</p>
<p>## 1. Consistent Spec Concerns</p>
<p>### Register Timing Violations (100% of captures — systemic)<br>Every single capture shows the <strong>&#x27;Round Best&#x27; register set</strong> with identical 5 D-PHY v1.1 violations:</p>
<p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|-----------|-----------|--------|----------|-----------|<br>| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
<p><strong>Critical insight:</strong> The THS_PREPARE+THS_ZERO violation (1.5 ns short) directly controls the data-lane SoT sequence. This is the interval during which the receiver must detect the HS-0 state and synchronise to the incoming data. Being 1.5 ns short means the SN65DSI83 has ~1% less time to complete bit-sync. Combined with the TCLK_PREPARE+TCLK_ZERO shortfall (3.7 ns), the clock lane&#x27;s HS entry is also marginal — the receiver may not have a stable clock reference when data arrives.</p>
<p>### LP Exit Duration (Pervasive)<br><strong>24 of 29 captures with LP data</strong> report LP exit → HS durations of 0–4 ns (spec ≥ 50 ns). This is not a measurement artefact — it reflects the PHY skipping or severely truncating the LP-01 → LP-00 states on the data lane. The programmed THS_PREPARE+THS_ZERO budget is too short to guarantee the LP-00 state is held long enough for the bridge&#x27;s LP receiver to register it.</p>
<p>Only 5 captures show compliant LP exit (108–348 ns): 0137, 0139, 0148, 0159, 0166.</p>
<p>### LP-11 Voltage<br>LP-11 voltage is consistently 1.013–1.016 V across all captures (spec 1.0–1.45 V). This is <strong>at the absolute floor</strong> of the D-PHY spec (VOH ≥ VIH_LP = ~1.0 V). The 1.8 V VDDIO is ~1.765 V (2% below nominal) and the LP drivers are delivering only 56% of VDDIO. This leaves <strong>no noise margin</strong> — any additional drop could cause LP-11 to be misread.</p>
<p>### HS Amplitude<br>- <strong>CLK lane:</strong> Stable at 165–167 mV differential — passes spec (140–270 mV) but with only ~26 mV margin above the 140 mV floor.<br>- <strong>DAT0 lane:</strong> 186–224 mV nominal, but <strong>persistent sub-140 mV samples</strong> in every capture (16 to 9742 samples). This indicates ISI-induced eye closure during data transitions.<br>- <strong>CLK common mode offset:</strong> Consistently +28–31 mV (positive skew), indicating slight impedance imbalance on CLK±.</p>
<p>### Single-Ended HS Amplitude (LP capture)<br>Bimodal: captures show either ~106–118 mV or ~16–32 mV single-ended HS amplitude. The low-amplitude group likely represents captures where the scope triggered on a blanking interval or the data lane was in LP-idle between video lines.</p>
<ul><li></li></ul>
<p>## 2. Trends Over Captures</p>
<p>| Parameter | Range | Trend |<br>|-----------|-------|-------|<br>| CLK Vdiff | 165.6–166.8 mV | <strong>Rock stable</strong> — no drift |<br>| DAT0 Vdiff | 186.5–223.6 mV | Occasional jumps (0140, 0153, 0161 show ~224 mV) — likely different data patterns |<br>| CLK jitter p-p | 141.7–177.4 ps | <strong>No trend</strong> — random variation |<br>| CLK jitter RMS | 52.2–56.6 ps | Stable |<br>| LP-11 voltage | 1.013–1.016 V | <strong>No drift</strong> — thermally stable |<br>| 1.8 V mean | 1.7644–1.7705 V | Stable |<br>| 1.8 V droop | 8.4–17.4 mV | No trend, occasional spikes (0137: 13.3, 0144: 17.4, 0154: 13.7, 0163: 13.6, 0165: 13.7) |<br>| LP-low plateau | 0–343 ns | <strong>Trimodal:</strong> 0 ns, ~108 ns, ~343 ns |<br>| DAT0 sub-140mV count | 16–9742 | High variance; spikes in 0141 (3347), 0143 (6189), 0151 (3815), 0166 (9742) |</p>
<p><strong>No progressive degradation.</strong> The system is thermally and electrically stable during a session. The variation is entirely in the SoT-moment behaviour, consistent with the bistable flicker description.</p>
<ul><li></li></ul>
<p>## 3. Anomalies</p>
<p>### FLICKER EVENT — Capture 0164<br>- <strong>LP-low plateau = 0 ns</strong> — the LP-01/LP-00 SoT states are <strong>completely absent</strong><br>- LP exit → HS = 2 ns (spec ≥ 50 ns)<br>- LP-11 voltage = 1.015 V (normal)<br>- 1.8 V supply: mean 1.7665 V, droop 10.5 mV, ripple 6.01 mV — <strong>nothing abnormal</strong><br>- Register values: identical &#x27;Round Best&#x27; violations as all other captures</p>
<p><strong>This confirms the root cause is timing, not supply:</strong> the SN65DSI83 never saw the LP-00 state, so it could not detect SoT and never locked to the HS data stream.</p>
<p>### DAT0 sig Capture Anomalies<br>- <strong>0138, 0146, 0152, 0154, 0158, 0165:</strong> sig/dat shows 0.0 mV — &quot;No HS signal detected.&quot; These captures caught the data lane during an LP-idle or blanking gap. This is a <strong>trigger timing issue</strong>, not a signal problem.<br>- <strong>0141 sig/dat:</strong> 324.8 mV differential — <strong>exceeds spec max 270 mV.</strong> This is likely an overshoot/ringing event captured during a transition. The CLK lane in the same capture is normal (166.8 mV), confirming the data lane has a reflection or impedance discontinuity that occasionally produces overshoot.</p>
<p>### DAT0 &quot;Only Negative Swings&quot;<br>Nearly every sig/dat capture shows only negative Vdiff with zero positive swing. This means the <strong>scope capture window consistently catches the same bit pattern</strong> (likely repeated zeros or sync bytes). The amplitude is likely underestimated by ~2×; true differential amplitude is probably ~390 mV, well within spec. However, the capture methodology should be verified — the sig trigger may need adjustment to catch both polarities.</p>
<p>### LP-Low Plateau Trimodal Distribution<br>| LP-low (ns) | Captures | Interpretation |<br>|-------------|----------|----------------|<br>| 0 | 0164 (flicker) | SoT completely missing — bridge fails to lock |<br>| ~108 | 0139, 0143, 0148, 0155, 0159 | Marginal — ~2 TLPX, borderline for SN65DSI83 |<br>| ~343 | All others | ~6 TLPX — this is the &quot;normal&quot; case |</p>
<p>The ~108 ns group didn&#x27;t flicker in this batch but represents a <strong>secondary risk tier</strong>. The quantisation into three discrete values suggests the PHY state machine has a timing race: it either completes the full LP-01→LP-00 sequence (~343 ns), partially completes it (~108 ns), or skips it entirely (0 ns / flicker).</p>
<p>### Capture 0145 — LP Data Processing Error<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP capture buffer was exactly full, causing an off-by-one indexing error in post-processing. <strong>No LP data for this capture.</strong> This is a script bug, not a signal issue.</p>
<ul><li></li></ul>
<p>## 4. Supply Correlation Analysis</p>
<p>| Metric | Flicker Capture (0164) | Non-Flicker Mean (n=28) | Correlation |<br>|--------|----------------------|------------------------|-------------|<br>| 1.8 V mean | 1.7665 V | 1.7658 V | None |<br>| 1.8 V min | 1.7560 V | 1.7556 V | None |<br>| Droop depth | 10.5 mV | 10.6 mV | None |<br>| Ripple RMS | 6.01 mV | 5.76 mV | None |</p>
<p><strong>No supply correlation whatsoever.</strong> The 1.8 V rail is well within spec (1.71–1.89 V) in all captures, droop is modest (&lt; 18 mV), and the flicker capture has completely average supply behaviour. The LP-11 voltage at 1.015 V in the flicker capture is indistinguishable from non-flicker captures. <strong>Supply is definitively ruled out as a contributing factor.</strong></p>
<ul><li></li></ul>
<p>## 5. WARNING/ERROR Explanation</p>
<p>| Warning | Cause | Action |<br>|---------|-------|--------|<br>| &quot;CLK lane is in continuous HS mode — LP states not expected on CLK&quot; | Normal — DSIM runs CLK in continuous HS mode per SN65DSI83 requirement | None needed |<br>| &quot;LP exit duration N ns below spec min 50 ns&quot; | THS_PREPARE+THS_ZERO too short (166.7 ns vs 168.2 ns spec); PHY truncates LP-00 state non-deterministically | <strong>Switch to &#x27;Round Up&#x27; registers</strong> |<br>| &quot;Only negative swings in capture window&quot; | Repetitive bit pattern in short sig capture window | Widen sig capture window or trigger on random data |<br>| &quot;No HS signal detected — line may be in LP state or idle&quot; | Trigger caught blanking interval | Add trigger holdoff or qualify trigger on active video |<br>| &quot;N settled samples below 140 mV&quot; | ISI eye closure during transitions; amplitude near spec floor | Normal for 432 Mbit/s with this trace geometry |<br>| &quot;Vdiff 325 mV above spec max 270 mV&quot; (0141) | Impedance mismatch causing overshoot on data lane | Check DAT0± trace impedance, termination, via stubs |<br>| &quot;index 200000 out of bounds&quot; (0145) | Off-by-one bug in LP analysis script | Fix: use `&lt; len(array)` not `&lt;= len(array)` |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### PRIMARY FIX (Critical — eliminates root cause)<br><strong>Switch from &#x27;Round Best&#x27; to &#x27;Round Up&#x27; PHY timing registers:</strong></p>
<p>```<br># In device tree or driver override:<br>DSIM_PHYTIMING (0xb4) = 0x00000306 # THS_EXIT=6 → 111.1 ns ✓<br>DSIM_PHYTIMING1 (0xb8) = 0x030f0a04 # TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4 ✓<br>DSIM_PHYTIMING2 (0xbc) = 0x00030706 # THS_ZERO=7, THS_TRAIL=6 ✓<br>```</p>
<p>This eliminates all 5 D-PHY violations. The key change is <strong>THS_PREPARE+THS_ZERO = 10 bc (185.2 ns)</strong> vs the current 9 bc (166.7 ns) — an extra 18.5 ns for the bridge to detect LP-00 and synchronise. This directly addresses the non-deterministic SoT failure.</p>
<p><strong>Implementation path:</strong> In the `samsung-dsim` driver (`drivers/gpu/drm/bridge/samsung-dsim.c`), the timing calculation function `samsung_dsim_set_phy_ctrl()` uses a rounding mode. The default rounds to the nearest byte-clock (&#x27;Round Best&#x27;). Override this to always round up:<br>- Patch the driver to use `DIV_ROUND_UP` instead of `DIV_ROUND_CLOSEST` for all timing parameters, OR<br>- Apply the register values directly via device tree `phy-timing` properties if supported by your BSP.</p>
<p>### SECONDARY (Recommended — improves margin)<br>1. <strong>Investigate LP-11 voltage:</strong> 1.015 V is technically compliant but dangerously low. Check if the VDDIO_MIPI domain has a series resistance or if LP pull-ups are undersized. The SN65DSI83 datasheet specifies VIH_LP ≥ 1.0 V, so 1.015 V gives only 15 mV of noise margin. If possible, ensure VDDIO is at 1.80 V nominal (currently 1.766 V — check LDO/DCDC output voltage setting and load regulation).</p>
<ol><li><strong>Investigate DAT0 impedance:</strong> The 324.8 mV overshoot in Capture 0141 and the consistent CLK common-mode offset (+29 mV) suggest minor impedance discontinuities. Review:</li><li>DAT0± trace impedance (target 100Ω differential)</li><li>Via stubs at connector transitions</li><li>SN65DSI83 input termination (internal 100Ω)</li></ol>
<ol><li><strong>Increase CLK amplitude margin:</strong> CLK Vdiff at 166 mV with sub-140 mV samples means the eye is marginal. If the i.MX 8M Mini DPHY allows TX emphasis or amplitude adjustment (DSIM_PLLCTRL or analog trim registers), increase CLK drive strength by one step.</li></ol>
<p>### TERTIARY (Measurement improvement)<br>4. Fix the LP analysis script off-by-one error (Capture 0145).<br>5. Adjust sig/dat trigger to capture both positive and negative differential swings for accurate amplitude measurement.<br>6. Consider a longer proto capture window to reduce the variability in sub-140 mV sample counts.</p>
<ul><li></li></ul>
<p>## 7. Summary</p>
<p><strong>The system is running non-compliant D-PHY timing (&#x27;Round Best&#x27; mode) with 5 spec violations that create a narrow, non-deterministic SoT failure window.</strong> The flicker event (Capture 0164, LP-low = 0 ns) is a direct consequence: the programmed THS_PREPARE+THS_ZERO is 1.5 ns short of spec, causing the LP-00 state to be occasionally skipped entirely, which prevents the SN65DSI83 from detecting Start-of-Transmission and locking to HS data. Supply rail, temperature, and HS signal quality are all stable and uncorrelated with the failure.</p>
<p><strong>Switching to the &#x27;Round Up&#x27; register set (0x00000306 / 0x030f0a04 / 0x00030706) will make all timing parameters D-PHY v1.1 compliant and is expected to eliminate the intermittent flicker.</strong> This is a software-only change with no hardware modification required. The 3% flicker rate at current timing margins should drop to 0% with the added ~18.5 ns of THS_ZERO headroom.</p>
<p class="tokens">Tokens: 45384 in / 3941 out</p>
</body>
</html>

115
reports/20260413_110338_analysis.html Normal file
View File

@@ -0,0 +1,115 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Analysis — Captures 0303–0332</title>
<style>
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
p { line-height: 1.6; }
ol, ul { line-height: 1.8; padding-left: 24px; }
li { margin: 4px 0; }
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
padding: 16px 20px; margin-bottom: 28px; }
.flicker-alert h2 { color: #e65100; margin-top: 0; }
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
table { border-collapse: collapse; width: 100%; }
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
@media print { body { margin: 20px; } }
</style>
</head>
<body>
<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 1 of 30 display load sessions (3%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0312</td><td>20260413_105141</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.1 ns</td><td>1.016 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0303</td><td>20260413_104826</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0304</td><td>20260413_104847</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0305</td><td>20260413_104909</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260413_104931</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260413_104952</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260413_105014</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260413_105036</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260413_105058</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260413_105119</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260413_105141</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260413_105203</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260413_105225</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260413_105247</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260413_105309</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260413_105331</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260413_105352</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260413_105414</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260413_105435</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260413_105457</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260413_105519</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260413_105541</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260413_105602</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260413_105624</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260413_105646</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260413_105708</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260413_105729</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260413_105751</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260413_105813</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260413_105834</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260413_105856</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-13 11:03:38 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0303–0332 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0303–0332 (30 sessions)</p>
<ul><li></li></ul>
<p>## 1. Consistent Spec Concerns</p>
<p>### A. PHY Timing Registers — 5 D-PHY v1.1 Violations (ALL 30 captures, 100%)</p>
<p>Every single capture shows identical register values (`Round Best` mode), confirming the driver is not applying the `Round Up` corrections:</p>
<p>| Parameter | Programmed | Actual | Spec Min | Deficit |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc → 92.6 ns | — | 100.0 ns | <strong>−7.4 ns</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc → 37.0 ns | — | 38.0 ns | <strong>−1.0 ns</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc → 55.6 ns | — | 60.0 ns | <strong>−4.4 ns</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc → 296.3 ns | — | 300.0 ns | <strong>−3.7 ns</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc → 166.7 ns | — | 168.2 ns | <strong>−1.5 ns</strong> |</p>
<p><strong>These are not marginal — they are hard violations.</strong> The SN65DSI83 must detect the SoT sequence within D-PHY spec windows. When the PHY&#x27;s TCLK_PREPARE is 1 ns short of the 38 ns floor and THS_PREPARE+THS_ZERO is 1.5 ns below the combined minimum, the bridge&#x27;s internal state machine has almost no margin to recognize the HS entry.</p>
<p>### B. LP Exit Duration — Systematically Violated</p>
<p>| Metric | Good captures (5/30) | Typical captures (22/30) | Flicker capture 0312 |<br>|---|---|---|---|<br>| LP exit → HS | <strong>348 ns</strong> ✓ | <strong>1–4 ns</strong> ✗ | <strong>0 ns</strong> ✗ |<br>| LP-low plateau | 342–343 ns | 108–343 ns | <strong>0 ns</strong> ✗ |</p>
<ul><li><strong>26 of 30 captures</strong> (87%) show LP exit durations of 1–4 ns — far below the 50 ns D-PHY minimum. This means the LP-01 → LP-00 state sequence required by the SoT protocol is either absent or completed in under one oscilloscope sample.</li><li>Only 5 captures (0305, 0316, 0326, 0328, 0329, 0332) show compliant 348 ns LP exit durations. <strong>These are the captures where the measurement resolved the full LP-01/LP-00 sequence.</strong></li><li>The fact that most &quot;good&quot; sessions also show ~2–4 ns LP exit suggests the measurement resolution may not always capture LP-01/LP-00 properly, <strong>but</strong> the flicker event (0312) shows LP-low = 0 ns, meaning the SoT sequence was genuinely absent or catastrophically compressed.</li></ul>
<p>### C. HS Differential Amplitude — Clock Lane Marginal</p>
<ul><li><strong>Clock lane Vdiff</strong>: 164.2–166.9 mV — nominally above the 140 mV floor but with <strong>28–230 settled samples below 140 mV</strong> in every proto capture. The negative half-swing is consistently ~30 mV weaker than the positive half (typ. +194 mV / −137 mV), producing a <strong>+28 mV common-mode offset</strong>.</li><li><strong>Data lane Vdiff</strong>: 178–223 mV median — healthy, but <strong>up to 12,596 settled samples below 140 mV</strong> (capture 0326). This is ISI/transition-related undershoot.</li></ul>
<p>### D. LP-11 Voltage — Consistent but Low</p>
<ul><li>LP-11 = <strong>1.014–1.016 V</strong> across all captures. The D-PHY spec requires ≥ 1.0 V (for 1.2 V VDDIO) but at 1.8 V VDDIO the expected LP-high is ~1.2 V. The <strong>1.015 V measured value</strong> is suspiciously low — only 15 mV above the absolute floor. This suggests either the LP driver pull-up impedance is too high, the 1.8 V rail is being divided down, or there is excessive loading on the LP lines (SN65DSI83 input + routing parasitics).</li></ul>
<ul><li></li></ul>
<p>## 2. Trends Over 30 Captures</p>
<p>### No Drift Detected — The System is Stationary</p>
<p>| Parameter | Min | Max | σ | Trend |<br>|---|---|---|---|---|<br>| CLK Vdiff | 165.0 mV | 166.9 mV | &lt; 0.5 mV | Flat |<br>| CLK jitter p-p | 147.3 ps | 171.8 ps | ~6 ps | Flat (noise) |<br>| CLK rise time | 164.3 ps | 166.0 ps | &lt; 1 ps | Flat |<br>| CLK frequency | 213.4–219.2 MHz | — | ~1.5 MHz | Measurement window variance only |<br>| 1.8 V mean | 1.764–1.770 V | — | ~2 mV | Flat |<br>| 1.8 V droop | 8.1–16.1 mV | — | ~2 mV | Flat |<br>| LP-11 voltage | 1.014–1.016 V | — | &lt; 1 mV | Flat |<br>| LP-11 duration | 1.73 µs | 1.73 µs | 0 | Constant |</p>
<p><strong>Conclusion: This is not a degradation or drift problem.</strong> The failure mode is purely stochastic at the SoT moment — consistent with a timing-margin race condition.</p>
<ul><li></li></ul>
<p>## 3. Anomalies</p>
<p>### 🔴 CRITICAL — Capture 0312: Confirmed Flicker Event<br>- <strong>LP-low plateau = 0 ns</strong> — the SoT LP-01 → LP-00 sequence was entirely absent<br>- <strong>LP exit → HS = 0 ns</strong> — the data lane jumped directly from LP-11 to HS with no intermediate states<br>- <strong>HS single-ended amplitude = 32 mV</strong> (vs ~108 mV typical) — the bridge never locked to HS, so HS data was essentially absent/garbage on that first burst<br>- <strong>LP-11 voltage = 1.016 V</strong> — marginally *higher* than average (not lower), ruling out supply droop as the trigger<br>- <strong>1.8 V supply: mean 1.769 V, droop 9.1 mV</strong> — actually *better* than average, ruling out supply sag</p>
<p><strong>Root cause of this specific event:</strong> The PHY transitioned from LP-11 directly to HS without executing the LP-01 → LP-00 SoT sequence. The SN65DSI83 never saw SoT, never entered HS receive mode, and remained stuck. This is a <strong>PHY state machine race condition</strong> exacerbated by the 5 timing violations.</p>
<p>### 🟡 Capture 0307: DAT0 Proto Shows 0 mV<br>- Data lane proto amplitude = 0.0 mV — &quot;No HS signal detected&quot;<br>- This is likely a <strong>trigger/capture timing issue</strong> where the proto window landed during an LP or blanking period, not a genuine signal absence (sig capture shows 193.7 mV, LP shows valid HS burst). <strong>Not a flicker event but a measurement artifact.</strong></p>
<p>### 🟡 Recurring: &quot;Only negative swings in capture window&quot;<br>- 27 of 30 dat sig captures show only negative swings. This is a <strong>probe/trigger alignment artifact</strong> — the high-res window consistently lands on the same phase of the data pattern. The amplitude is still correctly measured from the negative excursion. <strong>Not a signal integrity concern.</strong></p>
<p>### 🟡 LP-low Plateau Bimodal Distribution<br>- <strong>~342–343 ns</strong> (majority): Full LP-00 plateau resolved<br>- <strong>~108 ns</strong> (captures 0307, 0313, 0314, 0325, 0330): Shortened — possibly the measurement caught LP-01 but missed part of LP-00, or the PHY genuinely shortened the low period<br>- <strong>0 ns</strong> (capture 0312): Complete SoT failure → flicker</p>
<p>This 342 → 108 → 0 ns distribution suggests the SoT LP-low duration has <strong>significant jitter</strong> — it&#x27;s not always 342 ns. The 108 ns captures may represent borderline events where the bridge barely locked.</p>
<ul><li></li></ul>
<p>## 4. Supply Correlation Analysis</p>
<p>| Capture | LP-low (ns) | LP exit (ns) | Flicker? | 1.8V Mean (V) | Droop (mV) | Ripple RMS (mV) |<br>|---|---|---|---|---|---|---|<br>| 0312 (flicker) | <strong>0</strong> | <strong>0</strong> | <strong>YES</strong> | 1.7691 | 9.1 | 5.46 |<br>| 0305 (good LP) | 343 | 348 | no | 1.7658 | 13.8 | 5.86 |<br>| 0316 (good LP) | 343 | 348 | no | 1.7641 | 16.1 | 5.84 |<br>| 0322 (bad LP) | 343 | 4 | no | 1.7641 | 16.1 | 5.73 |</p>
<p><strong>No correlation between supply droop/ripple and SoT failures.</strong> The flicker capture (0312) had the <strong>best</strong> supply conditions in the batch (highest mean, lowest droop). Captures with the highest droop (16.1 mV in 0316, 0322) showed no flicker.</p>
<p><strong>The 1.8 V supply is not the root cause.</strong> The supply is healthy at 1.764–1.770 V with &lt; 17 mV droop — well within the 1.71–1.89 V spec.</p>
<ul><li></li></ul>
<p>## 5. Warning/Error Explanation</p>
<p>| Warning | Frequency | Likely Cause | Action |<br>|---|---|---|---|<br>| &quot;LP exit duration N ns below spec min 50 ns&quot; | 25/30 (83%) | <strong>PHY timing registers underprogram THS_PREPARE+THS_ZERO and TCLK_PREPARE</strong> — the SoT sequence is too fast for the scope (and bridge) to resolve individual LP-01/LP-00 states | Switch to `Round Up` registers |<br>| &quot;CLK lane in continuous HS mode&quot; | 30/30 (100%) | <strong>Expected</strong> — DSI video mode drives CLK continuously; LP-11/SoT only occurs on data lanes | No action needed |<br>| &quot;Only negative swings in capture window&quot; | 27/30 (90%) | High-res sig window triggers on consistent data phase; asymmetric capture | Consider random trigger offset; <strong>not a signal problem</strong> |<br>| &quot;N settled samples below 140 mV&quot; | 30/30 (100%) | ISI/transition undershoot during bit transitions; clock lane asymmetric swing | Monitor; acceptable if median is above 140 mV |<br>| &quot;No HS signal detected&quot; (0307 proto/dat) | 1/30 (3%) | Proto window landed during blanking/LP interval | Retrigger or extend window; <strong>measurement artifact</strong> |<br>| &quot;FLICKER SUSPECT: LP-low plateau absent&quot; (0312) | 1/30 (3%) | <strong>Genuine SoT failure — PHY skipped LP-01/LP-00</strong> | <strong>Root cause of flicker; fix registers</strong> |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### 🔴 IMMEDIATE — Switch to &#x27;Round Up&#x27; PHY Timing (Primary Fix)</p>
<p>Patch the samsung-dsim / sec-dsim driver to program `Round Up` values:</p>
<p>```<br>DSIM_PHYTIMING (0xb4): 0x00000306 → THS_EXIT=6 (111.1 ns ✓)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04 → TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4<br>DSIM_PHYTIMING2 (0xbc): 0x00030706 → THS_ZERO=7, THS_TRAIL=6<br>```</p>
<p>This eliminates all 5 D-PHY violations. Specifically:<br>- <strong>TCLK_PREPARE</strong> 37→55.6 ns: +18.6 ns margin above 38 ns floor<br>- <strong>THS_PREPARE+THS_ZERO</strong> 166.7→185.2 ns: +17 ns margin above 168.2 ns floor<br>- <strong>TCLK_PREPARE+TCLK_ZERO</strong> 296.3→333.3 ns: +33 ns margin above 300 ns floor<br>- <strong>THS_EXIT</strong> 92.6→111.1 ns: +11 ns margin above 100 ns floor<br>- <strong>TCLK_TRAIL</strong> 55.6→74.1 ns: +14 ns margin above 60 ns floor</p>
<p>The extra byte-clock per parameter costs ~18.5 ns of SoT overhead per frame entry — negligible at 60 Hz.</p>
<p><strong>Implementation:</strong> In the driver&#x27;s `samsung_dsim_set_phy_timing()` or equivalent, change the rounding mode from truncation to ceiling for all timing parameters. Alternatively, apply direct register overrides via device-tree `phy-timing` properties if supported.</p>
<p>### 🟡 SECONDARY — Investigate LP-11 Voltage (1.015 V)</p>
<p>At 1.8 V VDDIO, LP-high should be ~1.2 V (VDDIO × 0.67 typ). The measured 1.015 V is 15% low. Check:<br>1. <strong>Series resistance</strong> in LP path (PCB trace, protection resistors, ESD diodes)<br>2. <strong>SN65DSI83 LP input current</strong> loading — the DSI83 LP-mode input impedance may be lower than expected<br>3. <strong>VDDIO actual voltage</strong> at the PHY pad (not just at the regulator) — 1.766 V at the regulator minus PCB IR drop</p>
<p>While 1.015 V is technically compliant, it leaves zero margin and may contribute to the bridge&#x27;s inability to cleanly detect LP state transitions.</p>
<p>### 🟢 OPTIONAL — Clock Lane Amplitude Asymmetry</p>
<p>The consistent +194/−137 mV asymmetry (28 mV common-mode offset) on CLK suggests a slight impedance mismatch between CLK+ and CLK−. Check:<br>1. Differential pair trace length matching (&lt; 5 mil skew)<br>2. AC coupling capacitors (if present) for value tolerance<br>3. SN65DSI83 CLK input termination</p>
<p>This is not causing flicker but degrades noise margin.</p>
<ul><li></li></ul>
<p>## 7. Summary</p>
<p><strong>The system is running with 5 D-PHY v1.1 timing violations caused by the `Round Best` register programming mode, which truncates timing parameters to the nearest byte-clock below spec minimums.</strong> The most critical violations — THS_PREPARE+THS_ZERO (1.5 ns short) and TCLK_PREPARE (1.0 ns short) — compress the SoT handshake window to the point where the SN65DSI83 bridge&#x27;s SoT detector has essentially zero margin. On ~3% of pipeline startups, the PHY&#x27;s SoT state machine races past LP-01/LP-00 so quickly (or skips them entirely, as in capture 0312) that the bridge fails to enter HS receive mode, producing permanent flicker for that session.</p>
<p><strong>Switching to the `Round Up` register values (PHYTIMING=0x306, PHYTIMING1=0x030f0a04, PHYTIMING2=0x00030706) will eliminate all 5 violations with comfortable margin and is expected to resolve the intermittent flicker completely.</strong> The 1.8 V supply is healthy and not a contributing factor. No hardware changes are required — this is a software-only fix in the DSIM PHY timing configuration.</p>
<p class="tokens">Tokens: 45578 in / 4027 out</p>
</body>
</html>

105
reports/20260413_120809_analysis.html Normal file
View File

@@ -0,0 +1,105 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Analysis — Captures 0469–0498</title>
<style>
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
p { line-height: 1.6; }
ol, ul { line-height: 1.8; padding-left: 24px; }
li { margin: 4px 0; }
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
padding: 16px 20px; margin-bottom: 28px; }
.flicker-alert h2 { color: #e65100; margin-top: 0; }
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
table { border-collapse: collapse; width: 100%; }
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
@media print { body { margin: 20px; } }
</style>
</head>
<body>
<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 2 of 30 display load sessions (7%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0476</td><td>20260413_115521</td><td>dat</td><td style='color:red'>0.2 ns</td><td>347.8 ns</td><td>1.015 V</td></tr><tr><td>0480</td><td>20260413_115648</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.3 ns</td><td>1.014 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0469</td><td>20260413_115249</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0470</td><td>20260413_115311</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0471</td><td>20260413_115333</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0472</td><td>20260413_115354</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0473</td><td>20260413_115416</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0474</td><td>20260413_115438</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0475</td><td>20260413_115500</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0476</td><td>20260413_115521</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0477</td><td>20260413_115543</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0478</td><td>20260413_115605</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0479</td><td>20260413_115626</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0480</td><td>20260413_115648</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0481</td><td>20260413_115710</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0482</td><td>20260413_115732</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0483</td><td>20260413_115753</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0484</td><td>20260413_115815</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0485</td><td>20260413_115836</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0486</td><td>20260413_115858</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0487</td><td>20260413_115920</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0488</td><td>20260413_115941</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0489</td><td>20260413_120003</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0490</td><td>20260413_120025</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0491</td><td>20260413_120046</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0492</td><td>20260413_120108</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0493</td><td>20260413_120130</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0494</td><td>20260413_120151</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0495</td><td>20260413_120213</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0496</td><td>20260413_120235</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0497</td><td>20260413_120256</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0498</td><td>20260413_120318</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-13 12:08:09 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0469–0498 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0469–0498</p>
<p>## 1. Consistent Spec Concerns</p>
<p>### Register Timing Violations (100% of captures — systemic)<br>All 30 captures show identical register values confirming the system is running <strong>&#x27;Round Best&#x27; mode</strong> with <strong>5 D-PHY v1.1 violations</strong>:</p>
<p>| Parameter | Measured | Spec Min | Deficit | Severity |<br>|---|---|---|---|---|<br>| THS_EXIT | 92.6 ns | 100.0 ns | −7.4 ns (7.4%) | <strong>High — SoT critical</strong> |<br>| TCLK_PREPARE | 37.0 ns | 38.0 ns | −1.0 ns (2.6%) | <strong>High — clock SoT</strong> |<br>| TCLK_TRAIL | 55.6 ns | 60.0 ns | −4.4 ns (7.3%) | Moderate |<br>| TCLK_PREPARE+TCLK_ZERO | 296.3 ns | 300.0 ns | −3.7 ns (1.2%) | <strong>High — clock SoT</strong> |<br>| THS_PREPARE+THS_ZERO | 166.7 ns | 168.2 ns | −1.5 ns (0.9%) | <strong>High — data SoT</strong> |</p>
<p><strong>These are the root cause of the intermittent flicker.</strong> All five violations affect the SoT handshake sequence, and all shortfalls are within ~1 byte-clock (18.5 ns) of the spec minimum — small enough that PVT (process/voltage/temperature) variation and internal clock jitter make the outcome non-deterministic, exactly matching the observed bistable behaviour.</p>
<p>### LP Exit Duration — Universally Violated<br>- <strong>26 of 27 measurable captures</strong> show LP exit → HS of <strong>0–4 ns</strong> (spec ≥ 50 ns). Only 4 captures (0470, 0485, 0487, 0496) show ~113 ns, and Capture 0494 shows ~348 ns.<br>- This means the LP-01 → LP-00 intermediate states are being traversed in ≤ 4 ns rather than the required ≥ 50 ns. The PHY is skipping or compressing the SoT escape sequence.<br>- <strong>Direct cause:</strong> THS_EXIT = 5 bc (92.6 ns) is below the 100 ns minimum, and the too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns) means the data lane does not hold LP-00 long enough for the bridge to recognise SoT.</p>
<p>### LP-Low Plateau — Bimodal Distribution<br>The LP-low plateau clusters at three values:<br>- <strong>~108 ns</strong> (14 captures) — marginal but functional<br>- <strong>~343 ns</strong> (13 captures) — comfortable<br>- <strong>0 ns</strong> (2 captures: <strong>0476 and 0480</strong>) — <strong>both are confirmed flicker events</strong></p>
<p>The 0 ns plateau means the SN65DSI83 never sees LP-00 at all. With THS_PREPARE+THS_ZERO only 1.5 ns under spec, the PHY occasionally produces a prepare+zero sequence so short that LP-00 vanishes entirely from the wire. The bridge cannot detect SoT, never locks to the HS data stream, and flickers indefinitely.</p>
<p>### HS Voltage Below 140 mV Threshold<br>Every capture shows some samples below the 140 mV D-PHY minimum:<br>- <strong>CLK lane:</strong> 15–269 sub-threshold samples per capture (consistent, moderate)<br>- <strong>DAT0 lane:</strong> 2–9142 sub-threshold samples (highly variable)</p>
<p>The data lane violation count is notably higher in flicker captures: <strong>0476 has 2357, 0480 has 7209</strong> (the two worst after 0486&#x27;s 9142). This suggests that when the SoT sequence is malformed, the bridge misaligns to the HS stream and the receiver samples data at sub-optimal points, inflating the below-140 mV count. This is likely a consequence of SoT failure, not a cause.</p>
<p>### LP-11 Voltage — Consistently Low<br>- Range: <strong>1.014–1.016 V</strong> across all captures<br>- D-PHY spec: <strong>1.0–1.45 V</strong> → technically passing but at the <strong>absolute floor</strong> of the valid range<br>- Expected LP-11 with 1.8 V VDDIO: ~1.2 V (with typical LP driver divider)<br>- <strong>1.015 V is 200 mV below expected</strong>, suggesting either excessive resistive drop in the LP driver path, impedance mismatch on the LP lines, or a weak pull-up/driver configuration in the PHY.<br>- While within spec, this low LP-11 voltage reduces the noise margin for LP state detection by the SN65DSI83 to only <strong>~15 mV</strong> above the LP-11 recognition threshold. This further degrades the reliability of LP state transitions during SoT.</p>
<p>## 2. Trends Across Captures</p>
<p>### No Significant Drift<br>| Parameter | Range | Trend |<br>|---|---|---|<br>| CLK Vdiff amplitude | 165.4–166.0 mV | Flat — no degradation |<br>| DAT0 Vdiff amplitude | 186.5–199.8 mV | Flat — normal variation |<br>| CLK jitter (RMS) | 53.2–56.4 ps | Flat |<br>| CLK jitter (p-p) | 142.6–178.4 ps | Flat |<br>| Rise time (CLK/DAT) | 147.9–184.6 ps | Flat |<br>| LP-11 voltage | 1.014–1.016 V | Flat |<br>| 1.8 V supply mean | 1.7645–1.7705 V | Flat |<br>| 1.8 V supply min | 1.7520–1.7600 V | Flat |<br>| Droop depth | 8.5–12.6 mV | Flat |</p>
<p><strong>No temperature drift, ageing, or supply degradation is observed.</strong> The problem is purely timing non-determinism at each SoT event, consistent with the bistable description.</p>
<p>### Clock Frequency Variation<br>Most captures report ~216 MHz but several show 212.7–219.1 MHz. This ±1.5% spread is within PLL settling tolerance and likely reflects measurement window position (capturing during PLL lock). Not a direct concern but indicates the measurement sometimes catches the very first HS bursts.</p>
<p>## 3. Anomalies</p>
<p>### Flicker Events (Captures 0476 and 0480)<br>| | Capture 0476 | Capture 0480 |<br>|---|---|---|<br>| LP-low plateau | <strong>0 ns</strong> | <strong>0 ns</strong> |<br>| LP exit → HS | 348 ns ✓ | 3 ns ✗ |<br>| HS amplitude (SE) | 108 mV | 110 mV |<br>| DAT0 below-140mV | 2357 | <strong>7209</strong> |<br>| CLK jitter p-p | <strong>174.2 ps</strong> | <strong>178.4 ps</strong> |<br>| Supply droop | 9.4 mV | 8.5 mV |</p>
<p><strong>Key observation:</strong> Capture 0476 shows a long LP exit (348 ns) but <strong>zero LP-low plateau</strong> — the line transitioned from LP-11 directly to HS without dwelling in LP-00. This is a classic symptom of THS_PREPARE being executed but THS_ZERO being so short that LP-00 is never asserted on the wire. The 1.5 ns shortfall in THS_PREPARE+THS_ZERO (166.7 vs 168.2 ns) means the PHY&#x27;s internal counter is right at the rounding boundary; internal clock jitter (~55 ps RMS → ~330 ps 6σ) can easily push it 1–2 ns shorter on some attempts.</p>
<p><strong>Capture 0480</strong> additionally has the shortest LP exit (3 ns) AND zero LP-low plateau — a double failure where both the LP-01 and LP-00 states were essentially skipped.</p>
<p>Both flicker captures show slightly elevated CLK jitter p-p (174, 178 ps vs batch median ~160 ps), which could reflect the PHY operating with marginal internal timing at the moment of SoT.</p>
<p>### DAT0 sig Captures — Intermittent &quot;No HS Signal&quot;<br>Captures 0469, 0471, 0479, 0486, 0498 show DAT0 sig amplitude = 0.0 mV (&quot;No HS signal detected&quot;). This occurs because the high-res sig capture window is very narrow and the data lane is between HS bursts (LP or idle) at that instant. Not a hardware fault — the proto captures always show valid DAT0 amplitude.</p>
<p>### DAT0 &quot;Only Negative Swings&quot;<br>Approximately 60% of captures show DAT0 with only negative differential swings in the sig/proto window. This indicates the trigger point consistently lands on a data pattern dominated by one polarity (e.g., a run of 0x00 or 0xFF bytes). Not a signal integrity concern — the full differential amplitude is still 186–200 mV.</p>
<p>### CLK Common Mode Offset<br>The CLK lane shows a consistent <strong>+29 mV common mode offset</strong>. D-PHY spec allows ±25 mV variation around Vcm; at +29 mV this is slightly out of family but the absolute Vcm is within the receiver&#x27;s 200 mV tolerance band. <strong>Not a direct flicker cause</strong> but indicates slight impedance asymmetry in the CLK pair routing.</p>
<p>### Capture 0497 — LP DAT Processing Error<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP capture buffer was exactly full, and the analysis script attempted to read past the end. This means the LP→HS transition occurred very late in the capture window, or the HS burst extended to the end of the buffer. <strong>Not a hardware fault</strong> — adjust trigger position or increase buffer depth to avoid this.</p>
<p>## 4. Supply Correlation Analysis</p>
<p>### 1.8 V Supply vs. LP Anomalies</p>
<p>| Parameter | Flicker (0476/0480) | Non-flicker (all others) |<br>|---|---|---|<br>| Mean 1.8 V | 1.765 / 1.765 V | 1.764–1.771 V |<br>| Min 1.8 V | 1.756 / 1.756 V | 1.752–1.760 V |<br>| Droop | 9.4 / 8.5 mV | 8.5–12.6 mV |<br>| Ripple RMS | 5.65 / 5.38 mV | 5.24–6.14 mV |</p>
<p><strong>There is no correlation between supply droop/ripple and flicker.</strong> The flicker captures have average-to-good supply metrics. The worst droop (12.6 mV, Capture 0470) produced a clean SoT with 113 ns LP exit. The supply is solidly within spec at all times (min 1.752 V vs 1.71 V spec floor).</p>
<p><strong>Conclusion: The 1.8 V supply is not the flicker trigger.</strong> The root cause is purely the PHY timing register configuration, with the probabilistic outcome determined by internal PHY clock jitter at the SoT moment.</p>
<p>### LP-11 Voltage vs. Supply<br>LP-11 at ~1.015 V with VDDIO at ~1.765 V gives a ratio of 0.575, well below the expected ~0.67. This suggests the LP driver output impedance is higher than expected or there is a series resistance in the LP signal path. However, this is constant across all captures and does not differentiate flicker from non-flicker events.</p>
<p>## 5. Warning/Error Explanations</p>
<p>| Warning | Count | Likely Cause | Action |<br>|---|---|---|---|<br>| &quot;LP exit duration N ns below spec min 50 ns&quot; | 23/27 | <strong>THS_EXIT=5 bc (92.6 ns) and THS_PREPARE+THS_ZERO shortfall</strong> — PHY compresses LP-01→LP-00 states below detection threshold | <strong>Switch to &#x27;Round Up&#x27; registers</strong> |<br>| &quot;FLICKER SUSPECT: LP-low plateau absent&quot; | 2/27 | THS_PREPARE+THS_ZERO ~1.5 ns short; internal jitter occasionally eliminates LP-00 entirely | <strong>Switch to &#x27;Round Up&#x27; registers</strong> |<br>| &quot;No HS signal detected&quot; on DAT0 sig | 5/30 | Narrow capture window landed during LP/idle; data is bursty (video mode) | Widen sig capture window or trigger on HS preamble |<br>| &quot;Only negative swings in capture window&quot; | ~18/30 | Capture window hits a run of identical data bits | Not a concern — normal for video data |<br>| &quot;Settled samples below 140 mV&quot; on CLK | 30/30 | CLK amplitude ~166 mV with ~55 ps RMS jitter means crossing transitions occasionally dip below 140 mV | Moderate concern — increase CLK drive strength if possible |<br>| &quot;Settled samples below 140 mV&quot; on DAT0 | 29/30 | ISI from data transitions + ~1.5 ns short zero state → sampling during transition | Will improve with compliant timing |<br>| &quot;index 200000 out of bounds&quot; (0497) | 1/30 | Analysis buffer overflow — LP→HS transition at edge of capture window | Move trigger earlier or extend buffer |</p>
<p>## 6. Actionable Recommendations</p>
<p>### CRITICAL — Fix Immediately</p>
<p><strong>① Switch to &#x27;Round Up&#x27; PHY timing registers.</strong> This is the single change that will eliminate the flicker:</p>
<p>```<br># Apply via memtool, device tree, or driver patch:<br>DSIM_PHYTIMING (0x32e100b4) = 0x00000306 # THS_EXIT=6 → 111.1 ns ✓<br>DSIM_PHYTIMING1 (0x32e100b8) = 0x030f0a04 # TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4 ✓<br>DSIM_PHYTIMING2 (0x32e100bc) = 0x00030706 # THS_ZERO=7, THS_TRAIL=6 ✓<br>```</p>
<p>This adds exactly <strong>1 byte-clock (18.5 ns) of margin</strong> to each violated parameter, bringing all five into full D-PHY v1.1 compliance. The cost is ~18–37 ns additional latency per SoT sequence — completely negligible for a 60 Hz video stream.</p>
<p><strong>Driver-level fix:</strong> In the samsung-dsim (or sec-dsim) driver, the timing calculation function uses `DIV_ROUND_UP()` vs. truncating division for these fields. Ensure the driver is configured for ceiling rounding. On NXP BSPs, check `imx8mm-{board}.dts` for `samsung,phy-timing` overrides, or patch `samsung_dsim_set_phy_timing()` in `drivers/gpu/drm/bridge/samsung-dsim.c` to always round up.</p>
<p><strong>② Verify the fix eliminates LP-low = 0 ns events.</strong> After applying Round Up registers, re-run 50+ pipeline load cycles and confirm:<br>- LP-low plateau ≥ 50 ns on every capture<br>- LP exit → HS ≥ 50 ns on every capture<br>- Zero flicker events</p>
<p>### IMPORTANT — Address After Fix</p>
<p><strong>③ Investigate low LP-11 voltage (1.015 V).</strong> While in-spec, this is anomalously low:<br>- Check for series resistance in LP signal path (ferrite beads, ESD protection, connector contact resistance)<br>- Verify VDDIO_MIPI is directly connected to 1.8 V rail (not through a long trace or shared via)<br>- Confirm the PHY LP driver strength setting is correct for the load</p>
<p><strong>④ Address CLK lane common-mode offset (+29 mV).</strong> This suggests:<br>- Slight trace length mismatch on CLK± pair (~0.3 mm at 216 MHz)<br>- Or asymmetric loading (e.g., one CLK line has a test point or probe stub the other doesn&#x27;t)<br>- Verify CLK± differential pair routing is tightly coupled with matched lengths</p>
<p><strong>⑤ Consider adding margin beyond bare minimum.</strong> The &#x27;Round Up&#x27; values are still close to spec minimums. For production robustness, consider adding</p>
<p class="tokens">Tokens: 45337 in / 4096 out</p>
</body>
</html>

122
reports/20260413_131240_analysis.html Normal file
View File

@@ -0,0 +1,122 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Analysis — Captures 0635–0664</title>
<style>
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
p { line-height: 1.6; }
ol, ul { line-height: 1.8; padding-left: 24px; }
li { margin: 4px 0; }
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
padding: 16px 20px; margin-bottom: 28px; }
.flicker-alert h2 { color: #e65100; margin-top: 0; }
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
table { border-collapse: collapse; width: 100%; }
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
@media print { body { margin: 20px; } }
</style>
</head>
<body>
<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0648</td><td>20260413_130204</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>0659</td><td>20260413_130603</td><td>dat</td><td style='color:red'>0.4 ns</td><td>3.5 ns</td><td>1.016 V</td></tr><tr><td>0664</td><td>20260413_130751</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.8 ns</td><td>1.016 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0635</td><td>20260413_125723</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0636</td><td>20260413_125744</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0637</td><td>20260413_125806</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0638</td><td>20260413_125828</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0639</td><td>20260413_125849</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0640</td><td>20260413_125911</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0641</td><td>20260413_125933</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0642</td><td>20260413_125954</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0643</td><td>20260413_130016</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0644</td><td>20260413_130038</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0645</td><td>20260413_130059</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0646</td><td>20260413_130121</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0647</td><td>20260413_130142</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0648</td><td>20260413_130204</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0649</td><td>20260413_130226</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0650</td><td>20260413_130248</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0651</td><td>20260413_130309</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0652</td><td>20260413_130331</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0653</td><td>20260413_130353</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0654</td><td>20260413_130414</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0655</td><td>20260413_130436</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0656</td><td>20260413_130458</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0657</td><td>20260413_130519</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0658</td><td>20260413_130541</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0659</td><td>20260413_130603</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0660</td><td>20260413_130624</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0661</td><td>20260413_130646</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0662</td><td>20260413_130708</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0663</td><td>20260413_130729</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0664</td><td>20260413_130751</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-13 13:12:40 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0635–0664 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0635–0664 (30 sessions, 3 flicker events)</p>
<ul><li></li></ul>
<p>## 1. Consistent Spec Concerns</p>
<p>### A. PHY Timing Registers — 5 D-PHY v1.1 Violations (Every Capture, Unchanged)</p>
<p>All 30 captures show identical register values — the system is running <strong>&#x27;Round Best&#x27; mode</strong> with 5 timing violations:</p>
<p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns (7.4%)</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns (2.6%)</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns (7.3%)</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns (1.2%)</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns (0.9%)</strong> |</p>
<p><strong>Key insight</strong>: Every violation is a shortfall of 1–7 ns — exactly the kind of margin the SN65DSI83 may or may not tolerate depending on its internal sampling phase at the moment of SoT detection. This explains the <strong>bistable, non-deterministic</strong> flicker behaviour perfectly: the timing is close enough to work ~90% of the time, but the bridge&#x27;s SoT detector has a probabilistic window of acceptance when margins are this thin.</p>
<p>### B. LP Exit Duration — Universally Violated</p>
<p><strong>Every single capture</strong> shows LP exit → HS of 0–4 ns against a spec minimum of 50 ns. This is not a measurement artifact — it is a systematic violation:</p>
<p>| LP exit (ns) | Captures |<br>|---|---|<br>| 0 ns | 0656 |<br>| 1 ns | 0647 |<br>| 2 ns | 0648★, 0649 |<br>| 3 ns | 0638, 0639, 0643, 0645, 0646, 0651, 0652, 0654, 0658, 0660, 0664★ |<br>| 4 ns | 0635, 0636, 0637, 0640, 0642, 0648★, 0650, 0653, 0659★ |<br>| 113 ns | 0644, 0657 |<br>| 348 ns | 0641, 0661, 0662, 0663 |</p>
<p>★ = confirmed flicker event</p>
<p><strong>Critical observation</strong>: The LP-01→LP-00 transition states are either absent (&lt;4 ns, too fast for the bridge to detect) or properly formed (~108–348 ns). The 0–4 ns measurements indicate the PHY is <strong>skipping the LP-01/LP-00 states entirely</strong> on most startups, jumping directly from LP-11 to HS. The captures with 113 ns or 348 ns show the PHY occasionally executing the full SoT sequence correctly.</p>
<p>### C. LP-Low Plateau — Bimodal Distribution Correlating with Flicker</p>
<p>| LP-low plateau | Count | Flicker? |<br>|---|---|---|<br>| <strong>0 ns</strong> | 3 | <strong>ALL 3 flicker events</strong> (0648, 0659, 0664) |<br>| ~108 ns | 7 | No flicker |<br>| ~342–343 ns | 18 | No flicker |<br>| Error/missing | 1 (0655) | Unknown |</p>
<p><strong>This is the smoking gun</strong>: LP-low = 0 ns means the SoT sequence (LP-11→LP-01→LP-00→HS-0→HS data) was completely absent or truncated. The SN65DSI83 never saw a valid Start-of-Transmission and failed to synchronize. <strong>100% correlation between LP-low = 0 and flicker.</strong></p>
<p>The bimodal LP-low distribution (108 ns vs 342 ns) in non-flicker captures likely reflects whether the scope triggered on the first or second LP-low region in the SoT/EoT/SoT sequence, but both are long enough for the bridge to detect.</p>
<p>### D. HS Amplitude — Marginal with Persistent Below-Spec Samples</p>
<ul><li><strong>CLK lane</strong>: 164.5–166.9 mV mean differential — within spec (140–270 mV) but <strong>low</strong>. Every capture has 18–214 settled samples below 140 mV.</li><li><strong>DAT0 lane</strong>: 185.7–222.6 mV mean — better, but with <strong>253–16,593 below-140 mV samples</strong> per capture in proto windows.</li><li><strong>Clock lane asymmetry</strong>: Consistently +194 / −137 mV (common mode +28 mV), indicating a ~30 mV offset. This is within the ±25% Vdiff imbalance allowed but at the edge.</li></ul>
<p>### E. LP-11 Voltage — Low but In-Spec</p>
<p>LP-11 consistently reads 1.015–1.017 V against a spec range of 1.0–1.45 V. This is <strong>at the bottom of the range</strong> and only 15–17 mV above the minimum. At 1.8 V VDDIO, LP-11 should ideally be near 1.2 V. The low LP-11 voltage suggests either:<br>- Resistive loading on the LP lines (SN65DSI83 input bias or PCB leakage)<br>- VDDIO-referenced LP driver with a voltage divider effect<br>- The LP driver output impedance is high relative to the load</p>
<p>While technically passing, this leaves minimal noise margin for the bridge&#x27;s LP state detector.</p>
<ul><li></li></ul>
<p>## 2. Trends Across Captures</p>
<p>### A. No Significant Drift<br>- <strong>HS amplitude</strong>: CLK ±1.5 mV, DAT0 ±8 mV — stable<br>- <strong>Jitter</strong>: 136–177 ps p-p, 51–55 ps RMS — stable, no drift<br>- <strong>Clock frequency</strong>: 212.76–218.99 MHz — mostly 215.7–216.3 with occasional outliers (212.76, 213.04, 213.30 in captures 0646/0651/0654/0663; 218.99 in 0655/0663). The low-frequency outliers may be measurement artifacts from the scope&#x27;s frequency estimation with slightly different trigger windows.<br>- <strong>LP-11 voltage</strong>: 1.015–1.017 V — rock stable<br>- <strong>1.8 V supply</strong>: 1.7637–1.7695 V mean — no drift</p>
<p>### B. DAT0 Below-140-mV Count Varies Widely<br>Range: 13 to 16,593 samples across captures. This variation is <strong>data-dependent</strong> (the pattern being transmitted changes the ratio of transitions to settled bits), not a degradation trend.</p>
<ul><li></li></ul>
<p>## 3. Anomalies Flagged</p>
<p>### A. Three Confirmed Flicker Events (LP-low = 0 ns)</p>
<p>| Capture | LP exit | LP-low | Flicker |<br>|---|---|---|---|<br>| <strong>0648</strong> | 2 ns | <strong>0 ns</strong> | ✓ |<br>| <strong>0659</strong> | 4 ns | <strong>0 ns</strong> | ✓ |<br>| <strong>0664</strong> | 3 ns | <strong>0 ns</strong> | ✓ |</p>
<p>All three show the same signature: the data lane jumped from LP-11 directly to HS without executing the LP-01→LP-00 SoT sequence. The SN65DSI83 never received a valid SoT and could not lock its HS receiver, resulting in persistent flicker.</p>
<p>### B. DAT0 sig Capture Shows 0 mV in 4 Captures (0635, 0638, 0640, 0646, 0664★)<br>The high-res sig capture on DAT0 shows &quot;No HS signal detected&quot; in several captures. This is a <strong>trigger timing artifact</strong> — the sig window (~10 ns) captured during an LP or blanking gap rather than during HS data. Not a hardware concern.</p>
<p>### C. DAT0 &quot;Only Negative Swings&quot; Warning (Most sig/dat Captures)<br>The sig window captured during a data pattern that happened to have consecutive identical bits (HS-0 to HS-0 transitions) or caught only one polarity. Again a <strong>trigger timing artifact</strong>, not a hardware issue.</p>
<p>### D. Capture 0655 — LP Data Processing Error<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP capture buffer was exactly full, likely because the trigger point was at the very end of the acquisition window. This is a <strong>capture/processing artifact</strong>, not a hardware failure. Recommend extending the LP capture buffer or adjusting trigger position.</p>
<p>### E. CLK Lane in Continuous HS — Expected<br>The CLK lane shows &quot;LP→HS sequence NOT DETECTED&quot; in all captures. This is <strong>correct behaviour</strong> for the Samsung DSIM IP, which places the clock lane in continuous HS mode and only performs LP→HS transitions on data lanes.</p>
<ul><li></li></ul>
<p>## 4. Supply Correlation Analysis</p>
<p>### A. 1.8 V Supply — No Correlation with Flicker</p>
<p>| Metric | Flicker (0648, 0659, 0664) | Non-flicker (27 captures) |<br>|---|---|---|<br>| Mean voltage | 1.7643–1.7654 V | 1.7637–1.7695 V |<br>| Min voltage | 1.7560 V | 1.7520–1.7600 V |<br>| Droop | 8.3–9.5 mV | 7.8–12.8 mV |<br>| Ripple RMS | 5.45–5.55 mV | 5.19–5.85 mV |</p>
<p><strong>No correlation exists.</strong> The flicker events have average-to-good supply metrics. The worst droop (12.8 mV in 0642, 12.2 mV in 0645) and worst ripple (5.85 mV in 0662) all occurred in <strong>non-flicker</strong> sessions. This conclusively rules out supply-induced SoT failure.</p>
<p>### B. Supply Health Overall<br>- Mean 1.765 V is 35 mV below nominal 1.8 V — acceptable but leaving only 55 mV margin to 1.71 V lower limit<br>- All captures maintain min voltage ≥ 1.752 V — healthy<br>- Droop and ripple are well within spec</p>
<ul><li></li></ul>
<p>## 5. WARNING/ERROR Explanations</p>
<p>| Warning/Error | Cause | Action |<br>|---|---|---|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>PHY skipping LP-01/LP-00 states</strong> due to insufficient THS_PREPARE+THS_ZERO timing programmed in registers. The Samsung DSIM PHY&#x27;s SoT state machine runs the LP-01→LP-00 states for a duration derived from THS_PREPARE, and with only 2–3 bc programmed (37–56 ns), the LP-low states may be too brief for the scope to resolve, or the PHY may skip them entirely when internal timing jitter causes the state machine to advance before the LP lines settle. | <strong>Switch to &#x27;Round Up&#x27; register values</strong> |<br>| `LP-low plateau absent or &lt; 50 ns` — FLICKER SUSPECT | SoT sequence was completely missing. The PHY transitioned from LP-11 directly to HS-0 without the required LP-01→LP-00 intermediate states. | Root cause is register timing; fix registers |<br>| `No HS signal detected — line may be in LP state or idle` (sig/dat) | Trigger caught a blanking/LP period rather than active HS data. Normal for video mode DSI where data lanes go LP between lines/frames. | Ignore — adjust trigger if sig captures needed |<br>| `Only negative swings in capture window` | Short capture window caught a run of identical bits. Data-pattern dependent. | Ignore — no hardware concern |<br>| `X settled samples below 140 mV` (CLK and DAT) | Clock amplitude is at lower end of spec; data transitions create brief low-amplitude moments. Mostly ISI (inter-symbol interference) at transitions. | Monitor; consider PCB impedance review if count increases |<br>| `index 200000 out of bounds` (Capture 0655 lp_dat) | Processing script hit end-of-buffer — trigger too late in acquisition window | Extend buffer or add bounds checking |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### PRIORITY 1 — CRITICAL (Fix Immediately): Switch to &#x27;Round Up&#x27; PHY Timing</p>
<p>Modify the samsung-dsim driver timing calculation or apply a device-tree override to program <strong>&#x27;Round Up&#x27; register values</strong>:</p>
<p>```<br>DSIM_PHYTIMING (0xb4): 0x00000306 (THS_EXIT=6)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04 (TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706 (THS_ZERO=7, THS_TRAIL=6)<br>```</p>
<p>This eliminates all 5 D-PHY violations and adds 11–37 ns of margin to each parameter. The additional 1 byte-clock (18.5 ns) per parameter has <strong>zero impact</strong> on bandwidth or display performance at 432 Mbit/s.</p>
<p><strong>Implementation path</strong>: The samsung-dsim driver (drivers/gpu/drm/bridge/samsung-dsim.c) computes these values in `samsung_dsim_set_phy_timing()`. The &quot;Round Best&quot; mode uses `DIV_ROUND_CLOSEST` for the byte-clock conversion; change to `DIV_ROUND_UP` (ceiling), or apply hardcoded overrides via a platform-specific timing table. This is a <strong>one-line change</strong> in the rounding function.</p>
<p>### PRIORITY 2 — HIGH: Validate LP SoT Sequence After Register Fix</p>
<p>After applying Round Up timings, re-run the same 30-session capture batch and verify:<br>- LP-low plateau ≥ 50 ns in <strong>all</strong> sessions (currently 0 ns in 10% = flicker rate)<br>- LP exit → HS ≥ 50 ns<br>- No flicker events</p>
<p>The expectation is that increasing THS_PREPARE+THS_ZERO from 9 bc to 10 bc (166.7 → 185.2 ns) will give the PHY state machine sufficient time to reliably execute the LP-01→LP-00 sequence, eliminating the probabilistic skip.</p>
<p>### PRIORITY 3 — MEDIUM: Investigate LP-11 Voltage</p>
<p>LP-11 at 1.015–1.017 V (only 1.5% above the 1.0 V minimum) is abnormally low for a 1.8 V VDDIO system. Check:<br>1. LP termination resistance on the SN65DSI83 input — per datasheet, the SN65DSI83 has internal 200 kΩ pull-ups; if external pull-ups/pull-downs are present, they may be loading the line<br>2. Series resistance in the LP path — excessive via/trace resistance could create a divider<br>3. VDDIO at the PHY pad — confirm 1.8 V is reaching the i.MX 8M Mini MIPI PHY supply pin, not just the bulk decoupling point</p>
<p>While this is not the flicker root cause, it reduces noise margin and could contribute to problems at lower VDDIO or higher temperatures.</p>
<p>### PRIORITY 4 — LOW: Monitor CLK Lane Amplitude</p>
<p>CLK lane differential amplitude at 165 mV (only 25 mV / 18% above the 140 mV minimum) with persistent below-spec samples suggests:<br>1. Slightly high trace impedance or length mismatch on CLK P/N<br>2. PCB impedance above the 100Ω differential target<br>3. Verify CLK lane termination at the SN65DSI83 — a missing or incorrect termination resistor would reduce amplitude</p>
<p>This is not causing flicker but is a long-term reliability concern as components age and impedance drifts.</p>
<p>### PRIORITY 5 — LOW: Capture Script Improvements<br>- Add bounds checking for LP buffer</p>
<p class="tokens">Tokens: 45745 in / 4096 out</p>
</body>
</html>

113
reports/20260413_141707_analysis.html Normal file
View File

@@ -0,0 +1,113 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Analysis — Captures 0801–0830</title>
<style>
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
p { line-height: 1.6; }
ol, ul { line-height: 1.8; padding-left: 24px; }
li { margin: 4px 0; }
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
padding: 16px 20px; margin-bottom: 28px; }
.flicker-alert h2 { color: #e65100; margin-top: 0; }
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
table { border-collapse: collapse; width: 100%; }
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
@media print { body { margin: 20px; } }
</style>
</head>
<body>
<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0803</td><td>20260413_140238</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.9 ns</td><td>1.017 V</td></tr><tr><td>0810</td><td>20260413_140509</td><td>dat</td><td style='color:red'>0.2 ns</td><td>0.7 ns</td><td>1.016 V</td></tr><tr><td>0830</td><td>20260413_141222</td><td>dat</td><td style='color:red'>0.2 ns</td><td>3.4 ns</td><td>1.016 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0801</td><td>20260413_140154</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0802</td><td>20260413_140216</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0803</td><td>20260413_140238</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0804</td><td>20260413_140259</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0805</td><td>20260413_140321</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0806</td><td>20260413_140342</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0807</td><td>20260413_140404</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0808</td><td>20260413_140426</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0809</td><td>20260413_140448</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0810</td><td>20260413_140509</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0811</td><td>20260413_140531</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0812</td><td>20260413_140553</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0813</td><td>20260413_140615</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0814</td><td>20260413_140636</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0815</td><td>20260413_140658</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0816</td><td>20260413_140720</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0817</td><td>20260413_140741</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0818</td><td>20260413_140803</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0819</td><td>20260413_140824</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0820</td><td>20260413_140846</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0821</td><td>20260413_140908</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0822</td><td>20260413_140929</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0823</td><td>20260413_140951</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0824</td><td>20260413_141013</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0825</td><td>20260413_141035</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0826</td><td>20260413_141056</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0827</td><td>20260413_141118</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0828</td><td>20260413_141140</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0829</td><td>20260413_141201</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0830</td><td>20260413_141222</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-13 14:17:07 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0801–0830 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0801–0830</p>
<ul><li></li></ul>
<p>## 1. Executive Summary</p>
<p><strong>The system is running with non-compliant D-PHY timing registers (&quot;Round Best&quot; mode) that violate 5 D-PHY v1.1 Table 14 parameters. The LP→HS SoT sequence on the data lane is systematically degraded across ALL 30 captures — every single capture shows LP exit duration ≤ 4 ns (spec ≥ 50 ns), and the 3 confirmed flicker events (0803, 0810, 0830) correlate perfectly with LP-low plateau = 0 ns, meaning the SoT LP-01/LP-00 states were completely absent. The SN65DSI83 bridge&#x27;s SoT detector failed to recognise the HS entry because there was no discernible LP-low state to trigger on. Switching to &quot;Round Up&quot; compliant registers is the primary fix; the non-deterministic nature of the failure is explained by the timing margins being so thin that cycle-to-cycle byte-clock jitter pushes the PHY across the detection threshold stochastically.</strong></p>
<ul><li></li></ul>
<p>## 2. Consistent Spec Concerns</p>
<p>### 2.1 Register Timing Violations (ALL 30 captures — identical)</p>
<p>Every capture shows the same &quot;Round Best&quot; register values:</p>
<p>| Parameter | Register Value | Actual | Spec Min | Shortfall | Severity |<br>|-----------|---------------|--------|----------|-----------|----------|<br>| <strong>THS_EXIT</strong> | 5 bc → 92.6 ns | 92.6 ns | 100.0 ns | <strong>−7.4 ns (−7.4%)</strong> | HIGH — affects LP→HS exit |<br>| <strong>TCLK_PREPARE</strong> | 2 bc → 37.0 ns | 37.0 ns | 38.0 ns | <strong>−1.0 ns (−2.6%)</strong> | HIGH — CLK SoT init |<br>| <strong>TCLK_TRAIL</strong> | 3 bc → 55.6 ns | 55.6 ns | 60.0 ns | <strong>−4.4 ns (−7.3%)</strong> | MEDIUM — affects HS→LP |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc → 296.3 ns | 296.3 ns | 300.0 ns | <strong>−3.7 ns (−1.2%)</strong> | HIGH — CLK lane HS init |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc → 166.7 ns | 166.7 ns | 168.2 ns | <strong>−1.5 ns (−0.9%)</strong> | CRITICAL — DATA lane SoT |</p>
<p><strong>Key insight:</strong> THS_PREPARE+THS_ZERO is only 1.5 ns below spec. At 54 MHz byte clock, one byte-clock period is 18.5 ns — the quantisation granularity is much larger than the deficit. The PHY hardware implements these as digital counters, but the analog output has process/voltage/temperature variation. The 1.5 ns shortfall means the SN65DSI83&#x27;s SoT detector is operating at the very edge of its recognition window. Some attempts succeed, some fail — this is the stochastic mechanism.</p>
<p>### 2.2 LP→HS SoT Timing (Universal Degradation)</p>
<p>| Metric | Good Captures (no flicker) | Flicker Captures (0803, 0810, 0830) |<br>|--------|---------------------------|--------------------------------------|<br>| LP exit → HS | 1–4 ns (all ✗, spec ≥ 50 ns) | 1–3 ns (all ✗) |<br>| LP-low plateau | 108–348 ns | <strong>0 ns</strong> |<br>| HS amplitude (SE p-p/2) | 20–113 mV | 33–108 mV |</p>
<p><strong>Critical finding:</strong> Even the &quot;good&quot; captures show LP exit durations of 1–4 ns — universally violating the ≥ 50 ns specification. The difference between flicker and no-flicker is whether the LP-low plateau (the LP-00 state that signals SoT to the bridge) is present at all:</p>
<ul><li><strong>LP-low = 0 ns → FLICKER</strong> (bridge cannot detect SoT → stuck → persistent flicker)</li><li><strong>LP-low = 108–348 ns → NO FLICKER</strong> (bridge detects SoT despite short LP exit)</li></ul>
<p>This three-valued distribution of LP-low plateaux (0, ~108, ~343 ns) suggests the PHY&#x27;s internal state machine is quantised — the LP-00 state duration is set by a counter that sometimes loads 0 counts.</p>
<p>### 2.3 HS Differential Amplitude</p>
<p>| Lane | Median Amplitude | Spec Range | Concern |<br>|------|-----------------|------------|---------|<br>| CLK | 165.5 mV | 140–270 mV | <strong>Marginal low</strong> — only 25.5 mV above 140 mV floor |<br>| DAT0 | 190 mV | 140–270 mV | Acceptable but CLK positive/negative asymmetry: +194/−137 mV |</p>
<p><strong>CLK lane asymmetry:</strong> Consistently +194 mV positive, −137 mV negative → common mode offset of ~+29 mV. The negative swing (137 mV) is <strong>below 140 mV</strong> in many individual samples, explaining the persistent &quot;samples below 140 mV&quot; warnings (18–201 samples per capture on CLK). This is a systematic PHY output imbalance, likely due to termination mismatch or PCB trace asymmetry.</p>
<p>### 2.4 LP-11 Voltage</p>
<p>Consistently 1.015–1.017 V across all captures. Spec is 1.0–1.45 V (for 1.8 V VDDIO, LP-11 should be at VOH ≥ 1.1 V per D-PHY spec for reliable detection). <strong>At 1.016 V, this is at the absolute floor</strong> — the LP driver output is ~56% of VDDIO rather than the expected ~80%+. This reduces LP-state noise margin and makes SoT detection more susceptible to noise.</p>
<p><strong>Root cause:</strong> The LP-11 voltage at 1.016 V (rather than ~1.4–1.5 V) suggests either:<br>- The LP driver pull-up is fighting a low-impedance termination path to ground on the SN65DSI83 input<br>- PCB series resistance in the 1.8 V LP supply path<br>- The measurement is single-ended Dp or Dn only, and the LP voltage divider with the SN65DSI83&#x27;s internal 200 Ω termination is pulling it down</p>
<ul><li></li></ul>
<p>## 3. Trend Analysis Across Captures</p>
<p>### 3.1 No Temporal Drift<br>- <strong>HS amplitude:</strong> CLK 164–167 mV, DAT0 186–223 mV — flat, no drift<br>- <strong>Jitter:</strong> CLK p-p 143–180 ps, RMS 51–56 ps — stable<br>- <strong>1.8 V supply:</strong> Mean 1.762–1.769 V, droop 6.7–12.0 mV — stable<br>- <strong>LP-11 voltage:</strong> 1.015–1.017 V — dead flat<br>- <strong>LP-11 duration:</strong> 1.73 µs — identical across all captures (hardware timer)</p>
<p>### 3.2 LP-low Plateau Distribution (key finding)</p>
<p>Tabulating across all 30 captures with LP data:</p>
<p>| LP-low Plateau | Count | Flicker? |<br>|----------------|-------|----------|<br>| <strong>0 ns</strong> | 3 (0803, 0810, 0830) | <strong>YES — all 3 flicker events</strong> |<br>| <strong>~108 ns</strong> | 7 (0808, 0809, 0812, 0815, 0820, 0823, 0827, 0828) | No |<br>| <strong>~342-348 ns</strong> | 17 (0801, 0804, 0806, 0807, 0811, 0813, 0814, 0816, 0817, 0818, 0819, 0821, 0822, 0824, 0825, 0826, 0829) | No |<br>| <strong>No LP data</strong> | 2 (0802, 0805) — processing error | Unknown |</p>
<p>This trimodal distribution (0 / 108 / 343 ns) is <strong>highly diagnostic</strong>. The LP-low plateau appears to be quantised at ~0, ~6, or ~18.5 byte-clock intervals:<br>- 343 ns ÷ 18.5 ns/bc ≈ <strong>18.5 bc</strong> (likely 19 bc counter)<br>- 108 ns ÷ 18.5 ns/bc ≈ <strong>5.8 bc</strong> (likely 6 bc counter)<br>- 0 ns = <strong>counter not loaded / skipped</strong></p>
<p>The trimodal quantisation strongly suggests a <strong>race condition in the Samsung DSIM PHY state machine&#x27;s SoT sequencer</strong>. The byte-clock domain loads the LP-state counters, but a metastability event at the boundary between the LP clock domain and the byte-clock domain occasionally causes a counter to load 0 or a reduced value.</p>
<p><strong>The too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns spec) narrows the timing window for this counter load, making the race more likely to result in a 0 or reduced count.</strong></p>
<ul><li></li></ul>
<p>## 4. Supply Correlation Analysis</p>
<p>### 4.1 1.8 V Supply vs Flicker Events</p>
<p>| Capture | Flicker? | LP-low (ns) | 1.8V Mean (V) | Droop (mV) | Ripple RMS (mV) |<br>|---------|----------|-------------|----------------|------------|-----------------|<br>| 0803 | <strong>YES</strong> | 0 | 1.7638 | 7.9 | 5.65 |<br>| 0810 | <strong>YES</strong> | 0 | 1.7642 | 8.2 | 5.54 |<br>| 0830 | <strong>YES</strong> | 0 | 1.7685 | 8.5 | 5.42 |<br>| 0801 | No | 343 | 1.7644 | 8.4 | 5.40 |<br>| 0804 | No | 343 | 1.7680 | 12.0 | 5.97 |<br>| 0825 | No | 343 | 1.7625 | 10.5 | 5.92 |</p>
<p><strong>Conclusion: No supply correlation.</strong> The flicker captures have droop/ripple values well within the range of non-flicker captures. Capture 0804 has the *highest* droop (12.0 mV) and *highest* ripple (5.97 mV) yet works perfectly. Capture 0830 (flicker) has the *highest* supply voltage (1.7685 V) in the batch. <strong>The supply is not the trigger.</strong></p>
<p>### 4.2 Supply Health<br>- All captures: Min voltage ≥ 1.752 V (spec 1.71 V) ✓<br>- Maximum droop: 12.0 mV (&lt; 1% of 1.8 V) ✓<br>- Ripple RMS: 5.12–5.97 mV — clean<br>- <strong>Supply is healthy and not contributing to the flicker.</strong></p>
<ul><li></li></ul>
<p>## 5. Warning/Error Explanations</p>
<p>### 5.1 &quot;CLK lane is in continuous HS mode — LP states not expected on CLK&quot;<br><strong>Explanation:</strong> Normal. In DSI video mode, the CLK lane enters HS once at pipeline start and remains in continuous HS mode. LP→HS transitions are only expected on data lanes. <strong>No action needed.</strong></p>
<p>### 5.2 &quot;Only negative swings in capture window — amplitude may be underestimated&quot;<br><strong>Explanation:</strong> The scope trigger captured a window where DAT0 was sending a long run of one polarity (e.g., a blanking pattern or repeated byte). With DDR signalling, a long run of `0x00` or `0xFF` data would produce only one polarity of differential swing. The reported amplitude (190–195 mV) is consistent with the proto captures, so <strong>this is a trigger windowing artefact, not a signal problem.</strong> The amplitude is valid as a lower bound.</p>
<p>### 5.3 &quot;No HS signal detected — line may be in LP state or idle&quot; (sig/dat in 0804, 0808, 0811, 0813, 0827)<br><strong>Explanation:</strong> The high-res sig capture triggered during an inter-frame blanking interval when the data lane was in LP-11 or LP-00 idle state. In DSI video mode with non-burst timing, the data lane returns to LP between frames. <strong>Trigger timing variability, not a signal fault.</strong> Consider triggering sig captures on a specific HS burst.</p>
<p>### 5.4 &quot;[lp_dat] ERROR: index 200000 is out of bounds&quot; (0802, 0805)<br><strong>Explanation:</strong> The LP analysis script&#x27;s edge-detection algorithm ran off the end of the capture buffer without finding the expected LP→HS transition within the 200k-sample window. Most likely cause: <strong>the trigger fired too early or too late relative to the SoT event</strong>, placing it outside the capture window. These captures have no LP data — they are neither flicker-confirmed nor flicker-excluded. <strong>Increase LP capture depth or adjust trigger holdoff by ±1 µs.</strong></p>
<p>### 5.5 &quot;LP exit duration X ns below spec min 50 ns&quot; (ALL captures with LP data)<br><strong>Explanation:</strong> This is the systemic problem. Every single data-lane LP capture shows LP exit (time from LP-11 falling edge to HS-0 crossing) of 1–4 ns versus the 50 ns minimum. <strong>The PHY&#x27;s LP→HS transition is too fast for the bridge to track.</strong> The SN65DSI83&#x27;s input comparators need time to switch from LP mode (high-voltage, ~1 V common mode) to HS mode (low-voltage, ~200 mV differential). A 1–4 ns transition gives no settling time.</p>
<p><strong>Root cause linkage:</strong> This maps directly to the THS_EXIT violation (92.6 ns vs 100 ns spec). But the measured 1–4 ns is far shorter than even the programmed 92.6 ns. This suggests the LP exit metric is measuring a different event — likely the Dp/Dn single-ended fall time from LP-11 (~1.0 V) to 0 V, which is the analog slew rate of the LP driver turning off. The programmed THS_EXIT of 92.6 ns controls how long the PHY stays in LP-00 after LP-01 before asserting HS, but if the LP-01 and LP-00 states are being skipped or truncated (as the 0 ns LP-low plateau confirms), <strong>THS_EXIT never executes properly</strong>.</p>
<p>### 5.6 &quot;X settled samples below 140 mV&quot; (CLK lane, all captures)<br><strong>Explanation:</strong> CLK differential amplitude has a negative-swing shortfall (−137 mV typical vs −140 mV spec). With noise, ~0.5–5% of settled HS samples dip below 140 mV. This is the <strong>CLK common-mode offset (+29 mV)</strong> causing asymmetric clipping. While functional, it reduces clock eye margin.</p>
<ul><li></li></ul>
<p>## 6. Detailed Root Cause Analysis</p>
<p>### 6.1 Why the Flicker is Non-Deterministic</p>
<p>The failure mechanism is a <strong>digital race condition in the DSIM PHY&#x27;s SoT state machine</strong>, amplified by timing parameters set below spec:</p>
<ol><li>At pipeline load, the DSIM controller commands the PHY to execute LP-11 → LP-01 → LP-00 → HS-0 (SoT sequence)</li><li>The LP-state durations are controlled by byte-clock counters loaded from PHYTIMING/PHYTIMING2 registers</li><li>THS_PREPARE+THS_ZERO is programmed to 9 byte-clocks (166.7 ns) — <strong>1.5 ns below the 168.2 ns spec minimum</strong></li><li>The PHY&#x27;s internal clock-domain crossing between LP and HS domains has a synchronisation window</li><li>When the counter values are at the spec boundary, the synchroniser occasionally <strong>drops a count or skips the LP-00 state entirely</strong></li><li>This is a classic metastability-induced non-deterministic failure</li></ol>
<p>The trimodal LP-low distribution (0 / 108 /</p>
<p class="tokens">Tokens: 45448 in / 4096 out</p>
</body>
</html>

10
reports/flicker_log.csv
View File

@@ -35,3 +35,13 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v
2026-04-10 12:45:00,20260410_123438,0313,dat,1.4,0.1,1.015
2026-04-10 12:45:08,20260410_123710,0320,dat,0.2,1.9,1.017
2026-04-10 12:45:14,20260410_123858,0325,dat,0.3,3.5,1.015
2026-04-13 09:57:36,20260413_095340,0164,dat,0.3,2.3,1.015
2026-04-13 11:01:47,20260413_105141,0312,dat,0.3,0.1,1.016
2026-04-13 12:06:09,20260413_115521,0476,dat,0.2,347.8,1.015
2026-04-13 12:06:13,20260413_115648,0480,dat,0.3,3.3,1.014
2026-04-13 13:10:48,20260413_130204,0648,dat,0.3,2.4,1.015
2026-04-13 13:11:00,20260413_130603,0659,dat,0.4,3.5,1.016
2026-04-13 13:11:05,20260413_130751,0664,dat,0.2,2.8,1.016
2026-04-13 14:15:04,20260413_140238,0803,dat,0.2,2.9,1.017
2026-04-13 14:15:12,20260413_140509,0810,dat,0.2,0.7,1.016
2026-04-13 14:15:34,20260413_141222,0830,dat,0.2,3.4,1.016
1 logged_at capture_ts capture_num channel lp_low_duration_ns lp11_to_hs_ns lp11_voltage_v
35 2026-04-10 12:45:00 20260410_123438 0313 dat 1.4 0.1 1.015
36 2026-04-10 12:45:08 20260410_123710 0320 dat 0.2 1.9 1.017
37 2026-04-10 12:45:14 20260410_123858 0325 dat 0.3 3.5 1.015
38 2026-04-13 09:57:36 20260413_095340 0164 dat 0.3 2.3 1.015
39 2026-04-13 11:01:47 20260413_105141 0312 dat 0.3 0.1 1.016
40 2026-04-13 12:06:09 20260413_115521 0476 dat 0.2 347.8 1.015
41 2026-04-13 12:06:13 20260413_115648 0480 dat 0.3 3.3 1.014
42 2026-04-13 13:10:48 20260413_130204 0648 dat 0.3 2.4 1.015
43 2026-04-13 13:11:00 20260413_130603 0659 dat 0.4 3.5 1.016
44 2026-04-13 13:11:05 20260413_130751 0664 dat 0.2 2.8 1.016
45 2026-04-13 14:15:04 20260413_140238 0803 dat 0.2 2.9 1.017
46 2026-04-13 14:15:12 20260413_140509 0810 dat 0.2 0.7 1.016
47 2026-04-13 14:15:34 20260413_141222 0830 dat 0.2 3.4 1.016