114 lines
19 KiB
HTML
114 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0801–0830</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert h2 { color: #e65100; margin-top: 0; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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table { border-collapse: collapse; width: 100%; }
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th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 3 of 30 display load sessions (10%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0803</td><td>20260413_140238</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.9 ns</td><td>1.017 V</td></tr><tr><td>0810</td><td>20260413_140509</td><td>dat</td><td style='color:red'>0.2 ns</td><td>0.7 ns</td><td>1.016 V</td></tr><tr><td>0830</td><td>20260413_141222</td><td>dat</td><td style='color:red'>0.2 ns</td><td>3.4 ns</td><td>1.016 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0801</td><td>20260413_140154</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0802</td><td>20260413_140216</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0803</td><td>20260413_140238</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0804</td><td>20260413_140259</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0805</td><td>20260413_140321</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0806</td><td>20260413_140342</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0807</td><td>20260413_140404</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0808</td><td>20260413_140426</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0809</td><td>20260413_140448</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0810</td><td>20260413_140509</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0811</td><td>20260413_140531</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0812</td><td>20260413_140553</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0813</td><td>20260413_140615</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0814</td><td>20260413_140636</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0815</td><td>20260413_140658</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0816</td><td>20260413_140720</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0817</td><td>20260413_140741</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0818</td><td>20260413_140803</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0819</td><td>20260413_140824</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0820</td><td>20260413_140846</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0821</td><td>20260413_140908</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0822</td><td>20260413_140929</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0823</td><td>20260413_140951</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0824</td><td>20260413_141013</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0825</td><td>20260413_141035</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0826</td><td>20260413_141056</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0827</td><td>20260413_141118</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0828</td><td>20260413_141140</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0829</td><td>20260413_141201</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0830</td><td>20260413_141222</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-13 14:17:07 |
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<strong>Scope:</strong> Captures 0801–0830 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0801–0830</p>
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<ul><li></li></ul>
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<p>## 1. Executive Summary</p>
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<p><strong>The system is running with non-compliant D-PHY timing registers ("Round Best" mode) that violate 5 D-PHY v1.1 Table 14 parameters. The LP→HS SoT sequence on the data lane is systematically degraded across ALL 30 captures — every single capture shows LP exit duration ≤ 4 ns (spec ≥ 50 ns), and the 3 confirmed flicker events (0803, 0810, 0830) correlate perfectly with LP-low plateau = 0 ns, meaning the SoT LP-01/LP-00 states were completely absent. The SN65DSI83 bridge's SoT detector failed to recognise the HS entry because there was no discernible LP-low state to trigger on. Switching to "Round Up" compliant registers is the primary fix; the non-deterministic nature of the failure is explained by the timing margins being so thin that cycle-to-cycle byte-clock jitter pushes the PHY across the detection threshold stochastically.</strong></p>
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<ul><li></li></ul>
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<p>## 2. Consistent Spec Concerns</p>
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<p>### 2.1 Register Timing Violations (ALL 30 captures — identical)</p>
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<p>Every capture shows the same "Round Best" register values:</p>
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<p>| Parameter | Register Value | Actual | Spec Min | Shortfall | Severity |<br>|-----------|---------------|--------|----------|-----------|----------|<br>| <strong>THS_EXIT</strong> | 5 bc → 92.6 ns | 92.6 ns | 100.0 ns | <strong>−7.4 ns (−7.4%)</strong> | HIGH — affects LP→HS exit |<br>| <strong>TCLK_PREPARE</strong> | 2 bc → 37.0 ns | 37.0 ns | 38.0 ns | <strong>−1.0 ns (−2.6%)</strong> | HIGH — CLK SoT init |<br>| <strong>TCLK_TRAIL</strong> | 3 bc → 55.6 ns | 55.6 ns | 60.0 ns | <strong>−4.4 ns (−7.3%)</strong> | MEDIUM — affects HS→LP |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc → 296.3 ns | 296.3 ns | 300.0 ns | <strong>−3.7 ns (−1.2%)</strong> | HIGH — CLK lane HS init |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc → 166.7 ns | 166.7 ns | 168.2 ns | <strong>−1.5 ns (−0.9%)</strong> | CRITICAL — DATA lane SoT |</p>
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<p><strong>Key insight:</strong> THS_PREPARE+THS_ZERO is only 1.5 ns below spec. At 54 MHz byte clock, one byte-clock period is 18.5 ns — the quantisation granularity is much larger than the deficit. The PHY hardware implements these as digital counters, but the analog output has process/voltage/temperature variation. The 1.5 ns shortfall means the SN65DSI83's SoT detector is operating at the very edge of its recognition window. Some attempts succeed, some fail — this is the stochastic mechanism.</p>
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<p>### 2.2 LP→HS SoT Timing (Universal Degradation)</p>
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<p>| Metric | Good Captures (no flicker) | Flicker Captures (0803, 0810, 0830) |<br>|--------|---------------------------|--------------------------------------|<br>| LP exit → HS | 1–4 ns (all ✗, spec ≥ 50 ns) | 1–3 ns (all ✗) |<br>| LP-low plateau | 108–348 ns | <strong>0 ns</strong> |<br>| HS amplitude (SE p-p/2) | 20–113 mV | 33–108 mV |</p>
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<p><strong>Critical finding:</strong> Even the "good" captures show LP exit durations of 1–4 ns — universally violating the ≥ 50 ns specification. The difference between flicker and no-flicker is whether the LP-low plateau (the LP-00 state that signals SoT to the bridge) is present at all:</p>
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<ul><li><strong>LP-low = 0 ns → FLICKER</strong> (bridge cannot detect SoT → stuck → persistent flicker)</li><li><strong>LP-low = 108–348 ns → NO FLICKER</strong> (bridge detects SoT despite short LP exit)</li></ul>
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<p>This three-valued distribution of LP-low plateaux (0, ~108, ~343 ns) suggests the PHY's internal state machine is quantised — the LP-00 state duration is set by a counter that sometimes loads 0 counts.</p>
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<p>### 2.3 HS Differential Amplitude</p>
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<p>| Lane | Median Amplitude | Spec Range | Concern |<br>|------|-----------------|------------|---------|<br>| CLK | 165.5 mV | 140–270 mV | <strong>Marginal low</strong> — only 25.5 mV above 140 mV floor |<br>| DAT0 | 190 mV | 140–270 mV | Acceptable but CLK positive/negative asymmetry: +194/−137 mV |</p>
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<p><strong>CLK lane asymmetry:</strong> Consistently +194 mV positive, −137 mV negative → common mode offset of ~+29 mV. The negative swing (137 mV) is <strong>below 140 mV</strong> in many individual samples, explaining the persistent "samples below 140 mV" warnings (18–201 samples per capture on CLK). This is a systematic PHY output imbalance, likely due to termination mismatch or PCB trace asymmetry.</p>
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<p>### 2.4 LP-11 Voltage</p>
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<p>Consistently 1.015–1.017 V across all captures. Spec is 1.0–1.45 V (for 1.8 V VDDIO, LP-11 should be at VOH ≥ 1.1 V per D-PHY spec for reliable detection). <strong>At 1.016 V, this is at the absolute floor</strong> — the LP driver output is ~56% of VDDIO rather than the expected ~80%+. This reduces LP-state noise margin and makes SoT detection more susceptible to noise.</p>
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<p><strong>Root cause:</strong> The LP-11 voltage at 1.016 V (rather than ~1.4–1.5 V) suggests either:<br>- The LP driver pull-up is fighting a low-impedance termination path to ground on the SN65DSI83 input<br>- PCB series resistance in the 1.8 V LP supply path<br>- The measurement is single-ended Dp or Dn only, and the LP voltage divider with the SN65DSI83's internal 200 Ω termination is pulling it down</p>
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<ul><li></li></ul>
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<p>## 3. Trend Analysis Across Captures</p>
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<p>### 3.1 No Temporal Drift<br>- <strong>HS amplitude:</strong> CLK 164–167 mV, DAT0 186–223 mV — flat, no drift<br>- <strong>Jitter:</strong> CLK p-p 143–180 ps, RMS 51–56 ps — stable<br>- <strong>1.8 V supply:</strong> Mean 1.762–1.769 V, droop 6.7–12.0 mV — stable<br>- <strong>LP-11 voltage:</strong> 1.015–1.017 V — dead flat<br>- <strong>LP-11 duration:</strong> 1.73 µs — identical across all captures (hardware timer)</p>
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<p>### 3.2 LP-low Plateau Distribution (key finding)</p>
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<p>Tabulating across all 30 captures with LP data:</p>
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<p>| LP-low Plateau | Count | Flicker? |<br>|----------------|-------|----------|<br>| <strong>0 ns</strong> | 3 (0803, 0810, 0830) | <strong>YES — all 3 flicker events</strong> |<br>| <strong>~108 ns</strong> | 7 (0808, 0809, 0812, 0815, 0820, 0823, 0827, 0828) | No |<br>| <strong>~342-348 ns</strong> | 17 (0801, 0804, 0806, 0807, 0811, 0813, 0814, 0816, 0817, 0818, 0819, 0821, 0822, 0824, 0825, 0826, 0829) | No |<br>| <strong>No LP data</strong> | 2 (0802, 0805) — processing error | Unknown |</p>
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<p>This trimodal distribution (0 / 108 / 343 ns) is <strong>highly diagnostic</strong>. The LP-low plateau appears to be quantised at ~0, ~6, or ~18.5 byte-clock intervals:<br>- 343 ns ÷ 18.5 ns/bc ≈ <strong>18.5 bc</strong> (likely 19 bc counter)<br>- 108 ns ÷ 18.5 ns/bc ≈ <strong>5.8 bc</strong> (likely 6 bc counter)<br>- 0 ns = <strong>counter not loaded / skipped</strong></p>
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<p>The trimodal quantisation strongly suggests a <strong>race condition in the Samsung DSIM PHY state machine's SoT sequencer</strong>. The byte-clock domain loads the LP-state counters, but a metastability event at the boundary between the LP clock domain and the byte-clock domain occasionally causes a counter to load 0 or a reduced value.</p>
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<p><strong>The too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns spec) narrows the timing window for this counter load, making the race more likely to result in a 0 or reduced count.</strong></p>
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<ul><li></li></ul>
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<p>## 4. Supply Correlation Analysis</p>
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<p>### 4.1 1.8 V Supply vs Flicker Events</p>
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<p>| Capture | Flicker? | LP-low (ns) | 1.8V Mean (V) | Droop (mV) | Ripple RMS (mV) |<br>|---------|----------|-------------|----------------|------------|-----------------|<br>| 0803 | <strong>YES</strong> | 0 | 1.7638 | 7.9 | 5.65 |<br>| 0810 | <strong>YES</strong> | 0 | 1.7642 | 8.2 | 5.54 |<br>| 0830 | <strong>YES</strong> | 0 | 1.7685 | 8.5 | 5.42 |<br>| 0801 | No | 343 | 1.7644 | 8.4 | 5.40 |<br>| 0804 | No | 343 | 1.7680 | 12.0 | 5.97 |<br>| 0825 | No | 343 | 1.7625 | 10.5 | 5.92 |</p>
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<p><strong>Conclusion: No supply correlation.</strong> The flicker captures have droop/ripple values well within the range of non-flicker captures. Capture 0804 has the *highest* droop (12.0 mV) and *highest* ripple (5.97 mV) yet works perfectly. Capture 0830 (flicker) has the *highest* supply voltage (1.7685 V) in the batch. <strong>The supply is not the trigger.</strong></p>
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<p>### 4.2 Supply Health<br>- All captures: Min voltage ≥ 1.752 V (spec 1.71 V) ✓<br>- Maximum droop: 12.0 mV (< 1% of 1.8 V) ✓<br>- Ripple RMS: 5.12–5.97 mV — clean<br>- <strong>Supply is healthy and not contributing to the flicker.</strong></p>
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<ul><li></li></ul>
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<p>## 5. Warning/Error Explanations</p>
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<p>### 5.1 "CLK lane is in continuous HS mode — LP states not expected on CLK"<br><strong>Explanation:</strong> Normal. In DSI video mode, the CLK lane enters HS once at pipeline start and remains in continuous HS mode. LP→HS transitions are only expected on data lanes. <strong>No action needed.</strong></p>
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<p>### 5.2 "Only negative swings in capture window — amplitude may be underestimated"<br><strong>Explanation:</strong> The scope trigger captured a window where DAT0 was sending a long run of one polarity (e.g., a blanking pattern or repeated byte). With DDR signalling, a long run of `0x00` or `0xFF` data would produce only one polarity of differential swing. The reported amplitude (190–195 mV) is consistent with the proto captures, so <strong>this is a trigger windowing artefact, not a signal problem.</strong> The amplitude is valid as a lower bound.</p>
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<p>### 5.3 "No HS signal detected — line may be in LP state or idle" (sig/dat in 0804, 0808, 0811, 0813, 0827)<br><strong>Explanation:</strong> The high-res sig capture triggered during an inter-frame blanking interval when the data lane was in LP-11 or LP-00 idle state. In DSI video mode with non-burst timing, the data lane returns to LP between frames. <strong>Trigger timing variability, not a signal fault.</strong> Consider triggering sig captures on a specific HS burst.</p>
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<p>### 5.4 "[lp_dat] ERROR: index 200000 is out of bounds" (0802, 0805)<br><strong>Explanation:</strong> The LP analysis script's edge-detection algorithm ran off the end of the capture buffer without finding the expected LP→HS transition within the 200k-sample window. Most likely cause: <strong>the trigger fired too early or too late relative to the SoT event</strong>, placing it outside the capture window. These captures have no LP data — they are neither flicker-confirmed nor flicker-excluded. <strong>Increase LP capture depth or adjust trigger holdoff by ±1 µs.</strong></p>
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<p>### 5.5 "LP exit duration X ns below spec min 50 ns" (ALL captures with LP data)<br><strong>Explanation:</strong> This is the systemic problem. Every single data-lane LP capture shows LP exit (time from LP-11 falling edge to HS-0 crossing) of 1–4 ns versus the 50 ns minimum. <strong>The PHY's LP→HS transition is too fast for the bridge to track.</strong> The SN65DSI83's input comparators need time to switch from LP mode (high-voltage, ~1 V common mode) to HS mode (low-voltage, ~200 mV differential). A 1–4 ns transition gives no settling time.</p>
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<p><strong>Root cause linkage:</strong> This maps directly to the THS_EXIT violation (92.6 ns vs 100 ns spec). But the measured 1–4 ns is far shorter than even the programmed 92.6 ns. This suggests the LP exit metric is measuring a different event — likely the Dp/Dn single-ended fall time from LP-11 (~1.0 V) to 0 V, which is the analog slew rate of the LP driver turning off. The programmed THS_EXIT of 92.6 ns controls how long the PHY stays in LP-00 after LP-01 before asserting HS, but if the LP-01 and LP-00 states are being skipped or truncated (as the 0 ns LP-low plateau confirms), <strong>THS_EXIT never executes properly</strong>.</p>
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<p>### 5.6 "X settled samples below 140 mV" (CLK lane, all captures)<br><strong>Explanation:</strong> CLK differential amplitude has a negative-swing shortfall (−137 mV typical vs −140 mV spec). With noise, ~0.5–5% of settled HS samples dip below 140 mV. This is the <strong>CLK common-mode offset (+29 mV)</strong> causing asymmetric clipping. While functional, it reduces clock eye margin.</p>
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<ul><li></li></ul>
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<p>## 6. Detailed Root Cause Analysis</p>
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<p>### 6.1 Why the Flicker is Non-Deterministic</p>
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<p>The failure mechanism is a <strong>digital race condition in the DSIM PHY's SoT state machine</strong>, amplified by timing parameters set below spec:</p>
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<ol><li>At pipeline load, the DSIM controller commands the PHY to execute LP-11 → LP-01 → LP-00 → HS-0 (SoT sequence)</li><li>The LP-state durations are controlled by byte-clock counters loaded from PHYTIMING/PHYTIMING2 registers</li><li>THS_PREPARE+THS_ZERO is programmed to 9 byte-clocks (166.7 ns) — <strong>1.5 ns below the 168.2 ns spec minimum</strong></li><li>The PHY's internal clock-domain crossing between LP and HS domains has a synchronisation window</li><li>When the counter values are at the spec boundary, the synchroniser occasionally <strong>drops a count or skips the LP-00 state entirely</strong></li><li>This is a classic metastability-induced non-deterministic failure</li></ol>
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<p>The trimodal LP-low distribution (0 / 108 /</p>
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<p class="tokens">Tokens: 45448 in / 4096 out</p>
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</body>
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</html>
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