updates
This commit is contained in:
david rice
115
reports/20260417_084331_interactive.html
Normal file
115
reports/20260417_084331_interactive.html
Normal file
@@ -0,0 +1,115 @@
|
||||
<!DOCTYPE html>
|
||||
<html lang="en">
|
||||
<head>
|
||||
<meta charset="UTF-8">
|
||||
<title>MIPI Interactive Flicker Test — 2026-04-17 08:43:31</title>
|
||||
<style>
|
||||
body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
|
||||
padding: 0 20px; color: #222; }
|
||||
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
|
||||
h2 { color: #1a3a5c; margin-top: 32px; }
|
||||
h3 { color: #333; }
|
||||
.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
|
||||
.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
|
||||
padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
|
||||
.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
|
||||
border-radius: 6px; font-size: 1.05em; font-weight: bold; }
|
||||
.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
|
||||
.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
|
||||
.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
|
||||
table { border-collapse: collapse; width: 100%; margin-top: 8px; }
|
||||
th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
|
||||
td { border: 1px solid #ddd; padding: 5px 10px; }
|
||||
tr:nth-child(even) { background: #fafafa; }
|
||||
pre { margin: 0; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
|
||||
<h1>MIPI Interactive Flicker Test Report</h1>
|
||||
<p class="meta">
|
||||
Generated: 2026-04-17 08:43:31 |
|
||||
Model: claude-opus-4-6
|
||||
</p>
|
||||
|
||||
<div class="stop-box">
|
||||
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
|
||||
</div>
|
||||
|
||||
<div>
|
||||
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
|
||||
<div class="stat s-false">0 false alarm(s)</div>
|
||||
<div class="stat s-claude-no">0 Claude said no</div>
|
||||
</div>
|
||||
|
||||
<h2>D-PHY Configuration</h2>
|
||||
<p>
|
||||
Pixel clock: <strong>72.0 MHz</strong> |
|
||||
Bit rate: <strong>432.0 Mbit/s per lane</strong> |
|
||||
Byte clock: <strong>54.000 MHz</strong>
|
||||
(18.519 ns/byte) |
|
||||
UI: <strong>2.315 ns</strong>
|
||||
</p>
|
||||
|
||||
<table>
|
||||
<tr>
|
||||
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
|
||||
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
|
||||
</tr>
|
||||
<tr><td><code>lpx</code></td><td>≥ 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
|
||||
<tr><td><code>hs_prepare</code></td><td>49.3 – 98.9</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
|
||||
<tr><td><code>hs_zero</code></td><td>≥ 112.6</td><td>6</td><td>7</td><td>+0</td><td><strong>7</strong></td><td>129.63</td><td>✓</td></tr>
|
||||
<tr><td><code>hs_trail</code></td><td>≥ 69.3</td><td>4</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>✓</td></tr>
|
||||
<tr><td><code>hs_exit</code></td><td>≥ 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>✓</td></tr>
|
||||
<tr><td><code>clk_prepare</code></td><td>38.0 – 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
|
||||
<tr><td><code>clk_zero</code></td><td>≥ 244.4</td><td>13</td><td>14</td><td>+0</td><td><strong>14</strong></td><td>259.26</td><td>✓</td></tr>
|
||||
<tr><td><code>clk_post</code></td><td>≥ 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>✓</td></tr>
|
||||
<tr><td><code>clk_trail</code></td><td>≥ 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>✓</td></tr>
|
||||
|
||||
</table>
|
||||
|
||||
<p style="color:#2e7d32">✓ All D-PHY v1.1 Table 14 constraints satisfied.</p>
|
||||
|
||||
<h3>Samsung DSIM Registers</h3>
|
||||
<table>
|
||||
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
|
||||
<tr>
|
||||
<td>PHY_TIMING</td><td><code>0xb4</code></td>
|
||||
<td><code>0x00000306</code></td>
|
||||
<td>lpx=3 hs_exit=6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
|
||||
<td><code>0x030e0a04</code></td>
|
||||
<td>clk_prepare=3 clk_zero=14
|
||||
clk_post=10 clk_trail=4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
|
||||
<td><code>0x00030704</code></td>
|
||||
<td>hs_prepare=3 hs_zero=7
|
||||
hs_trail=4</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
<h3>u-boot Commands</h3>
|
||||
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
|
||||
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
|
||||
#
|
||||
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
|
||||
# PHY_TIMING1 (0xb8) = 0x030e0a04 clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
|
||||
# PHY_TIMING2 (0xbc) = 0x00030704 hs_prepare=3 hs_zero=7 hs_trail=4
|
||||
|
||||
# Enable Round-Up rounding (dsi-tweak bit 2)
|
||||
setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"
|
||||
|
||||
saveenv
|
||||
boot</pre>
|
||||
|
||||
<h2>Event Log</h2>
|
||||
<p>No flicker suspects were detected during this test run.</p>
|
||||
|
||||
|
||||
|
||||
</body>
|
||||
</html>
|
||||
Reference in New Issue
Block a user