From c196a2a29cf76b6679d7d4de9f268a8b9c6cb806 Mon Sep 17 00:00:00 2001 From: david rice Date: Fri, 17 Apr 2026 11:27:41 +0100 Subject: [PATCH] updates --- __pycache__/csv_preprocessor.cpython-312.pyc | Bin 41190 -> 41319 bytes csv_preprocessor.py | 46 +++--- reports/20260417_080439_interactive.html | 115 +++++++++++++++ reports/20260417_084331_interactive.html | 115 +++++++++++++++ reports/20260417_092953_interactive.html | 126 ++++++++++++++++ reports/20260417_102901_interactive.html | 143 +++++++++++++++++++ reports/flicker_log.csv | 19 +++ reports/interactive_log.csv | 19 +++ 8 files changed, 564 insertions(+), 19 deletions(-) create mode 100644 reports/20260417_080439_interactive.html create mode 100644 reports/20260417_084331_interactive.html create mode 100644 reports/20260417_092953_interactive.html create mode 100644 reports/20260417_102901_interactive.html diff --git a/__pycache__/csv_preprocessor.cpython-312.pyc b/__pycache__/csv_preprocessor.cpython-312.pyc index 91776f4c77603fb5140bac8374a066194df15664..3950fb9864c8ca1e473f6caee1a7ae4343b891ff 100644 GIT binary patch delta 908 zcmYjOUr19?7(eIEo4ae*tJAx(ImM=1Y0f*-bpA;V(jZ3l;8VhI+)zTxYeEnN^(~!v;QYRGe!t&$&i9@3ZI#)1 z%cOkdc>{v+!tk|yYVK)DoWPSh&Tw(Th`@W@6KJK6&LRPD7k4K0U9At-7f|Z;LN*qf7C-;q(00AvNHlZ#*Kcb6e=cNsD0+_;q;Ez)kJl zdIq3ptCfO(Adlq+?q=F<-J!GgGr{dEyIO++nfuFx3*aRD?zMPaQT_MrzJO z6l){(7vr%3M;b5fvO1e-T+m)ln{cxoahAorb-g`?Fz1LEvlqn;qdm$Z))X}$?)bE_ zuD8WdGG~YwEnC^;8^-dO4t7yJN{J`(_D$ZiT(ec}*(mhH5W`!)2w719u^CY_)zAL1 zUQR-M$?x3;j7qQKfDxKq(+N#((|aA?RIBCA^; OwfjFtd$jEZ1O5l`;P@2) delta 743 zcmYk2Ur1AN6vyxHUN^mScWY~R>hwBvEiLulWzIiIkQV7fQV>3gsPjhoP{cN~?01b! zb4v;H7@8rC@=XHcKJ-*!NYEc>G9UKPgHK7lv?d8bP-mLa4}PET?|jeU{0?X1HT!v) zwY(Pu6NAU}V!bba?wKWdGbfJ5m@>nF@4OpcmQBH<;d)NdjIb<=@NL*Z6o|Amvrz>; zwB%sen}I9;A=jkca4AWHogl4^t6Y zL+waEm65fy0?1u*mg!{))5~dA%`$**_&SkG>h-OOYh3o1F8nXpreB$yB)WA9_v+LA zppqi%g-}7>s!fDr4TbPy+GQF-KaOh+wdw`;pK`6m zo=-OCbZ|zyr^Py!N)vhhgst{}t0a+Eld$=}bHrYoY&e2yYfK((%4jo59zU^Z;M|tT zX}$1)oivs+eEw`Wp5sX~9IqtJg=@uitLC~ihtayZAm)ghy=emmDI+7e)+Bk=ET?$J z;7C~@I`>Pu&M`vu&&`vBsX0SJW*mQov$hx6-*Q5Gss8xk03k!*nvW9D7v`U^&WkKD U&hASw8I3h=ZfmMr?~IwqAJc)^rvLx| diff --git a/csv_preprocessor.py b/csv_preprocessor.py index d2aee3f..d83f162 100644 --- a/csv_preprocessor.py +++ b/csv_preprocessor.py @@ -811,10 +811,11 @@ def analyze_lp_file(path: Path) -> "LPMetrics": if hs_bursts: s, e, _ = hs_bursts[0] burst_volts = volts[s:e] - hs_amplitude_mv = round( - (float(np.percentile(burst_volts, 95)) - - float(np.percentile(burst_volts, 5))) / 2 * 1000, 1 - ) + if len(burst_volts) >= 2: + hs_amplitude_mv = round( + (float(np.percentile(burst_volts, 95)) - + float(np.percentile(burst_volts, 5))) / 2 * 1000, 1 + ) # ── Warnings ───────────────────────────────────────────────────────── warnings = [] @@ -842,27 +843,34 @@ def analyze_lp_file(path: Path) -> "LPMetrics": warnings.append("No HS bursts detected after LP transition") # Flicker suspect: either the LP-low plateau is absent/short, OR the HS burst - # amplitude is too low (indicating the HS burst never actually started). + # amplitude is too low. Two confirmed failure modes on this hardware: # - # The second condition catches the confirmed failure mode on this hardware: - # LP-11 → LP-01/LP-00 preamble (normal ~342 ns) → bridge misses SoT - # → driver returns to LP-11 without entering HS mode - # → burst window is DC LP-11, hs_amplitude ≈ 15–30 mV (vs normal 105–122 mV). - # In this case lp_low_duration_ns = ~342 ns (above threshold), so the LP-low - # check alone produces a false negative. + # A) Normal LP-low (~342–380 ns) → bridge misses SoT → returns to LP-11 + # Signature: lp11_to_hs fires at real LP-low end (~347 ns), hs_amplitude ≈ 15–30 mV. + # Guard: lp11_to_hs >= LP_LOW_DUR_MIN_NS prevents DC-content false positives + # where the ~3 ns noise spike fires the gate but HS IS present. + # + # B) Short LP-low (50–200 ns, vs nominal ~342–380 ns) → marginal SoT timing + # → HS burst starts but is weak, hs_amplitude ≈ 40–60 mV (vs normal 100–122 mV). + # Signature: lp_low anomalously short, lp11_to_hs fires at noise spike (~3 ns). + # The lp11_to_hs guard cannot be used here (noise spike looks the same as mode A + # false positives), so LP-low duration itself gates the amplitude check. + # Confirmed example: capture 0120 (lp_low=108 ns, lp11_to_hs=1.7 ns, amp=49 mV). # # Only flag DAT lane (CLK is continuous HS — LP states not expected). - # Guard: require lp11_to_hs_ns >= LP_LOW_DUR_MIN_NS to rule out the consistent - # ~3 ns noise spike at LP-11 exit. On good captures the rolling-std gate fires - # at ~3 ns (hardware artifact); on confirmed flicker it fires at ~347 ns (real - # LP-low completes, then HS never starts → bridge returns to LP-11). - # Without this guard, DC-like HS data (uniform display content) produces low - # amplitude on otherwise good captures and causes false positives. + _lp_low_short = ( + lp_low_duration_ns is not None + and lp_low_duration_ns < 200.0 # below this, LP-low is anomalously brief + ) hs_burst_absent = ( hs_amplitude_mv is not None and hs_amplitude_mv < HS_BURST_AMPLITUDE_MIN_MV - and lp11_to_hs_ns is not None - and lp11_to_hs_ns >= LP_LOW_DUR_MIN_NS + and ( + # Mode A: LP-low normal, HS never started (rolling-std confirms it) + (lp11_to_hs_ns is not None and lp11_to_hs_ns >= LP_LOW_DUR_MIN_NS) + # Mode B: LP-low anomalously short + low amplitude = marginal HS launch + or _lp_low_short + ) ) flicker_suspect = ( channel == "dat" diff --git a/reports/20260417_080439_interactive.html b/reports/20260417_080439_interactive.html new file mode 100644 index 0000000..1d98ef7 --- /dev/null +++ b/reports/20260417_080439_interactive.html @@ -0,0 +1,115 @@ + + + + +MIPI Interactive Flicker Test — 2026-04-17 08:04:39 + + + + +

MIPI Interactive Flicker Test Report

+

+ Generated: 2026-04-17 08:04:39  |  + Model: claude-opus-4-6 +

+ +
+ Stop reason: Test interrupted by operator (Ctrl+C) +
+ +
+
0 confirmed flicker(s)
+
0 false alarm(s)
+
0 Claude said no
+
+ +

D-PHY Configuration

+

+ Pixel clock: 72.0 MHz  |  + Bit rate: 432.0 Mbit/s per lane  |  + Byte clock: 54.000 MHz + (18.519 ns/byte)  |  + UI: 2.315 ns +

+ + + + + + + + + + + + + + + + +
FieldSpec (ns)Rnd BestRnd UpExtraFinalActual (ns)Status
lpx≥ 50.033+0355.56✓
hs_prepare49.3 – 98.933+0355.56✓
hs_zero≥ 112.667+07129.63✓
hs_trail≥ 69.344+0474.07✓
hs_exit≥ 100.056+06111.11✓
clk_prepare38.0 – 95.023+0355.56✓
clk_zero≥ 244.41314+014259.26✓
clk_post≥ 180.41010+010185.19✓
clk_trail≥ 60.034+0474.07✓
+ +

✓ All D-PHY v1.1 Table 14 constraints satisfied.

+ +

Samsung DSIM Registers

+ + + + + + + + + + + + + + + + + +
RegisterAddressValueField breakdown
PHY_TIMING0xb40x00000306lpx=3   hs_exit=6
PHY_TIMING10xb80x030e0a04clk_prepare=3   clk_zero=14   + clk_post=10   clk_trail=4
PHY_TIMING20xbc0x00030704hs_prepare=3   hs_zero=7   + hs_trail=4
+ +

u-boot Commands

+
# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
+#
+# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
+# PHY_TIMING1 (0xb8) = 0x030e0a04   clk_prepare=3  clk_zero=14  clk_post=10  clk_trail=4
+# PHY_TIMING2 (0xbc) = 0x00030704   hs_prepare=3  hs_zero=7  hs_trail=4
+
+# Enable Round-Up rounding (dsi-tweak bit 2)
+setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"
+
+saveenv
+boot
+ +

Event Log

+

No flicker suspects were detected during this test run.

+ + + + + diff --git a/reports/20260417_084331_interactive.html b/reports/20260417_084331_interactive.html new file mode 100644 index 0000000..232659f --- /dev/null +++ b/reports/20260417_084331_interactive.html @@ -0,0 +1,115 @@ + + + + +MIPI Interactive Flicker Test — 2026-04-17 08:43:31 + + + + +

MIPI Interactive Flicker Test Report

+

+ Generated: 2026-04-17 08:43:31  |  + Model: claude-opus-4-6 +

+ +
+ Stop reason: Test interrupted by operator (Ctrl+C) +
+ +
+
0 confirmed flicker(s)
+
0 false alarm(s)
+
0 Claude said no
+
+ +

D-PHY Configuration

+

+ Pixel clock: 72.0 MHz  |  + Bit rate: 432.0 Mbit/s per lane  |  + Byte clock: 54.000 MHz + (18.519 ns/byte)  |  + UI: 2.315 ns +

+ + + + + + + + + + + + + + + + +
FieldSpec (ns)Rnd BestRnd UpExtraFinalActual (ns)Status
lpx≥ 50.033+0355.56✓
hs_prepare49.3 – 98.933+0355.56✓
hs_zero≥ 112.667+07129.63✓
hs_trail≥ 69.344+0474.07✓
hs_exit≥ 100.056+06111.11✓
clk_prepare38.0 – 95.023+0355.56✓
clk_zero≥ 244.41314+014259.26✓
clk_post≥ 180.41010+010185.19✓
clk_trail≥ 60.034+0474.07✓
+ +

✓ All D-PHY v1.1 Table 14 constraints satisfied.

+ +

Samsung DSIM Registers

+ + + + + + + + + + + + + + + + + +
RegisterAddressValueField breakdown
PHY_TIMING0xb40x00000306lpx=3   hs_exit=6
PHY_TIMING10xb80x030e0a04clk_prepare=3   clk_zero=14   + clk_post=10   clk_trail=4
PHY_TIMING20xbc0x00030704hs_prepare=3   hs_zero=7   + hs_trail=4
+ +

u-boot Commands

+
# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
+#
+# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
+# PHY_TIMING1 (0xb8) = 0x030e0a04   clk_prepare=3  clk_zero=14  clk_post=10  clk_trail=4
+# PHY_TIMING2 (0xbc) = 0x00030704   hs_prepare=3  hs_zero=7  hs_trail=4
+
+# Enable Round-Up rounding (dsi-tweak bit 2)
+setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"
+
+saveenv
+boot
+ +

Event Log

+

No flicker suspects were detected during this test run.

+ + + + + diff --git a/reports/20260417_092953_interactive.html b/reports/20260417_092953_interactive.html new file mode 100644 index 0000000..bba20a2 --- /dev/null +++ b/reports/20260417_092953_interactive.html @@ -0,0 +1,126 @@ + + + + +MIPI Interactive Flicker Test — 2026-04-17 09:29:53 + + + + +

MIPI Interactive Flicker Test Report

+

+ Generated: 2026-04-17 09:29:53  |  + Model: claude-opus-4-6 +

+ +
+ Stop reason: Test interrupted by operator (Ctrl+C) +
+ +
+
0 confirmed flicker(s)
+
2 false alarm(s)
+
6 Claude said no
+
+ +

D-PHY Configuration

+

+ Pixel clock: 72.0 MHz  |  + Bit rate: 432.0 Mbit/s per lane  |  + Byte clock: 54.000 MHz + (18.519 ns/byte)  |  + UI: 2.315 ns +

+ + + + + + + + + + + + + + + + +
FieldSpec (ns)Rnd BestRnd UpExtraFinalActual (ns)Status
lpx≥ 50.033+0355.56✓
hs_prepare49.3 – 98.933+0355.56✓
hs_zero≥ 112.667+07129.63✓
hs_trail≥ 69.344+0474.07✓
hs_exit≥ 100.056+06111.11✓
clk_prepare38.0 – 95.023+0355.56✓
clk_zero≥ 244.41314+014259.26✓
clk_post≥ 180.41010+010185.19✓
clk_trail≥ 60.034+0474.07✓
+ +

✓ All D-PHY v1.1 Table 14 constraints satisfied.

+ +

Samsung DSIM Registers

+ + + + + + + + + + + + + + + + + +
RegisterAddressValueField breakdown
PHY_TIMING0xb40x00000306lpx=3   hs_exit=6
PHY_TIMING10xb80x030e0a04clk_prepare=3   clk_zero=14   + clk_post=10   clk_trail=4
PHY_TIMING20xbc0x00030704hs_prepare=3   hs_zero=7   + hs_trail=4
+ +

u-boot Commands

+
# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
+#
+# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
+# PHY_TIMING1 (0xb8) = 0x030e0a04   clk_prepare=3  clk_zero=14  clk_post=10  clk_trail=4
+# PHY_TIMING2 (0xbc) = 0x00030704   hs_prepare=3  hs_zero=7  hs_trail=4
+
+# Enable Round-Up rounding (dsi-tweak bit 2)
+setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"
+
+saveenv
+boot
+ +

Event Log

+ + + + + + + +
CaptureTimestampChannelLP-low plateauLP exit→HSLP-11 voltageClaude: flicker?Outcome
000120260417_084455dat107.8 ns112.9 ns1.016 VNOClaude said NO — user not asked
000520260417_084634dat53.2 ns58.3 ns1.016 VNOClaude said NO — user not asked
002320260417_085336dat342.4 ns347.7 ns1.016 VNOClaude said NO — user not asked
002920260417_085602dat342.6 ns347.8 ns1.015 VNOClaude said NO — user not asked
003320260417_085742dat342.5 ns347.5 ns1.016 VNOClaude said NO — user not asked
007920260417_091529dat12.2 ns0.6 ns1.015 VYES✓ FALSE ALARM
008220260417_091657dat6.8 ns0.0 ns1.016 VYES✓ FALSE ALARM
008520260417_091825dat342.5 ns347.8 ns1.016 VNOClaude said NO — user not asked
+ +

Claude Assessments

Capture 0079 [20260417_091529] — FALSE ALARM

YES
+
+The LP-low plateau of 12.2 ns is far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, at only ~24% of the threshold. The LP exit-to-HS transition of just 0.6–1 ns confirms the LP-01/LP-00 preamble states were essentially skipped, giving the bridge no meaningful window to recognize the start-of-transmission. Despite the HS amplitude (116 mV) and LP-11 voltage (1.015 V) being within normal ranges—indicating the PHY is electrically healthy—the critically truncated LP-low plateau means the SN65DSI83 almost certainly missed this SoT entry, resulting in a lost or corrupted video frame and visible flicker.

Capture 0082 [20260417_091657] — FALSE ALARM

YES
+
+The LP-low plateau of 6.8 ns is dramatically below the SN65DSI83's 50 ns minimum requirement for SoT detection — it is only ~14% of the needed duration. The LP exit-to-HS transition time of 0 ns further confirms that the LP-01/LP-00 preamble states were essentially absent or too brief to be resolved, meaning the bridge almost certainly missed the start-of-transmission. The slightly elevated HS amplitude of 131 mV (above the normal 105–122 mV range) suggests the transmitter may have entered HS mode abruptly without proper state progression, consistent with a truncated entry sequence that would cause the SN65DSI83 to lose frame sync and produce visible flicker.
+ + + diff --git a/reports/20260417_102901_interactive.html b/reports/20260417_102901_interactive.html new file mode 100644 index 0000000..4760a48 --- /dev/null +++ b/reports/20260417_102901_interactive.html @@ -0,0 +1,143 @@ + + + + +MIPI Interactive Flicker Test — 2026-04-17 10:29:01 + + + + +

MIPI Interactive Flicker Test Report

+

+ Generated: 2026-04-17 10:29:01  |  + Model: claude-opus-4-6 +

+ +
+ Stop reason: Test interrupted by operator (Ctrl+C) +
+ +
+
0 confirmed flicker(s)
+
8 false alarm(s)
+
3 Claude said no
+
+ +

D-PHY Configuration

+

+ Pixel clock: 72.0 MHz  |  + Bit rate: 432.0 Mbit/s per lane  |  + Byte clock: 54.000 MHz + (18.519 ns/byte)  |  + UI: 2.315 ns +

+ + + + + + + + + + + + + + + + +
FieldSpec (ns)Rnd BestRnd UpExtraFinalActual (ns)Status
lpx≥ 50.033+0355.56✓
hs_prepare49.3 – 98.933+1474.07✓
hs_zero≥ 94.156+06111.11✓
hs_trail≥ 69.344+1592.59✓
hs_exit≥ 100.056+06111.11✓
clk_prepare38.0 – 95.023+0355.56✓
clk_zero≥ 244.41314+317314.81✓
clk_post≥ 180.41010+010185.19✓
clk_trail≥ 60.034+0474.07✓
+ +

✓ All D-PHY v1.1 Table 14 constraints satisfied.

+ +

Samsung DSIM Registers

+ + + + + + + + + + + + + + + + + +
RegisterAddressValueField breakdown
PHY_TIMING0xb40x00000306lpx=3   hs_exit=6
PHY_TIMING10xb80x03110a04clk_prepare=3   clk_zero=17   + clk_post=10   clk_trail=4
PHY_TIMING20xbc0x00040605hs_prepare=4   hs_zero=6   + hs_trail=5
+ +

u-boot Commands

+
# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
+#
+# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
+# PHY_TIMING1 (0xb8) = 0x03110a04   clk_prepare=3  clk_zero=17  clk_post=10  clk_trail=4
+# PHY_TIMING2 (0xbc) = 0x00040605   hs_prepare=4  hs_zero=6  hs_trail=5
+
+# Enable Round-Up rounding (dsi-tweak bit 2)
+setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"
+
+# Extra PHY cycles above Round-Up minimum
+setenv flb_dtovar "${flb_dtovar} dsi-phy-extra-hs-prepare=1"
+setenv flb_dtovar "${flb_dtovar} dsi-phy-extra-hs-trail=1"
+setenv flb_dtovar "${flb_dtovar} dsi-phy-extra-clk-zero=3"
+
+saveenv
+boot
+ +

Event Log

+ + + + + + + +
CaptureTimestampChannelLP-low plateauLP exit→HSLP-11 voltageClaude: flicker?Outcome
000220260417_094040dat379.5 ns384.6 ns1.016 VNOClaude said NO — user not asked
002620260417_095000dat33.0 ns3.0 ns1.015 VYES✓ FALSE ALARM
004020260417_095538dat379.7 ns384.8 ns1.015 VNOClaude said NO — user not asked
005120260417_100005dat27.0 ns0.1 ns1.016 VYES✓ FALSE ALARM
005220260417_100044dat25.7 ns0.1 ns1.016 VYES✓ FALSE ALARM
005320260417_100121dat46.4 ns2.9 ns1.014 VYES✓ FALSE ALARM
006320260417_100527datNone ns0.0 ns1.016 VYES✓ FALSE ALARM
008420260417_101343dat42.9 ns0.6 ns1.014 VYES✓ FALSE ALARM
008720260417_101509dat34.1 ns0.2 ns1.016 VYES✓ FALSE ALARM
009220260417_101718datNone ns0.0 ns1.016 VYES✓ FALSE ALARM
010620260417_102300dat379.5 ns384.6 ns1.015 VNOClaude said NO — user not asked
+ +

Claude Assessments

Capture 0026 [20260417_095000] — FALSE ALARM

YES
+
+The LP-low plateau of 33 ns is well below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of only 3 ns (versus the 50 ns spec minimum) confirms that the LP-01/LP-00 preamble states were too brief for the bridge to properly recognize the start-of-transmission. With these two critical timing violations—LP-low plateau at 66% of the required minimum and the LP exit duration at just 6% of spec—the bridge almost certainly missed the SoT, resulting in a lost or corrupted HS burst. The HS amplitude of 116 mV is healthy and the LP-11 voltage is in spec, so this is purely an LP timing issue causing the flicker, not a signal level problem.

Capture 0051 [20260417_100005] — FALSE ALARM

YES
+
+The LP-low plateau of 27 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition time of 0.1 ns confirms the LP-01/LP-00 preamble states were essentially absent. Additionally, the HS amplitude of 42 mV is far below the normal 105–122 mV range and sits below the 50 mV threshold, indicating the bridge almost certainly failed to lock onto the HS data burst. These three compounding failures — insufficient LP-low plateau duration, missing LP exit timing, and sub-threshold HS amplitude — make it virtually certain the SN65DSI83 missed this SoT, resulting in a dropped or corrupted frame and visible flicker.

Capture 0052 [20260417_100044] — FALSE ALARM

YES
+
+The LP-low plateau measured at 25.7–26 ns is roughly half the SN65DSI83's required ≥ 50 ns minimum, meaning the bridge almost certainly failed to detect the Start-of-Transmission. The LP exit-to-HS transition of 0–0.1 ns further confirms that the LP-01/LP-00 states were essentially absent or far too brief for reliable SoT recognition. Although the HS amplitude (128 mV) and LP-11 voltage (1.016 V) are within or near normal bounds, the critically short LP-low preamble is the dominant failure mode and would cause the SN65DSI83 to miss this HS burst, resulting in visible display flicker.

Capture 0053 [20260417_100121] — FALSE ALARM

YES
+
+The LP-low plateau of 46.4 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of only 2.9–3 ns is drastically shorter than the 50 ns specification minimum, indicating the LP-01/LP-00 preamble states were too brief for the bridge to properly recognize the start-of-transmission. The HS amplitude of 131 mV, while indicating an HS burst did occur, is slightly above the normal 105–122 mV range, suggesting possible impedance or termination anomalies that could compound the timing issue. With both the LP-low plateau and LP exit duration failing spec, the SN65DSI83 almost certainly missed this SoT entry, resulting in a dropped or corrupted video frame and visible flicker.

Capture 0063 [20260417_100527] — FALSE ALARM

YES
+
+The LP-low plateau is reported as `None` (absent), and the LP exit → HS transition time is 0 ns—both far below the SN65DSI83's required ≥ 50 ns LP-01/LP-00 preamble for reliable SoT detection. Additionally, the HS amplitude is 0 mV (well below the normal 105–122 mV range and below the 50 mV detection threshold), confirming the bridge almost certainly did not recognize valid HS data in this burst. Together, the missing LP-low preamble and absent HS signaling mean the SN65DSI83 would have failed to lock onto the start-of-transmission, producing a visible flicker event on the display.

Capture 0084 [20260417_101343] — FALSE ALARM

YES
+
+The LP-low plateau of 42.9 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection. Additionally, the LP exit-to-HS transition of only 1 ns (vs. the 50 ns spec minimum) indicates the LP-01/LP-00 preamble states were essentially skipped, making it nearly impossible for the bridge to recognize the start-of-transmission. The HS amplitude of 49 mV is also critically low—well below the normal 105–122 mV range and at the threshold of being classified as absent—which further confirms the bridge likely failed to lock onto the HS data burst. All three anomalies together make this a clear flicker event.

Capture 0087 [20260417_101509] — FALSE ALARM

YES
+
+The LP-low plateau of 34.1 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, falling short by nearly 16 ns (~32%). Additionally, the LP exit → HS transition time of 0 ns confirms the LP-01/LP-00 preamble states are essentially absent or too brief to be properly resolved, which the bridge needs to recognize the start-of-transmission sequence. Despite the HS amplitude (119 mV) and LP-11 voltage (1.016 V) being within normal operating ranges—indicating the PHY is otherwise functional—the truncated LP-low plateau means the SN65DSI83 will almost certainly miss this SoT event, causing a lost video line or frame and resulting in visible display flicker.

Capture 0092 [20260417_101718] — FALSE ALARM

YES
+
+The LP-low plateau is completely absent (reported as `None` / 0 ns), far below the SN65DSI83's minimum 50 ns requirement for SoT detection. Additionally, the HS amplitude of only 5 mV is well below the normal 105–122 mV range and even below the 50 mV "absent" threshold, confirming the bridge could not have locked onto a valid HS data burst. Together, the missing LP-01/LP-00 preamble and effectively absent HS signaling mean the SN65DSI83 would have failed to recognize this transmission entirely, producing a dropped frame and visible flicker.
+ + + diff --git a/reports/flicker_log.csv b/reports/flicker_log.csv index 5a7695c..64ee995 100644 --- a/reports/flicker_log.csv +++ b/reports/flicker_log.csv @@ -123,3 +123,22 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v 2026-04-16 14:17:02,20260416_141640,0309,dat,342.8,347.6,1.015 2026-04-16 14:22:07,20260416_142146,0322,dat,342.7,347.8,1.015 2026-04-16 14:28:21,20260416_142759,0338,dat,,,1.015 +2026-04-17 08:45:17,20260417_084455,0001,dat,107.8,112.9,1.016 +2026-04-17 08:46:56,20260417_084634,0005,dat,53.2,58.3,1.016 +2026-04-17 08:53:58,20260417_085336,0023,dat,342.4,347.7,1.016 +2026-04-17 08:56:24,20260417_085602,0029,dat,342.6,347.8,1.015 +2026-04-17 08:58:05,20260417_085742,0033,dat,342.5,347.5,1.016 +2026-04-17 09:15:50,20260417_091529,0079,dat,12.2,0.6,1.015 +2026-04-17 09:17:18,20260417_091657,0082,dat,6.8,0.0,1.016 +2026-04-17 09:18:46,20260417_091825,0085,dat,342.5,347.8,1.016 +2026-04-17 09:41:02,20260417_094040,0002,dat,379.5,384.6,1.016 +2026-04-17 09:50:21,20260417_095000,0026,dat,33.0,3.0,1.015 +2026-04-17 09:56:00,20260417_095538,0040,dat,379.7,384.8,1.015 +2026-04-17 10:00:26,20260417_100005,0051,dat,27.0,0.1,1.016 +2026-04-17 10:01:06,20260417_100044,0052,dat,25.7,0.1,1.016 +2026-04-17 10:01:43,20260417_100121,0053,dat,46.4,2.9,1.014 +2026-04-17 10:05:49,20260417_100527,0063,dat,,0.0,1.016 +2026-04-17 10:14:04,20260417_101343,0084,dat,42.9,0.6,1.014 +2026-04-17 10:15:31,20260417_101509,0087,dat,34.1,0.2,1.016 +2026-04-17 10:17:40,20260417_101718,0092,dat,,0.0,1.016 +2026-04-17 10:23:22,20260417_102300,0106,dat,379.5,384.6,1.015 diff --git a/reports/interactive_log.csv b/reports/interactive_log.csv index bc7ec8b..2637d07 100644 --- a/reports/interactive_log.csv +++ b/reports/interactive_log.csv @@ -53,3 +53,22 @@ logged_at,capture_ts,capture_num,claude_said_flicker,user_confirmed,lp_low_ns,re 2026-04-16 14:17:09,20260416_141640,0309,NO,NOT_ASKED,342.8,NO The LP-low plateau of 342.8 ns and the LP-11→HS transition time of 347.6 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for 2026-04-16 14:22:13,20260416_142146,0322,NO,NOT_ASKED,342.7,"NO The LP-low plateau of 342.7 ns and the LP-11-to-HS transition time of 347.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement, " 2026-04-16 15:36:49,20260416_142759,0338,YES,NO,,"YES The LP-low plateau is reported as `None` (absent), meaning the DAT0 lane never presented a valid LP-01/LP-00 preamble long enough to be measured " +2026-04-17 08:45:23,20260417_084455,0001,NO,NOT_ASKED,107.8,"NO The LP-low plateau measures 107.8 ns, which comfortably exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection. The LP-11 voltage (1." +2026-04-17 08:47:03,20260417_084634,0005,NO,NOT_ASKED,53.2,"NO The LP-low plateau measures 53.2 ns, which exceeds the SN65DSI83's 50 ns minimum detection threshold, so the SoT preamble timing itself is valid a" +2026-04-17 08:54:05,20260417_085336,0023,NO,NOT_ASKED,342.4,"NO The LP-low plateau of 342.4 ns and the LP-11-to-HS transition time of 347.7 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement, " +2026-04-17 08:56:31,20260417_085602,0029,NO,NOT_ASKED,342.6,NO The LP-low plateau of 342.6 ns and the LP-11-to-HS transition time of 347.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement f +2026-04-17 08:58:12,20260417_085742,0033,NO,NOT_ASKED,342.5,NO The LP-low plateau of 342.5 ns and LP-11→HS transition time of 347.5 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for SoT +2026-04-17 09:16:09,20260417_091529,0079,YES,NO,12.2,"YES The LP-low plateau of 12.2 ns is far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, at only ~24% of the threshold. Th" +2026-04-17 09:17:37,20260417_091657,0082,YES,NO,6.8,YES The LP-low plateau of 6.8 ns is dramatically below the SN65DSI83's 50 ns minimum requirement for SoT detection — it is only ~14% of the needed du +2026-04-17 09:18:54,20260417_091825,0085,NO,NOT_ASKED,342.5,NO The LP-low plateau of 342.5 ns and the LP-exit-to-HS transition time of 348 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement f +2026-04-17 09:41:09,20260417_094040,0002,NO,NOT_ASKED,379.5,"NO The LP-low plateau measures 379.5 ns, which comfortably exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection, and the full LP→HS en" +2026-04-17 09:50:37,20260417_095000,0026,YES,NO,33.0,"YES The LP-low plateau of 33 ns is well below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of " +2026-04-17 09:56:13,20260417_095538,0040,NO,NOT_ASKED,379.7,NO The LP-low plateau of 379.7 ns and LP-11→HS transition time of 384.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for SoT +2026-04-17 10:00:43,20260417_100005,0051,YES,NO,27.0,"YES The LP-low plateau of 27 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition t" +2026-04-17 10:01:20,20260417_100044,0052,YES,NO,25.7,"YES The LP-low plateau measured at 25.7–26 ns is roughly half the SN65DSI83's required ≥ 50 ns minimum, meaning the bridge almost certainly failed to" +2026-04-17 10:01:58,20260417_100121,0053,YES,NO,46.4,"YES The LP-low plateau of 46.4 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of onl" +2026-04-17 10:06:02,20260417_100527,0063,YES,NO,,"YES The LP-low plateau is reported as `None` (absent), and the LP exit → HS transition time is 0 ns—both far below the SN65DSI83's required ≥ 50 ns L" +2026-04-17 10:14:21,20260417_101343,0084,YES,NO,42.9,"YES The LP-low plateau of 42.9 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection. Additionally, the LP exit-to-HS transit" +2026-04-17 10:15:46,20260417_101509,0087,YES,NO,34.1,"YES The LP-low plateau of 34.1 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, falling short by nearly 16 ns (~" +2026-04-17 10:18:00,20260417_101718,0092,YES,NO,,"YES The LP-low plateau is completely absent (reported as `None` / 0 ns), far below the SN65DSI83's minimum 50 ns requirement for SoT detection. Addit" +2026-04-17 10:23:29,20260417_102300,0106,NO,NOT_ASKED,379.5,"NO The LP-low plateau of 379.5 ns far exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection, and the LP→HS transition timing of 384.6 n"