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david rice
2026-04-17 11:27:41 +01:00
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<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Interactive Flicker Test &mdash; 2026-04-17 08:04:39</title>
<style>
body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
h2 { color: #1a3a5c; margin-top: 32px; }
h3 { color: #333; }
.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
border-radius: 6px; font-size: 1.05em; font-weight: bold; }
.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
table { border-collapse: collapse; width: 100%; margin-top: 8px; }
th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
tr:nth-child(even) { background: #fafafa; }
pre { margin: 0; }
</style>
</head>
<body>
<h1>MIPI Interactive Flicker Test Report</h1>
<p class="meta">
Generated: 2026-04-17 08:04:39 &nbsp;|&nbsp;
Model: claude-opus-4-6
</p>
<div class="stop-box">
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
</div>
<div>
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
<div class="stat s-false">0 false alarm(s)</div>
<div class="stat s-claude-no">0 Claude said no</div>
</div>
<h2>D-PHY Configuration</h2>
<p>
Pixel clock: <strong>72.0 MHz</strong> &nbsp;|&nbsp;
Bit rate: <strong>432.0 Mbit/s per lane</strong> &nbsp;|&nbsp;
Byte clock: <strong>54.000 MHz</strong>
(18.519&thinsp;ns/byte) &nbsp;|&nbsp;
UI: <strong>2.315 ns</strong>
</p>
<table>
<tr>
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
</tr>
<tr><td><code>lpx</code></td><td>&ge; 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_prepare</code></td><td>49.3 &ndash; 98.9</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_zero</code></td><td>&ge; 112.6</td><td>6</td><td>7</td><td>+0</td><td><strong>7</strong></td><td>129.63</td><td>&#10003;</td></tr>
<tr><td><code>hs_trail</code></td><td>&ge; 69.3</td><td>4</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
<tr><td><code>hs_exit</code></td><td>&ge; 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>clk_prepare</code></td><td>38.0 &ndash; 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>clk_zero</code></td><td>&ge; 244.4</td><td>13</td><td>14</td><td>+0</td><td><strong>14</strong></td><td>259.26</td><td>&#10003;</td></tr>
<tr><td><code>clk_post</code></td><td>&ge; 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>&#10003;</td></tr>
<tr><td><code>clk_trail</code></td><td>&ge; 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
</table>
<p style="color:#2e7d32">&#10003; All D-PHY v1.1 Table&nbsp;14 constraints satisfied.</p>
<h3>Samsung DSIM Registers</h3>
<table>
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
<tr>
<td>PHY_TIMING</td><td><code>0xb4</code></td>
<td><code>0x00000306</code></td>
<td>lpx=3 &nbsp; hs_exit=6</td>
</tr>
<tr>
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
<td><code>0x030e0a04</code></td>
<td>clk_prepare=3 &nbsp; clk_zero=14 &nbsp;
clk_post=10 &nbsp; clk_trail=4</td>
</tr>
<tr>
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
<td><code>0x00030704</code></td>
<td>hs_prepare=3 &nbsp; hs_zero=7 &nbsp;
hs_trail=4</td>
</tr>
</table>
<h3>u-boot Commands</h3>
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04 clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704 hs_prepare=3 hs_zero=7 hs_trail=4
# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar &quot;${flb_dtovar} dsi-tweak=4&quot;
saveenv
boot</pre>
<h2>Event Log</h2>
<p>No flicker suspects were detected during this test run.</p>
</body>
</html>

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<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Interactive Flicker Test &mdash; 2026-04-17 08:43:31</title>
<style>
body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
h2 { color: #1a3a5c; margin-top: 32px; }
h3 { color: #333; }
.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
border-radius: 6px; font-size: 1.05em; font-weight: bold; }
.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
table { border-collapse: collapse; width: 100%; margin-top: 8px; }
th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
tr:nth-child(even) { background: #fafafa; }
pre { margin: 0; }
</style>
</head>
<body>
<h1>MIPI Interactive Flicker Test Report</h1>
<p class="meta">
Generated: 2026-04-17 08:43:31 &nbsp;|&nbsp;
Model: claude-opus-4-6
</p>
<div class="stop-box">
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
</div>
<div>
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
<div class="stat s-false">0 false alarm(s)</div>
<div class="stat s-claude-no">0 Claude said no</div>
</div>
<h2>D-PHY Configuration</h2>
<p>
Pixel clock: <strong>72.0 MHz</strong> &nbsp;|&nbsp;
Bit rate: <strong>432.0 Mbit/s per lane</strong> &nbsp;|&nbsp;
Byte clock: <strong>54.000 MHz</strong>
(18.519&thinsp;ns/byte) &nbsp;|&nbsp;
UI: <strong>2.315 ns</strong>
</p>
<table>
<tr>
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
</tr>
<tr><td><code>lpx</code></td><td>&ge; 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_prepare</code></td><td>49.3 &ndash; 98.9</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_zero</code></td><td>&ge; 112.6</td><td>6</td><td>7</td><td>+0</td><td><strong>7</strong></td><td>129.63</td><td>&#10003;</td></tr>
<tr><td><code>hs_trail</code></td><td>&ge; 69.3</td><td>4</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
<tr><td><code>hs_exit</code></td><td>&ge; 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>clk_prepare</code></td><td>38.0 &ndash; 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>clk_zero</code></td><td>&ge; 244.4</td><td>13</td><td>14</td><td>+0</td><td><strong>14</strong></td><td>259.26</td><td>&#10003;</td></tr>
<tr><td><code>clk_post</code></td><td>&ge; 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>&#10003;</td></tr>
<tr><td><code>clk_trail</code></td><td>&ge; 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
</table>
<p style="color:#2e7d32">&#10003; All D-PHY v1.1 Table&nbsp;14 constraints satisfied.</p>
<h3>Samsung DSIM Registers</h3>
<table>
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
<tr>
<td>PHY_TIMING</td><td><code>0xb4</code></td>
<td><code>0x00000306</code></td>
<td>lpx=3 &nbsp; hs_exit=6</td>
</tr>
<tr>
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
<td><code>0x030e0a04</code></td>
<td>clk_prepare=3 &nbsp; clk_zero=14 &nbsp;
clk_post=10 &nbsp; clk_trail=4</td>
</tr>
<tr>
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
<td><code>0x00030704</code></td>
<td>hs_prepare=3 &nbsp; hs_zero=7 &nbsp;
hs_trail=4</td>
</tr>
</table>
<h3>u-boot Commands</h3>
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04 clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704 hs_prepare=3 hs_zero=7 hs_trail=4
# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar &quot;${flb_dtovar} dsi-tweak=4&quot;
saveenv
boot</pre>
<h2>Event Log</h2>
<p>No flicker suspects were detected during this test run.</p>
</body>
</html>

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<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Interactive Flicker Test &mdash; 2026-04-17 09:29:53</title>
<style>
body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
h2 { color: #1a3a5c; margin-top: 32px; }
h3 { color: #333; }
.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
border-radius: 6px; font-size: 1.05em; font-weight: bold; }
.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
table { border-collapse: collapse; width: 100%; margin-top: 8px; }
th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
tr:nth-child(even) { background: #fafafa; }
pre { margin: 0; }
</style>
</head>
<body>
<h1>MIPI Interactive Flicker Test Report</h1>
<p class="meta">
Generated: 2026-04-17 09:29:53 &nbsp;|&nbsp;
Model: claude-opus-4-6
</p>
<div class="stop-box">
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
</div>
<div>
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
<div class="stat s-false">2 false alarm(s)</div>
<div class="stat s-claude-no">6 Claude said no</div>
</div>
<h2>D-PHY Configuration</h2>
<p>
Pixel clock: <strong>72.0 MHz</strong> &nbsp;|&nbsp;
Bit rate: <strong>432.0 Mbit/s per lane</strong> &nbsp;|&nbsp;
Byte clock: <strong>54.000 MHz</strong>
(18.519&thinsp;ns/byte) &nbsp;|&nbsp;
UI: <strong>2.315 ns</strong>
</p>
<table>
<tr>
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
</tr>
<tr><td><code>lpx</code></td><td>&ge; 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_prepare</code></td><td>49.3 &ndash; 98.9</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_zero</code></td><td>&ge; 112.6</td><td>6</td><td>7</td><td>+0</td><td><strong>7</strong></td><td>129.63</td><td>&#10003;</td></tr>
<tr><td><code>hs_trail</code></td><td>&ge; 69.3</td><td>4</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
<tr><td><code>hs_exit</code></td><td>&ge; 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>clk_prepare</code></td><td>38.0 &ndash; 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>clk_zero</code></td><td>&ge; 244.4</td><td>13</td><td>14</td><td>+0</td><td><strong>14</strong></td><td>259.26</td><td>&#10003;</td></tr>
<tr><td><code>clk_post</code></td><td>&ge; 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>&#10003;</td></tr>
<tr><td><code>clk_trail</code></td><td>&ge; 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
</table>
<p style="color:#2e7d32">&#10003; All D-PHY v1.1 Table&nbsp;14 constraints satisfied.</p>
<h3>Samsung DSIM Registers</h3>
<table>
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
<tr>
<td>PHY_TIMING</td><td><code>0xb4</code></td>
<td><code>0x00000306</code></td>
<td>lpx=3 &nbsp; hs_exit=6</td>
</tr>
<tr>
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
<td><code>0x030e0a04</code></td>
<td>clk_prepare=3 &nbsp; clk_zero=14 &nbsp;
clk_post=10 &nbsp; clk_trail=4</td>
</tr>
<tr>
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
<td><code>0x00030704</code></td>
<td>hs_prepare=3 &nbsp; hs_zero=7 &nbsp;
hs_trail=4</td>
</tr>
</table>
<h3>u-boot Commands</h3>
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04 clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704 hs_prepare=3 hs_zero=7 hs_trail=4
# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar &quot;${flb_dtovar} dsi-tweak=4&quot;
saveenv
boot</pre>
<h2>Event Log</h2>
<table>
<tr>
<th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th>
<th>Claude: flicker?</th><th>Outcome</th>
</tr>
<tr><td>0001</td><td>20260417_084455</td><td>dat</td><td>107.8 ns</td><td>112.9 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0005</td><td>20260417_084634</td><td>dat</td><td>53.2 ns</td><td>58.3 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0023</td><td>20260417_085336</td><td>dat</td><td>342.4 ns</td><td>347.7 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0029</td><td>20260417_085602</td><td>dat</td><td>342.6 ns</td><td>347.8 ns</td><td>1.015 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0033</td><td>20260417_085742</td><td>dat</td><td>342.5 ns</td><td>347.5 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0079</td><td>20260417_091529</td><td>dat</td><td style="color:red">12.2 ns</td><td>0.6 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0082</td><td>20260417_091657</td><td>dat</td><td style="color:red">6.8 ns</td><td>0.0 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0085</td><td>20260417_091825</td><td>dat</td><td>342.5 ns</td><td>347.8 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr>
</table>
<h2>Claude Assessments</h2><h3>Capture 0079 [20260417_091529] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 12.2 ns is far below the SN65DSI83&#x27;s required ≥ 50 ns minimum for reliable SoT detection, at only ~24% of the threshold. The LP exit-to-HS transition of just 0.6–1 ns confirms the LP-01/LP-00 preamble states were essentially skipped, giving the bridge no meaningful window to recognize the start-of-transmission. Despite the HS amplitude (116 mV) and LP-11 voltage (1.015 V) being within normal ranges—indicating the PHY is electrically healthy—the critically truncated LP-low plateau means the SN65DSI83 almost certainly missed this SoT entry, resulting in a lost or corrupted video frame and visible flicker.</pre><h3>Capture 0082 [20260417_091657] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 6.8 ns is dramatically below the SN65DSI83&#x27;s 50 ns minimum requirement for SoT detection — it is only ~14% of the needed duration. The LP exit-to-HS transition time of 0 ns further confirms that the LP-01/LP-00 preamble states were essentially absent or too brief to be resolved, meaning the bridge almost certainly missed the start-of-transmission. The slightly elevated HS amplitude of 131 mV (above the normal 105–122 mV range) suggests the transmitter may have entered HS mode abruptly without proper state progression, consistent with a truncated entry sequence that would cause the SN65DSI83 to lose frame sync and produce visible flicker.</pre>
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<title>MIPI Interactive Flicker Test &mdash; 2026-04-17 10:29:01</title>
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<body>
<h1>MIPI Interactive Flicker Test Report</h1>
<p class="meta">
Generated: 2026-04-17 10:29:01 &nbsp;|&nbsp;
Model: claude-opus-4-6
</p>
<div class="stop-box">
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
</div>
<div>
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
<div class="stat s-false">8 false alarm(s)</div>
<div class="stat s-claude-no">3 Claude said no</div>
</div>
<h2>D-PHY Configuration</h2>
<p>
Pixel clock: <strong>72.0 MHz</strong> &nbsp;|&nbsp;
Bit rate: <strong>432.0 Mbit/s per lane</strong> &nbsp;|&nbsp;
Byte clock: <strong>54.000 MHz</strong>
(18.519&thinsp;ns/byte) &nbsp;|&nbsp;
UI: <strong>2.315 ns</strong>
</p>
<table>
<tr>
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
</tr>
<tr><td><code>lpx</code></td><td>&ge; 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_prepare</code></td><td>49.3 &ndash; 98.9</td><td>3</td><td>3</td><td>+1</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
<tr><td><code>hs_zero</code></td><td>&ge; 94.1</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>hs_trail</code></td><td>&ge; 69.3</td><td>4</td><td>4</td><td>+1</td><td><strong>5</strong></td><td>92.59</td><td>&#10003;</td></tr>
<tr><td><code>hs_exit</code></td><td>&ge; 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>clk_prepare</code></td><td>38.0 &ndash; 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>clk_zero</code></td><td>&ge; 244.4</td><td>13</td><td>14</td><td>+3</td><td><strong>17</strong></td><td>314.81</td><td>&#10003;</td></tr>
<tr><td><code>clk_post</code></td><td>&ge; 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>&#10003;</td></tr>
<tr><td><code>clk_trail</code></td><td>&ge; 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
</table>
<p style="color:#2e7d32">&#10003; All D-PHY v1.1 Table&nbsp;14 constraints satisfied.</p>
<h3>Samsung DSIM Registers</h3>
<table>
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
<tr>
<td>PHY_TIMING</td><td><code>0xb4</code></td>
<td><code>0x00000306</code></td>
<td>lpx=3 &nbsp; hs_exit=6</td>
</tr>
<tr>
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
<td><code>0x03110a04</code></td>
<td>clk_prepare=3 &nbsp; clk_zero=17 &nbsp;
clk_post=10 &nbsp; clk_trail=4</td>
</tr>
<tr>
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
<td><code>0x00040605</code></td>
<td>hs_prepare=4 &nbsp; hs_zero=6 &nbsp;
hs_trail=5</td>
</tr>
</table>
<h3>u-boot Commands</h3>
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
# PHY_TIMING1 (0xb8) = 0x03110a04 clk_prepare=3 clk_zero=17 clk_post=10 clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00040605 hs_prepare=4 hs_zero=6 hs_trail=5
# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar &quot;${flb_dtovar} dsi-tweak=4&quot;
# Extra PHY cycles above Round-Up minimum
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-hs-prepare=1&quot;
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-hs-trail=1&quot;
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-clk-zero=3&quot;
saveenv
boot</pre>
<h2>Event Log</h2>
<table>
<tr>
<th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th>
<th>Claude: flicker?</th><th>Outcome</th>
</tr>
<tr><td>0002</td><td>20260417_094040</td><td>dat</td><td>379.5 ns</td><td>384.6 ns</td><td>1.016 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0026</td><td>20260417_095000</td><td>dat</td><td style="color:red">33.0 ns</td><td>3.0 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0040</td><td>20260417_095538</td><td>dat</td><td>379.7 ns</td><td>384.8 ns</td><td>1.015 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr><tr><td>0051</td><td>20260417_100005</td><td>dat</td><td style="color:red">27.0 ns</td><td>0.1 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0052</td><td>20260417_100044</td><td>dat</td><td style="color:red">25.7 ns</td><td>0.1 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0053</td><td>20260417_100121</td><td>dat</td><td style="color:red">46.4 ns</td><td>2.9 ns</td><td>1.014 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0063</td><td>20260417_100527</td><td>dat</td><td style="color:red">None ns</td><td>0.0 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0084</td><td>20260417_101343</td><td>dat</td><td style="color:red">42.9 ns</td><td>0.6 ns</td><td>1.014 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0087</td><td>20260417_101509</td><td>dat</td><td style="color:red">34.1 ns</td><td>0.2 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0092</td><td>20260417_101718</td><td>dat</td><td style="color:red">None ns</td><td>0.0 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0106</td><td>20260417_102300</td><td>dat</td><td>379.5 ns</td><td>384.6 ns</td><td>1.015 V</td><td>NO</td><td><span style="color:#e65100">Claude said NO — user not asked</span></td></tr>
</table>
<h2>Claude Assessments</h2><h3>Capture 0026 [20260417_095000] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 33 ns is well below the SN65DSI83&#x27;s required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of only 3 ns (versus the 50 ns spec minimum) confirms that the LP-01/LP-00 preamble states were too brief for the bridge to properly recognize the start-of-transmission. With these two critical timing violations—LP-low plateau at 66% of the required minimum and the LP exit duration at just 6% of spec—the bridge almost certainly missed the SoT, resulting in a lost or corrupted HS burst. The HS amplitude of 116 mV is healthy and the LP-11 voltage is in spec, so this is purely an LP timing issue causing the flicker, not a signal level problem.</pre><h3>Capture 0051 [20260417_100005] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 27 ns is well below the SN65DSI83&#x27;s required ≥ 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition time of 0.1 ns confirms the LP-01/LP-00 preamble states were essentially absent. Additionally, the HS amplitude of 42 mV is far below the normal 105–122 mV range and sits below the 50 mV threshold, indicating the bridge almost certainly failed to lock onto the HS data burst. These three compounding failures — insufficient LP-low plateau duration, missing LP exit timing, and sub-threshold HS amplitude — make it virtually certain the SN65DSI83 missed this SoT, resulting in a dropped or corrupted frame and visible flicker.</pre><h3>Capture 0052 [20260417_100044] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau measured at 25.7–26 ns is roughly half the SN65DSI83&#x27;s required ≥ 50 ns minimum, meaning the bridge almost certainly failed to detect the Start-of-Transmission. The LP exit-to-HS transition of 0–0.1 ns further confirms that the LP-01/LP-00 states were essentially absent or far too brief for reliable SoT recognition. Although the HS amplitude (128 mV) and LP-11 voltage (1.016 V) are within or near normal bounds, the critically short LP-low preamble is the dominant failure mode and would cause the SN65DSI83 to miss this HS burst, resulting in visible display flicker.</pre><h3>Capture 0053 [20260417_100121] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 46.4 ns is below the SN65DSI83&#x27;s required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of only 2.9–3 ns is drastically shorter than the 50 ns specification minimum, indicating the LP-01/LP-00 preamble states were too brief for the bridge to properly recognize the start-of-transmission. The HS amplitude of 131 mV, while indicating an HS burst did occur, is slightly above the normal 105–122 mV range, suggesting possible impedance or termination anomalies that could compound the timing issue. With both the LP-low plateau and LP exit duration failing spec, the SN65DSI83 almost certainly missed this SoT entry, resulting in a dropped or corrupted video frame and visible flicker.</pre><h3>Capture 0063 [20260417_100527] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau is reported as `None` (absent), and the LP exit → HS transition time is 0 ns—both far below the SN65DSI83&#x27;s required ≥ 50 ns LP-01/LP-00 preamble for reliable SoT detection. Additionally, the HS amplitude is 0 mV (well below the normal 105–122 mV range and below the 50 mV detection threshold), confirming the bridge almost certainly did not recognize valid HS data in this burst. Together, the missing LP-low preamble and absent HS signaling mean the SN65DSI83 would have failed to lock onto the start-of-transmission, producing a visible flicker event on the display.</pre><h3>Capture 0084 [20260417_101343] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 42.9 ns is below the SN65DSI83&#x27;s required 50 ns minimum for reliable SoT detection. Additionally, the LP exit-to-HS transition of only 1 ns (vs. the 50 ns spec minimum) indicates the LP-01/LP-00 preamble states were essentially skipped, making it nearly impossible for the bridge to recognize the start-of-transmission. The HS amplitude of 49 mV is also critically low—well below the normal 105–122 mV range and at the threshold of being classified as absent—which further confirms the bridge likely failed to lock onto the HS data burst. All three anomalies together make this a clear flicker event.</pre><h3>Capture 0087 [20260417_101509] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 34.1 ns is well below the SN65DSI83&#x27;s required ≥ 50 ns minimum for reliable SoT detection, falling short by nearly 16 ns (~32%). Additionally, the LP exit → HS transition time of 0 ns confirms the LP-01/LP-00 preamble states are essentially absent or too brief to be properly resolved, which the bridge needs to recognize the start-of-transmission sequence. Despite the HS amplitude (119 mV) and LP-11 voltage (1.016 V) being within normal operating ranges—indicating the PHY is otherwise functional—the truncated LP-low plateau means the SN65DSI83 will almost certainly miss this SoT event, causing a lost video line or frame and resulting in visible display flicker.</pre><h3>Capture 0092 [20260417_101718] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau is completely absent (reported as `None` / 0 ns), far below the SN65DSI83&#x27;s minimum 50 ns requirement for SoT detection. Additionally, the HS amplitude of only 5 mV is well below the normal 105–122 mV range and even below the 50 mV &quot;absent&quot; threshold, confirming the bridge could not have locked onto a valid HS data burst. Together, the missing LP-01/LP-00 preamble and effectively absent HS signaling mean the SN65DSI83 would have failed to recognize this transmission entirely, producing a dropped frame and visible flicker.</pre>
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reports/flicker_log.csv
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@@ -123,3 +123,22 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v
2026-04-16 14:17:02,20260416_141640,0309,dat,342.8,347.6,1.015
2026-04-16 14:22:07,20260416_142146,0322,dat,342.7,347.8,1.015
2026-04-16 14:28:21,20260416_142759,0338,dat,,,1.015
2026-04-17 08:45:17,20260417_084455,0001,dat,107.8,112.9,1.016
2026-04-17 08:46:56,20260417_084634,0005,dat,53.2,58.3,1.016
2026-04-17 08:53:58,20260417_085336,0023,dat,342.4,347.7,1.016
2026-04-17 08:56:24,20260417_085602,0029,dat,342.6,347.8,1.015
2026-04-17 08:58:05,20260417_085742,0033,dat,342.5,347.5,1.016
2026-04-17 09:15:50,20260417_091529,0079,dat,12.2,0.6,1.015
2026-04-17 09:17:18,20260417_091657,0082,dat,6.8,0.0,1.016
2026-04-17 09:18:46,20260417_091825,0085,dat,342.5,347.8,1.016
2026-04-17 09:41:02,20260417_094040,0002,dat,379.5,384.6,1.016
2026-04-17 09:50:21,20260417_095000,0026,dat,33.0,3.0,1.015
2026-04-17 09:56:00,20260417_095538,0040,dat,379.7,384.8,1.015
2026-04-17 10:00:26,20260417_100005,0051,dat,27.0,0.1,1.016
2026-04-17 10:01:06,20260417_100044,0052,dat,25.7,0.1,1.016
2026-04-17 10:01:43,20260417_100121,0053,dat,46.4,2.9,1.014
2026-04-17 10:05:49,20260417_100527,0063,dat,,0.0,1.016
2026-04-17 10:14:04,20260417_101343,0084,dat,42.9,0.6,1.014
2026-04-17 10:15:31,20260417_101509,0087,dat,34.1,0.2,1.016
2026-04-17 10:17:40,20260417_101718,0092,dat,,0.0,1.016
2026-04-17 10:23:22,20260417_102300,0106,dat,379.5,384.6,1.015
1 logged_at capture_ts capture_num channel lp_low_duration_ns lp11_to_hs_ns lp11_voltage_v
123 2026-04-16 14:17:02 20260416_141640 0309 dat 342.8 347.6 1.015
124 2026-04-16 14:22:07 20260416_142146 0322 dat 342.7 347.8 1.015
125 2026-04-16 14:28:21 20260416_142759 0338 dat 1.015
126 2026-04-17 08:45:17 20260417_084455 0001 dat 107.8 112.9 1.016
127 2026-04-17 08:46:56 20260417_084634 0005 dat 53.2 58.3 1.016
128 2026-04-17 08:53:58 20260417_085336 0023 dat 342.4 347.7 1.016
129 2026-04-17 08:56:24 20260417_085602 0029 dat 342.6 347.8 1.015
130 2026-04-17 08:58:05 20260417_085742 0033 dat 342.5 347.5 1.016
131 2026-04-17 09:15:50 20260417_091529 0079 dat 12.2 0.6 1.015
132 2026-04-17 09:17:18 20260417_091657 0082 dat 6.8 0.0 1.016
133 2026-04-17 09:18:46 20260417_091825 0085 dat 342.5 347.8 1.016
134 2026-04-17 09:41:02 20260417_094040 0002 dat 379.5 384.6 1.016
135 2026-04-17 09:50:21 20260417_095000 0026 dat 33.0 3.0 1.015
136 2026-04-17 09:56:00 20260417_095538 0040 dat 379.7 384.8 1.015
137 2026-04-17 10:00:26 20260417_100005 0051 dat 27.0 0.1 1.016
138 2026-04-17 10:01:06 20260417_100044 0052 dat 25.7 0.1 1.016
139 2026-04-17 10:01:43 20260417_100121 0053 dat 46.4 2.9 1.014
140 2026-04-17 10:05:49 20260417_100527 0063 dat 0.0 1.016
141 2026-04-17 10:14:04 20260417_101343 0084 dat 42.9 0.6 1.014
142 2026-04-17 10:15:31 20260417_101509 0087 dat 34.1 0.2 1.016
143 2026-04-17 10:17:40 20260417_101718 0092 dat 0.0 1.016
144 2026-04-17 10:23:22 20260417_102300 0106 dat 379.5 384.6 1.015

19
reports/interactive_log.csv
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@@ -53,3 +53,22 @@ logged_at,capture_ts,capture_num,claude_said_flicker,user_confirmed,lp_low_ns,re
2026-04-16 14:17:09,20260416_141640,0309,NO,NOT_ASKED,342.8,NO The LP-low plateau of 342.8 ns and the LP-11→HS transition time of 347.6 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for
2026-04-16 14:22:13,20260416_142146,0322,NO,NOT_ASKED,342.7,"NO The LP-low plateau of 342.7 ns and the LP-11-to-HS transition time of 347.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement, "
2026-04-16 15:36:49,20260416_142759,0338,YES,NO,,"YES The LP-low plateau is reported as `None` (absent), meaning the DAT0 lane never presented a valid LP-01/LP-00 preamble long enough to be measured "
2026-04-17 08:45:23,20260417_084455,0001,NO,NOT_ASKED,107.8,"NO The LP-low plateau measures 107.8 ns, which comfortably exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection. The LP-11 voltage (1."
2026-04-17 08:47:03,20260417_084634,0005,NO,NOT_ASKED,53.2,"NO The LP-low plateau measures 53.2 ns, which exceeds the SN65DSI83's 50 ns minimum detection threshold, so the SoT preamble timing itself is valid a"
2026-04-17 08:54:05,20260417_085336,0023,NO,NOT_ASKED,342.4,"NO The LP-low plateau of 342.4 ns and the LP-11-to-HS transition time of 347.7 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement, "
2026-04-17 08:56:31,20260417_085602,0029,NO,NOT_ASKED,342.6,NO The LP-low plateau of 342.6 ns and the LP-11-to-HS transition time of 347.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement f
2026-04-17 08:58:12,20260417_085742,0033,NO,NOT_ASKED,342.5,NO The LP-low plateau of 342.5 ns and LP-11→HS transition time of 347.5 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for SoT
2026-04-17 09:16:09,20260417_091529,0079,YES,NO,12.2,"YES The LP-low plateau of 12.2 ns is far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, at only ~24% of the threshold. Th"
2026-04-17 09:17:37,20260417_091657,0082,YES,NO,6.8,YES The LP-low plateau of 6.8 ns is dramatically below the SN65DSI83's 50 ns minimum requirement for SoT detection — it is only ~14% of the needed du
2026-04-17 09:18:54,20260417_091825,0085,NO,NOT_ASKED,342.5,NO The LP-low plateau of 342.5 ns and the LP-exit-to-HS transition time of 348 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement f
2026-04-17 09:41:09,20260417_094040,0002,NO,NOT_ASKED,379.5,"NO The LP-low plateau measures 379.5 ns, which comfortably exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection, and the full LP→HS en"
2026-04-17 09:50:37,20260417_095000,0026,YES,NO,33.0,"YES The LP-low plateau of 33 ns is well below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of "
2026-04-17 09:56:13,20260417_095538,0040,NO,NOT_ASKED,379.7,NO The LP-low plateau of 379.7 ns and LP-11→HS transition time of 384.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for SoT
2026-04-17 10:00:43,20260417_100005,0051,YES,NO,27.0,"YES The LP-low plateau of 27 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition t"
2026-04-17 10:01:20,20260417_100044,0052,YES,NO,25.7,"YES The LP-low plateau measured at 25.7–26 ns is roughly half the SN65DSI83's required ≥ 50 ns minimum, meaning the bridge almost certainly failed to"
2026-04-17 10:01:58,20260417_100121,0053,YES,NO,46.4,"YES The LP-low plateau of 46.4 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of onl"
2026-04-17 10:06:02,20260417_100527,0063,YES,NO,,"YES The LP-low plateau is reported as `None` (absent), and the LP exit → HS transition time is 0 ns—both far below the SN65DSI83's required ≥ 50 ns L"
2026-04-17 10:14:21,20260417_101343,0084,YES,NO,42.9,"YES The LP-low plateau of 42.9 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection. Additionally, the LP exit-to-HS transit"
2026-04-17 10:15:46,20260417_101509,0087,YES,NO,34.1,"YES The LP-low plateau of 34.1 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, falling short by nearly 16 ns (~"
2026-04-17 10:18:00,20260417_101718,0092,YES,NO,,"YES The LP-low plateau is completely absent (reported as `None` / 0 ns), far below the SN65DSI83's minimum 50 ns requirement for SoT detection. Addit"
2026-04-17 10:23:29,20260417_102300,0106,NO,NOT_ASKED,379.5,"NO The LP-low plateau of 379.5 ns far exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection, and the LP→HS transition timing of 384.6 n"
1 logged_at capture_ts capture_num claude_said_flicker user_confirmed lp_low_ns reasoning_summary
53 2026-04-16 14:17:09 20260416_141640 0309 NO NOT_ASKED 342.8 NO The LP-low plateau of 342.8 ns and the LP-11→HS transition time of 347.6 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for
54 2026-04-16 14:22:13 20260416_142146 0322 NO NOT_ASKED 342.7 NO The LP-low plateau of 342.7 ns and the LP-11-to-HS transition time of 347.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement,
55 2026-04-16 15:36:49 20260416_142759 0338 YES NO YES The LP-low plateau is reported as `None` (absent), meaning the DAT0 lane never presented a valid LP-01/LP-00 preamble long enough to be measured
56 2026-04-17 08:45:23 20260417_084455 0001 NO NOT_ASKED 107.8 NO The LP-low plateau measures 107.8 ns, which comfortably exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection. The LP-11 voltage (1.
57 2026-04-17 08:47:03 20260417_084634 0005 NO NOT_ASKED 53.2 NO The LP-low plateau measures 53.2 ns, which exceeds the SN65DSI83's 50 ns minimum detection threshold, so the SoT preamble timing itself is valid a
58 2026-04-17 08:54:05 20260417_085336 0023 NO NOT_ASKED 342.4 NO The LP-low plateau of 342.4 ns and the LP-11-to-HS transition time of 347.7 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement,
59 2026-04-17 08:56:31 20260417_085602 0029 NO NOT_ASKED 342.6 NO The LP-low plateau of 342.6 ns and the LP-11-to-HS transition time of 347.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement f
60 2026-04-17 08:58:12 20260417_085742 0033 NO NOT_ASKED 342.5 NO The LP-low plateau of 342.5 ns and LP-11→HS transition time of 347.5 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for SoT
61 2026-04-17 09:16:09 20260417_091529 0079 YES NO 12.2 YES The LP-low plateau of 12.2 ns is far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, at only ~24% of the threshold. Th
62 2026-04-17 09:17:37 20260417_091657 0082 YES NO 6.8 YES The LP-low plateau of 6.8 ns is dramatically below the SN65DSI83's 50 ns minimum requirement for SoT detection — it is only ~14% of the needed du
63 2026-04-17 09:18:54 20260417_091825 0085 NO NOT_ASKED 342.5 NO The LP-low plateau of 342.5 ns and the LP-exit-to-HS transition time of 348 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement f
64 2026-04-17 09:41:09 20260417_094040 0002 NO NOT_ASKED 379.5 NO The LP-low plateau measures 379.5 ns, which comfortably exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection, and the full LP→HS en
65 2026-04-17 09:50:37 20260417_095000 0026 YES NO 33.0 YES The LP-low plateau of 33 ns is well below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of
66 2026-04-17 09:56:13 20260417_095538 0040 NO NOT_ASKED 379.7 NO The LP-low plateau of 379.7 ns and LP-11→HS transition time of 384.8 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for SoT
67 2026-04-17 10:00:43 20260417_100005 0051 YES NO 27.0 YES The LP-low plateau of 27 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition t
68 2026-04-17 10:01:20 20260417_100044 0052 YES NO 25.7 YES The LP-low plateau measured at 25.7–26 ns is roughly half the SN65DSI83's required ≥ 50 ns minimum, meaning the bridge almost certainly failed to
69 2026-04-17 10:01:58 20260417_100121 0053 YES NO 46.4 YES The LP-low plateau of 46.4 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of onl
70 2026-04-17 10:06:02 20260417_100527 0063 YES NO YES The LP-low plateau is reported as `None` (absent), and the LP exit → HS transition time is 0 ns—both far below the SN65DSI83's required ≥ 50 ns L
71 2026-04-17 10:14:21 20260417_101343 0084 YES NO 42.9 YES The LP-low plateau of 42.9 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection. Additionally, the LP exit-to-HS transit
72 2026-04-17 10:15:46 20260417_101509 0087 YES NO 34.1 YES The LP-low plateau of 34.1 ns is well below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, falling short by nearly 16 ns (~
73 2026-04-17 10:18:00 20260417_101718 0092 YES NO YES The LP-low plateau is completely absent (reported as `None` / 0 ns), far below the SN65DSI83's minimum 50 ns requirement for SoT detection. Addit
74 2026-04-17 10:23:29 20260417_102300 0106 NO NOT_ASKED 379.5 NO The LP-low plateau of 379.5 ns far exceeds the SN65DSI83's 50 ns minimum requirement for SoT detection, and the LP→HS transition timing of 384.6 n