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<!DOCTYPE html>
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<meta charset="UTF-8">
<title>MIPI Analysis — Captures 0138–0167</title>
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<body>
<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 4 of 30 display load sessions (13%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0143</td><td>20260410_112853</td><td>dat</td><td style='color:red'>0.2 ns</td><td>4.5 ns</td><td>1.016 V</td></tr><tr><td>0148</td><td>20260410_113041</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.015 V</td></tr><tr><td>0152</td><td>20260410_113207</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.9 ns</td><td>1.016 V</td></tr><tr><td>0164</td><td>20260410_113628</td><td>dat</td><td style='color:red'>0.2 ns</td><td>3.2 ns</td><td>1.015 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0138</td><td>20260410_112705</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260410_112727</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260410_112748</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260410_112810</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260410_112831</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260410_112853</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260410_112915</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260410_112936</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260410_112958</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260410_113020</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260410_113041</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260410_113102</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260410_113124</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260410_113146</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260410_113207</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260410_113229</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260410_113251</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260410_113312</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260410_113334</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260410_113356</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260410_113417</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260410_113439</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260410_113501</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260410_113522</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260410_113544</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260410_113606</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260410_113628</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260410_113649</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260410_113711</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0167</td><td>20260410_113733</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-10 11:42:18 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0138–0167 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0138–0167</p>
<ul><li></li></ul>
<p>## 1. CRITICAL FINDING: Register Mismatch Is the Root Cause</p>
<p>### Actual vs. Target Register Values</p>
<p>| Register | Target | Actual (all captures) | Impact |<br>|---|---|---|---|<br>| <strong>PHYTIMING (0xb4)</strong> | <strong>0x00000306</strong> | <strong>0x00000305</strong> | THS_EXIT=5 → 92.6 ns (spec ≥100 ns) <strong>✗ VIOLATION</strong> |<br>| <strong>PHYTIMING1 (0xb8)</strong> | <strong>0x03110A04</strong> | <strong>0x020e0a03</strong> | TCLK_PREPARE=2 → 37 ns (spec 38–95 ns) <strong>✗ VIOLATION</strong>; TCLK_ZERO=14 → 259 ns (spec ≥300 ns) <strong>✗ VIOLATION</strong>; TCLK_TRAIL=3 → 55.6 ns (spec ≥60 ns) <strong>✗ VIOLATION</strong> |<br>| <strong>PHYTIMING2 (0xbc)</strong> | <strong>0x00040A03</strong> | <strong>0x00030605</strong> | THS_PREPARE=5 → 92.6 ns (spec 40+4×UI=49 ns to 85+6×UI=99 ns) <strong>✗ BORDERLINE/VIOLATION at 93 ns</strong>; THS_ZERO=6 → 111 ns (spec ≥ 145+10×UI=168 ns) <strong>✗ VIOLATION</strong>; THS_TRAIL=3 → 55.6 ns (spec ≥ max(8×UI, 60+4×UI)=69.3 ns) <strong>✗ VIOLATION</strong> |</p>
<p><strong>Every single DSIM PHY timing register is wrong.</strong> The driver is not applying the target values. All 30 captures show the identical incorrect values, confirming this is a persistent configuration bug — not a transient failure.</p>
<p>### Decoded Timing Violations (actual register values)</p>
<p>| Parameter | Field Value | Actual Duration | D-PHY v1.1 Min | Status |<br>|---|---|---|---|---|<br>| TLPX | 3 | 55.6 ns | 50 ns | ✓ marginal |<br>| THS_EXIT | 5 | 92.6 ns | 100 ns | <strong>✗ SHORT by 7.4 ns</strong> |<br>| TCLK_PREPARE | 2 | 37.0 ns | 38 ns | <strong>✗ SHORT by 1 ns</strong> |<br>| TCLK_ZERO | 14 (0x0e) | 259 ns | 300 ns | <strong>✗ SHORT by 41 ns</strong> |<br>| TCLK_POST | 10 (0x0a) | 185 ns | ~180 ns | ✓ barely |<br>| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | <strong>✗ SHORT by 4.4 ns</strong> |<br>| THS_PREPARE | 5 | 92.6 ns | 49–99 ns | ✓ but high-side |<br>| THS_ZERO | 6 | 111 ns | 168 ns | <strong>✗ SHORT by 57 ns</strong> |<br>| THS_TRAIL | 3 | 55.6 ns | 69.3 ns | <strong>✗ SHORT by 13.7 ns</strong> |</p>
<p><strong>Six of nine timing parameters violate D-PHY v1.1 spec.</strong> The most damaging are:</p>
<ul><li><strong>THS_ZERO = 111 ns vs. 168 ns required</strong>: The data lane HS-Zero state is 34% too short. This is the interval where the receiver must detect the HS-0 level before the SoT (sync byte 0xB8). When it&#x27;s too short, the SN65DSI83&#x27;s CDR has insufficient time to lock before data arrives.</li><li><strong>TCLK_ZERO = 259 ns vs. 300 ns required</strong>: The clock lane HS-Zero is 14% too short, reducing the receiver&#x27;s window to acquire clock lock.</li><li><strong>THS_EXIT = 92.6 ns vs. 100 ns required</strong>: Exit from HS back to LP is too fast for receivers to reliably detect the transition.</li></ul>
<ul><li></li></ul>
<p>## 2. LP-Low Plateau Analysis: The Flicker Mechanism</p>
<p>### Distribution of LP-low plateau durations across all captures</p>
<p>| LP-low Plateau | Count | Flicker? | Captures |<br>|---|---|---|---|<br>| <strong>0 ns (absent)</strong> | <strong>4</strong> | <strong>YES — all 4</strong> | 0143, 0148, 0152, 0164 |<br>| ~108 ns | 4 | No | 0139, 0155, 0158, 0160, 0162 |<br>| ~342–348 ns | 20 | No | Remainder |<br>| Missing data | 1 | Unknown | 0141 (processing error) |</p>
<p><strong>Perfect correlation:</strong> Every flicker event corresponds to LP-low plateau = 0 ns. Every non-flicker event has LP-low ≥ 108 ns. There are no exceptions.</p>
<p>The LP-low plateau represents the combined duration of the LP-01 → LP-00 sequence that constitutes the data lane SoT entry. When THS_ZERO is programmed at only 111 ns (vs. 168 ns required), the PHY&#x27;s internal state machine has almost no timing margin. Under normal conditions, the silicon *happens* to produce a recognizable LP-00 state of ~342 ns — well above spec. But intermittently (~13% of startups), a race condition within the PHY causes the LP-01/LP-00 states to be completely swallowed, producing a direct LP-11 → HS transition with no detectable SoT sequence.</p>
<p><strong>Why it&#x27;s non-deterministic:</strong> The Samsung DSIM PHY&#x27;s internal PLL lock time and lane synchronization have cycle-to-cycle jitter. With the programmed THS_ZERO 34% below spec, the internal sequencer&#x27;s timing margin is negative. Most of the time the PLL locks fast enough that the sequencer still outputs the LP states; occasionally it doesn&#x27;t, and the SoT is corrupted.</p>
<p>The &quot;LP exit → HS&quot; metric (1–4 ns across all captures, including non-flicker ones) confirms that the LP-01 state itself is never being held for the required TLPX ≥ 50 ns — even on &quot;good&quot; startups, the LP-01 pulse is undetectably brief. What saves non-flicker sessions is the ~342 ns LP-00 plateau, which gives the SN65DSI83 enough time to detect the HS entry. When even that disappears (flicker cases), the bridge never acquires sync.</p>
<ul><li></li></ul>
<p>## 3. HS Signal Quality</p>
<p>### Consistent observations across all 30 captures:</p>
<p>| Parameter | CLK | DAT0 | Assessment |<br>|---|---|---|---|<br>| Vdiff amplitude | 165.6–169.1 mV | 177–224 mV | <strong>Marginal-low on CLK</strong> (spec 140–270 mV, only 26 mV above floor) |<br>| Common mode | +26.6 to +32.0 mV | −98 to +5 mV | CLK offset ✓; DAT asymmetric |<br>| Rise time 20–80% | 163.6–165.4 ps | 143.8–219.4 ps | ✓ within spec |<br>| Jitter p-p | 145–177 ps | — | ✓ acceptable |<br>| Samples below 140 mV | 21–153 per capture | 18–7280 per capture | <strong>✗ Persistent sub-spec excursions</strong> |</p>
<p><strong>Clock amplitude is running at ~167 mV — only 19% above the 140 mV floor.</strong> This provides essentially no margin against supply droop, temperature variation, or aging. The persistent sub-140 mV samples on both clock and data indicate ISI/reflection-induced amplitude dips that regularly breach the minimum.</p>
<p><strong>DAT0 asymmetry:</strong> Most sig/dat captures show only negative differential swings (Vdiff pos = 0.0 mV), indicating a probe/measurement artifact (likely single-ended measurement of one line only, or trigger position capturing only one data phase). However, proto/dat captures with both polarities show a consistent ~7–10 mV asymmetry between positive and negative swings, suggesting slight impedance mismatch or common-mode offset on the data lane.</p>
<ul><li></li></ul>
<p>## 4. 1.8 V Supply Rail Correlation</p>
<p>### Supply droop statistics:</p>
<p>| Droop Category | Count | Flicker events in category |<br>|---|---|---|<br>| &lt; 30 mV (healthy) | 7 | <strong>2 flicker</strong> (0143: 31 mV, 0148: 30.7 mV, 0164: 28.4 mV) |<br>| 30–50 mV (marginal) | 8 | 1 flicker (0152: 55.6 mV) |<br>| 50–68 mV (poor, some below 1.71 V) | 12 | 0 flicker |<br>| Below 1.71 V spec minimum | 5 | 0 flicker |</p>
<p><strong>No correlation between supply droop and flicker.</strong> Three of four flicker events occurred at modest droop (&lt;32 mV), while the deepest droops (66–68 mV, Vmin = 1.700 V) produced no flicker. This confirms the flicker is not supply-induced — it&#x27;s a timing/sequencing issue.</p>
<p>However, the supply health is independently concerning:<br>- <strong>5 captures</strong> dropped below the 1.71 V MIPI VDDIO minimum (0142: 1.700 V, 0147: 1.704 V, 0150: 1.700 V, 0151: 1.700 V, 0166: 1.708 V)<br>- Mean droop is ~43 mV; worst case is 67.7 mV<br>- This indicates <strong>insufficient bulk/MLCC decoupling</strong> near the MIPI PHY VDDIO pin</p>
<ul><li></li></ul>
<p>## 5. Warning/Error Explanations</p>
<p>| Warning | Cause | Action |<br>|---|---|---|<br>| &quot;CLK lane is in continuous HS mode&quot; | Normal for video-mode DSI — CLK runs continuously HS; no LP→HS expected on CLK | None needed |<br>| &quot;Only negative swings in capture window&quot; | sig/dat probe capturing during a single data symbol (long run of zeros/ones), or single-ended probe on one line only | Verify differential probe connection; not a device fault |<br>| &quot;No HS signal detected&quot; (sig/dat 0162, 0163; proto/dat 0155) | Trigger caught blanking interval (HFP/HBP) where DAT0 is in LP; CLK continues HS | Trigger refinement; not a device fault |<br>| &quot;LP exit duration X ns below spec min 50 ns&quot; | <strong>Register misconfiguration</strong>: THS_PREPARE (92.6 ns) is correct but the LP-01 state is too brief because the PHY sequencer races through it with the underspecified THS_ZERO | Fix registers |<br>| &quot;index 200000 is out of bounds&quot; (Capture 0141) | Buffer overrun in LP analysis script; the LP→HS edge was at or beyond the end of the capture window | Re-capture with wider window or earlier trigger |<br>| &quot;Supply droops below 1.71 V&quot; | Insufficient decoupling or trace resistance on VDDIO | Add MLCC capacitance |<br>| &quot;Settled samples below 140 mV&quot; | ISI/reflection causing Vdiff dips below 140 mV floor during HS toggling | Improve termination/routing; increase PHY drive strength if available |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### PRIORITY 1 — Fix PHY Timing Registers (ROOT CAUSE OF FLICKER)</p>
<p>The samsung-dsim (sec-dsim) driver is computing or writing incorrect values. Apply the <strong>target</strong> values via device-tree override or driver patch:</p>
<p>```<br>/* Device tree or driver patch */<br>DSIM_PHYTIMING = 0x00000306 /* TLPX=3, THS_EXIT=6 */<br>DSIM_PHYTIMING1 = 0x03110A04 /* TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4 */<br>DSIM_PHYTIMING2 = 0x00040A03 /* THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3 */<br>```</p>
<p><strong>Specific fixes and expected impact:</strong></p>
<p>| Field | Current → Target | Duration Change | Why It Matters |<br>|---|---|---|---|<br>| THS_ZERO | 6 → <strong>10</strong> | 111 → <strong>185 ns</strong> | Gives receiver 74 ns more to detect HS-0 before sync byte. <strong>Primary flicker fix.</strong> |<br>| TCLK_ZERO | 14 → <strong>17</strong> | 259 → <strong>315 ns</strong> | Allows proper clock CDR acquisition. Eliminates clock lock failures. |<br>| THS_EXIT | 5 → <strong>6</strong> | 92.6 → <strong>111 ns</strong> | Meets 100 ns minimum. Prevents LP re-entry confusion. |<br>| TCLK_PREPARE | 2 → <strong>3</strong> | 37 → <strong>55.6 ns</strong> | Meets 38 ns minimum with margin. |<br>| TCLK_TRAIL | 3 → <strong>4</strong> | 55.6 → <strong>74 ns</strong> | Meets 60 ns minimum with margin. |<br>| THS_TRAIL | 3 → <strong>4</strong> | 55.6 → <strong>74 ns</strong> | Meets 69.3 ns minimum with margin. |<br>| THS_PREPARE | 5 → <strong>3</strong> | 92.6 → <strong>55.6 ns</strong> | Moves from 93 ns (borderline over 99 ns max) to comfortable mid-range. |</p>
<p><strong>Verification:</strong> After applying, read back registers with `memtool md -l 0x32e100b4+0x0c` and confirm the target values. Run 100+ pipeline load/unload cycles to verify zero flicker.</p>
<p><strong>Driver investigation:</strong> The samsung-dsim driver&#x27;s `samsung_dsim_set_phy_timing()` function computes timing from the HS clock rate. At 432 Mbit/s the formula may be rounding down. Check:<br>- `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` in NXP BSP)<br>- The timing computation uses integer division that truncates; for low bitrates like 432 Mbps, every byte-clock unit matters<br>- Consider whether the NXP BSP has a known erratum or patch for this</p>
<p>### PRIORITY 2 — Improve 1.8 V VDDIO Decoupling</p>
<p>Although not correlated with flicker, the supply is out-of-spec:</p>
<ol><li><strong>Add 2×4.7 µF + 2×100 nF MLCC</strong> as close as possible to the MIPI PHY VDDIO pins on the SOM carrier board</li><li><strong>Check VDDIO trace impedance</strong> — the 67 mV droop at LP→HS transition (4 lanes switching simultaneously) suggests &gt;100 mΩ path resistance</li><li>Target: droop &lt; 30 mV, Vmin &gt; 1.71 V under all conditions</li></ol>
<p>### PRIORITY 3 — Clock Amplitude Margin</p>
<p>CLK differential amplitude at ~167 mV is only 19% above the 140 mV minimum:</p>
<ol><li>Check for excessive series resistance in AC coupling capacitors (use 0402 or 0201 with low ESR)</li><li>Verify 100 Ω differential termination at receiver (SN65DSI83 has internal, but external may be present and wrong value)</li><li>If the i.MX 8M Mini DPHY has programmable drive strength, increase by one step</li><li>Reduce trace length / improve impedance matching to eliminate the sub-140 mV ISI dips</li></ol>
<p>### PRIORITY 4 — Add Software Retry as Belt-and-Suspenders</p>
<p>Even after fixing registers, add a startup verification loop:</p>
<p>```c<br>/* After DSI pipeline enable, read SN65DSI83 status register 0x0A */<br>/* Bit 0 = PLL lock. If not locked within 50ms, unload and reload pipeline */<br>for (retries = 0</p>
<p class="tokens">Tokens: 33253 in / 4096 out</p>
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<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Analysis — Captures 0305–0334</title>
<style>
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
p { line-height: 1.6; }
ol, ul { line-height: 1.8; padding-left: 24px; }
li { margin: 4px 0; }
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
padding: 16px 20px; margin-bottom: 28px; }
.flicker-alert h2 { color: #e65100; margin-top: 0; }
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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table { border-collapse: collapse; width: 100%; }
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
@media print { body { margin: 20px; } }
</style>
</head>
<body>
<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0313</td><td>20260410_123438</td><td>dat</td><td style='color:red'>1.4 ns</td><td>0.1 ns</td><td>1.015 V</td></tr><tr><td>0320</td><td>20260410_123710</td><td>dat</td><td style='color:red'>0.2 ns</td><td>1.9 ns</td><td>1.017 V</td></tr><tr><td>0325</td><td>20260410_123858</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.5 ns</td><td>1.015 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0305</td><td>20260410_123145</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260410_123206</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260410_123228</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260410_123250</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260410_123312</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260410_123333</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260410_123355</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260410_123417</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260410_123438</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260410_123500</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260410_123521</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260410_123543</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260410_123604</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260410_123626</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260410_123648</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260410_123710</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260410_123731</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260410_123753</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260410_123815</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260410_123836</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260410_123858</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260410_123920</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260410_123941</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260410_124003</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260410_124024</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260410_124046</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260410_124108</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260410_124130</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0333</td><td>20260410_124151</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0334</td><td>20260410_124213</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-10 12:46:56 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0305–0334 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0305–0334</p>
<p>## 1. Root Cause Identification</p>
<p>### The Primary Problem: Register Mismatch — Driver Not Applying Target Timing</p>
<p><strong>This is the single most important finding.</strong> Every capture shows the same register values:</p>
<p>| Register | Actual (all captures) | Target (spec-compliant) | Delta |<br>|---|---|---|---|<br>| PHYTIMING (0xb4) | `0x00000305` | `0x00000306` | THS_EXIT: 5→93 ns vs 6→111 ns |<br>| PHYTIMING1 (0xb8) | `0x020e0a03` | `0x03110A04` | TCLK_PREPARE: 2→37 ns vs 3→56 ns; <strong>TCLK_ZERO: 14→259 ns vs 17→315 ns</strong>; TCLK_TRAIL: 3→56 ns vs 4→74 ns |<br>| PHYTIMING2 (0xbc) | `0x00030605` | `0x00040A03` | <strong>THS_PREPARE: 5→93 ns vs 3→56 ns</strong>; <strong>THS_ZERO: 6→111 ns vs 10→185 ns</strong>; THS_TRAIL: 3→56 ns vs 4→74 ns |</p>
<p><strong>Critical field-level decode of actual register 0xbc = `0x00030605`:</strong></p>
<p>| Field | Actual | Duration | D-PHY v1.1 Spec | Status |<br>|---|---|---|---|---|<br>| THS_PREPARE | 5 | 92.6 ns | 40+4×UI=49.3 ns … 85+6×UI=98.9 ns | ✓ but at upper edge |<br>| THS_ZERO | 6 | 111.1 ns | <strong>THS_ZERO + THS_PREPARE ≥ 145+10×UI = 168.2 ns</strong> → need THS_ZERO ≥ ~4.1 → 5 min | Marginal ✓ (combined = 203.7 ns ≥ 168.2 ns) |<br>| THS_TRAIL | 3 | 55.6 ns | max(n×8×UI, 60+n×4×UI) = 60+4×2.315 = <strong>69.3 ns</strong> | <strong>✗ VIOLATION</strong> |</p>
<p><strong>Critical field-level decode of actual register 0xb8 = `0x020e0a03`:</strong></p>
<p>| Field | Actual | Duration | Spec | Status |<br>|---|---|---|---|---|<br>| TCLK_PREPARE | 2 | 37.0 ns | 38 ns … 95 ns | <strong>✗ VIOLATION (37 &lt; 38 ns)</strong> |<br>| TCLK_ZERO | 14 (0x0e) | 259.3 ns | TCLK_PREPARE + TCLK_ZERO ≥ 300 ns | <strong>✗ VIOLATION (296.3 &lt; 300 ns)</strong> |<br>| TCLK_POST | 10 (0x0a) | 185.2 ns | 60 + 52×UI = 180.4 ns | ✓ barely |<br>| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | <strong>✗ VIOLATION (55.6 &lt; 60 ns)</strong> |</p>
<p>### Summary of Timing Violations in Running Registers</p>
<p>| Parameter | Required | Actual | Margin | Verdict |<br>|---|---|---|---|---|<br>| TCLK_PREPARE | ≥ 38 ns | 37.0 ns | <strong>−1 ns</strong> | <strong>FAIL</strong> |<br>| TCLK_PREPARE + TCLK_ZERO | ≥ 300 ns | 296.3 ns | <strong>−3.7 ns</strong> | <strong>FAIL</strong> |<br>| TCLK_TRAIL | ≥ 60 ns | 55.6 ns | <strong>−4.4 ns</strong> | <strong>FAIL</strong> |<br>| THS_TRAIL | ≥ 69.3 ns | 55.6 ns | <strong>−13.7 ns</strong> | <strong>FAIL</strong> |<br>| THS_EXIT | ≥ 100 ns | 92.6 ns | <strong>−7.4 ns</strong> | <strong>FAIL</strong> |<br>| TLPX | ≥ 50 ns | 55.6 ns | +5.6 ns | ✓ marginal |</p>
<p><strong>Five timing parameters are out of spec.</strong> The samsung-dsim driver is computing or applying incorrect values. The target values (which you&#x27;ve verified as compliant) are not reaching the hardware.</p>
<ul><li></li></ul>
<p>## 2. LP SoT Sequence Analysis — The Flicker Mechanism</p>
<p>### LP-Low Plateau Distribution (all captures with valid LP data)</p>
<p>| LP-low plateau | Captures | Flicker? |<br>|---|---|---|<br>| ~342–343 ns | 0305, 0306, 0310, 0312, 0316, 0317, 0319, 0321, 0322, 0323, 0324, 0329, 0332, 0333, 0334 | All NO |<br>| ~108 ns | 0308 (69 ns), 0311, 0315, 0326, 0327, 0328 | All NO |<br>| <strong>0–1.4 ns</strong> | <strong>0313 (1 ns), 0320 (0 ns), 0325 (0 ns)</strong> | <strong>ALL YES</strong> |</p>
<p><strong>The correlation is absolute:</strong> Flicker occurs if and only if the LP-low plateau is effectively absent (&lt; ~2 ns). The SN65DSI83 requires a well-formed LP-11 → LP-01 → LP-00 → HS-0 SoT entry sequence on the data lanes. When the LP-low states are compressed to zero, the bridge cannot detect the SoT, fails to lock to the HS data stream, and remains stuck for the entire session.</p>
<p>### Why LP-Low Disappears Intermittently</p>
<p>The LP exit → HS measurement is universally 0–4 ns across <strong>all</strong> captures (good and bad), meaning the LP-01 transition state is always extremely brief. This is consistent with the TLPX register value of 3 byte-clocks (55.6 ns) — marginally above the 50 ns spec minimum — combined with the fact that TCLK_PREPARE, THS_PREPARE, and THS_EXIT are all either at or below spec limits.</p>
<p>The key observation is that the LP-low plateau shows a <strong>trimodal distribution</strong>: ~343 ns, ~108 ns, or ~0 ns. This suggests:</p>
<ol><li>The PHY state machine has a race condition at the LP→HS transition</li><li>The combination of marginal/violated timing parameters creates a window where the PHY occasionally skips the LP-00 hold state entirely</li><li>The ~343 ns cases likely represent a full nominal hold; ~108 ns represents one byte-clock step shorter (≈6 byte-clocks vs ~18.5 byte-clocks); 0 ns represents complete state skip</li></ol>
<p>The THS_TRAIL violation (55.6 ns vs required 69.3 ns) and THS_EXIT violation (92.6 ns vs required 100 ns) are particularly relevant: if the PHY&#x27;s internal LP state machine uses these timers to sequence the LP-01→LP-00→HS-0 entry, short timers increase the probability that on any given startup, the state machine races through or skips the low states.</p>
<ul><li></li></ul>
<p>## 3. HS Signal Health</p>
<p>### Consistent Concerns</p>
<p>| Parameter | Typical Value | Spec | Assessment |<br>|---|---|---|---|<br>| CLK Vdiff | 166.2–167.2 mV | 140–270 mV | ✓ but only <strong>19% above floor</strong> — very low margin |<br>| DAT Vdiff | 186–197 mV | 140–270 mV | ✓ acceptable |<br>| CLK common mode | +28–32 mV | ±25 mV recommended | Slightly high, minor |<br>| CLK asymmetry | +196/−136 mV | Should be symmetric | <strong>60 mV offset — significant</strong> |<br>| DAT below-140mV samples | 29–16234 per capture | 0 | <strong>Persistent spec violation</strong> |<br>| CLK below-140mV samples | 40–274 per capture | 0 | <strong>Persistent spec violation</strong> |</p>
<p>The clock amplitude of ~167 mV is only 27 mV above the 140 mV absolute minimum. The persistent sub-140 mV excursions are transition-region violations (ISI/ringing during edge transitions), not a settled-level problem, but they represent genuine eye-closure events.</p>
<p><strong>Clock asymmetry</strong> (+196/−136 mV, ~60 mV offset) indicates either a DC offset in the PHY output driver or an impedance mismatch on the CLK+ vs CLK− traces. This doesn&#x27;t directly cause flicker but reduces noise margin.</p>
<p>### No Significant Trends Over Time</p>
<p>| Parameter | Capture 0305 | Capture 0334 | Trend |<br>|---|---|---|---|<br>| CLK Vdiff | 166.5 mV | 166.2 mV | Flat |<br>| DAT Vdiff | 187.2 mV | 186.4 mV | Flat |<br>| CLK jitter RMS | 54.6 ps | 53.8 ps | Flat |<br>| LP-11 voltage | 1.015 V | 1.014 V | Flat |<br>| 1.8V mean | 1.7663 V | 1.7670 V | Flat |</p>
<p>No thermal drift, aging, or progressive degradation detected across this batch.</p>
<ul><li></li></ul>
<p>## 4. Supply Rail Correlation</p>
<p>### 1.8V Supply Statistics</p>
<p>| Metric | Range | Spec |<br>|---|---|---|<br>| Mean | 1.7655–1.7724 V | 1.71–1.89 V ✓ but 34–45 mV below nominal |<br>| Min | 1.6960–1.7440 V | ≥ 1.71 V |<br>| Droop | 24.5–69.7 mV | — |</p>
<p>Two captures breach the 1.71 V floor: <strong>0305</strong> (1.700 V, 66 mV droop) and <strong>0314</strong> (1.696 V, 70 mV droop).</p>
<p>### Supply vs Flicker Correlation</p>
<p>| Capture | Flicker? | LP-low | Droop (mV) | Min V |<br>|---|---|---|---|---|<br>| <strong>0313</strong> | <strong>YES</strong> | 1 ns | 35.4 | 1.732 V |<br>| <strong>0320</strong> | <strong>YES</strong> | 0 ns | 55.3 | 1.712 V |<br>| <strong>0325</strong> | <strong>YES</strong> | 0 ns | 38.2 | 1.728 V |<br>| 0305 | no | 343 ns | <strong>66.3</strong> | <strong>1.700 V</strong> |<br>| 0314 | no (no LP data) | — | <strong>69.7</strong> | <strong>1.696 V</strong> |<br>| 0329 | no | 343 ns | 50.0 | 1.716 V |</p>
<p><strong>No correlation between supply droop and flicker.</strong> Capture 0313 (flicker) has only 35 mV droop, while 0305 and 0314 (no flicker) have the worst droops at 66–70 mV. The flicker mechanism is not supply-droop-driven. However, the supply violations are a separate concern that should be addressed.</p>
<ul><li></li></ul>
<p>## 5. Warning/Error Explanations</p>
<p>| Warning/Error | Frequency | Most Likely Cause | Action |<br>|---|---|---|---|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>100% of LP captures</strong> | Register TLPX=3 (55.6 ns) is marginal; actual LP-01 state is being measured at single-ended level with limited bandwidth — the 0–4 ns measurement likely reflects the fast single-ended slew between LP-11 and LP-00, not a true timing violation at the protocol level. But the LP-01→LP-00 transition is clearly being squeezed. | Increase TLPX to 4 (74 ns) in target registers |<br>| `LP-low plateau absent or &lt; 50 ns` (FLICKER) | 3/30 (10%) | PHY state machine race — LP-00 hold state skipped due to marginal/violated timing register values | <strong>Apply correct registers (see §6)</strong> |<br>| `Only negative swings in capture window` | ~60% of sig/dat | Oscilloscope trigger or probe captured during a run of consecutive &#x27;0&#x27; bits (or blanking with HS-0 idle) | Non-actionable — adjust trigger or increase capture window for sig captures |<br>| `index 200000 out of bounds` | 5 captures | LP data array too short — likely the SoT transition occurred outside the trigger window or the capture didn&#x27;t include the LP→HS edge | Adjust trigger delay or increase pre-trigger buffer |<br>| `CLK lane continuous HS mode — LP states not expected` | 100% | Expected — DSI clock lane runs in continuous HS mode (non-burst) at this configuration | Non-actionable, correct behavior |<br>| `Supply droops below 1.71 V` | 2/30 (7%) | Insufficient bulk + HF decoupling on VDDIO near PHY, combined with LP→HS transient current draw (~tens of mA step) | Add 10 µF + 100 nF ceramic caps close to MIPI PHY VDDIO pins |<br>| `No HS signal detected` (sig/dat) | 2 captures (0325, 0328, 0332) | Scope captured during blanking interval or LP state on data lane — no HS activity in window | Non-actionable artifact |<br>| `Settled samples below 140 mV` | 100% of proto captures | ISI-induced eye closure during transitions and during low-amplitude data patterns; clock amplitude is marginal at 167 mV | Monitor; consider trace impedance tuning if layout revision is possible |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### CRITICAL — Fix #1: Force Correct PHY Timing Registers</p>
<p>The samsung-dsim driver is not applying your target values. The actual registers show shorter timings that violate D-PHY spec in 5 parameters. <strong>This is the root cause of the intermittent flicker.</strong></p>
<p><strong>Option A — Device Tree override (preferred, no driver patch):</strong><br>In the DSIM node of the device tree, check if `samsung,phy-timing` properties exist. The `sec-dsim` / `samsung-dsim` driver in some BSP versions computes timings from the bit rate using internal formulas that may undercount at 432 Mbit/s. If the DT accepts explicit timing overrides:</p>
<p>```dts<br>&amp;mipi_dsi {<br> samsung,phy-timing = &lt;0x00000306 0x03110A04 0x00040A03&gt;;<br> /* Or individual fields if supported by your BSP version */<br>};<br>```</p>
<p><strong>Option B — Direct register poke (validation only):</strong><br>```bash<br># After pipeline load but before enable:<br>memtool mw -l 0x32e100b4=0x00000306<br>memtool mw -l 0x32e100b8=0x03110A04<br>memtool mw -l 0x32e100bc=0x00040A03<br>```</p>
<p><strong>Option C — Driver patch:</strong><br>In `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` depending on BSP), find the `samsung_dsim_set_phy_timing()` function and either:<br>- Override the computed values with hardcoded values for your bit rate, or<br>- Fix the computation formula (the standard formula uses `ceil((ns_value / byte_clk_period) - 1)` which at 432 Mbit/s rounds down for several parameters)</p>
<p><strong>Expected effect:</strong> Increasing THS_ZERO from 6→10, THS_TRAIL from 3→4, TCLK_PREPARE from 2→3, TCLK_ZERO from 14→17, and TCLK_TRAIL from 3→4 will bring all parameters into spec. More importantly, the longer THS_ZERO/THS_PREPARE timing combination gives the PHY state machine more time to properly sequence LP</p>
<p class="tokens">Tokens: 32742 in / 4096 out</p>
</body>
</html>

7
reports/flicker_log.csv
View File

@@ -28,3 +28,10 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v
2026-04-10 10:08:33,20260410_100114,0489,dat,0.2,0.8,1.016
2026-04-10 10:08:34,20260410_100135,0490,dat,0.3,1.2,1.016
2026-04-10 10:08:46,20260410_100533,0501,dat,0.3,0.1,1.017
2026-04-10 11:40:17,20260410_112853,0143,dat,0.2,4.5,1.016
2026-04-10 11:40:23,20260410_113041,0148,dat,0.3,2.3,1.015
2026-04-10 11:40:27,20260410_113207,0152,dat,0.3,0.9,1.016
2026-04-10 11:40:41,20260410_113628,0164,dat,0.2,3.2,1.015
2026-04-10 12:45:00,20260410_123438,0313,dat,1.4,0.1,1.015
2026-04-10 12:45:08,20260410_123710,0320,dat,0.2,1.9,1.017
2026-04-10 12:45:14,20260410_123858,0325,dat,0.3,3.5,1.015
1 logged_at capture_ts capture_num channel lp_low_duration_ns lp11_to_hs_ns lp11_voltage_v
28 2026-04-10 10:08:33 20260410_100114 0489 dat 0.2 0.8 1.016
29 2026-04-10 10:08:34 20260410_100135 0490 dat 0.3 1.2 1.016
30 2026-04-10 10:08:46 20260410_100533 0501 dat 0.3 0.1 1.017
31 2026-04-10 11:40:17 20260410_112853 0143 dat 0.2 4.5 1.016
32 2026-04-10 11:40:23 20260410_113041 0148 dat 0.3 2.3 1.015
33 2026-04-10 11:40:27 20260410_113207 0152 dat 0.3 0.9 1.016
34 2026-04-10 11:40:41 20260410_113628 0164 dat 0.2 3.2 1.015
35 2026-04-10 12:45:00 20260410_123438 0313 dat 1.4 0.1 1.015
36 2026-04-10 12:45:08 20260410_123710 0320 dat 0.2 1.9 1.017
37 2026-04-10 12:45:14 20260410_123858 0325 dat 0.3 3.5 1.015