From 17d393cbd17f8fc5a5ca78dc8d2df78c48273c2f Mon Sep 17 00:00:00 2001 From: david rice Date: Fri, 10 Apr 2026 12:48:39 +0100 Subject: [PATCH] updates --- reports/20260410_114218_analysis.html | 113 ++++++++++++++++++++++++++ reports/20260410_124656_analysis.html | 113 ++++++++++++++++++++++++++ reports/flicker_log.csv | 7 ++ 3 files changed, 233 insertions(+) create mode 100644 reports/20260410_114218_analysis.html create mode 100644 reports/20260410_124656_analysis.html diff --git a/reports/20260410_114218_analysis.html b/reports/20260410_114218_analysis.html new file mode 100644 index 0000000..f5b4c3d --- /dev/null +++ b/reports/20260410_114218_analysis.html @@ -0,0 +1,113 @@ + + + + +MIPI Analysis — Captures 0138–0167 + + + +

MIPI D-PHY Analysis Report

+ +
+

⚠ FLICKER DETECTED — 4 of 30 display load sessions (13%) flickered

+

Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at + pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge + missed the SoT sequence and dropped a frame.
+ LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief + for the SN65DSI83 bridge to detect start-of-transmission.

+ + + + +
CaptureTimestampChannelLP-low plateauLP exit→HSLP-11 voltage
014320260410_112853dat0.2 ns4.5 ns1.016 V
014820260410_113041dat0.3 ns2.3 ns1.015 V
015220260410_113207dat0.3 ns0.9 ns1.016 V
016420260410_113628dat0.2 ns3.2 ns1.015 V
+
+ +
+ + DSI Register Snapshots (30 captures) + +
+ + + +
CaptureTimestamp0x32e100b4
DSIM_PHYTIMING		0x32e100b8
DSIM_PHYTIMING1		0x32e100bc
DSIM_PHYTIMING2
013820260410_1127050x000003050x020e0a030x00030605
013920260410_1127270x000003050x020e0a030x00030605
014020260410_1127480x000003050x020e0a030x00030605
014120260410_1128100x000003050x020e0a030x00030605
014220260410_1128310x000003050x020e0a030x00030605
014320260410_1128530x000003050x020e0a030x00030605
014420260410_1129150x000003050x020e0a030x00030605
014520260410_1129360x000003050x020e0a030x00030605
014620260410_1129580x000003050x020e0a030x00030605
014720260410_1130200x000003050x020e0a030x00030605
014820260410_1130410x000003050x020e0a030x00030605
014920260410_1131020x000003050x020e0a030x00030605
015020260410_1131240x000003050x020e0a030x00030605
015120260410_1131460x000003050x020e0a030x00030605
015220260410_1132070x000003050x020e0a030x00030605
015320260410_1132290x000003050x020e0a030x00030605
015420260410_1132510x000003050x020e0a030x00030605
015520260410_1133120x000003050x020e0a030x00030605
015620260410_1133340x000003050x020e0a030x00030605
015720260410_1133560x000003050x020e0a030x00030605
015820260410_1134170x000003050x020e0a030x00030605
015920260410_1134390x000003050x020e0a030x00030605
016020260410_1135010x000003050x020e0a030x00030605
016120260410_1135220x000003050x020e0a030x00030605
016220260410_1135440x000003050x020e0a030x00030605
016320260410_1136060x000003050x020e0a030x00030605
016420260410_1136280x000003050x020e0a030x00030605
016520260410_1136490x000003050x020e0a030x00030605
016620260410_1137110x000003050x020e0a030x00030605
016720260410_1137330x000003050x020e0a030x00030605
+
+
+

+ Generated: 2026-04-10 11:42:18  |  + Scope: Captures 0138–0167  |  + Model: claude-opus-4-6 +

+

# MIPI D-PHY Signal Integrity Analysis — Captures 0138–0167

+ +

## 1. CRITICAL FINDING: Register Mismatch Is the Root Cause

+

### Actual vs. Target Register Values

+

| Register | Target | Actual (all captures) | Impact |
|---|---|---|---|
| PHYTIMING (0xb4) | 0x00000306 | 0x00000305 | THS_EXIT=5 → 92.6 ns (spec ≥100 ns) ✗ VIOLATION |
| PHYTIMING1 (0xb8) | 0x03110A04 | 0x020e0a03 | TCLK_PREPARE=2 → 37 ns (spec 38–95 ns) ✗ VIOLATION; TCLK_ZERO=14 → 259 ns (spec ≥300 ns) ✗ VIOLATION; TCLK_TRAIL=3 → 55.6 ns (spec ≥60 ns) ✗ VIOLATION |
| PHYTIMING2 (0xbc) | 0x00040A03 | 0x00030605 | THS_PREPARE=5 → 92.6 ns (spec 40+4×UI=49 ns to 85+6×UI=99 ns) ✗ BORDERLINE/VIOLATION at 93 ns; THS_ZERO=6 → 111 ns (spec ≥ 145+10×UI=168 ns) ✗ VIOLATION; THS_TRAIL=3 → 55.6 ns (spec ≥ max(8×UI, 60+4×UI)=69.3 ns) ✗ VIOLATION |

+

Every single DSIM PHY timing register is wrong. The driver is not applying the target values. All 30 captures show the identical incorrect values, confirming this is a persistent configuration bug — not a transient failure.

+

### Decoded Timing Violations (actual register values)

+

| Parameter | Field Value | Actual Duration | D-PHY v1.1 Min | Status |
|---|---|---|---|---|
| TLPX | 3 | 55.6 ns | 50 ns | ✓ marginal |
| THS_EXIT | 5 | 92.6 ns | 100 ns | ✗ SHORT by 7.4 ns |
| TCLK_PREPARE | 2 | 37.0 ns | 38 ns | ✗ SHORT by 1 ns |
| TCLK_ZERO | 14 (0x0e) | 259 ns | 300 ns | ✗ SHORT by 41 ns |
| TCLK_POST | 10 (0x0a) | 185 ns | ~180 ns | ✓ barely |
| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | ✗ SHORT by 4.4 ns |
| THS_PREPARE | 5 | 92.6 ns | 49–99 ns | ✓ but high-side |
| THS_ZERO | 6 | 111 ns | 168 ns | ✗ SHORT by 57 ns |
| THS_TRAIL | 3 | 55.6 ns | 69.3 ns | ✗ SHORT by 13.7 ns |

+

Six of nine timing parameters violate D-PHY v1.1 spec. The most damaging are:

+ + +

## 2. LP-Low Plateau Analysis: The Flicker Mechanism

+

### Distribution of LP-low plateau durations across all captures

+

| LP-low Plateau | Count | Flicker? | Captures |
|---|---|---|---|
| 0 ns (absent) | 4 | YES — all 4 | 0143, 0148, 0152, 0164 |
| ~108 ns | 4 | No | 0139, 0155, 0158, 0160, 0162 |
| ~342–348 ns | 20 | No | Remainder |
| Missing data | 1 | Unknown | 0141 (processing error) |

+

Perfect correlation: Every flicker event corresponds to LP-low plateau = 0 ns. Every non-flicker event has LP-low ≥ 108 ns. There are no exceptions.

+

The LP-low plateau represents the combined duration of the LP-01 → LP-00 sequence that constitutes the data lane SoT entry. When THS_ZERO is programmed at only 111 ns (vs. 168 ns required), the PHY's internal state machine has almost no timing margin. Under normal conditions, the silicon *happens* to produce a recognizable LP-00 state of ~342 ns — well above spec. But intermittently (~13% of startups), a race condition within the PHY causes the LP-01/LP-00 states to be completely swallowed, producing a direct LP-11 → HS transition with no detectable SoT sequence.

+

Why it's non-deterministic: The Samsung DSIM PHY's internal PLL lock time and lane synchronization have cycle-to-cycle jitter. With the programmed THS_ZERO 34% below spec, the internal sequencer's timing margin is negative. Most of the time the PLL locks fast enough that the sequencer still outputs the LP states; occasionally it doesn't, and the SoT is corrupted.

+

The "LP exit → HS" metric (1–4 ns across all captures, including non-flicker ones) confirms that the LP-01 state itself is never being held for the required TLPX ≥ 50 ns — even on "good" startups, the LP-01 pulse is undetectably brief. What saves non-flicker sessions is the ~342 ns LP-00 plateau, which gives the SN65DSI83 enough time to detect the HS entry. When even that disappears (flicker cases), the bridge never acquires sync.

+ +

## 3. HS Signal Quality

+

### Consistent observations across all 30 captures:

+

| Parameter | CLK | DAT0 | Assessment |
|---|---|---|---|
| Vdiff amplitude | 165.6–169.1 mV | 177–224 mV | Marginal-low on CLK (spec 140–270 mV, only 26 mV above floor) |
| Common mode | +26.6 to +32.0 mV | −98 to +5 mV | CLK offset ✓; DAT asymmetric |
| Rise time 20–80% | 163.6–165.4 ps | 143.8–219.4 ps | ✓ within spec |
| Jitter p-p | 145–177 ps | — | ✓ acceptable |
| Samples below 140 mV | 21–153 per capture | 18–7280 per capture | ✗ Persistent sub-spec excursions |

+

Clock amplitude is running at ~167 mV — only 19% above the 140 mV floor. This provides essentially no margin against supply droop, temperature variation, or aging. The persistent sub-140 mV samples on both clock and data indicate ISI/reflection-induced amplitude dips that regularly breach the minimum.

+

DAT0 asymmetry: Most sig/dat captures show only negative differential swings (Vdiff pos = 0.0 mV), indicating a probe/measurement artifact (likely single-ended measurement of one line only, or trigger position capturing only one data phase). However, proto/dat captures with both polarities show a consistent ~7–10 mV asymmetry between positive and negative swings, suggesting slight impedance mismatch or common-mode offset on the data lane.

+ +

## 4. 1.8 V Supply Rail Correlation

+

### Supply droop statistics:

+

| Droop Category | Count | Flicker events in category |
|---|---|---|
| < 30 mV (healthy) | 7 | 2 flicker (0143: 31 mV, 0148: 30.7 mV, 0164: 28.4 mV) |
| 30–50 mV (marginal) | 8 | 1 flicker (0152: 55.6 mV) |
| 50–68 mV (poor, some below 1.71 V) | 12 | 0 flicker |
| Below 1.71 V spec minimum | 5 | 0 flicker |

+

No correlation between supply droop and flicker. Three of four flicker events occurred at modest droop (<32 mV), while the deepest droops (66–68 mV, Vmin = 1.700 V) produced no flicker. This confirms the flicker is not supply-induced — it's a timing/sequencing issue.

+

However, the supply health is independently concerning:
- 5 captures dropped below the 1.71 V MIPI VDDIO minimum (0142: 1.700 V, 0147: 1.704 V, 0150: 1.700 V, 0151: 1.700 V, 0166: 1.708 V)
- Mean droop is ~43 mV; worst case is 67.7 mV
- This indicates insufficient bulk/MLCC decoupling near the MIPI PHY VDDIO pin

+ +

## 5. Warning/Error Explanations

+

| Warning | Cause | Action |
|---|---|---|
| "CLK lane is in continuous HS mode" | Normal for video-mode DSI — CLK runs continuously HS; no LP→HS expected on CLK | None needed |
| "Only negative swings in capture window" | sig/dat probe capturing during a single data symbol (long run of zeros/ones), or single-ended probe on one line only | Verify differential probe connection; not a device fault |
| "No HS signal detected" (sig/dat 0162, 0163; proto/dat 0155) | Trigger caught blanking interval (HFP/HBP) where DAT0 is in LP; CLK continues HS | Trigger refinement; not a device fault |
| "LP exit duration X ns below spec min 50 ns" | Register misconfiguration: THS_PREPARE (92.6 ns) is correct but the LP-01 state is too brief because the PHY sequencer races through it with the underspecified THS_ZERO | Fix registers |
| "index 200000 is out of bounds" (Capture 0141) | Buffer overrun in LP analysis script; the LP→HS edge was at or beyond the end of the capture window | Re-capture with wider window or earlier trigger |
| "Supply droops below 1.71 V" | Insufficient decoupling or trace resistance on VDDIO | Add MLCC capacitance |
| "Settled samples below 140 mV" | ISI/reflection causing Vdiff dips below 140 mV floor during HS toggling | Improve termination/routing; increase PHY drive strength if available |

+ +

## 6. Actionable Recommendations

+

### PRIORITY 1 — Fix PHY Timing Registers (ROOT CAUSE OF FLICKER)

+

The samsung-dsim (sec-dsim) driver is computing or writing incorrect values. Apply the target values via device-tree override or driver patch:

+

```
/* Device tree or driver patch */
DSIM_PHYTIMING = 0x00000306 /* TLPX=3, THS_EXIT=6 */
DSIM_PHYTIMING1 = 0x03110A04 /* TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4 */
DSIM_PHYTIMING2 = 0x00040A03 /* THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3 */
```

+

Specific fixes and expected impact:

+

| Field | Current → Target | Duration Change | Why It Matters |
|---|---|---|---|
| THS_ZERO | 6 → 10 | 111 → 185 ns | Gives receiver 74 ns more to detect HS-0 before sync byte. Primary flicker fix. |
| TCLK_ZERO | 14 → 17 | 259 → 315 ns | Allows proper clock CDR acquisition. Eliminates clock lock failures. |
| THS_EXIT | 5 → 6 | 92.6 → 111 ns | Meets 100 ns minimum. Prevents LP re-entry confusion. |
| TCLK_PREPARE | 2 → 3 | 37 → 55.6 ns | Meets 38 ns minimum with margin. |
| TCLK_TRAIL | 3 → 4 | 55.6 → 74 ns | Meets 60 ns minimum with margin. |
| THS_TRAIL | 3 → 4 | 55.6 → 74 ns | Meets 69.3 ns minimum with margin. |
| THS_PREPARE | 5 → 3 | 92.6 → 55.6 ns | Moves from 93 ns (borderline over 99 ns max) to comfortable mid-range. |

+

Verification: After applying, read back registers with `memtool md -l 0x32e100b4+0x0c` and confirm the target values. Run 100+ pipeline load/unload cycles to verify zero flicker.

+

Driver investigation: The samsung-dsim driver's `samsung_dsim_set_phy_timing()` function computes timing from the HS clock rate. At 432 Mbit/s the formula may be rounding down. Check:
- `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` in NXP BSP)
- The timing computation uses integer division that truncates; for low bitrates like 432 Mbps, every byte-clock unit matters
- Consider whether the NXP BSP has a known erratum or patch for this

+

### PRIORITY 2 — Improve 1.8 V VDDIO Decoupling

+

Although not correlated with flicker, the supply is out-of-spec:

+
  1. Add 2×4.7 µF + 2×100 nF MLCC as close as possible to the MIPI PHY VDDIO pins on the SOM carrier board
  2. Check VDDIO trace impedance — the 67 mV droop at LP→HS transition (4 lanes switching simultaneously) suggests >100 mΩ path resistance
  3. Target: droop < 30 mV, Vmin > 1.71 V under all conditions
+

### PRIORITY 3 — Clock Amplitude Margin

+

CLK differential amplitude at ~167 mV is only 19% above the 140 mV minimum:

+
  1. Check for excessive series resistance in AC coupling capacitors (use 0402 or 0201 with low ESR)
  2. Verify 100 Ω differential termination at receiver (SN65DSI83 has internal, but external may be present and wrong value)
  3. If the i.MX 8M Mini DPHY has programmable drive strength, increase by one step
  4. Reduce trace length / improve impedance matching to eliminate the sub-140 mV ISI dips
+

### PRIORITY 4 — Add Software Retry as Belt-and-Suspenders

+

Even after fixing registers, add a startup verification loop:

+

```c
/* After DSI pipeline enable, read SN65DSI83 status register 0x0A */
/* Bit 0 = PLL lock. If not locked within 50ms, unload and reload pipeline */
for (retries = 0

+

Tokens: 33253 in / 4096 out

+ + diff --git a/reports/20260410_124656_analysis.html b/reports/20260410_124656_analysis.html new file mode 100644 index 0000000..449fe33 --- /dev/null +++ b/reports/20260410_124656_analysis.html @@ -0,0 +1,113 @@ + + + + +MIPI Analysis — Captures 0305–0334 + + + +

MIPI D-PHY Analysis Report

+ +
+

⚠ FLICKER DETECTED — 3 of 30 display load sessions (10%) flickered

+

Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at + pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge + missed the SoT sequence and dropped a frame.
+ LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief + for the SN65DSI83 bridge to detect start-of-transmission.

+ + + + +
CaptureTimestampChannelLP-low plateauLP exit→HSLP-11 voltage
031320260410_123438dat1.4 ns0.1 ns1.015 V
032020260410_123710dat0.2 ns1.9 ns1.017 V
032520260410_123858dat0.3 ns3.5 ns1.015 V
+
+ +
+ + DSI Register Snapshots (30 captures) + +
+ + + +
CaptureTimestamp0x32e100b4
DSIM_PHYTIMING		0x32e100b8
DSIM_PHYTIMING1		0x32e100bc
DSIM_PHYTIMING2
030520260410_1231450x000003050x020e0a030x00030605
030620260410_1232060x000003050x020e0a030x00030605
030720260410_1232280x000003050x020e0a030x00030605
030820260410_1232500x000003050x020e0a030x00030605
030920260410_1233120x000003050x020e0a030x00030605
031020260410_1233330x000003050x020e0a030x00030605
031120260410_1233550x000003050x020e0a030x00030605
031220260410_1234170x000003050x020e0a030x00030605
031320260410_1234380x000003050x020e0a030x00030605
031420260410_1235000x000003050x020e0a030x00030605
031520260410_1235210x000003050x020e0a030x00030605
031620260410_1235430x000003050x020e0a030x00030605
031720260410_1236040x000003050x020e0a030x00030605
031820260410_1236260x000003050x020e0a030x00030605
031920260410_1236480x000003050x020e0a030x00030605
032020260410_1237100x000003050x020e0a030x00030605
032120260410_1237310x000003050x020e0a030x00030605
032220260410_1237530x000003050x020e0a030x00030605
032320260410_1238150x000003050x020e0a030x00030605
032420260410_1238360x000003050x020e0a030x00030605
032520260410_1238580x000003050x020e0a030x00030605
032620260410_1239200x000003050x020e0a030x00030605
032720260410_1239410x000003050x020e0a030x00030605
032820260410_1240030x000003050x020e0a030x00030605
032920260410_1240240x000003050x020e0a030x00030605
033020260410_1240460x000003050x020e0a030x00030605
033120260410_1241080x000003050x020e0a030x00030605
033220260410_1241300x000003050x020e0a030x00030605
033320260410_1241510x000003050x020e0a030x00030605
033420260410_1242130x000003050x020e0a030x00030605
+
+
+

+ Generated: 2026-04-10 12:46:56  |  + Scope: Captures 0305–0334  |  + Model: claude-opus-4-6 +

+

# MIPI D-PHY Signal Integrity Analysis — Captures 0305–0334

+

## 1. Root Cause Identification

+

### The Primary Problem: Register Mismatch — Driver Not Applying Target Timing

+

This is the single most important finding. Every capture shows the same register values:

+

| Register | Actual (all captures) | Target (spec-compliant) | Delta |
|---|---|---|---|
| PHYTIMING (0xb4) | `0x00000305` | `0x00000306` | THS_EXIT: 5→93 ns vs 6→111 ns |
| PHYTIMING1 (0xb8) | `0x020e0a03` | `0x03110A04` | TCLK_PREPARE: 2→37 ns vs 3→56 ns; TCLK_ZERO: 14→259 ns vs 17→315 ns; TCLK_TRAIL: 3→56 ns vs 4→74 ns |
| PHYTIMING2 (0xbc) | `0x00030605` | `0x00040A03` | THS_PREPARE: 5→93 ns vs 3→56 ns; THS_ZERO: 6→111 ns vs 10→185 ns; THS_TRAIL: 3→56 ns vs 4→74 ns |

+

Critical field-level decode of actual register 0xbc = `0x00030605`:

+

| Field | Actual | Duration | D-PHY v1.1 Spec | Status |
|---|---|---|---|---|
| THS_PREPARE | 5 | 92.6 ns | 40+4×UI=49.3 ns … 85+6×UI=98.9 ns | ✓ but at upper edge |
| THS_ZERO | 6 | 111.1 ns | THS_ZERO + THS_PREPARE ≥ 145+10×UI = 168.2 ns → need THS_ZERO ≥ ~4.1 → 5 min | Marginal ✓ (combined = 203.7 ns ≥ 168.2 ns) |
| THS_TRAIL | 3 | 55.6 ns | max(n×8×UI, 60+n×4×UI) = 60+4×2.315 = 69.3 ns | ✗ VIOLATION |

+

Critical field-level decode of actual register 0xb8 = `0x020e0a03`:

+

| Field | Actual | Duration | Spec | Status |
|---|---|---|---|---|
| TCLK_PREPARE | 2 | 37.0 ns | 38 ns … 95 ns | ✗ VIOLATION (37 < 38 ns) |
| TCLK_ZERO | 14 (0x0e) | 259.3 ns | TCLK_PREPARE + TCLK_ZERO ≥ 300 ns | ✗ VIOLATION (296.3 < 300 ns) |
| TCLK_POST | 10 (0x0a) | 185.2 ns | 60 + 52×UI = 180.4 ns | ✓ barely |
| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | ✗ VIOLATION (55.6 < 60 ns) |

+

### Summary of Timing Violations in Running Registers

+

| Parameter | Required | Actual | Margin | Verdict |
|---|---|---|---|---|
| TCLK_PREPARE | ≥ 38 ns | 37.0 ns | −1 ns | FAIL |
| TCLK_PREPARE + TCLK_ZERO | ≥ 300 ns | 296.3 ns | −3.7 ns | FAIL |
| TCLK_TRAIL | ≥ 60 ns | 55.6 ns | −4.4 ns | FAIL |
| THS_TRAIL | ≥ 69.3 ns | 55.6 ns | −13.7 ns | FAIL |
| THS_EXIT | ≥ 100 ns | 92.6 ns | −7.4 ns | FAIL |
| TLPX | ≥ 50 ns | 55.6 ns | +5.6 ns | ✓ marginal |

+

Five timing parameters are out of spec. The samsung-dsim driver is computing or applying incorrect values. The target values (which you've verified as compliant) are not reaching the hardware.

+ +

## 2. LP SoT Sequence Analysis — The Flicker Mechanism

+

### LP-Low Plateau Distribution (all captures with valid LP data)

+

| LP-low plateau | Captures | Flicker? |
|---|---|---|
| ~342–343 ns | 0305, 0306, 0310, 0312, 0316, 0317, 0319, 0321, 0322, 0323, 0324, 0329, 0332, 0333, 0334 | All NO |
| ~108 ns | 0308 (69 ns), 0311, 0315, 0326, 0327, 0328 | All NO |
| 0–1.4 ns | 0313 (1 ns), 0320 (0 ns), 0325 (0 ns) | ALL YES |

+

The correlation is absolute: Flicker occurs if and only if the LP-low plateau is effectively absent (< ~2 ns). The SN65DSI83 requires a well-formed LP-11 → LP-01 → LP-00 → HS-0 SoT entry sequence on the data lanes. When the LP-low states are compressed to zero, the bridge cannot detect the SoT, fails to lock to the HS data stream, and remains stuck for the entire session.

+

### Why LP-Low Disappears Intermittently

+

The LP exit → HS measurement is universally 0–4 ns across all captures (good and bad), meaning the LP-01 transition state is always extremely brief. This is consistent with the TLPX register value of 3 byte-clocks (55.6 ns) — marginally above the 50 ns spec minimum — combined with the fact that TCLK_PREPARE, THS_PREPARE, and THS_EXIT are all either at or below spec limits.

+

The key observation is that the LP-low plateau shows a trimodal distribution: ~343 ns, ~108 ns, or ~0 ns. This suggests:

+
  1. The PHY state machine has a race condition at the LP→HS transition
  2. The combination of marginal/violated timing parameters creates a window where the PHY occasionally skips the LP-00 hold state entirely
  3. The ~343 ns cases likely represent a full nominal hold; ~108 ns represents one byte-clock step shorter (≈6 byte-clocks vs ~18.5 byte-clocks); 0 ns represents complete state skip
+

The THS_TRAIL violation (55.6 ns vs required 69.3 ns) and THS_EXIT violation (92.6 ns vs required 100 ns) are particularly relevant: if the PHY's internal LP state machine uses these timers to sequence the LP-01→LP-00→HS-0 entry, short timers increase the probability that on any given startup, the state machine races through or skips the low states.

+ +

## 3. HS Signal Health

+

### Consistent Concerns

+

| Parameter | Typical Value | Spec | Assessment |
|---|---|---|---|
| CLK Vdiff | 166.2–167.2 mV | 140–270 mV | ✓ but only 19% above floor — very low margin |
| DAT Vdiff | 186–197 mV | 140–270 mV | ✓ acceptable |
| CLK common mode | +28–32 mV | ±25 mV recommended | Slightly high, minor |
| CLK asymmetry | +196/−136 mV | Should be symmetric | 60 mV offset — significant |
| DAT below-140mV samples | 29–16234 per capture | 0 | Persistent spec violation |
| CLK below-140mV samples | 40–274 per capture | 0 | Persistent spec violation |

+

The clock amplitude of ~167 mV is only 27 mV above the 140 mV absolute minimum. The persistent sub-140 mV excursions are transition-region violations (ISI/ringing during edge transitions), not a settled-level problem, but they represent genuine eye-closure events.

+

Clock asymmetry (+196/−136 mV, ~60 mV offset) indicates either a DC offset in the PHY output driver or an impedance mismatch on the CLK+ vs CLK− traces. This doesn't directly cause flicker but reduces noise margin.

+

### No Significant Trends Over Time

+

| Parameter | Capture 0305 | Capture 0334 | Trend |
|---|---|---|---|
| CLK Vdiff | 166.5 mV | 166.2 mV | Flat |
| DAT Vdiff | 187.2 mV | 186.4 mV | Flat |
| CLK jitter RMS | 54.6 ps | 53.8 ps | Flat |
| LP-11 voltage | 1.015 V | 1.014 V | Flat |
| 1.8V mean | 1.7663 V | 1.7670 V | Flat |

+

No thermal drift, aging, or progressive degradation detected across this batch.

+ +

## 4. Supply Rail Correlation

+

### 1.8V Supply Statistics

+

| Metric | Range | Spec |
|---|---|---|
| Mean | 1.7655–1.7724 V | 1.71–1.89 V ✓ but 34–45 mV below nominal |
| Min | 1.6960–1.7440 V | ≥ 1.71 V |
| Droop | 24.5–69.7 mV | — |

+

Two captures breach the 1.71 V floor: 0305 (1.700 V, 66 mV droop) and 0314 (1.696 V, 70 mV droop).

+

### Supply vs Flicker Correlation

+

| Capture | Flicker? | LP-low | Droop (mV) | Min V |
|---|---|---|---|---|
| 0313 | YES | 1 ns | 35.4 | 1.732 V |
| 0320 | YES | 0 ns | 55.3 | 1.712 V |
| 0325 | YES | 0 ns | 38.2 | 1.728 V |
| 0305 | no | 343 ns | 66.3 | 1.700 V |
| 0314 | no (no LP data) | — | 69.7 | 1.696 V |
| 0329 | no | 343 ns | 50.0 | 1.716 V |

+

No correlation between supply droop and flicker. Capture 0313 (flicker) has only 35 mV droop, while 0305 and 0314 (no flicker) have the worst droops at 66–70 mV. The flicker mechanism is not supply-droop-driven. However, the supply violations are a separate concern that should be addressed.

+ +

## 5. Warning/Error Explanations

+

| Warning/Error | Frequency | Most Likely Cause | Action |
|---|---|---|---|
| `LP exit duration X ns below spec min 50 ns` | 100% of LP captures | Register TLPX=3 (55.6 ns) is marginal; actual LP-01 state is being measured at single-ended level with limited bandwidth — the 0–4 ns measurement likely reflects the fast single-ended slew between LP-11 and LP-00, not a true timing violation at the protocol level. But the LP-01→LP-00 transition is clearly being squeezed. | Increase TLPX to 4 (74 ns) in target registers |
| `LP-low plateau absent or < 50 ns` (FLICKER) | 3/30 (10%) | PHY state machine race — LP-00 hold state skipped due to marginal/violated timing register values | Apply correct registers (see §6) |
| `Only negative swings in capture window` | ~60% of sig/dat | Oscilloscope trigger or probe captured during a run of consecutive '0' bits (or blanking with HS-0 idle) | Non-actionable — adjust trigger or increase capture window for sig captures |
| `index 200000 out of bounds` | 5 captures | LP data array too short — likely the SoT transition occurred outside the trigger window or the capture didn't include the LP→HS edge | Adjust trigger delay or increase pre-trigger buffer |
| `CLK lane continuous HS mode — LP states not expected` | 100% | Expected — DSI clock lane runs in continuous HS mode (non-burst) at this configuration | Non-actionable, correct behavior |
| `Supply droops below 1.71 V` | 2/30 (7%) | Insufficient bulk + HF decoupling on VDDIO near PHY, combined with LP→HS transient current draw (~tens of mA step) | Add 10 µF + 100 nF ceramic caps close to MIPI PHY VDDIO pins |
| `No HS signal detected` (sig/dat) | 2 captures (0325, 0328, 0332) | Scope captured during blanking interval or LP state on data lane — no HS activity in window | Non-actionable artifact |
| `Settled samples below 140 mV` | 100% of proto captures | ISI-induced eye closure during transitions and during low-amplitude data patterns; clock amplitude is marginal at 167 mV | Monitor; consider trace impedance tuning if layout revision is possible |

+ +

## 6. Actionable Recommendations

+

### CRITICAL — Fix #1: Force Correct PHY Timing Registers

+

The samsung-dsim driver is not applying your target values. The actual registers show shorter timings that violate D-PHY spec in 5 parameters. This is the root cause of the intermittent flicker.

+

Option A — Device Tree override (preferred, no driver patch):
In the DSIM node of the device tree, check if `samsung,phy-timing` properties exist. The `sec-dsim` / `samsung-dsim` driver in some BSP versions computes timings from the bit rate using internal formulas that may undercount at 432 Mbit/s. If the DT accepts explicit timing overrides:

+

```dts
&mipi_dsi {
samsung,phy-timing = <0x00000306 0x03110A04 0x00040A03>;
/* Or individual fields if supported by your BSP version */
};
```

+

Option B — Direct register poke (validation only):
```bash
# After pipeline load but before enable:
memtool mw -l 0x32e100b4=0x00000306
memtool mw -l 0x32e100b8=0x03110A04
memtool mw -l 0x32e100bc=0x00040A03
```

+

Option C — Driver patch:
In `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` depending on BSP), find the `samsung_dsim_set_phy_timing()` function and either:
- Override the computed values with hardcoded values for your bit rate, or
- Fix the computation formula (the standard formula uses `ceil((ns_value / byte_clk_period) - 1)` which at 432 Mbit/s rounds down for several parameters)

+

Expected effect: Increasing THS_ZERO from 6→10, THS_TRAIL from 3→4, TCLK_PREPARE from 2→3, TCLK_ZERO from 14→17, and TCLK_TRAIL from 3→4 will bring all parameters into spec. More importantly, the longer THS_ZERO/THS_PREPARE timing combination gives the PHY state machine more time to properly sequence LP

+

Tokens: 32742 in / 4096 out

+ + diff --git a/reports/flicker_log.csv b/reports/flicker_log.csv index 0625535..03dc8bb 100644 --- a/reports/flicker_log.csv +++ b/reports/flicker_log.csv @@ -28,3 +28,10 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v 2026-04-10 10:08:33,20260410_100114,0489,dat,0.2,0.8,1.016 2026-04-10 10:08:34,20260410_100135,0490,dat,0.3,1.2,1.016 2026-04-10 10:08:46,20260410_100533,0501,dat,0.3,0.1,1.017 +2026-04-10 11:40:17,20260410_112853,0143,dat,0.2,4.5,1.016 +2026-04-10 11:40:23,20260410_113041,0148,dat,0.3,2.3,1.015 +2026-04-10 11:40:27,20260410_113207,0152,dat,0.3,0.9,1.016 +2026-04-10 11:40:41,20260410_113628,0164,dat,0.2,3.2,1.015 +2026-04-10 12:45:00,20260410_123438,0313,dat,1.4,0.1,1.015 +2026-04-10 12:45:08,20260410_123710,0320,dat,0.2,1.9,1.017 +2026-04-10 12:45:14,20260410_123858,0325,dat,0.3,3.5,1.015