118 lines
3.8 KiB
Python
118 lines
3.8 KiB
Python
"""Central configuration for the MIPI flicker investigation suite.
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All IP addresses, register addresses, MIPI D-PHY spec minimums, and probe
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calibration constants live here. This is the single tuning surface — modules
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should import from here rather than hard-coding values.
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"""
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# ---------------------------------------------------------------------------
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# Network
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# ---------------------------------------------------------------------------
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TARGET_IP = "192.168.45.8"
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TARGET_PORT = 5000
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SCOPE_IP = "192.168.45.4"
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PSU_IP = "192.168.45.3"
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# ---------------------------------------------------------------------------
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# Scope hardware
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# ---------------------------------------------------------------------------
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SCOPE_CHANNELS = {
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"CLK_P": 1,
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"CLK_N": 2,
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"DAT0_P": 3,
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"DAT0_N": 4,
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}
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PROBE_ATTENUATION = 19.2
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SCOPE_TIMEBASE = 5e-9
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SCOPE_POINTS = 500_000
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TRIGGER_CHANNEL = 3
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TRIGGER_LEVEL_V = 0.05
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TRIGGER_SLOPE = "NEGative"
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# ---------------------------------------------------------------------------
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# PSU
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# ---------------------------------------------------------------------------
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PSU_CHANNEL_DISPLAY = 1
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PSU_DISPLAY_VOLTAGE = 3.3
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PSU_DISPLAY_CURRENT = 1.0
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PSU_POWER_CYCLE_DELAY_S = 2.0
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# ---------------------------------------------------------------------------
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# Pixel clock & DSI parameters
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# ---------------------------------------------------------------------------
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PIXEL_CLOCK_HZ = 72_000_000
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DSI_LANES = 4
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BITS_PER_PIXEL = 24
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def derive_clocks(pixel_clock_hz: int) -> dict:
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"""Recompute DSI/byte clock and UI for a given pixel clock.
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Used when --pixel-clock overrides the default — UI feeds into several
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DPHY_SPEC minimums, so they must be recomputed from the live value.
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"""
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dsi_clk_hz = pixel_clock_hz * BITS_PER_PIXEL // DSI_LANES
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byte_clk_hz = dsi_clk_hz // 8
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ui_ns = 1e9 / dsi_clk_hz
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return {
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"DSI_CLK_HZ": dsi_clk_hz,
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"BYTE_CLK_HZ": byte_clk_hz,
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"UI_NS": ui_ns,
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}
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_clocks = derive_clocks(PIXEL_CLOCK_HZ)
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DSI_CLK_HZ = _clocks["DSI_CLK_HZ"]
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BYTE_CLK_HZ = _clocks["BYTE_CLK_HZ"]
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UI_NS = _clocks["UI_NS"]
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def build_dphy_spec(ui_ns: float) -> dict:
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"""Build the MIPI D-PHY v1.1 minimum-timing dict for a given UI."""
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return {
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"t_lpx": 50.0,
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"t_clk_prepare": 38.0,
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"t_clk_zero": 262.0,
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"t_clk_prepare_plus_zero": 300.0,
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"t_clk_trail": 60.0,
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"t_clk_post": 60.0 + 52 * ui_ns,
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"t_hs_prepare": 40.0 + 4 * ui_ns,
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"t_hs_zero": 145.0 + 10 * ui_ns,
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"t_hs_trail": max(8 * ui_ns, 60.0 + 4 * ui_ns),
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"t_hs_exit": 100.0,
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}
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DPHY_SPEC = build_dphy_spec(UI_NS)
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# ---------------------------------------------------------------------------
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# SN65DSI83 I2C
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# ---------------------------------------------------------------------------
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SN65_I2C_ADDR = 0x2C
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SN65_I2C_BUS = 4 # Spec §11 says 2; live hardware shows the bridge on bus 4
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SN65_REG_IRQ = 0xE5
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SN65_REG_PLL = 0x0A
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SN65_REG_CLK = 0x0B
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SN65_ERR_SYNCH = 1 << 3
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SN65_ERR_SOT = 1 << 4
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SN65_ERR_UNC = 1 << 6
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SN65_FLICKER_MASK = SN65_ERR_SYNCH | SN65_ERR_SOT | SN65_ERR_UNC
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# ---------------------------------------------------------------------------
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# DSIM PHY timing registers (i.MX8M Mini, samsung-dsim)
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# ---------------------------------------------------------------------------
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DSIM_PHYTIMING_BASE = 0x32E100B4
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DSIM_PHYTIMING1 = 0x32E100B8
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DSIM_PHYTIMING2 = 0x32E100BC
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# ---------------------------------------------------------------------------
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# U-boot dsi-tweak bitmask (reference — not written from here)
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# ---------------------------------------------------------------------------
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TWEAK_BIT_FIFO_FLUSH = 1 << 0
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TWEAK_BIT_ROUND_UP = 1 << 2
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# ---------------------------------------------------------------------------
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# Output
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# ---------------------------------------------------------------------------
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CAPTURE_ROOT = "captures" |