27 lines
1.1 KiB
Tcl
27 lines
1.1 KiB
Tcl
# lvds_monitor.sdc
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# Timing constraints for the LVDS FlatLink monitor.
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# ---- primary clocks ----
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create_clock -name clk_50mhz -period 20.000 [get_ports {clk_50mhz}]
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# DS90CF386 RxCLKOUT for the Ampire 1280x800 panel: ~71.5 MHz typical.
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# Use 13.500 ns (74 MHz) to give a small worst-case margin.
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create_clock -name rx_clk -period 13.500 [get_ports {rx_clk}]
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derive_clock_uncertainty
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# ---- async clock domain crossing ----
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# req_tog and the latched data registers in the pix domain are sampled
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# by 2-FF synchronisers on the UART domain. Treat the two clocks as
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# fully asynchronous; per-path false_path on the individual register
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# crossings is more precise, but set_clock_groups suffices here.
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set_clock_groups -asynchronous \
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-group [get_clocks {rx_clk}] \
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-group [get_clocks {clk_50mhz}]
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# ---- inputs (asynchronous to internal logic; tell TimeQuest to skip) ----
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set_false_path -from [get_ports {de vsync hsync rst_n_pin}] -to [all_registers]
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# ---- output ----
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# UART TX is asynchronous from the receiver's standpoint; don't constrain it.
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set_false_path -from [all_registers] -to [get_ports {uart_tx_pin}]
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