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c01006628fbf8b8a94b5ebab537a1a1206d86f1a
Automotive-Power-Simulator/Debug/POWER_SWITCH.list
David Rice c01006628f updates
2026-01-21 15:40:46 +00:00

21972 lines
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POWER_SWITCH.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001d8 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00008524 080001d8 080001d8 000011d8 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000040 080086fc 080086fc 000096fc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800873c 0800873c 0000a028 2**0
CONTENTS, READONLY
4 .ARM 00000008 0800873c 0800873c 0000973c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08008744 08008744 0000a028 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08008744 08008744 00009744 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08008748 08008748 00009748 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000028 20000000 0800874c 0000a000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000003a4 20000028 08008774 0000a028 2**2
ALLOC
10 ._user_heap_stack 00000604 200003cc 08008774 0000a3cc 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000a028 2**0
CONTENTS, READONLY
12 .debug_info 000174f5 00000000 00000000 0000a058 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00002a9b 00000000 00000000 0002154d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000014d0 00000000 00000000 00023fe8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00001048 00000000 00000000 000254b8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000202c4 00000000 00000000 00026500 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00016af0 00000000 00000000 000467c4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000db1f9 00000000 00000000 0005d2b4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 001384ad 2**0
CONTENTS, READONLY
20 .debug_frame 00005b74 00000000 00000000 001384f0 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000006d 00000000 00000000 0013e064 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001d8 <__do_global_dtors_aux>:
80001d8: b510 push {r4, lr}
80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>)
80001dc: 7823 ldrb r3, [r4, #0]
80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>)
80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>)
80001e6: f3af 8000 nop.w
80001ea: 2301 movs r3, #1
80001ec: 7023 strb r3, [r4, #0]
80001ee: bd10 pop {r4, pc}
80001f0: 20000028 .word 0x20000028
80001f4: 00000000 .word 0x00000000
80001f8: 080086e4 .word 0x080086e4
080001fc <frame_dummy>:
80001fc: b508 push {r3, lr}
80001fe: 4b03 ldr r3, [pc, #12] @ (800020c <frame_dummy+0x10>)
8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
8000202: 4903 ldr r1, [pc, #12] @ (8000210 <frame_dummy+0x14>)
8000204: 4803 ldr r0, [pc, #12] @ (8000214 <frame_dummy+0x18>)
8000206: f3af 8000 nop.w
800020a: bd08 pop {r3, pc}
800020c: 00000000 .word 0x00000000
8000210: 2000002c .word 0x2000002c
8000214: 080086e4 .word 0x080086e4
08000218 <__aeabi_dmul>:
8000218: b570 push {r4, r5, r6, lr}
800021a: f04f 0cff mov.w ip, #255 @ 0xff
800021e: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000222: ea1c 5411 ands.w r4, ip, r1, lsr #20
8000226: bf1d ittte ne
8000228: ea1c 5513 andsne.w r5, ip, r3, lsr #20
800022c: ea94 0f0c teqne r4, ip
8000230: ea95 0f0c teqne r5, ip
8000234: f000 f8de bleq 80003f4 <__aeabi_dmul+0x1dc>
8000238: 442c add r4, r5
800023a: ea81 0603 eor.w r6, r1, r3
800023e: ea21 514c bic.w r1, r1, ip, lsl #21
8000242: ea23 534c bic.w r3, r3, ip, lsl #21
8000246: ea50 3501 orrs.w r5, r0, r1, lsl #12
800024a: bf18 it ne
800024c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000250: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000254: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8000258: d038 beq.n 80002cc <__aeabi_dmul+0xb4>
800025a: fba0 ce02 umull ip, lr, r0, r2
800025e: f04f 0500 mov.w r5, #0
8000262: fbe1 e502 umlal lr, r5, r1, r2
8000266: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
800026a: fbe0 e503 umlal lr, r5, r0, r3
800026e: f04f 0600 mov.w r6, #0
8000272: fbe1 5603 umlal r5, r6, r1, r3
8000276: f09c 0f00 teq ip, #0
800027a: bf18 it ne
800027c: f04e 0e01 orrne.w lr, lr, #1
8000280: f1a4 04ff sub.w r4, r4, #255 @ 0xff
8000284: f5b6 7f00 cmp.w r6, #512 @ 0x200
8000288: f564 7440 sbc.w r4, r4, #768 @ 0x300
800028c: d204 bcs.n 8000298 <__aeabi_dmul+0x80>
800028e: ea5f 0e4e movs.w lr, lr, lsl #1
8000292: 416d adcs r5, r5
8000294: eb46 0606 adc.w r6, r6, r6
8000298: ea42 21c6 orr.w r1, r2, r6, lsl #11
800029c: ea41 5155 orr.w r1, r1, r5, lsr #21
80002a0: ea4f 20c5 mov.w r0, r5, lsl #11
80002a4: ea40 505e orr.w r0, r0, lr, lsr #21
80002a8: ea4f 2ece mov.w lr, lr, lsl #11
80002ac: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
80002b0: bf88 it hi
80002b2: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
80002b6: d81e bhi.n 80002f6 <__aeabi_dmul+0xde>
80002b8: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
80002bc: bf08 it eq
80002be: ea5f 0e50 movseq.w lr, r0, lsr #1
80002c2: f150 0000 adcs.w r0, r0, #0
80002c6: eb41 5104 adc.w r1, r1, r4, lsl #20
80002ca: bd70 pop {r4, r5, r6, pc}
80002cc: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
80002d0: ea46 0101 orr.w r1, r6, r1
80002d4: ea40 0002 orr.w r0, r0, r2
80002d8: ea81 0103 eor.w r1, r1, r3
80002dc: ebb4 045c subs.w r4, r4, ip, lsr #1
80002e0: bfc2 ittt gt
80002e2: ebd4 050c rsbsgt r5, r4, ip
80002e6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80002ea: bd70 popgt {r4, r5, r6, pc}
80002ec: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80002f0: f04f 0e00 mov.w lr, #0
80002f4: 3c01 subs r4, #1
80002f6: f300 80ab bgt.w 8000450 <__aeabi_dmul+0x238>
80002fa: f114 0f36 cmn.w r4, #54 @ 0x36
80002fe: bfde ittt le
8000300: 2000 movle r0, #0
8000302: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
8000306: bd70 pople {r4, r5, r6, pc}
8000308: f1c4 0400 rsb r4, r4, #0
800030c: 3c20 subs r4, #32
800030e: da35 bge.n 800037c <__aeabi_dmul+0x164>
8000310: 340c adds r4, #12
8000312: dc1b bgt.n 800034c <__aeabi_dmul+0x134>
8000314: f104 0414 add.w r4, r4, #20
8000318: f1c4 0520 rsb r5, r4, #32
800031c: fa00 f305 lsl.w r3, r0, r5
8000320: fa20 f004 lsr.w r0, r0, r4
8000324: fa01 f205 lsl.w r2, r1, r5
8000328: ea40 0002 orr.w r0, r0, r2
800032c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000330: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000334: eb10 70d3 adds.w r0, r0, r3, lsr #31
8000338: fa21 f604 lsr.w r6, r1, r4
800033c: eb42 0106 adc.w r1, r2, r6
8000340: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000344: bf08 it eq
8000346: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800034a: bd70 pop {r4, r5, r6, pc}
800034c: f1c4 040c rsb r4, r4, #12
8000350: f1c4 0520 rsb r5, r4, #32
8000354: fa00 f304 lsl.w r3, r0, r4
8000358: fa20 f005 lsr.w r0, r0, r5
800035c: fa01 f204 lsl.w r2, r1, r4
8000360: ea40 0002 orr.w r0, r0, r2
8000364: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000368: eb10 70d3 adds.w r0, r0, r3, lsr #31
800036c: f141 0100 adc.w r1, r1, #0
8000370: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000374: bf08 it eq
8000376: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800037a: bd70 pop {r4, r5, r6, pc}
800037c: f1c4 0520 rsb r5, r4, #32
8000380: fa00 f205 lsl.w r2, r0, r5
8000384: ea4e 0e02 orr.w lr, lr, r2
8000388: fa20 f304 lsr.w r3, r0, r4
800038c: fa01 f205 lsl.w r2, r1, r5
8000390: ea43 0302 orr.w r3, r3, r2
8000394: fa21 f004 lsr.w r0, r1, r4
8000398: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800039c: fa21 f204 lsr.w r2, r1, r4
80003a0: ea20 0002 bic.w r0, r0, r2
80003a4: eb00 70d3 add.w r0, r0, r3, lsr #31
80003a8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80003ac: bf08 it eq
80003ae: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80003b2: bd70 pop {r4, r5, r6, pc}
80003b4: f094 0f00 teq r4, #0
80003b8: d10f bne.n 80003da <__aeabi_dmul+0x1c2>
80003ba: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
80003be: 0040 lsls r0, r0, #1
80003c0: eb41 0101 adc.w r1, r1, r1
80003c4: f411 1f80 tst.w r1, #1048576 @ 0x100000
80003c8: bf08 it eq
80003ca: 3c01 subeq r4, #1
80003cc: d0f7 beq.n 80003be <__aeabi_dmul+0x1a6>
80003ce: ea41 0106 orr.w r1, r1, r6
80003d2: f095 0f00 teq r5, #0
80003d6: bf18 it ne
80003d8: 4770 bxne lr
80003da: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
80003de: 0052 lsls r2, r2, #1
80003e0: eb43 0303 adc.w r3, r3, r3
80003e4: f413 1f80 tst.w r3, #1048576 @ 0x100000
80003e8: bf08 it eq
80003ea: 3d01 subeq r5, #1
80003ec: d0f7 beq.n 80003de <__aeabi_dmul+0x1c6>
80003ee: ea43 0306 orr.w r3, r3, r6
80003f2: 4770 bx lr
80003f4: ea94 0f0c teq r4, ip
80003f8: ea0c 5513 and.w r5, ip, r3, lsr #20
80003fc: bf18 it ne
80003fe: ea95 0f0c teqne r5, ip
8000402: d00c beq.n 800041e <__aeabi_dmul+0x206>
8000404: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000408: bf18 it ne
800040a: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800040e: d1d1 bne.n 80003b4 <__aeabi_dmul+0x19c>
8000410: ea81 0103 eor.w r1, r1, r3
8000414: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000418: f04f 0000 mov.w r0, #0
800041c: bd70 pop {r4, r5, r6, pc}
800041e: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000422: bf06 itte eq
8000424: 4610 moveq r0, r2
8000426: 4619 moveq r1, r3
8000428: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800042c: d019 beq.n 8000462 <__aeabi_dmul+0x24a>
800042e: ea94 0f0c teq r4, ip
8000432: d102 bne.n 800043a <__aeabi_dmul+0x222>
8000434: ea50 3601 orrs.w r6, r0, r1, lsl #12
8000438: d113 bne.n 8000462 <__aeabi_dmul+0x24a>
800043a: ea95 0f0c teq r5, ip
800043e: d105 bne.n 800044c <__aeabi_dmul+0x234>
8000440: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000444: bf1c itt ne
8000446: 4610 movne r0, r2
8000448: 4619 movne r1, r3
800044a: d10a bne.n 8000462 <__aeabi_dmul+0x24a>
800044c: ea81 0103 eor.w r1, r1, r3
8000450: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000454: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000458: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
800045c: f04f 0000 mov.w r0, #0
8000460: bd70 pop {r4, r5, r6, pc}
8000462: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000466: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
800046a: bd70 pop {r4, r5, r6, pc}
0800046c <__aeabi_drsub>:
800046c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
8000470: e002 b.n 8000478 <__adddf3>
8000472: bf00 nop
08000474 <__aeabi_dsub>:
8000474: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
08000478 <__adddf3>:
8000478: b530 push {r4, r5, lr}
800047a: ea4f 0441 mov.w r4, r1, lsl #1
800047e: ea4f 0543 mov.w r5, r3, lsl #1
8000482: ea94 0f05 teq r4, r5
8000486: bf08 it eq
8000488: ea90 0f02 teqeq r0, r2
800048c: bf1f itttt ne
800048e: ea54 0c00 orrsne.w ip, r4, r0
8000492: ea55 0c02 orrsne.w ip, r5, r2
8000496: ea7f 5c64 mvnsne.w ip, r4, asr #21
800049a: ea7f 5c65 mvnsne.w ip, r5, asr #21
800049e: f000 80e2 beq.w 8000666 <__adddf3+0x1ee>
80004a2: ea4f 5454 mov.w r4, r4, lsr #21
80004a6: ebd4 5555 rsbs r5, r4, r5, lsr #21
80004aa: bfb8 it lt
80004ac: 426d neglt r5, r5
80004ae: dd0c ble.n 80004ca <__adddf3+0x52>
80004b0: 442c add r4, r5
80004b2: ea80 0202 eor.w r2, r0, r2
80004b6: ea81 0303 eor.w r3, r1, r3
80004ba: ea82 0000 eor.w r0, r2, r0
80004be: ea83 0101 eor.w r1, r3, r1
80004c2: ea80 0202 eor.w r2, r0, r2
80004c6: ea81 0303 eor.w r3, r1, r3
80004ca: 2d36 cmp r5, #54 @ 0x36
80004cc: bf88 it hi
80004ce: bd30 pophi {r4, r5, pc}
80004d0: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80004d4: ea4f 3101 mov.w r1, r1, lsl #12
80004d8: f44f 1c80 mov.w ip, #1048576 @ 0x100000
80004dc: ea4c 3111 orr.w r1, ip, r1, lsr #12
80004e0: d002 beq.n 80004e8 <__adddf3+0x70>
80004e2: 4240 negs r0, r0
80004e4: eb61 0141 sbc.w r1, r1, r1, lsl #1
80004e8: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
80004ec: ea4f 3303 mov.w r3, r3, lsl #12
80004f0: ea4c 3313 orr.w r3, ip, r3, lsr #12
80004f4: d002 beq.n 80004fc <__adddf3+0x84>
80004f6: 4252 negs r2, r2
80004f8: eb63 0343 sbc.w r3, r3, r3, lsl #1
80004fc: ea94 0f05 teq r4, r5
8000500: f000 80a7 beq.w 8000652 <__adddf3+0x1da>
8000504: f1a4 0401 sub.w r4, r4, #1
8000508: f1d5 0e20 rsbs lr, r5, #32
800050c: db0d blt.n 800052a <__adddf3+0xb2>
800050e: fa02 fc0e lsl.w ip, r2, lr
8000512: fa22 f205 lsr.w r2, r2, r5
8000516: 1880 adds r0, r0, r2
8000518: f141 0100 adc.w r1, r1, #0
800051c: fa03 f20e lsl.w r2, r3, lr
8000520: 1880 adds r0, r0, r2
8000522: fa43 f305 asr.w r3, r3, r5
8000526: 4159 adcs r1, r3
8000528: e00e b.n 8000548 <__adddf3+0xd0>
800052a: f1a5 0520 sub.w r5, r5, #32
800052e: f10e 0e20 add.w lr, lr, #32
8000532: 2a01 cmp r2, #1
8000534: fa03 fc0e lsl.w ip, r3, lr
8000538: bf28 it cs
800053a: f04c 0c02 orrcs.w ip, ip, #2
800053e: fa43 f305 asr.w r3, r3, r5
8000542: 18c0 adds r0, r0, r3
8000544: eb51 71e3 adcs.w r1, r1, r3, asr #31
8000548: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
800054c: d507 bpl.n 800055e <__adddf3+0xe6>
800054e: f04f 0e00 mov.w lr, #0
8000552: f1dc 0c00 rsbs ip, ip, #0
8000556: eb7e 0000 sbcs.w r0, lr, r0
800055a: eb6e 0101 sbc.w r1, lr, r1
800055e: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
8000562: d31b bcc.n 800059c <__adddf3+0x124>
8000564: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
8000568: d30c bcc.n 8000584 <__adddf3+0x10c>
800056a: 0849 lsrs r1, r1, #1
800056c: ea5f 0030 movs.w r0, r0, rrx
8000570: ea4f 0c3c mov.w ip, ip, rrx
8000574: f104 0401 add.w r4, r4, #1
8000578: ea4f 5244 mov.w r2, r4, lsl #21
800057c: f512 0f80 cmn.w r2, #4194304 @ 0x400000
8000580: f080 809a bcs.w 80006b8 <__adddf3+0x240>
8000584: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
8000588: bf08 it eq
800058a: ea5f 0c50 movseq.w ip, r0, lsr #1
800058e: f150 0000 adcs.w r0, r0, #0
8000592: eb41 5104 adc.w r1, r1, r4, lsl #20
8000596: ea41 0105 orr.w r1, r1, r5
800059a: bd30 pop {r4, r5, pc}
800059c: ea5f 0c4c movs.w ip, ip, lsl #1
80005a0: 4140 adcs r0, r0
80005a2: eb41 0101 adc.w r1, r1, r1
80005a6: 3c01 subs r4, #1
80005a8: bf28 it cs
80005aa: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80005ae: d2e9 bcs.n 8000584 <__adddf3+0x10c>
80005b0: f091 0f00 teq r1, #0
80005b4: bf04 itt eq
80005b6: 4601 moveq r1, r0
80005b8: 2000 moveq r0, #0
80005ba: fab1 f381 clz r3, r1
80005be: bf08 it eq
80005c0: 3320 addeq r3, #32
80005c2: f1a3 030b sub.w r3, r3, #11
80005c6: f1b3 0220 subs.w r2, r3, #32
80005ca: da0c bge.n 80005e6 <__adddf3+0x16e>
80005cc: 320c adds r2, #12
80005ce: dd08 ble.n 80005e2 <__adddf3+0x16a>
80005d0: f102 0c14 add.w ip, r2, #20
80005d4: f1c2 020c rsb r2, r2, #12
80005d8: fa01 f00c lsl.w r0, r1, ip
80005dc: fa21 f102 lsr.w r1, r1, r2
80005e0: e00c b.n 80005fc <__adddf3+0x184>
80005e2: f102 0214 add.w r2, r2, #20
80005e6: bfd8 it le
80005e8: f1c2 0c20 rsble ip, r2, #32
80005ec: fa01 f102 lsl.w r1, r1, r2
80005f0: fa20 fc0c lsr.w ip, r0, ip
80005f4: bfdc itt le
80005f6: ea41 010c orrle.w r1, r1, ip
80005fa: 4090 lslle r0, r2
80005fc: 1ae4 subs r4, r4, r3
80005fe: bfa2 ittt ge
8000600: eb01 5104 addge.w r1, r1, r4, lsl #20
8000604: 4329 orrge r1, r5
8000606: bd30 popge {r4, r5, pc}
8000608: ea6f 0404 mvn.w r4, r4
800060c: 3c1f subs r4, #31
800060e: da1c bge.n 800064a <__adddf3+0x1d2>
8000610: 340c adds r4, #12
8000612: dc0e bgt.n 8000632 <__adddf3+0x1ba>
8000614: f104 0414 add.w r4, r4, #20
8000618: f1c4 0220 rsb r2, r4, #32
800061c: fa20 f004 lsr.w r0, r0, r4
8000620: fa01 f302 lsl.w r3, r1, r2
8000624: ea40 0003 orr.w r0, r0, r3
8000628: fa21 f304 lsr.w r3, r1, r4
800062c: ea45 0103 orr.w r1, r5, r3
8000630: bd30 pop {r4, r5, pc}
8000632: f1c4 040c rsb r4, r4, #12
8000636: f1c4 0220 rsb r2, r4, #32
800063a: fa20 f002 lsr.w r0, r0, r2
800063e: fa01 f304 lsl.w r3, r1, r4
8000642: ea40 0003 orr.w r0, r0, r3
8000646: 4629 mov r1, r5
8000648: bd30 pop {r4, r5, pc}
800064a: fa21 f004 lsr.w r0, r1, r4
800064e: 4629 mov r1, r5
8000650: bd30 pop {r4, r5, pc}
8000652: f094 0f00 teq r4, #0
8000656: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800065a: bf06 itte eq
800065c: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
8000660: 3401 addeq r4, #1
8000662: 3d01 subne r5, #1
8000664: e74e b.n 8000504 <__adddf3+0x8c>
8000666: ea7f 5c64 mvns.w ip, r4, asr #21
800066a: bf18 it ne
800066c: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000670: d029 beq.n 80006c6 <__adddf3+0x24e>
8000672: ea94 0f05 teq r4, r5
8000676: bf08 it eq
8000678: ea90 0f02 teqeq r0, r2
800067c: d005 beq.n 800068a <__adddf3+0x212>
800067e: ea54 0c00 orrs.w ip, r4, r0
8000682: bf04 itt eq
8000684: 4619 moveq r1, r3
8000686: 4610 moveq r0, r2
8000688: bd30 pop {r4, r5, pc}
800068a: ea91 0f03 teq r1, r3
800068e: bf1e ittt ne
8000690: 2100 movne r1, #0
8000692: 2000 movne r0, #0
8000694: bd30 popne {r4, r5, pc}
8000696: ea5f 5c54 movs.w ip, r4, lsr #21
800069a: d105 bne.n 80006a8 <__adddf3+0x230>
800069c: 0040 lsls r0, r0, #1
800069e: 4149 adcs r1, r1
80006a0: bf28 it cs
80006a2: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80006a6: bd30 pop {r4, r5, pc}
80006a8: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80006ac: bf3c itt cc
80006ae: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80006b2: bd30 popcc {r4, r5, pc}
80006b4: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80006b8: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
80006bc: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80006c0: f04f 0000 mov.w r0, #0
80006c4: bd30 pop {r4, r5, pc}
80006c6: ea7f 5c64 mvns.w ip, r4, asr #21
80006ca: bf1a itte ne
80006cc: 4619 movne r1, r3
80006ce: 4610 movne r0, r2
80006d0: ea7f 5c65 mvnseq.w ip, r5, asr #21
80006d4: bf1c itt ne
80006d6: 460b movne r3, r1
80006d8: 4602 movne r2, r0
80006da: ea50 3401 orrs.w r4, r0, r1, lsl #12
80006de: bf06 itte eq
80006e0: ea52 3503 orrseq.w r5, r2, r3, lsl #12
80006e4: ea91 0f03 teqeq r1, r3
80006e8: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
80006ec: bd30 pop {r4, r5, pc}
80006ee: bf00 nop
080006f0 <__aeabi_ui2d>:
80006f0: f090 0f00 teq r0, #0
80006f4: bf04 itt eq
80006f6: 2100 moveq r1, #0
80006f8: 4770 bxeq lr
80006fa: b530 push {r4, r5, lr}
80006fc: f44f 6480 mov.w r4, #1024 @ 0x400
8000700: f104 0432 add.w r4, r4, #50 @ 0x32
8000704: f04f 0500 mov.w r5, #0
8000708: f04f 0100 mov.w r1, #0
800070c: e750 b.n 80005b0 <__adddf3+0x138>
800070e: bf00 nop
08000710 <__aeabi_i2d>:
8000710: f090 0f00 teq r0, #0
8000714: bf04 itt eq
8000716: 2100 moveq r1, #0
8000718: 4770 bxeq lr
800071a: b530 push {r4, r5, lr}
800071c: f44f 6480 mov.w r4, #1024 @ 0x400
8000720: f104 0432 add.w r4, r4, #50 @ 0x32
8000724: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
8000728: bf48 it mi
800072a: 4240 negmi r0, r0
800072c: f04f 0100 mov.w r1, #0
8000730: e73e b.n 80005b0 <__adddf3+0x138>
8000732: bf00 nop
08000734 <__aeabi_f2d>:
8000734: 0042 lsls r2, r0, #1
8000736: ea4f 01e2 mov.w r1, r2, asr #3
800073a: ea4f 0131 mov.w r1, r1, rrx
800073e: ea4f 7002 mov.w r0, r2, lsl #28
8000742: bf1f itttt ne
8000744: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
8000748: f093 4f7f teqne r3, #4278190080 @ 0xff000000
800074c: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000750: 4770 bxne lr
8000752: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
8000756: bf08 it eq
8000758: 4770 bxeq lr
800075a: f093 4f7f teq r3, #4278190080 @ 0xff000000
800075e: bf04 itt eq
8000760: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
8000764: 4770 bxeq lr
8000766: b530 push {r4, r5, lr}
8000768: f44f 7460 mov.w r4, #896 @ 0x380
800076c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000770: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000774: e71c b.n 80005b0 <__adddf3+0x138>
8000776: bf00 nop
08000778 <__aeabi_ul2d>:
8000778: ea50 0201 orrs.w r2, r0, r1
800077c: bf08 it eq
800077e: 4770 bxeq lr
8000780: b530 push {r4, r5, lr}
8000782: f04f 0500 mov.w r5, #0
8000786: e00a b.n 800079e <__aeabi_l2d+0x16>
08000788 <__aeabi_l2d>:
8000788: ea50 0201 orrs.w r2, r0, r1
800078c: bf08 it eq
800078e: 4770 bxeq lr
8000790: b530 push {r4, r5, lr}
8000792: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
8000796: d502 bpl.n 800079e <__aeabi_l2d+0x16>
8000798: 4240 negs r0, r0
800079a: eb61 0141 sbc.w r1, r1, r1, lsl #1
800079e: f44f 6480 mov.w r4, #1024 @ 0x400
80007a2: f104 0432 add.w r4, r4, #50 @ 0x32
80007a6: ea5f 5c91 movs.w ip, r1, lsr #22
80007aa: f43f aed8 beq.w 800055e <__adddf3+0xe6>
80007ae: f04f 0203 mov.w r2, #3
80007b2: ea5f 0cdc movs.w ip, ip, lsr #3
80007b6: bf18 it ne
80007b8: 3203 addne r2, #3
80007ba: ea5f 0cdc movs.w ip, ip, lsr #3
80007be: bf18 it ne
80007c0: 3203 addne r2, #3
80007c2: eb02 02dc add.w r2, r2, ip, lsr #3
80007c6: f1c2 0320 rsb r3, r2, #32
80007ca: fa00 fc03 lsl.w ip, r0, r3
80007ce: fa20 f002 lsr.w r0, r0, r2
80007d2: fa01 fe03 lsl.w lr, r1, r3
80007d6: ea40 000e orr.w r0, r0, lr
80007da: fa21 f102 lsr.w r1, r1, r2
80007de: 4414 add r4, r2
80007e0: e6bd b.n 800055e <__adddf3+0xe6>
80007e2: bf00 nop
080007e4 <__aeabi_d2uiz>:
80007e4: 004a lsls r2, r1, #1
80007e6: d211 bcs.n 800080c <__aeabi_d2uiz+0x28>
80007e8: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
80007ec: d211 bcs.n 8000812 <__aeabi_d2uiz+0x2e>
80007ee: d50d bpl.n 800080c <__aeabi_d2uiz+0x28>
80007f0: f46f 7378 mvn.w r3, #992 @ 0x3e0
80007f4: ebb3 5262 subs.w r2, r3, r2, asr #21
80007f8: d40e bmi.n 8000818 <__aeabi_d2uiz+0x34>
80007fa: ea4f 23c1 mov.w r3, r1, lsl #11
80007fe: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000802: ea43 5350 orr.w r3, r3, r0, lsr #21
8000806: fa23 f002 lsr.w r0, r3, r2
800080a: 4770 bx lr
800080c: f04f 0000 mov.w r0, #0
8000810: 4770 bx lr
8000812: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000816: d102 bne.n 800081e <__aeabi_d2uiz+0x3a>
8000818: f04f 30ff mov.w r0, #4294967295
800081c: 4770 bx lr
800081e: f04f 0000 mov.w r0, #0
8000822: 4770 bx lr
08000824 <__aeabi_uldivmod>:
8000824: b953 cbnz r3, 800083c <__aeabi_uldivmod+0x18>
8000826: b94a cbnz r2, 800083c <__aeabi_uldivmod+0x18>
8000828: 2900 cmp r1, #0
800082a: bf08 it eq
800082c: 2800 cmpeq r0, #0
800082e: bf1c itt ne
8000830: f04f 31ff movne.w r1, #4294967295
8000834: f04f 30ff movne.w r0, #4294967295
8000838: f000 b988 b.w 8000b4c <__aeabi_idiv0>
800083c: f1ad 0c08 sub.w ip, sp, #8
8000840: e96d ce04 strd ip, lr, [sp, #-16]!
8000844: f000 f806 bl 8000854 <__udivmoddi4>
8000848: f8dd e004 ldr.w lr, [sp, #4]
800084c: e9dd 2302 ldrd r2, r3, [sp, #8]
8000850: b004 add sp, #16
8000852: 4770 bx lr
08000854 <__udivmoddi4>:
8000854: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000858: 9d08 ldr r5, [sp, #32]
800085a: 468e mov lr, r1
800085c: 4604 mov r4, r0
800085e: 4688 mov r8, r1
8000860: 2b00 cmp r3, #0
8000862: d14a bne.n 80008fa <__udivmoddi4+0xa6>
8000864: 428a cmp r2, r1
8000866: 4617 mov r7, r2
8000868: d962 bls.n 8000930 <__udivmoddi4+0xdc>
800086a: fab2 f682 clz r6, r2
800086e: b14e cbz r6, 8000884 <__udivmoddi4+0x30>
8000870: f1c6 0320 rsb r3, r6, #32
8000874: fa01 f806 lsl.w r8, r1, r6
8000878: fa20 f303 lsr.w r3, r0, r3
800087c: 40b7 lsls r7, r6
800087e: ea43 0808 orr.w r8, r3, r8
8000882: 40b4 lsls r4, r6
8000884: ea4f 4e17 mov.w lr, r7, lsr #16
8000888: fa1f fc87 uxth.w ip, r7
800088c: fbb8 f1fe udiv r1, r8, lr
8000890: 0c23 lsrs r3, r4, #16
8000892: fb0e 8811 mls r8, lr, r1, r8
8000896: ea43 4308 orr.w r3, r3, r8, lsl #16
800089a: fb01 f20c mul.w r2, r1, ip
800089e: 429a cmp r2, r3
80008a0: d909 bls.n 80008b6 <__udivmoddi4+0x62>
80008a2: 18fb adds r3, r7, r3
80008a4: f101 30ff add.w r0, r1, #4294967295
80008a8: f080 80ea bcs.w 8000a80 <__udivmoddi4+0x22c>
80008ac: 429a cmp r2, r3
80008ae: f240 80e7 bls.w 8000a80 <__udivmoddi4+0x22c>
80008b2: 3902 subs r1, #2
80008b4: 443b add r3, r7
80008b6: 1a9a subs r2, r3, r2
80008b8: b2a3 uxth r3, r4
80008ba: fbb2 f0fe udiv r0, r2, lr
80008be: fb0e 2210 mls r2, lr, r0, r2
80008c2: ea43 4302 orr.w r3, r3, r2, lsl #16
80008c6: fb00 fc0c mul.w ip, r0, ip
80008ca: 459c cmp ip, r3
80008cc: d909 bls.n 80008e2 <__udivmoddi4+0x8e>
80008ce: 18fb adds r3, r7, r3
80008d0: f100 32ff add.w r2, r0, #4294967295
80008d4: f080 80d6 bcs.w 8000a84 <__udivmoddi4+0x230>
80008d8: 459c cmp ip, r3
80008da: f240 80d3 bls.w 8000a84 <__udivmoddi4+0x230>
80008de: 443b add r3, r7
80008e0: 3802 subs r0, #2
80008e2: ea40 4001 orr.w r0, r0, r1, lsl #16
80008e6: eba3 030c sub.w r3, r3, ip
80008ea: 2100 movs r1, #0
80008ec: b11d cbz r5, 80008f6 <__udivmoddi4+0xa2>
80008ee: 40f3 lsrs r3, r6
80008f0: 2200 movs r2, #0
80008f2: e9c5 3200 strd r3, r2, [r5]
80008f6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80008fa: 428b cmp r3, r1
80008fc: d905 bls.n 800090a <__udivmoddi4+0xb6>
80008fe: b10d cbz r5, 8000904 <__udivmoddi4+0xb0>
8000900: e9c5 0100 strd r0, r1, [r5]
8000904: 2100 movs r1, #0
8000906: 4608 mov r0, r1
8000908: e7f5 b.n 80008f6 <__udivmoddi4+0xa2>
800090a: fab3 f183 clz r1, r3
800090e: 2900 cmp r1, #0
8000910: d146 bne.n 80009a0 <__udivmoddi4+0x14c>
8000912: 4573 cmp r3, lr
8000914: d302 bcc.n 800091c <__udivmoddi4+0xc8>
8000916: 4282 cmp r2, r0
8000918: f200 8105 bhi.w 8000b26 <__udivmoddi4+0x2d2>
800091c: 1a84 subs r4, r0, r2
800091e: eb6e 0203 sbc.w r2, lr, r3
8000922: 2001 movs r0, #1
8000924: 4690 mov r8, r2
8000926: 2d00 cmp r5, #0
8000928: d0e5 beq.n 80008f6 <__udivmoddi4+0xa2>
800092a: e9c5 4800 strd r4, r8, [r5]
800092e: e7e2 b.n 80008f6 <__udivmoddi4+0xa2>
8000930: 2a00 cmp r2, #0
8000932: f000 8090 beq.w 8000a56 <__udivmoddi4+0x202>
8000936: fab2 f682 clz r6, r2
800093a: 2e00 cmp r6, #0
800093c: f040 80a4 bne.w 8000a88 <__udivmoddi4+0x234>
8000940: 1a8a subs r2, r1, r2
8000942: 0c03 lsrs r3, r0, #16
8000944: ea4f 4e17 mov.w lr, r7, lsr #16
8000948: b280 uxth r0, r0
800094a: b2bc uxth r4, r7
800094c: 2101 movs r1, #1
800094e: fbb2 fcfe udiv ip, r2, lr
8000952: fb0e 221c mls r2, lr, ip, r2
8000956: ea43 4302 orr.w r3, r3, r2, lsl #16
800095a: fb04 f20c mul.w r2, r4, ip
800095e: 429a cmp r2, r3
8000960: d907 bls.n 8000972 <__udivmoddi4+0x11e>
8000962: 18fb adds r3, r7, r3
8000964: f10c 38ff add.w r8, ip, #4294967295
8000968: d202 bcs.n 8000970 <__udivmoddi4+0x11c>
800096a: 429a cmp r2, r3
800096c: f200 80e0 bhi.w 8000b30 <__udivmoddi4+0x2dc>
8000970: 46c4 mov ip, r8
8000972: 1a9b subs r3, r3, r2
8000974: fbb3 f2fe udiv r2, r3, lr
8000978: fb0e 3312 mls r3, lr, r2, r3
800097c: ea40 4303 orr.w r3, r0, r3, lsl #16
8000980: fb02 f404 mul.w r4, r2, r4
8000984: 429c cmp r4, r3
8000986: d907 bls.n 8000998 <__udivmoddi4+0x144>
8000988: 18fb adds r3, r7, r3
800098a: f102 30ff add.w r0, r2, #4294967295
800098e: d202 bcs.n 8000996 <__udivmoddi4+0x142>
8000990: 429c cmp r4, r3
8000992: f200 80ca bhi.w 8000b2a <__udivmoddi4+0x2d6>
8000996: 4602 mov r2, r0
8000998: 1b1b subs r3, r3, r4
800099a: ea42 400c orr.w r0, r2, ip, lsl #16
800099e: e7a5 b.n 80008ec <__udivmoddi4+0x98>
80009a0: f1c1 0620 rsb r6, r1, #32
80009a4: 408b lsls r3, r1
80009a6: fa22 f706 lsr.w r7, r2, r6
80009aa: 431f orrs r7, r3
80009ac: fa0e f401 lsl.w r4, lr, r1
80009b0: fa20 f306 lsr.w r3, r0, r6
80009b4: fa2e fe06 lsr.w lr, lr, r6
80009b8: ea4f 4917 mov.w r9, r7, lsr #16
80009bc: 4323 orrs r3, r4
80009be: fa00 f801 lsl.w r8, r0, r1
80009c2: fa1f fc87 uxth.w ip, r7
80009c6: fbbe f0f9 udiv r0, lr, r9
80009ca: 0c1c lsrs r4, r3, #16
80009cc: fb09 ee10 mls lr, r9, r0, lr
80009d0: ea44 440e orr.w r4, r4, lr, lsl #16
80009d4: fb00 fe0c mul.w lr, r0, ip
80009d8: 45a6 cmp lr, r4
80009da: fa02 f201 lsl.w r2, r2, r1
80009de: d909 bls.n 80009f4 <__udivmoddi4+0x1a0>
80009e0: 193c adds r4, r7, r4
80009e2: f100 3aff add.w sl, r0, #4294967295
80009e6: f080 809c bcs.w 8000b22 <__udivmoddi4+0x2ce>
80009ea: 45a6 cmp lr, r4
80009ec: f240 8099 bls.w 8000b22 <__udivmoddi4+0x2ce>
80009f0: 3802 subs r0, #2
80009f2: 443c add r4, r7
80009f4: eba4 040e sub.w r4, r4, lr
80009f8: fa1f fe83 uxth.w lr, r3
80009fc: fbb4 f3f9 udiv r3, r4, r9
8000a00: fb09 4413 mls r4, r9, r3, r4
8000a04: ea4e 4404 orr.w r4, lr, r4, lsl #16
8000a08: fb03 fc0c mul.w ip, r3, ip
8000a0c: 45a4 cmp ip, r4
8000a0e: d908 bls.n 8000a22 <__udivmoddi4+0x1ce>
8000a10: 193c adds r4, r7, r4
8000a12: f103 3eff add.w lr, r3, #4294967295
8000a16: f080 8082 bcs.w 8000b1e <__udivmoddi4+0x2ca>
8000a1a: 45a4 cmp ip, r4
8000a1c: d97f bls.n 8000b1e <__udivmoddi4+0x2ca>
8000a1e: 3b02 subs r3, #2
8000a20: 443c add r4, r7
8000a22: ea43 4000 orr.w r0, r3, r0, lsl #16
8000a26: eba4 040c sub.w r4, r4, ip
8000a2a: fba0 ec02 umull lr, ip, r0, r2
8000a2e: 4564 cmp r4, ip
8000a30: 4673 mov r3, lr
8000a32: 46e1 mov r9, ip
8000a34: d362 bcc.n 8000afc <__udivmoddi4+0x2a8>
8000a36: d05f beq.n 8000af8 <__udivmoddi4+0x2a4>
8000a38: b15d cbz r5, 8000a52 <__udivmoddi4+0x1fe>
8000a3a: ebb8 0203 subs.w r2, r8, r3
8000a3e: eb64 0409 sbc.w r4, r4, r9
8000a42: fa04 f606 lsl.w r6, r4, r6
8000a46: fa22 f301 lsr.w r3, r2, r1
8000a4a: 431e orrs r6, r3
8000a4c: 40cc lsrs r4, r1
8000a4e: e9c5 6400 strd r6, r4, [r5]
8000a52: 2100 movs r1, #0
8000a54: e74f b.n 80008f6 <__udivmoddi4+0xa2>
8000a56: fbb1 fcf2 udiv ip, r1, r2
8000a5a: 0c01 lsrs r1, r0, #16
8000a5c: ea41 410e orr.w r1, r1, lr, lsl #16
8000a60: b280 uxth r0, r0
8000a62: ea40 4201 orr.w r2, r0, r1, lsl #16
8000a66: 463b mov r3, r7
8000a68: 4638 mov r0, r7
8000a6a: 463c mov r4, r7
8000a6c: 46b8 mov r8, r7
8000a6e: 46be mov lr, r7
8000a70: 2620 movs r6, #32
8000a72: fbb1 f1f7 udiv r1, r1, r7
8000a76: eba2 0208 sub.w r2, r2, r8
8000a7a: ea41 410c orr.w r1, r1, ip, lsl #16
8000a7e: e766 b.n 800094e <__udivmoddi4+0xfa>
8000a80: 4601 mov r1, r0
8000a82: e718 b.n 80008b6 <__udivmoddi4+0x62>
8000a84: 4610 mov r0, r2
8000a86: e72c b.n 80008e2 <__udivmoddi4+0x8e>
8000a88: f1c6 0220 rsb r2, r6, #32
8000a8c: fa2e f302 lsr.w r3, lr, r2
8000a90: 40b7 lsls r7, r6
8000a92: 40b1 lsls r1, r6
8000a94: fa20 f202 lsr.w r2, r0, r2
8000a98: ea4f 4e17 mov.w lr, r7, lsr #16
8000a9c: 430a orrs r2, r1
8000a9e: fbb3 f8fe udiv r8, r3, lr
8000aa2: b2bc uxth r4, r7
8000aa4: fb0e 3318 mls r3, lr, r8, r3
8000aa8: 0c11 lsrs r1, r2, #16
8000aaa: ea41 4103 orr.w r1, r1, r3, lsl #16
8000aae: fb08 f904 mul.w r9, r8, r4
8000ab2: 40b0 lsls r0, r6
8000ab4: 4589 cmp r9, r1
8000ab6: ea4f 4310 mov.w r3, r0, lsr #16
8000aba: b280 uxth r0, r0
8000abc: d93e bls.n 8000b3c <__udivmoddi4+0x2e8>
8000abe: 1879 adds r1, r7, r1
8000ac0: f108 3cff add.w ip, r8, #4294967295
8000ac4: d201 bcs.n 8000aca <__udivmoddi4+0x276>
8000ac6: 4589 cmp r9, r1
8000ac8: d81f bhi.n 8000b0a <__udivmoddi4+0x2b6>
8000aca: eba1 0109 sub.w r1, r1, r9
8000ace: fbb1 f9fe udiv r9, r1, lr
8000ad2: fb09 f804 mul.w r8, r9, r4
8000ad6: fb0e 1119 mls r1, lr, r9, r1
8000ada: b292 uxth r2, r2
8000adc: ea42 4201 orr.w r2, r2, r1, lsl #16
8000ae0: 4542 cmp r2, r8
8000ae2: d229 bcs.n 8000b38 <__udivmoddi4+0x2e4>
8000ae4: 18ba adds r2, r7, r2
8000ae6: f109 31ff add.w r1, r9, #4294967295
8000aea: d2c4 bcs.n 8000a76 <__udivmoddi4+0x222>
8000aec: 4542 cmp r2, r8
8000aee: d2c2 bcs.n 8000a76 <__udivmoddi4+0x222>
8000af0: f1a9 0102 sub.w r1, r9, #2
8000af4: 443a add r2, r7
8000af6: e7be b.n 8000a76 <__udivmoddi4+0x222>
8000af8: 45f0 cmp r8, lr
8000afa: d29d bcs.n 8000a38 <__udivmoddi4+0x1e4>
8000afc: ebbe 0302 subs.w r3, lr, r2
8000b00: eb6c 0c07 sbc.w ip, ip, r7
8000b04: 3801 subs r0, #1
8000b06: 46e1 mov r9, ip
8000b08: e796 b.n 8000a38 <__udivmoddi4+0x1e4>
8000b0a: eba7 0909 sub.w r9, r7, r9
8000b0e: 4449 add r1, r9
8000b10: f1a8 0c02 sub.w ip, r8, #2
8000b14: fbb1 f9fe udiv r9, r1, lr
8000b18: fb09 f804 mul.w r8, r9, r4
8000b1c: e7db b.n 8000ad6 <__udivmoddi4+0x282>
8000b1e: 4673 mov r3, lr
8000b20: e77f b.n 8000a22 <__udivmoddi4+0x1ce>
8000b22: 4650 mov r0, sl
8000b24: e766 b.n 80009f4 <__udivmoddi4+0x1a0>
8000b26: 4608 mov r0, r1
8000b28: e6fd b.n 8000926 <__udivmoddi4+0xd2>
8000b2a: 443b add r3, r7
8000b2c: 3a02 subs r2, #2
8000b2e: e733 b.n 8000998 <__udivmoddi4+0x144>
8000b30: f1ac 0c02 sub.w ip, ip, #2
8000b34: 443b add r3, r7
8000b36: e71c b.n 8000972 <__udivmoddi4+0x11e>
8000b38: 4649 mov r1, r9
8000b3a: e79c b.n 8000a76 <__udivmoddi4+0x222>
8000b3c: eba1 0109 sub.w r1, r1, r9
8000b40: 46c4 mov ip, r8
8000b42: fbb1 f9fe udiv r9, r1, lr
8000b46: fb09 f804 mul.w r8, r9, r4
8000b4a: e7c4 b.n 8000ad6 <__udivmoddi4+0x282>
08000b4c <__aeabi_idiv0>:
8000b4c: 4770 bx lr
8000b4e: bf00 nop
08000b50 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b50: b580 push {r7, lr}
8000b52: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b54: f001 f92f bl 8001db6 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b58: f000 f8a0 bl 8000c9c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b5c: f000 faec bl 8001138 <MX_GPIO_Init>
MX_USART2_UART_Init();
8000b60: f000 fa9e bl 80010a0 <MX_USART2_UART_Init>
MX_ADC2_Init();
8000b64: f000 f95e bl 8000e24 <MX_ADC2_Init>
MX_TIM2_Init();
8000b68: f000 f9d2 bl 8000f10 <MX_TIM2_Init>
MX_ADC1_Init();
8000b6c: f000 f8e2 bl 8000d34 <MX_ADC1_Init>
MX_TIM16_Init();
8000b70: f000 fa1c bl 8000fac <MX_TIM16_Init>
/* USER CODE BEGIN 2 */
/*Configure GPIO pin output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000b74: 2200 movs r2, #0
8000b76: f44f 7180 mov.w r1, #256 @ 0x100
8000b7a: 4836 ldr r0, [pc, #216] @ (8000c54 <main+0x104>)
8000b7c: f003 f99c bl 8003eb8 <HAL_GPIO_WritePin>
/* Run ADC calibration */
HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);
8000b80: 217f movs r1, #127 @ 0x7f
8000b82: 4835 ldr r0, [pc, #212] @ (8000c58 <main+0x108>)
8000b84: f002 fd40 bl 8003608 <HAL_ADCEx_Calibration_Start>
HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED);
8000b88: 217f movs r1, #127 @ 0x7f
8000b8a: 4834 ldr r0, [pc, #208] @ (8000c5c <main+0x10c>)
8000b8c: f002 fd3c bl 8003608 <HAL_ADCEx_Calibration_Start>
/* Setup UART interrupts */
/* Make sure UART Rx counters and flags are reset */
rx_counter = 0x00;
8000b90: 4b33 ldr r3, [pc, #204] @ (8000c60 <main+0x110>)
8000b92: 2200 movs r2, #0
8000b94: 701a strb r2, [r3, #0]
rx_len = 0x00;
8000b96: 4b33 ldr r3, [pc, #204] @ (8000c64 <main+0x114>)
8000b98: 2200 movs r2, #0
8000b9a: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
8000b9c: 4b32 ldr r3, [pc, #200] @ (8000c68 <main+0x118>)
8000b9e: 2200 movs r2, #0
8000ba0: 701a strb r2, [r3, #0]
adc_task_flag = 0x00;
8000ba2: 4b32 ldr r3, [pc, #200] @ (8000c6c <main+0x11c>)
8000ba4: 2200 movs r2, #0
8000ba6: 701a strb r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
8000ba8: 2201 movs r2, #1
8000baa: 4931 ldr r1, [pc, #196] @ (8000c70 <main+0x120>)
8000bac: 4831 ldr r0, [pc, #196] @ (8000c74 <main+0x124>)
8000bae: f005 fd3b bl 8006628 <HAL_UART_Receive_IT>
/* Get real VDDA value */
vdd_ref = get_actual_vdda(&hadc1);
8000bb2: 4829 ldr r0, [pc, #164] @ (8000c58 <main+0x108>)
8000bb4: f000 fbba bl 800132c <get_actual_vdda>
8000bb8: 4603 mov r3, r0
8000bba: 4a2f ldr r2, [pc, #188] @ (8000c78 <main+0x128>)
8000bbc: 6013 str r3, [r2, #0]
/* Start output PWM at zero */
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
8000bbe: 4b2f ldr r3, [pc, #188] @ (8000c7c <main+0x12c>)
8000bc0: 681b ldr r3, [r3, #0]
8000bc2: 2200 movs r2, #0
8000bc4: 635a str r2, [r3, #52] @ 0x34
HAL_TIM_PWM_Start(&htim16, TIM_CHANNEL_1);
8000bc6: 2100 movs r1, #0
8000bc8: 482c ldr r0, [pc, #176] @ (8000c7c <main+0x12c>)
8000bca: f004 fa17 bl 8004ffc <HAL_TIM_PWM_Start>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
if (adc_task_flag == 0xff)
8000bce: 4b27 ldr r3, [pc, #156] @ (8000c6c <main+0x11c>)
8000bd0: 781b ldrb r3, [r3, #0]
8000bd2: 2bff cmp r3, #255 @ 0xff
8000bd4: d114 bne.n 8000c00 <main+0xb0>
{
adc_task_flag = 0x00;
8000bd6: 4b25 ldr r3, [pc, #148] @ (8000c6c <main+0x11c>)
8000bd8: 2200 movs r2, #0
8000bda: 701a strb r2, [r3, #0]
if (vset_task_flag != 0xff)
8000bdc: 4b28 ldr r3, [pc, #160] @ (8000c80 <main+0x130>)
8000bde: 781b ldrb r3, [r3, #0]
8000be0: 2bff cmp r3, #255 @ 0xff
8000be2: d00b beq.n 8000bfc <main+0xac>
{
adc_task();
8000be4: f000 fd62 bl 80016ac <adc_task>
vout_adc_val_av = MA_Update (&movavFilter, vout_adc_val);
8000be8: 4b26 ldr r3, [pc, #152] @ (8000c84 <main+0x134>)
8000bea: 881b ldrh r3, [r3, #0]
8000bec: 4619 mov r1, r3
8000bee: 4826 ldr r0, [pc, #152] @ (8000c88 <main+0x138>)
8000bf0: f000 fb5c bl 80012ac <MA_Update>
8000bf4: 4603 mov r3, r0
8000bf6: 461a mov r2, r3
8000bf8: 4b24 ldr r3, [pc, #144] @ (8000c8c <main+0x13c>)
8000bfa: 801a strh r2, [r3, #0]
}
voltage_conversion_task();
8000bfc: f000 fc04 bl 8001408 <voltage_conversion_task>
}
if (serial_number_flag == 0xff)
8000c00: 4b23 ldr r3, [pc, #140] @ (8000c90 <main+0x140>)
8000c02: 781b ldrb r3, [r3, #0]
8000c04: 2bff cmp r3, #255 @ 0xff
8000c06: d104 bne.n 8000c12 <main+0xc2>
{
serial_number_flag = 0x00;
8000c08: 4b21 ldr r3, [pc, #132] @ (8000c90 <main+0x140>)
8000c0a: 2200 movs r2, #0
8000c0c: 701a strb r2, [r3, #0]
serial_number_task ();
8000c0e: f000 fcb5 bl 800157c <serial_number_task>
}
if (vset_task_flag == 0xff)
8000c12: 4b1b ldr r3, [pc, #108] @ (8000c80 <main+0x130>)
8000c14: 781b ldrb r3, [r3, #0]
8000c16: 2bff cmp r3, #255 @ 0xff
8000c18: d116 bne.n 8000c48 <main+0xf8>
{
adc_task();
8000c1a: f000 fd47 bl 80016ac <adc_task>
vout_adc_val_av = MA_Update (&movavFilter, vout_adc_val);
8000c1e: 4b19 ldr r3, [pc, #100] @ (8000c84 <main+0x134>)
8000c20: 881b ldrh r3, [r3, #0]
8000c22: 4619 mov r1, r3
8000c24: 4818 ldr r0, [pc, #96] @ (8000c88 <main+0x138>)
8000c26: f000 fb41 bl 80012ac <MA_Update>
8000c2a: 4603 mov r3, r0
8000c2c: 461a mov r2, r3
8000c2e: 4b17 ldr r3, [pc, #92] @ (8000c8c <main+0x13c>)
8000c30: 801a strh r2, [r3, #0]
voltage_conversion_task_no_tx();
8000c32: f000 fc8d bl 8001550 <voltage_conversion_task_no_tx>
Control_Loop_Update(v_target, vout_val);
8000c36: 4b17 ldr r3, [pc, #92] @ (8000c94 <main+0x144>)
8000c38: 681b ldr r3, [r3, #0]
8000c3a: 4a17 ldr r2, [pc, #92] @ (8000c98 <main+0x148>)
8000c3c: 6812 ldr r2, [r2, #0]
8000c3e: 4611 mov r1, r2
8000c40: 4618 mov r0, r3
8000c42: f000 fab9 bl 80011b8 <Control_Loop_Update>
8000c46: e7c2 b.n 8000bce <main+0x7e>
}
else
{
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
8000c48: 4b0c ldr r3, [pc, #48] @ (8000c7c <main+0x12c>)
8000c4a: 681b ldr r3, [r3, #0]
8000c4c: 2200 movs r2, #0
8000c4e: 635a str r2, [r3, #52] @ 0x34
if (adc_task_flag == 0xff)
8000c50: e7bd b.n 8000bce <main+0x7e>
8000c52: bf00 nop
8000c54: 48000400 .word 0x48000400
8000c58: 20000044 .word 0x20000044
8000c5c: 200000b0 .word 0x200000b0
8000c60: 20000292 .word 0x20000292
8000c64: 20000293 .word 0x20000293
8000c68: 20000294 .word 0x20000294
8000c6c: 200002a0 .word 0x200002a0
8000c70: 2000024c .word 0x2000024c
8000c74: 200001b4 .word 0x200001b4
8000c78: 200002a8 .word 0x200002a8
8000c7c: 20000168 .word 0x20000168
8000c80: 200002b8 .word 0x200002b8
8000c84: 200002a4 .word 0x200002a4
8000c88: 200002bc .word 0x200002bc
8000c8c: 200002a6 .word 0x200002a6
8000c90: 200002b9 .word 0x200002b9
8000c94: 200002b4 .word 0x200002b4
8000c98: 200002b0 .word 0x200002b0
08000c9c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000c9c: b580 push {r7, lr}
8000c9e: b094 sub sp, #80 @ 0x50
8000ca0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000ca2: f107 0318 add.w r3, r7, #24
8000ca6: 2238 movs r2, #56 @ 0x38
8000ca8: 2100 movs r1, #0
8000caa: 4618 mov r0, r3
8000cac: f007 fcee bl 800868c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000cb0: 1d3b adds r3, r7, #4
8000cb2: 2200 movs r2, #0
8000cb4: 601a str r2, [r3, #0]
8000cb6: 605a str r2, [r3, #4]
8000cb8: 609a str r2, [r3, #8]
8000cba: 60da str r2, [r3, #12]
8000cbc: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
8000cbe: f44f 7000 mov.w r0, #512 @ 0x200
8000cc2: f003 f911 bl 8003ee8 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000cc6: 2302 movs r3, #2
8000cc8: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000cca: f44f 7380 mov.w r3, #256 @ 0x100
8000cce: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000cd0: 2340 movs r3, #64 @ 0x40
8000cd2: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000cd4: 2302 movs r3, #2
8000cd6: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000cd8: 2302 movs r3, #2
8000cda: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
8000cdc: 2301 movs r3, #1
8000cde: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLN = 16;
8000ce0: 2310 movs r3, #16
8000ce2: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000ce4: 2302 movs r3, #2
8000ce6: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8000ce8: 2302 movs r3, #2
8000cea: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8000cec: 2302 movs r3, #2
8000cee: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000cf0: f107 0318 add.w r3, r7, #24
8000cf4: 4618 mov r0, r3
8000cf6: f003 f9ab bl 8004050 <HAL_RCC_OscConfig>
8000cfa: 4603 mov r3, r0
8000cfc: 2b00 cmp r3, #0
8000cfe: d001 beq.n 8000d04 <SystemClock_Config+0x68>
{
Error_Handler();
8000d00: f000 fe54 bl 80019ac <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000d04: 230f movs r3, #15
8000d06: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000d08: 2303 movs r3, #3
8000d0a: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000d0c: 2300 movs r3, #0
8000d0e: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000d10: 2300 movs r3, #0
8000d12: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000d14: 2300 movs r3, #0
8000d16: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
8000d18: 1d3b adds r3, r7, #4
8000d1a: 2104 movs r1, #4
8000d1c: 4618 mov r0, r3
8000d1e: f003 fca9 bl 8004674 <HAL_RCC_ClockConfig>
8000d22: 4603 mov r3, r0
8000d24: 2b00 cmp r3, #0
8000d26: d001 beq.n 8000d2c <SystemClock_Config+0x90>
{
Error_Handler();
8000d28: f000 fe40 bl 80019ac <Error_Handler>
}
}
8000d2c: bf00 nop
8000d2e: 3750 adds r7, #80 @ 0x50
8000d30: 46bd mov sp, r7
8000d32: bd80 pop {r7, pc}
08000d34 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000d34: b580 push {r7, lr}
8000d36: b08c sub sp, #48 @ 0x30
8000d38: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
8000d3a: f107 0324 add.w r3, r7, #36 @ 0x24
8000d3e: 2200 movs r2, #0
8000d40: 601a str r2, [r3, #0]
8000d42: 605a str r2, [r3, #4]
8000d44: 609a str r2, [r3, #8]
ADC_ChannelConfTypeDef sConfig = {0};
8000d46: 1d3b adds r3, r7, #4
8000d48: 2220 movs r2, #32
8000d4a: 2100 movs r1, #0
8000d4c: 4618 mov r0, r3
8000d4e: f007 fc9d bl 800868c <memset>
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8000d52: 4b32 ldr r3, [pc, #200] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d54: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
8000d58: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
8000d5a: 4b30 ldr r3, [pc, #192] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d5c: f44f 1200 mov.w r2, #2097152 @ 0x200000
8000d60: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000d62: 4b2e ldr r3, [pc, #184] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d64: 2200 movs r2, #0
8000d66: 609a str r2, [r3, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000d68: 4b2c ldr r3, [pc, #176] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d6a: 2200 movs r2, #0
8000d6c: 60da str r2, [r3, #12]
hadc1.Init.GainCompensation = 0;
8000d6e: 4b2b ldr r3, [pc, #172] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d70: 2200 movs r2, #0
8000d72: 611a str r2, [r3, #16]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000d74: 4b29 ldr r3, [pc, #164] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d76: 2200 movs r2, #0
8000d78: 615a str r2, [r3, #20]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000d7a: 4b28 ldr r3, [pc, #160] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d7c: 2204 movs r2, #4
8000d7e: 619a str r2, [r3, #24]
hadc1.Init.LowPowerAutoWait = DISABLE;
8000d80: 4b26 ldr r3, [pc, #152] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d82: 2200 movs r2, #0
8000d84: 771a strb r2, [r3, #28]
hadc1.Init.ContinuousConvMode = DISABLE;
8000d86: 4b25 ldr r3, [pc, #148] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d88: 2200 movs r2, #0
8000d8a: 775a strb r2, [r3, #29]
hadc1.Init.NbrOfConversion = 1;
8000d8c: 4b23 ldr r3, [pc, #140] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d8e: 2201 movs r2, #1
8000d90: 621a str r2, [r3, #32]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000d92: 4b22 ldr r3, [pc, #136] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d94: 2200 movs r2, #0
8000d96: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000d9a: 4b20 ldr r3, [pc, #128] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000d9c: 2200 movs r2, #0
8000d9e: 62da str r2, [r3, #44] @ 0x2c
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000da0: 4b1e ldr r3, [pc, #120] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000da2: 2200 movs r2, #0
8000da4: 631a str r2, [r3, #48] @ 0x30
hadc1.Init.DMAContinuousRequests = DISABLE;
8000da6: 4b1d ldr r3, [pc, #116] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000da8: 2200 movs r2, #0
8000daa: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8000dae: 4b1b ldr r3, [pc, #108] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000db0: 2200 movs r2, #0
8000db2: 63da str r2, [r3, #60] @ 0x3c
hadc1.Init.OversamplingMode = DISABLE;
8000db4: 4b19 ldr r3, [pc, #100] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000db6: 2200 movs r2, #0
8000db8: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000dbc: 4817 ldr r0, [pc, #92] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000dbe: f001 fae5 bl 800238c <HAL_ADC_Init>
8000dc2: 4603 mov r3, r0
8000dc4: 2b00 cmp r3, #0
8000dc6: d001 beq.n 8000dcc <MX_ADC1_Init+0x98>
{
Error_Handler();
8000dc8: f000 fdf0 bl 80019ac <Error_Handler>
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
8000dcc: 2300 movs r3, #0
8000dce: 627b str r3, [r7, #36] @ 0x24
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
8000dd0: f107 0324 add.w r3, r7, #36 @ 0x24
8000dd4: 4619 mov r1, r3
8000dd6: 4811 ldr r0, [pc, #68] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000dd8: f002 fc78 bl 80036cc <HAL_ADCEx_MultiModeConfigChannel>
8000ddc: 4603 mov r3, r0
8000dde: 2b00 cmp r3, #0
8000de0: d001 beq.n 8000de6 <MX_ADC1_Init+0xb2>
{
Error_Handler();
8000de2: f000 fde3 bl 80019ac <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_VREFINT;
8000de6: 4b0e ldr r3, [pc, #56] @ (8000e20 <MX_ADC1_Init+0xec>)
8000de8: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000dea: 2306 movs r3, #6
8000dec: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
8000dee: 2307 movs r3, #7
8000df0: 60fb str r3, [r7, #12]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000df2: 237f movs r3, #127 @ 0x7f
8000df4: 613b str r3, [r7, #16]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000df6: 2304 movs r3, #4
8000df8: 617b str r3, [r7, #20]
sConfig.Offset = 0;
8000dfa: 2300 movs r3, #0
8000dfc: 61bb str r3, [r7, #24]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000dfe: 1d3b adds r3, r7, #4
8000e00: 4619 mov r1, r3
8000e02: 4806 ldr r0, [pc, #24] @ (8000e1c <MX_ADC1_Init+0xe8>)
8000e04: f001 fe1c bl 8002a40 <HAL_ADC_ConfigChannel>
8000e08: 4603 mov r3, r0
8000e0a: 2b00 cmp r3, #0
8000e0c: d001 beq.n 8000e12 <MX_ADC1_Init+0xde>
{
Error_Handler();
8000e0e: f000 fdcd bl 80019ac <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000e12: bf00 nop
8000e14: 3730 adds r7, #48 @ 0x30
8000e16: 46bd mov sp, r7
8000e18: bd80 pop {r7, pc}
8000e1a: bf00 nop
8000e1c: 20000044 .word 0x20000044
8000e20: cb840000 .word 0xcb840000
08000e24 <MX_ADC2_Init>:
* @brief ADC2 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC2_Init(void)
{
8000e24: b580 push {r7, lr}
8000e26: b088 sub sp, #32
8000e28: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000e2a: 463b mov r3, r7
8000e2c: 2220 movs r2, #32
8000e2e: 2100 movs r1, #0
8000e30: 4618 mov r0, r3
8000e32: f007 fc2b bl 800868c <memset>
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
8000e36: 4b32 ldr r3, [pc, #200] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e38: 4a32 ldr r2, [pc, #200] @ (8000f04 <MX_ADC2_Init+0xe0>)
8000e3a: 601a str r2, [r3, #0]
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
8000e3c: 4b30 ldr r3, [pc, #192] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e3e: f44f 1200 mov.w r2, #2097152 @ 0x200000
8000e42: 605a str r2, [r3, #4]
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
8000e44: 4b2e ldr r3, [pc, #184] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e46: 2200 movs r2, #0
8000e48: 609a str r2, [r3, #8]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000e4a: 4b2d ldr r3, [pc, #180] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e4c: 2200 movs r2, #0
8000e4e: 60da str r2, [r3, #12]
hadc2.Init.GainCompensation = 0;
8000e50: 4b2b ldr r3, [pc, #172] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e52: 2200 movs r2, #0
8000e54: 611a str r2, [r3, #16]
hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
8000e56: 4b2a ldr r3, [pc, #168] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e58: 2201 movs r2, #1
8000e5a: 615a str r2, [r3, #20]
hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000e5c: 4b28 ldr r3, [pc, #160] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e5e: 2204 movs r2, #4
8000e60: 619a str r2, [r3, #24]
hadc2.Init.LowPowerAutoWait = DISABLE;
8000e62: 4b27 ldr r3, [pc, #156] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e64: 2200 movs r2, #0
8000e66: 771a strb r2, [r3, #28]
hadc2.Init.ContinuousConvMode = DISABLE;
8000e68: 4b25 ldr r3, [pc, #148] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e6a: 2200 movs r2, #0
8000e6c: 775a strb r2, [r3, #29]
hadc2.Init.NbrOfConversion = 2;
8000e6e: 4b24 ldr r3, [pc, #144] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e70: 2202 movs r2, #2
8000e72: 621a str r2, [r3, #32]
hadc2.Init.DiscontinuousConvMode = DISABLE;
8000e74: 4b22 ldr r3, [pc, #136] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e76: 2200 movs r2, #0
8000e78: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000e7c: 4b20 ldr r3, [pc, #128] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e7e: 2200 movs r2, #0
8000e80: 62da str r2, [r3, #44] @ 0x2c
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000e82: 4b1f ldr r3, [pc, #124] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e84: 2200 movs r2, #0
8000e86: 631a str r2, [r3, #48] @ 0x30
hadc2.Init.DMAContinuousRequests = DISABLE;
8000e88: 4b1d ldr r3, [pc, #116] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e8a: 2200 movs r2, #0
8000e8c: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8000e90: 4b1b ldr r3, [pc, #108] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e92: 2200 movs r2, #0
8000e94: 63da str r2, [r3, #60] @ 0x3c
hadc2.Init.OversamplingMode = DISABLE;
8000e96: 4b1a ldr r3, [pc, #104] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000e98: 2200 movs r2, #0
8000e9a: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8000e9e: 4818 ldr r0, [pc, #96] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000ea0: f001 fa74 bl 800238c <HAL_ADC_Init>
8000ea4: 4603 mov r3, r0
8000ea6: 2b00 cmp r3, #0
8000ea8: d001 beq.n 8000eae <MX_ADC2_Init+0x8a>
{
Error_Handler();
8000eaa: f000 fd7f bl 80019ac <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
8000eae: 4b16 ldr r3, [pc, #88] @ (8000f08 <MX_ADC2_Init+0xe4>)
8000eb0: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000eb2: 2306 movs r3, #6
8000eb4: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
8000eb6: 2307 movs r3, #7
8000eb8: 60bb str r3, [r7, #8]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000eba: 237f movs r3, #127 @ 0x7f
8000ebc: 60fb str r3, [r7, #12]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000ebe: 2304 movs r3, #4
8000ec0: 613b str r3, [r7, #16]
sConfig.Offset = 0;
8000ec2: 2300 movs r3, #0
8000ec4: 617b str r3, [r7, #20]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000ec6: 463b mov r3, r7
8000ec8: 4619 mov r1, r3
8000eca: 480d ldr r0, [pc, #52] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000ecc: f001 fdb8 bl 8002a40 <HAL_ADC_ConfigChannel>
8000ed0: 4603 mov r3, r0
8000ed2: 2b00 cmp r3, #0
8000ed4: d001 beq.n 8000eda <MX_ADC2_Init+0xb6>
{
Error_Handler();
8000ed6: f000 fd69 bl 80019ac <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
8000eda: 4b0c ldr r3, [pc, #48] @ (8000f0c <MX_ADC2_Init+0xe8>)
8000edc: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_2;
8000ede: 230c movs r3, #12
8000ee0: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000ee2: 463b mov r3, r7
8000ee4: 4619 mov r1, r3
8000ee6: 4806 ldr r0, [pc, #24] @ (8000f00 <MX_ADC2_Init+0xdc>)
8000ee8: f001 fdaa bl 8002a40 <HAL_ADC_ConfigChannel>
8000eec: 4603 mov r3, r0
8000eee: 2b00 cmp r3, #0
8000ef0: d001 beq.n 8000ef6 <MX_ADC2_Init+0xd2>
{
Error_Handler();
8000ef2: f000 fd5b bl 80019ac <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
8000ef6: bf00 nop
8000ef8: 3720 adds r7, #32
8000efa: 46bd mov sp, r7
8000efc: bd80 pop {r7, pc}
8000efe: bf00 nop
8000f00: 200000b0 .word 0x200000b0
8000f04: 50000100 .word 0x50000100
8000f08: 0c900008 .word 0x0c900008
8000f0c: 10c00010 .word 0x10c00010
08000f10 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8000f10: b580 push {r7, lr}
8000f12: b088 sub sp, #32
8000f14: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000f16: f107 0310 add.w r3, r7, #16
8000f1a: 2200 movs r2, #0
8000f1c: 601a str r2, [r3, #0]
8000f1e: 605a str r2, [r3, #4]
8000f20: 609a str r2, [r3, #8]
8000f22: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000f24: 1d3b adds r3, r7, #4
8000f26: 2200 movs r2, #0
8000f28: 601a str r2, [r3, #0]
8000f2a: 605a str r2, [r3, #4]
8000f2c: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000f2e: 4b1d ldr r3, [pc, #116] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f30: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8000f34: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
8000f36: 4b1b ldr r3, [pc, #108] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f38: 2200 movs r2, #0
8000f3a: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000f3c: 4b19 ldr r3, [pc, #100] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f3e: 2200 movs r2, #0
8000f40: 609a str r2, [r3, #8]
htim2.Init.Period = 128999;
8000f42: 4b18 ldr r3, [pc, #96] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f44: 4a18 ldr r2, [pc, #96] @ (8000fa8 <MX_TIM2_Init+0x98>)
8000f46: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000f48: 4b16 ldr r3, [pc, #88] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f4a: 2200 movs r2, #0
8000f4c: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000f4e: 4b15 ldr r3, [pc, #84] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f50: 2200 movs r2, #0
8000f52: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8000f54: 4813 ldr r0, [pc, #76] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f56: f003 ff99 bl 8004e8c <HAL_TIM_Base_Init>
8000f5a: 4603 mov r3, r0
8000f5c: 2b00 cmp r3, #0
8000f5e: d001 beq.n 8000f64 <MX_TIM2_Init+0x54>
{
Error_Handler();
8000f60: f000 fd24 bl 80019ac <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000f64: f44f 5380 mov.w r3, #4096 @ 0x1000
8000f68: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8000f6a: f107 0310 add.w r3, r7, #16
8000f6e: 4619 mov r1, r3
8000f70: 480c ldr r0, [pc, #48] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f72: f004 fba7 bl 80056c4 <HAL_TIM_ConfigClockSource>
8000f76: 4603 mov r3, r0
8000f78: 2b00 cmp r3, #0
8000f7a: d001 beq.n 8000f80 <MX_TIM2_Init+0x70>
{
Error_Handler();
8000f7c: f000 fd16 bl 80019ac <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000f80: 2300 movs r3, #0
8000f82: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000f84: 2300 movs r3, #0
8000f86: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000f88: 1d3b adds r3, r7, #4
8000f8a: 4619 mov r1, r3
8000f8c: 4805 ldr r0, [pc, #20] @ (8000fa4 <MX_TIM2_Init+0x94>)
8000f8e: f005 f919 bl 80061c4 <HAL_TIMEx_MasterConfigSynchronization>
8000f92: 4603 mov r3, r0
8000f94: 2b00 cmp r3, #0
8000f96: d001 beq.n 8000f9c <MX_TIM2_Init+0x8c>
{
Error_Handler();
8000f98: f000 fd08 bl 80019ac <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
8000f9c: bf00 nop
8000f9e: 3720 adds r7, #32
8000fa0: 46bd mov sp, r7
8000fa2: bd80 pop {r7, pc}
8000fa4: 2000011c .word 0x2000011c
8000fa8: 0001f7e7 .word 0x0001f7e7
08000fac <MX_TIM16_Init>:
* @brief TIM16 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM16_Init(void)
{
8000fac: b580 push {r7, lr}
8000fae: b094 sub sp, #80 @ 0x50
8000fb0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM16_Init 0 */
/* USER CODE END TIM16_Init 0 */
TIM_OC_InitTypeDef sConfigOC = {0};
8000fb2: f107 0334 add.w r3, r7, #52 @ 0x34
8000fb6: 2200 movs r2, #0
8000fb8: 601a str r2, [r3, #0]
8000fba: 605a str r2, [r3, #4]
8000fbc: 609a str r2, [r3, #8]
8000fbe: 60da str r2, [r3, #12]
8000fc0: 611a str r2, [r3, #16]
8000fc2: 615a str r2, [r3, #20]
8000fc4: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8000fc6: 463b mov r3, r7
8000fc8: 2234 movs r2, #52 @ 0x34
8000fca: 2100 movs r1, #0
8000fcc: 4618 mov r0, r3
8000fce: f007 fb5d bl 800868c <memset>
/* USER CODE BEGIN TIM16_Init 1 */
/* USER CODE END TIM16_Init 1 */
htim16.Instance = TIM16;
8000fd2: 4b31 ldr r3, [pc, #196] @ (8001098 <MX_TIM16_Init+0xec>)
8000fd4: 4a31 ldr r2, [pc, #196] @ (800109c <MX_TIM16_Init+0xf0>)
8000fd6: 601a str r2, [r3, #0]
htim16.Init.Prescaler = 1;
8000fd8: 4b2f ldr r3, [pc, #188] @ (8001098 <MX_TIM16_Init+0xec>)
8000fda: 2201 movs r2, #1
8000fdc: 605a str r2, [r3, #4]
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
8000fde: 4b2e ldr r3, [pc, #184] @ (8001098 <MX_TIM16_Init+0xec>)
8000fe0: 2200 movs r2, #0
8000fe2: 609a str r2, [r3, #8]
htim16.Init.Period = 63999;
8000fe4: 4b2c ldr r3, [pc, #176] @ (8001098 <MX_TIM16_Init+0xec>)
8000fe6: f64f 12ff movw r2, #63999 @ 0xf9ff
8000fea: 60da str r2, [r3, #12]
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000fec: 4b2a ldr r3, [pc, #168] @ (8001098 <MX_TIM16_Init+0xec>)
8000fee: 2200 movs r2, #0
8000ff0: 611a str r2, [r3, #16]
htim16.Init.RepetitionCounter = 0;
8000ff2: 4b29 ldr r3, [pc, #164] @ (8001098 <MX_TIM16_Init+0xec>)
8000ff4: 2200 movs r2, #0
8000ff6: 615a str r2, [r3, #20]
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000ff8: 4b27 ldr r3, [pc, #156] @ (8001098 <MX_TIM16_Init+0xec>)
8000ffa: 2200 movs r2, #0
8000ffc: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
8000ffe: 4826 ldr r0, [pc, #152] @ (8001098 <MX_TIM16_Init+0xec>)
8001000: f003 ff44 bl 8004e8c <HAL_TIM_Base_Init>
8001004: 4603 mov r3, r0
8001006: 2b00 cmp r3, #0
8001008: d001 beq.n 800100e <MX_TIM16_Init+0x62>
{
Error_Handler();
800100a: f000 fccf bl 80019ac <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim16) != HAL_OK)
800100e: 4822 ldr r0, [pc, #136] @ (8001098 <MX_TIM16_Init+0xec>)
8001010: f003 ff93 bl 8004f3a <HAL_TIM_PWM_Init>
8001014: 4603 mov r3, r0
8001016: 2b00 cmp r3, #0
8001018: d001 beq.n 800101e <MX_TIM16_Init+0x72>
{
Error_Handler();
800101a: f000 fcc7 bl 80019ac <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800101e: 2360 movs r3, #96 @ 0x60
8001020: 637b str r3, [r7, #52] @ 0x34
sConfigOC.Pulse = 0;
8001022: 2300 movs r3, #0
8001024: 63bb str r3, [r7, #56] @ 0x38
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001026: 2300 movs r3, #0
8001028: 63fb str r3, [r7, #60] @ 0x3c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
800102a: 2300 movs r3, #0
800102c: 643b str r3, [r7, #64] @ 0x40
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
800102e: 2300 movs r3, #0
8001030: 647b str r3, [r7, #68] @ 0x44
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
8001032: 2300 movs r3, #0
8001034: 64bb str r3, [r7, #72] @ 0x48
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
8001036: 2300 movs r3, #0
8001038: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_TIM_PWM_ConfigChannel(&htim16, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800103a: f107 0334 add.w r3, r7, #52 @ 0x34
800103e: 2200 movs r2, #0
8001040: 4619 mov r1, r3
8001042: 4815 ldr r0, [pc, #84] @ (8001098 <MX_TIM16_Init+0xec>)
8001044: f004 fa2a bl 800549c <HAL_TIM_PWM_ConfigChannel>
8001048: 4603 mov r3, r0
800104a: 2b00 cmp r3, #0
800104c: d001 beq.n 8001052 <MX_TIM16_Init+0xa6>
{
Error_Handler();
800104e: f000 fcad bl 80019ac <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
8001052: 2300 movs r3, #0
8001054: 603b str r3, [r7, #0]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8001056: 2300 movs r3, #0
8001058: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
800105a: 2300 movs r3, #0
800105c: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.DeadTime = 0;
800105e: 2300 movs r3, #0
8001060: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8001062: 2300 movs r3, #0
8001064: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8001066: f44f 5300 mov.w r3, #8192 @ 0x2000
800106a: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakFilter = 0;
800106c: 2300 movs r3, #0
800106e: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8001070: 2300 movs r3, #0
8001072: 633b str r3, [r7, #48] @ 0x30
if (HAL_TIMEx_ConfigBreakDeadTime(&htim16, &sBreakDeadTimeConfig) != HAL_OK)
8001074: 463b mov r3, r7
8001076: 4619 mov r1, r3
8001078: 4807 ldr r0, [pc, #28] @ (8001098 <MX_TIM16_Init+0xec>)
800107a: f005 f925 bl 80062c8 <HAL_TIMEx_ConfigBreakDeadTime>
800107e: 4603 mov r3, r0
8001080: 2b00 cmp r3, #0
8001082: d001 beq.n 8001088 <MX_TIM16_Init+0xdc>
{
Error_Handler();
8001084: f000 fc92 bl 80019ac <Error_Handler>
}
/* USER CODE BEGIN TIM16_Init 2 */
/* USER CODE END TIM16_Init 2 */
HAL_TIM_MspPostInit(&htim16);
8001088: 4803 ldr r0, [pc, #12] @ (8001098 <MX_TIM16_Init+0xec>)
800108a: f000 fd7d bl 8001b88 <HAL_TIM_MspPostInit>
}
800108e: bf00 nop
8001090: 3750 adds r7, #80 @ 0x50
8001092: 46bd mov sp, r7
8001094: bd80 pop {r7, pc}
8001096: bf00 nop
8001098: 20000168 .word 0x20000168
800109c: 40014400 .word 0x40014400
080010a0 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
80010a0: b580 push {r7, lr}
80010a2: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
80010a4: 4b22 ldr r3, [pc, #136] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010a6: 4a23 ldr r2, [pc, #140] @ (8001134 <MX_USART2_UART_Init+0x94>)
80010a8: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
80010aa: 4b21 ldr r3, [pc, #132] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010ac: f44f 32e1 mov.w r2, #115200 @ 0x1c200
80010b0: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
80010b2: 4b1f ldr r3, [pc, #124] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010b4: 2200 movs r2, #0
80010b6: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
80010b8: 4b1d ldr r3, [pc, #116] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010ba: 2200 movs r2, #0
80010bc: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
80010be: 4b1c ldr r3, [pc, #112] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010c0: 2200 movs r2, #0
80010c2: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
80010c4: 4b1a ldr r3, [pc, #104] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010c6: 220c movs r2, #12
80010c8: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80010ca: 4b19 ldr r3, [pc, #100] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010cc: 2200 movs r2, #0
80010ce: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
80010d0: 4b17 ldr r3, [pc, #92] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010d2: 2200 movs r2, #0
80010d4: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80010d6: 4b16 ldr r3, [pc, #88] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010d8: 2200 movs r2, #0
80010da: 621a str r2, [r3, #32]
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
80010dc: 4b14 ldr r3, [pc, #80] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010de: 2200 movs r2, #0
80010e0: 625a str r2, [r3, #36] @ 0x24
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80010e2: 4b13 ldr r3, [pc, #76] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010e4: 2200 movs r2, #0
80010e6: 629a str r2, [r3, #40] @ 0x28
if (HAL_UART_Init(&huart2) != HAL_OK)
80010e8: 4811 ldr r0, [pc, #68] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010ea: f005 f9bf bl 800646c <HAL_UART_Init>
80010ee: 4603 mov r3, r0
80010f0: 2b00 cmp r3, #0
80010f2: d001 beq.n 80010f8 <MX_USART2_UART_Init+0x58>
{
Error_Handler();
80010f4: f000 fc5a bl 80019ac <Error_Handler>
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
80010f8: 2100 movs r1, #0
80010fa: 480d ldr r0, [pc, #52] @ (8001130 <MX_USART2_UART_Init+0x90>)
80010fc: f007 f9fb bl 80084f6 <HAL_UARTEx_SetTxFifoThreshold>
8001100: 4603 mov r3, r0
8001102: 2b00 cmp r3, #0
8001104: d001 beq.n 800110a <MX_USART2_UART_Init+0x6a>
{
Error_Handler();
8001106: f000 fc51 bl 80019ac <Error_Handler>
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
800110a: 2100 movs r1, #0
800110c: 4808 ldr r0, [pc, #32] @ (8001130 <MX_USART2_UART_Init+0x90>)
800110e: f007 fa30 bl 8008572 <HAL_UARTEx_SetRxFifoThreshold>
8001112: 4603 mov r3, r0
8001114: 2b00 cmp r3, #0
8001116: d001 beq.n 800111c <MX_USART2_UART_Init+0x7c>
{
Error_Handler();
8001118: f000 fc48 bl 80019ac <Error_Handler>
}
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
800111c: 4804 ldr r0, [pc, #16] @ (8001130 <MX_USART2_UART_Init+0x90>)
800111e: f007 f9b1 bl 8008484 <HAL_UARTEx_DisableFifoMode>
8001122: 4603 mov r3, r0
8001124: 2b00 cmp r3, #0
8001126: d001 beq.n 800112c <MX_USART2_UART_Init+0x8c>
{
Error_Handler();
8001128: f000 fc40 bl 80019ac <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
800112c: bf00 nop
800112e: bd80 pop {r7, pc}
8001130: 200001b4 .word 0x200001b4
8001134: 40004400 .word 0x40004400
08001138 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001138: b580 push {r7, lr}
800113a: b088 sub sp, #32
800113c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800113e: f107 030c add.w r3, r7, #12
8001142: 2200 movs r2, #0
8001144: 601a str r2, [r3, #0]
8001146: 605a str r2, [r3, #4]
8001148: 609a str r2, [r3, #8]
800114a: 60da str r2, [r3, #12]
800114c: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
800114e: 4b18 ldr r3, [pc, #96] @ (80011b0 <MX_GPIO_Init+0x78>)
8001150: 6cdb ldr r3, [r3, #76] @ 0x4c
8001152: 4a17 ldr r2, [pc, #92] @ (80011b0 <MX_GPIO_Init+0x78>)
8001154: f043 0301 orr.w r3, r3, #1
8001158: 64d3 str r3, [r2, #76] @ 0x4c
800115a: 4b15 ldr r3, [pc, #84] @ (80011b0 <MX_GPIO_Init+0x78>)
800115c: 6cdb ldr r3, [r3, #76] @ 0x4c
800115e: f003 0301 and.w r3, r3, #1
8001162: 60bb str r3, [r7, #8]
8001164: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001166: 4b12 ldr r3, [pc, #72] @ (80011b0 <MX_GPIO_Init+0x78>)
8001168: 6cdb ldr r3, [r3, #76] @ 0x4c
800116a: 4a11 ldr r2, [pc, #68] @ (80011b0 <MX_GPIO_Init+0x78>)
800116c: f043 0302 orr.w r3, r3, #2
8001170: 64d3 str r3, [r2, #76] @ 0x4c
8001172: 4b0f ldr r3, [pc, #60] @ (80011b0 <MX_GPIO_Init+0x78>)
8001174: 6cdb ldr r3, [r3, #76] @ 0x4c
8001176: f003 0302 and.w r3, r3, #2
800117a: 607b str r3, [r7, #4]
800117c: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
800117e: 2200 movs r2, #0
8001180: f44f 7180 mov.w r1, #256 @ 0x100
8001184: 480b ldr r0, [pc, #44] @ (80011b4 <MX_GPIO_Init+0x7c>)
8001186: f002 fe97 bl 8003eb8 <HAL_GPIO_WritePin>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
800118a: f44f 7380 mov.w r3, #256 @ 0x100
800118e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001190: 2301 movs r3, #1
8001192: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001194: 2300 movs r3, #0
8001196: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001198: 2300 movs r3, #0
800119a: 61bb str r3, [r7, #24]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
800119c: f107 030c add.w r3, r7, #12
80011a0: 4619 mov r1, r3
80011a2: 4804 ldr r0, [pc, #16] @ (80011b4 <MX_GPIO_Init+0x7c>)
80011a4: f002 fd06 bl 8003bb4 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80011a8: bf00 nop
80011aa: 3720 adds r7, #32
80011ac: 46bd mov sp, r7
80011ae: bd80 pop {r7, pc}
80011b0: 40021000 .word 0x40021000
80011b4: 48000400 .word 0x48000400
080011b8 <Control_Loop_Update>:
/* USER CODE BEGIN 4 */
void Control_Loop_Update(uint32_t setpoint_mv, uint32_t measured_mv)
{
80011b8: b480 push {r7}
80011ba: b085 sub sp, #20
80011bc: af00 add r7, sp, #0
80011be: 6078 str r0, [r7, #4]
80011c0: 6039 str r1, [r7, #0]
/* Positive error = need more power */
/* Negative error = need less power */
int32_t error = (int32_t)setpoint_mv - (int32_t)measured_mv;
80011c2: 687a ldr r2, [r7, #4]
80011c4: 683b ldr r3, [r7, #0]
80011c6: 1ad3 subs r3, r2, r3
80011c8: 60fb str r3, [r7, #12]
if (abs(error) < DEADBAND_MV)
80011ca: 68fb ldr r3, [r7, #12]
80011cc: f113 0f18 cmn.w r3, #24
80011d0: db04 blt.n 80011dc <Control_Loop_Update+0x24>
80011d2: 68fb ldr r3, [r7, #12]
80011d4: 2b18 cmp r3, #24
80011d6: dc01 bgt.n 80011dc <Control_Loop_Update+0x24>
{
error = 0; /* Don't change PWM if we are "close enough" */
80011d8: 2300 movs r3, #0
80011da: 60fb str r3, [r7, #12]
}
/* Proportional Calculation */
float p_term = KP * (float)error;
80011dc: 68fb ldr r3, [r7, #12]
80011de: ee07 3a90 vmov s15, r3
80011e2: eef8 7ae7 vcvt.f32.s32 s15, s15
80011e6: ed9f 7a1c vldr s14, [pc, #112] @ 8001258 <Control_Loop_Update+0xa0>
80011ea: ee67 7a87 vmul.f32 s15, s15, s14
80011ee: edc7 7a02 vstr s15, [r7, #8]
/* Adjust the Duty Cycle */
static float current_duty = 32000.0f; // Start at 50%
current_duty += p_term;
80011f2: 4b1a ldr r3, [pc, #104] @ (800125c <Control_Loop_Update+0xa4>)
80011f4: ed93 7a00 vldr s14, [r3]
80011f8: edd7 7a02 vldr s15, [r7, #8]
80011fc: ee77 7a27 vadd.f32 s15, s14, s15
8001200: 4b16 ldr r3, [pc, #88] @ (800125c <Control_Loop_Update+0xa4>)
8001202: edc3 7a00 vstr s15, [r3]
/* Anti-Windup / Saturation (Crucial for bidirectional) */
/* Prevents the PWM from trying to go to -50% or 200% */
if (current_duty > MAX_PWM) current_duty = (float)MAX_PWM;
8001206: 4b15 ldr r3, [pc, #84] @ (800125c <Control_Loop_Update+0xa4>)
8001208: edd3 7a00 vldr s15, [r3]
800120c: ed9f 7a14 vldr s14, [pc, #80] @ 8001260 <Control_Loop_Update+0xa8>
8001210: eef4 7ac7 vcmpe.f32 s15, s14
8001214: eef1 fa10 vmrs APSR_nzcv, fpscr
8001218: dd02 ble.n 8001220 <Control_Loop_Update+0x68>
800121a: 4b10 ldr r3, [pc, #64] @ (800125c <Control_Loop_Update+0xa4>)
800121c: 4a11 ldr r2, [pc, #68] @ (8001264 <Control_Loop_Update+0xac>)
800121e: 601a str r2, [r3, #0]
if (current_duty < 0.0f) current_duty = 0.0f;
8001220: 4b0e ldr r3, [pc, #56] @ (800125c <Control_Loop_Update+0xa4>)
8001222: edd3 7a00 vldr s15, [r3]
8001226: eef5 7ac0 vcmpe.f32 s15, #0.0
800122a: eef1 fa10 vmrs APSR_nzcv, fpscr
800122e: d503 bpl.n 8001238 <Control_Loop_Update+0x80>
8001230: 4b0a ldr r3, [pc, #40] @ (800125c <Control_Loop_Update+0xa4>)
8001232: f04f 0200 mov.w r2, #0
8001236: 601a str r2, [r3, #0]
/* Update PWM */
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, (uint32_t)current_duty);
8001238: 4b08 ldr r3, [pc, #32] @ (800125c <Control_Loop_Update+0xa4>)
800123a: edd3 7a00 vldr s15, [r3]
800123e: 4b0a ldr r3, [pc, #40] @ (8001268 <Control_Loop_Update+0xb0>)
8001240: 681b ldr r3, [r3, #0]
8001242: eefc 7ae7 vcvt.u32.f32 s15, s15
8001246: ee17 2a90 vmov r2, s15
800124a: 635a str r2, [r3, #52] @ 0x34
}
800124c: bf00 nop
800124e: 3714 adds r7, #20
8001250: 46bd mov sp, r7
8001252: f85d 7b04 ldr.w r7, [sp], #4
8001256: 4770 bx lr
8001258: 3e19999a .word 0x3e19999a
800125c: 20000018 .word 0x20000018
8001260: 4779ff00 .word 0x4779ff00
8001264: 4779ff00 .word 0x4779ff00
8001268: 20000168 .word 0x20000168
0800126c <MA_Init>:
void MA_Init(MovingAverageFilter *filter)
{
800126c: b480 push {r7}
800126e: b085 sub sp, #20
8001270: af00 add r7, sp, #0
8001272: 6078 str r0, [r7, #4]
for (int i = 0; i < FILTER_SIZE; i++)
8001274: 2300 movs r3, #0
8001276: 60fb str r3, [r7, #12]
8001278: e007 b.n 800128a <MA_Init+0x1e>
{
filter->buffer[i] = 0;
800127a: 687b ldr r3, [r7, #4]
800127c: 68fa ldr r2, [r7, #12]
800127e: 2100 movs r1, #0
8001280: f823 1012 strh.w r1, [r3, r2, lsl #1]
for (int i = 0; i < FILTER_SIZE; i++)
8001284: 68fb ldr r3, [r7, #12]
8001286: 3301 adds r3, #1
8001288: 60fb str r3, [r7, #12]
800128a: 68fb ldr r3, [r7, #12]
800128c: 2b7f cmp r3, #127 @ 0x7f
800128e: ddf4 ble.n 800127a <MA_Init+0xe>
}
filter->sum = 0;
8001290: 687b ldr r3, [r7, #4]
8001292: 2200 movs r2, #0
8001294: f8c3 2100 str.w r2, [r3, #256] @ 0x100
filter->index = 0;
8001298: 687b ldr r3, [r7, #4]
800129a: 2200 movs r2, #0
800129c: f883 2104 strb.w r2, [r3, #260] @ 0x104
}
80012a0: bf00 nop
80012a2: 3714 adds r7, #20
80012a4: 46bd mov sp, r7
80012a6: f85d 7b04 ldr.w r7, [sp], #4
80012aa: 4770 bx lr
080012ac <MA_Update>:
uint16_t MA_Update(MovingAverageFilter *filter, uint16_t new_sample)
{
80012ac: b480 push {r7}
80012ae: b083 sub sp, #12
80012b0: af00 add r7, sp, #0
80012b2: 6078 str r0, [r7, #4]
80012b4: 460b mov r3, r1
80012b6: 807b strh r3, [r7, #2]
/* Subtract the oldest value from the running sum */
filter->sum -= filter->buffer[filter->index];
80012b8: 687b ldr r3, [r7, #4]
80012ba: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100
80012be: 687a ldr r2, [r7, #4]
80012c0: f892 2104 ldrb.w r2, [r2, #260] @ 0x104
80012c4: 4611 mov r1, r2
80012c6: 687a ldr r2, [r7, #4]
80012c8: f832 2011 ldrh.w r2, [r2, r1, lsl #1]
80012cc: 1a9a subs r2, r3, r2
80012ce: 687b ldr r3, [r7, #4]
80012d0: f8c3 2100 str.w r2, [r3, #256] @ 0x100
/* Add the new value to the running sum */
filter->sum += new_sample;
80012d4: 687b ldr r3, [r7, #4]
80012d6: f8d3 2100 ldr.w r2, [r3, #256] @ 0x100
80012da: 887b ldrh r3, [r7, #2]
80012dc: 441a add r2, r3
80012de: 687b ldr r3, [r7, #4]
80012e0: f8c3 2100 str.w r2, [r3, #256] @ 0x100
/* Store the new value in the buffer, overwriting the oldest one */
filter->buffer[filter->index] = new_sample;
80012e4: 687b ldr r3, [r7, #4]
80012e6: f893 3104 ldrb.w r3, [r3, #260] @ 0x104
80012ea: 4619 mov r1, r3
80012ec: 687b ldr r3, [r7, #4]
80012ee: 887a ldrh r2, [r7, #2]
80012f0: f823 2011 strh.w r2, [r3, r1, lsl #1]
/* Move the index to the next position (circular buffer wrap-around) */
filter->index++;
80012f4: 687b ldr r3, [r7, #4]
80012f6: f893 3104 ldrb.w r3, [r3, #260] @ 0x104
80012fa: 3301 adds r3, #1
80012fc: b2da uxtb r2, r3
80012fe: 687b ldr r3, [r7, #4]
8001300: f883 2104 strb.w r2, [r3, #260] @ 0x104
filter->index &= (FILTER_SIZE - 1); /* Equivalent to: if (filter->index >= FILTER_SIZE) filter->index = 0; */
8001304: 687b ldr r3, [r7, #4]
8001306: f893 3104 ldrb.w r3, [r3, #260] @ 0x104
800130a: f003 037f and.w r3, r3, #127 @ 0x7f
800130e: b2da uxtb r2, r3
8001310: 687b ldr r3, [r7, #4]
8001312: f883 2104 strb.w r2, [r3, #260] @ 0x104
/* Calculate the average using bit-shifting (faster than division by power of 2) */
/* For FILTER_SIZE = 16, this is a right shift by 4 bits (sum / 16) */
/* If used 32, it would be sum >> 5 */
return (uint16_t)(filter->sum >> 7);
8001316: 687b ldr r3, [r7, #4]
8001318: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100
800131c: 09db lsrs r3, r3, #7
800131e: b29b uxth r3, r3
}
8001320: 4618 mov r0, r3
8001322: 370c adds r7, #12
8001324: 46bd mov sp, r7
8001326: f85d 7b04 ldr.w r7, [sp], #4
800132a: 4770 bx lr
0800132c <get_actual_vdda>:
uint32_t get_actual_vdda(ADC_HandleTypeDef *hadc)
{
800132c: b580 push {r7, lr}
800132e: b084 sub sp, #16
8001330: af00 add r7, sp, #0
8001332: 6078 str r0, [r7, #4]
uint32_t vrefint_raw = 0;
8001334: 2300 movs r3, #0
8001336: 60fb str r3, [r7, #12]
/* Perform ADC reading of the VREFINT channel */
HAL_ADC_Start(hadc);
8001338: 6878 ldr r0, [r7, #4]
800133a: f001 f9ab bl 8002694 <HAL_ADC_Start>
if (HAL_ADC_PollForConversion(hadc, 10) == HAL_OK) {
800133e: 210a movs r1, #10
8001340: 6878 ldr r0, [r7, #4]
8001342: f001 fa97 bl 8002874 <HAL_ADC_PollForConversion>
8001346: 4603 mov r3, r0
8001348: 2b00 cmp r3, #0
800134a: d103 bne.n 8001354 <get_actual_vdda+0x28>
vrefint_raw = HAL_ADC_GetValue(hadc);
800134c: 6878 ldr r0, [r7, #4]
800134e: f001 fb69 bl 8002a24 <HAL_ADC_GetValue>
8001352: 60f8 str r0, [r7, #12]
}
HAL_ADC_Stop(hadc);
8001354: 6878 ldr r0, [r7, #4]
8001356: f001 fa59 bl 800280c <HAL_ADC_Stop>
if (vrefint_raw == 0) return 0; /* Avoid division by zero */
800135a: 68fb ldr r3, [r7, #12]
800135c: 2b00 cmp r3, #0
800135e: d101 bne.n 8001364 <get_actual_vdda+0x38>
8001360: 2300 movs r3, #0
8001362: e00b b.n 800137c <get_actual_vdda+0x50>
/* Use the standard ST formula to calculate VDDA */
/* VDDA = VREFINT_CAL_VREF * VREFINT_CAL / VREFINT_DATA */
uint32_t vdda_mv = (VREFINT_CAL_VREF * (uint32_t)(*VREFINT_CAL_ADDR)) / vrefint_raw;
8001364: 4b07 ldr r3, [pc, #28] @ (8001384 <get_actual_vdda+0x58>)
8001366: 881b ldrh r3, [r3, #0]
8001368: 461a mov r2, r3
800136a: f640 33b8 movw r3, #3000 @ 0xbb8
800136e: fb03 f202 mul.w r2, r3, r2
8001372: 68fb ldr r3, [r7, #12]
8001374: fbb2 f3f3 udiv r3, r2, r3
8001378: 60bb str r3, [r7, #8]
return vdda_mv;
800137a: 68bb ldr r3, [r7, #8]
}
800137c: 4618 mov r0, r3
800137e: 3710 adds r7, #16
8001380: 46bd mov sp, r7
8001382: bd80 pop {r7, pc}
8001384: 1fff75aa .word 0x1fff75aa
08001388 <get_divider_input_mv>:
/* Calculate original input voltage from a 22k/2.2k divider in mV */
uint32_t get_divider_input_mv(uint32_t raw_adc_value, uint32_t vdda_mv)
{
8001388: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr}
800138c: b086 sub sp, #24
800138e: af00 add r7, sp, #0
8001390: 6078 str r0, [r7, #4]
8001392: 6039 str r1, [r7, #0]
/* Calculate the voltage at the ADC pin (Vout of the divider) */
/* Using 64-bit for intermediate to avoid overflow: (Raw * VDDA) / 4095 */
uint64_t vout_mv = ((uint64_t)raw_adc_value * vdda_mv) / 4095;
8001394: 6879 ldr r1, [r7, #4]
8001396: 2000 movs r0, #0
8001398: 4688 mov r8, r1
800139a: 4681 mov r9, r0
800139c: 6839 ldr r1, [r7, #0]
800139e: 2000 movs r0, #0
80013a0: 460a mov r2, r1
80013a2: 4603 mov r3, r0
80013a4: fb02 f009 mul.w r0, r2, r9
80013a8: fb08 f103 mul.w r1, r8, r3
80013ac: 4401 add r1, r0
80013ae: fba8 4502 umull r4, r5, r8, r2
80013b2: 194b adds r3, r1, r5
80013b4: 461d mov r5, r3
80013b6: f640 72ff movw r2, #4095 @ 0xfff
80013ba: f04f 0300 mov.w r3, #0
80013be: 4620 mov r0, r4
80013c0: 4629 mov r1, r5
80013c2: f7ff fa2f bl 8000824 <__aeabi_uldivmod>
80013c6: 4602 mov r2, r0
80013c8: 460b mov r3, r1
80013ca: e9c7 2304 strd r2, r3, [r7, #16]
/* Scale by the divider ratio: (22k + 2.2k) / 2.2k = 11 */
uint32_t vin_mv = (uint32_t)(vout_mv * 10.9);
80013ce: e9d7 0104 ldrd r0, r1, [r7, #16]
80013d2: f7ff f9d1 bl 8000778 <__aeabi_ul2d>
80013d6: a30a add r3, pc, #40 @ (adr r3, 8001400 <get_divider_input_mv+0x78>)
80013d8: e9d3 2300 ldrd r2, r3, [r3]
80013dc: f7fe ff1c bl 8000218 <__aeabi_dmul>
80013e0: 4602 mov r2, r0
80013e2: 460b mov r3, r1
80013e4: 4610 mov r0, r2
80013e6: 4619 mov r1, r3
80013e8: f7ff f9fc bl 80007e4 <__aeabi_d2uiz>
80013ec: 4603 mov r3, r0
80013ee: 60fb str r3, [r7, #12]
return vin_mv;
80013f0: 68fb ldr r3, [r7, #12]
}
80013f2: 4618 mov r0, r3
80013f4: 3718 adds r7, #24
80013f6: 46bd mov sp, r7
80013f8: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc}
80013fc: f3af 8000 nop.w
8001400: cccccccd .word 0xcccccccd
8001404: 4025cccc .word 0x4025cccc
08001408 <voltage_conversion_task>:
/* Voltage Conversion Task */
void voltage_conversion_task(void)
{
8001408: b580 push {r7, lr}
800140a: af00 add r7, sp, #0
/* Get Vin voltage */
vin_val = get_divider_input_mv(vin_adc_val, vdd_ref);
800140c: 4b46 ldr r3, [pc, #280] @ (8001528 <voltage_conversion_task+0x120>)
800140e: 881b ldrh r3, [r3, #0]
8001410: 461a mov r2, r3
8001412: 4b46 ldr r3, [pc, #280] @ (800152c <voltage_conversion_task+0x124>)
8001414: 681b ldr r3, [r3, #0]
8001416: 4619 mov r1, r3
8001418: 4610 mov r0, r2
800141a: f7ff ffb5 bl 8001388 <get_divider_input_mv>
800141e: 4603 mov r3, r0
8001420: 4a43 ldr r2, [pc, #268] @ (8001530 <voltage_conversion_task+0x128>)
8001422: 6013 str r3, [r2, #0]
/* Get Vout voltage */
vout_val = get_divider_input_mv(vout_adc_val_av, vdd_ref);
8001424: 4b43 ldr r3, [pc, #268] @ (8001534 <voltage_conversion_task+0x12c>)
8001426: 881b ldrh r3, [r3, #0]
8001428: 461a mov r2, r3
800142a: 4b40 ldr r3, [pc, #256] @ (800152c <voltage_conversion_task+0x124>)
800142c: 681b ldr r3, [r3, #0]
800142e: 4619 mov r1, r3
8001430: 4610 mov r0, r2
8001432: f7ff ffa9 bl 8001388 <get_divider_input_mv>
8001436: 4603 mov r3, r0
8001438: 4a3f ldr r2, [pc, #252] @ (8001538 <voltage_conversion_task+0x130>)
800143a: 6013 str r3, [r2, #0]
tx_len = 0x08;
800143c: 4b3f ldr r3, [pc, #252] @ (800153c <voltage_conversion_task+0x134>)
800143e: 2208 movs r2, #8
8001440: 701a strb r2, [r3, #0]
tx_buffer[0] = IN_SYNC_BYTE_1;
8001442: 4b3f ldr r3, [pc, #252] @ (8001540 <voltage_conversion_task+0x138>)
8001444: 2241 movs r2, #65 @ 0x41
8001446: 701a strb r2, [r3, #0]
tx_buffer[1] = IN_SYNC_BYTE_2;
8001448: 4b3d ldr r3, [pc, #244] @ (8001540 <voltage_conversion_task+0x138>)
800144a: 2252 movs r2, #82 @ 0x52
800144c: 705a strb r2, [r3, #1]
tx_buffer[2] = tx_len;
800144e: 4b3b ldr r3, [pc, #236] @ (800153c <voltage_conversion_task+0x134>)
8001450: 781a ldrb r2, [r3, #0]
8001452: 4b3b ldr r3, [pc, #236] @ (8001540 <voltage_conversion_task+0x138>)
8001454: 709a strb r2, [r3, #2]
tx_buffer[3] = (uint8_t)((vin_val >> 24) & 0xFF);
8001456: 4b36 ldr r3, [pc, #216] @ (8001530 <voltage_conversion_task+0x128>)
8001458: 681b ldr r3, [r3, #0]
800145a: 0e1b lsrs r3, r3, #24
800145c: b2da uxtb r2, r3
800145e: 4b38 ldr r3, [pc, #224] @ (8001540 <voltage_conversion_task+0x138>)
8001460: 70da strb r2, [r3, #3]
tx_buffer[4] = (uint8_t)((vin_val >> 16) & 0xFF);
8001462: 4b33 ldr r3, [pc, #204] @ (8001530 <voltage_conversion_task+0x128>)
8001464: 681b ldr r3, [r3, #0]
8001466: 0c1b lsrs r3, r3, #16
8001468: b2da uxtb r2, r3
800146a: 4b35 ldr r3, [pc, #212] @ (8001540 <voltage_conversion_task+0x138>)
800146c: 711a strb r2, [r3, #4]
tx_buffer[5] = (uint8_t)((vin_val >> 8) & 0xFF);
800146e: 4b30 ldr r3, [pc, #192] @ (8001530 <voltage_conversion_task+0x128>)
8001470: 681b ldr r3, [r3, #0]
8001472: 0a1b lsrs r3, r3, #8
8001474: b2da uxtb r2, r3
8001476: 4b32 ldr r3, [pc, #200] @ (8001540 <voltage_conversion_task+0x138>)
8001478: 715a strb r2, [r3, #5]
tx_buffer[6] = (uint8_t)(vin_val & 0xFF);
800147a: 4b2d ldr r3, [pc, #180] @ (8001530 <voltage_conversion_task+0x128>)
800147c: 681b ldr r3, [r3, #0]
800147e: b2da uxtb r2, r3
8001480: 4b2f ldr r3, [pc, #188] @ (8001540 <voltage_conversion_task+0x138>)
8001482: 719a strb r2, [r3, #6]
tx_buffer[7] = (uint8_t)((vout_val >> 24) & 0xFF);
8001484: 4b2c ldr r3, [pc, #176] @ (8001538 <voltage_conversion_task+0x130>)
8001486: 681b ldr r3, [r3, #0]
8001488: 0e1b lsrs r3, r3, #24
800148a: b2da uxtb r2, r3
800148c: 4b2c ldr r3, [pc, #176] @ (8001540 <voltage_conversion_task+0x138>)
800148e: 71da strb r2, [r3, #7]
tx_buffer[8] = (uint8_t)((vout_val >> 16) & 0xFF);
8001490: 4b29 ldr r3, [pc, #164] @ (8001538 <voltage_conversion_task+0x130>)
8001492: 681b ldr r3, [r3, #0]
8001494: 0c1b lsrs r3, r3, #16
8001496: b2da uxtb r2, r3
8001498: 4b29 ldr r3, [pc, #164] @ (8001540 <voltage_conversion_task+0x138>)
800149a: 721a strb r2, [r3, #8]
tx_buffer[9] = (uint8_t)((vout_val >> 8) & 0xFF);
800149c: 4b26 ldr r3, [pc, #152] @ (8001538 <voltage_conversion_task+0x130>)
800149e: 681b ldr r3, [r3, #0]
80014a0: 0a1b lsrs r3, r3, #8
80014a2: b2da uxtb r2, r3
80014a4: 4b26 ldr r3, [pc, #152] @ (8001540 <voltage_conversion_task+0x138>)
80014a6: 725a strb r2, [r3, #9]
tx_buffer[10] = (uint8_t)(vout_val & 0xFF);
80014a8: 4b23 ldr r3, [pc, #140] @ (8001538 <voltage_conversion_task+0x130>)
80014aa: 681b ldr r3, [r3, #0]
80014ac: b2da uxtb r2, r3
80014ae: 4b24 ldr r3, [pc, #144] @ (8001540 <voltage_conversion_task+0x138>)
80014b0: 729a strb r2, [r3, #10]
/* Need to apply checksum to all data bits */
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
80014b2: 4b24 ldr r3, [pc, #144] @ (8001544 <voltage_conversion_task+0x13c>)
80014b4: 2200 movs r2, #0
80014b6: 701a strb r2, [r3, #0]
80014b8: e011 b.n 80014de <voltage_conversion_task+0xd6>
{
tx_checksum += tx_buffer[tx_len_counter + 3];
80014ba: 4b22 ldr r3, [pc, #136] @ (8001544 <voltage_conversion_task+0x13c>)
80014bc: 781b ldrb r3, [r3, #0]
80014be: 3303 adds r3, #3
80014c0: 4a1f ldr r2, [pc, #124] @ (8001540 <voltage_conversion_task+0x138>)
80014c2: 5cd3 ldrb r3, [r2, r3]
80014c4: 461a mov r2, r3
80014c6: 4b20 ldr r3, [pc, #128] @ (8001548 <voltage_conversion_task+0x140>)
80014c8: 881b ldrh r3, [r3, #0]
80014ca: 4413 add r3, r2
80014cc: b29a uxth r2, r3
80014ce: 4b1e ldr r3, [pc, #120] @ (8001548 <voltage_conversion_task+0x140>)
80014d0: 801a strh r2, [r3, #0]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
80014d2: 4b1c ldr r3, [pc, #112] @ (8001544 <voltage_conversion_task+0x13c>)
80014d4: 781b ldrb r3, [r3, #0]
80014d6: 3301 adds r3, #1
80014d8: b2da uxtb r2, r3
80014da: 4b1a ldr r3, [pc, #104] @ (8001544 <voltage_conversion_task+0x13c>)
80014dc: 701a strb r2, [r3, #0]
80014de: 4b19 ldr r3, [pc, #100] @ (8001544 <voltage_conversion_task+0x13c>)
80014e0: 781a ldrb r2, [r3, #0]
80014e2: 4b16 ldr r3, [pc, #88] @ (800153c <voltage_conversion_task+0x134>)
80014e4: 781b ldrb r3, [r3, #0]
80014e6: 429a cmp r2, r3
80014e8: d3e7 bcc.n 80014ba <voltage_conversion_task+0xb2>
}
tx_checksum = ~tx_checksum;
80014ea: 4b17 ldr r3, [pc, #92] @ (8001548 <voltage_conversion_task+0x140>)
80014ec: 881b ldrh r3, [r3, #0]
80014ee: 43db mvns r3, r3
80014f0: b29a uxth r2, r3
80014f2: 4b15 ldr r3, [pc, #84] @ (8001548 <voltage_conversion_task+0x140>)
80014f4: 801a strh r2, [r3, #0]
tx_buffer[11] = (uint8_t)((tx_checksum >> 8) & 0xFF);
80014f6: 4b14 ldr r3, [pc, #80] @ (8001548 <voltage_conversion_task+0x140>)
80014f8: 881b ldrh r3, [r3, #0]
80014fa: 0a1b lsrs r3, r3, #8
80014fc: b29b uxth r3, r3
80014fe: b2da uxtb r2, r3
8001500: 4b0f ldr r3, [pc, #60] @ (8001540 <voltage_conversion_task+0x138>)
8001502: 72da strb r2, [r3, #11]
tx_buffer[12] = (uint8_t)(tx_checksum & 0xFF);
8001504: 4b10 ldr r3, [pc, #64] @ (8001548 <voltage_conversion_task+0x140>)
8001506: 881b ldrh r3, [r3, #0]
8001508: b2da uxtb r2, r3
800150a: 4b0d ldr r3, [pc, #52] @ (8001540 <voltage_conversion_task+0x138>)
800150c: 731a strb r2, [r3, #12]
tx_len = 0x0D;
800150e: 4b0b ldr r3, [pc, #44] @ (800153c <voltage_conversion_task+0x134>)
8001510: 220d movs r2, #13
8001512: 701a strb r2, [r3, #0]
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
8001514: 4b09 ldr r3, [pc, #36] @ (800153c <voltage_conversion_task+0x134>)
8001516: 781b ldrb r3, [r3, #0]
8001518: 461a mov r2, r3
800151a: 2364 movs r3, #100 @ 0x64
800151c: 4908 ldr r1, [pc, #32] @ (8001540 <voltage_conversion_task+0x138>)
800151e: 480b ldr r0, [pc, #44] @ (800154c <voltage_conversion_task+0x144>)
8001520: f004 fff4 bl 800650c <HAL_UART_Transmit>
}
8001524: bf00 nop
8001526: bd80 pop {r7, pc}
8001528: 200002a2 .word 0x200002a2
800152c: 200002a8 .word 0x200002a8
8001530: 200002ac .word 0x200002ac
8001534: 200002a6 .word 0x200002a6
8001538: 200002b0 .word 0x200002b0
800153c: 20000290 .word 0x20000290
8001540: 20000270 .word 0x20000270
8001544: 20000291 .word 0x20000291
8001548: 20000298 .word 0x20000298
800154c: 200001b4 .word 0x200001b4
08001550 <voltage_conversion_task_no_tx>:
/* Voltage Conversion Task with No UART Tx */
void voltage_conversion_task_no_tx(void)
{
8001550: b580 push {r7, lr}
8001552: af00 add r7, sp, #0
/* Get Vout voltage */
vout_val = get_divider_input_mv(vout_adc_val_av, vdd_ref);
8001554: 4b06 ldr r3, [pc, #24] @ (8001570 <voltage_conversion_task_no_tx+0x20>)
8001556: 881b ldrh r3, [r3, #0]
8001558: 461a mov r2, r3
800155a: 4b06 ldr r3, [pc, #24] @ (8001574 <voltage_conversion_task_no_tx+0x24>)
800155c: 681b ldr r3, [r3, #0]
800155e: 4619 mov r1, r3
8001560: 4610 mov r0, r2
8001562: f7ff ff11 bl 8001388 <get_divider_input_mv>
8001566: 4603 mov r3, r0
8001568: 4a03 ldr r2, [pc, #12] @ (8001578 <voltage_conversion_task_no_tx+0x28>)
800156a: 6013 str r3, [r2, #0]
}
800156c: bf00 nop
800156e: bd80 pop {r7, pc}
8001570: 200002a6 .word 0x200002a6
8001574: 200002a8 .word 0x200002a8
8001578: 200002b0 .word 0x200002b0
0800157c <serial_number_task>:
void serial_number_task (void)
{
800157c: b580 push {r7, lr}
800157e: af00 add r7, sp, #0
tx_len = 0x13;
8001580: 4b42 ldr r3, [pc, #264] @ (800168c <serial_number_task+0x110>)
8001582: 2213 movs r2, #19
8001584: 701a strb r2, [r3, #0]
tx_buffer[0] = IN_SYNC_BYTE_1;
8001586: 4b42 ldr r3, [pc, #264] @ (8001690 <serial_number_task+0x114>)
8001588: 2241 movs r2, #65 @ 0x41
800158a: 701a strb r2, [r3, #0]
tx_buffer[1] = IN_SYNC_BYTE_2;
800158c: 4b40 ldr r3, [pc, #256] @ (8001690 <serial_number_task+0x114>)
800158e: 2252 movs r2, #82 @ 0x52
8001590: 705a strb r2, [r3, #1]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8001592: 4b40 ldr r3, [pc, #256] @ (8001694 <serial_number_task+0x118>)
8001594: 2200 movs r2, #0
8001596: 701a strb r2, [r3, #0]
8001598: e00f b.n 80015ba <serial_number_task+0x3e>
{
tx_buffer[tx_len_counter + 3] = serial_number[tx_len_counter];
800159a: 4b3e ldr r3, [pc, #248] @ (8001694 <serial_number_task+0x118>)
800159c: 781b ldrb r3, [r3, #0]
800159e: 4619 mov r1, r3
80015a0: 4b3c ldr r3, [pc, #240] @ (8001694 <serial_number_task+0x118>)
80015a2: 781b ldrb r3, [r3, #0]
80015a4: 3303 adds r3, #3
80015a6: 4a3c ldr r2, [pc, #240] @ (8001698 <serial_number_task+0x11c>)
80015a8: 5c51 ldrb r1, [r2, r1]
80015aa: 4a39 ldr r2, [pc, #228] @ (8001690 <serial_number_task+0x114>)
80015ac: 54d1 strb r1, [r2, r3]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
80015ae: 4b39 ldr r3, [pc, #228] @ (8001694 <serial_number_task+0x118>)
80015b0: 781b ldrb r3, [r3, #0]
80015b2: 3301 adds r3, #1
80015b4: b2da uxtb r2, r3
80015b6: 4b37 ldr r3, [pc, #220] @ (8001694 <serial_number_task+0x118>)
80015b8: 701a strb r2, [r3, #0]
80015ba: 4b36 ldr r3, [pc, #216] @ (8001694 <serial_number_task+0x118>)
80015bc: 781a ldrb r2, [r3, #0]
80015be: 4b33 ldr r3, [pc, #204] @ (800168c <serial_number_task+0x110>)
80015c0: 781b ldrb r3, [r3, #0]
80015c2: 429a cmp r2, r3
80015c4: d3e9 bcc.n 800159a <serial_number_task+0x1e>
}
tx_buffer[tx_len + 3] = 0x3A;
80015c6: 4b31 ldr r3, [pc, #196] @ (800168c <serial_number_task+0x110>)
80015c8: 781b ldrb r3, [r3, #0]
80015ca: 3303 adds r3, #3
80015cc: 4a30 ldr r2, [pc, #192] @ (8001690 <serial_number_task+0x114>)
80015ce: 213a movs r1, #58 @ 0x3a
80015d0: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 4] = fw_rev_h + 0x30;
80015d2: 4b32 ldr r3, [pc, #200] @ (800169c <serial_number_task+0x120>)
80015d4: 781a ldrb r2, [r3, #0]
80015d6: 4b2d ldr r3, [pc, #180] @ (800168c <serial_number_task+0x110>)
80015d8: 781b ldrb r3, [r3, #0]
80015da: 3304 adds r3, #4
80015dc: 3230 adds r2, #48 @ 0x30
80015de: b2d1 uxtb r1, r2
80015e0: 4a2b ldr r2, [pc, #172] @ (8001690 <serial_number_task+0x114>)
80015e2: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 5] = fw_rev_l + 0x30;
80015e4: 4b2e ldr r3, [pc, #184] @ (80016a0 <serial_number_task+0x124>)
80015e6: 781a ldrb r2, [r3, #0]
80015e8: 4b28 ldr r3, [pc, #160] @ (800168c <serial_number_task+0x110>)
80015ea: 781b ldrb r3, [r3, #0]
80015ec: 3305 adds r3, #5
80015ee: 3230 adds r2, #48 @ 0x30
80015f0: b2d1 uxtb r1, r2
80015f2: 4a27 ldr r2, [pc, #156] @ (8001690 <serial_number_task+0x114>)
80015f4: 54d1 strb r1, [r2, r3]
tx_len = 0x16;
80015f6: 4b25 ldr r3, [pc, #148] @ (800168c <serial_number_task+0x110>)
80015f8: 2216 movs r2, #22
80015fa: 701a strb r2, [r3, #0]
tx_buffer[2] = tx_len;
80015fc: 4b23 ldr r3, [pc, #140] @ (800168c <serial_number_task+0x110>)
80015fe: 781a ldrb r2, [r3, #0]
8001600: 4b23 ldr r3, [pc, #140] @ (8001690 <serial_number_task+0x114>)
8001602: 709a strb r2, [r3, #2]
tx_checksum = 0x00;
8001604: 4b27 ldr r3, [pc, #156] @ (80016a4 <serial_number_task+0x128>)
8001606: 2200 movs r2, #0
8001608: 801a strh r2, [r3, #0]
/* Need to apply checksum to all data bits */
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
800160a: 4b22 ldr r3, [pc, #136] @ (8001694 <serial_number_task+0x118>)
800160c: 2200 movs r2, #0
800160e: 701a strb r2, [r3, #0]
8001610: e011 b.n 8001636 <serial_number_task+0xba>
{
tx_checksum += tx_buffer[tx_len_counter + 3];
8001612: 4b20 ldr r3, [pc, #128] @ (8001694 <serial_number_task+0x118>)
8001614: 781b ldrb r3, [r3, #0]
8001616: 3303 adds r3, #3
8001618: 4a1d ldr r2, [pc, #116] @ (8001690 <serial_number_task+0x114>)
800161a: 5cd3 ldrb r3, [r2, r3]
800161c: 461a mov r2, r3
800161e: 4b21 ldr r3, [pc, #132] @ (80016a4 <serial_number_task+0x128>)
8001620: 881b ldrh r3, [r3, #0]
8001622: 4413 add r3, r2
8001624: b29a uxth r2, r3
8001626: 4b1f ldr r3, [pc, #124] @ (80016a4 <serial_number_task+0x128>)
8001628: 801a strh r2, [r3, #0]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
800162a: 4b1a ldr r3, [pc, #104] @ (8001694 <serial_number_task+0x118>)
800162c: 781b ldrb r3, [r3, #0]
800162e: 3301 adds r3, #1
8001630: b2da uxtb r2, r3
8001632: 4b18 ldr r3, [pc, #96] @ (8001694 <serial_number_task+0x118>)
8001634: 701a strb r2, [r3, #0]
8001636: 4b17 ldr r3, [pc, #92] @ (8001694 <serial_number_task+0x118>)
8001638: 781a ldrb r2, [r3, #0]
800163a: 4b14 ldr r3, [pc, #80] @ (800168c <serial_number_task+0x110>)
800163c: 781b ldrb r3, [r3, #0]
800163e: 429a cmp r2, r3
8001640: d3e7 bcc.n 8001612 <serial_number_task+0x96>
}
tx_checksum = ~tx_checksum;
8001642: 4b18 ldr r3, [pc, #96] @ (80016a4 <serial_number_task+0x128>)
8001644: 881b ldrh r3, [r3, #0]
8001646: 43db mvns r3, r3
8001648: b29a uxth r2, r3
800164a: 4b16 ldr r3, [pc, #88] @ (80016a4 <serial_number_task+0x128>)
800164c: 801a strh r2, [r3, #0]
tx_buffer[tx_len + 3] = (uint8_t)((tx_checksum >> 8) & 0xFF);
800164e: 4b15 ldr r3, [pc, #84] @ (80016a4 <serial_number_task+0x128>)
8001650: 881b ldrh r3, [r3, #0]
8001652: 0a1b lsrs r3, r3, #8
8001654: b29a uxth r2, r3
8001656: 4b0d ldr r3, [pc, #52] @ (800168c <serial_number_task+0x110>)
8001658: 781b ldrb r3, [r3, #0]
800165a: 3303 adds r3, #3
800165c: b2d1 uxtb r1, r2
800165e: 4a0c ldr r2, [pc, #48] @ (8001690 <serial_number_task+0x114>)
8001660: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 4] = (uint8_t)(tx_checksum & 0xFF);
8001662: 4b10 ldr r3, [pc, #64] @ (80016a4 <serial_number_task+0x128>)
8001664: 881a ldrh r2, [r3, #0]
8001666: 4b09 ldr r3, [pc, #36] @ (800168c <serial_number_task+0x110>)
8001668: 781b ldrb r3, [r3, #0]
800166a: 3304 adds r3, #4
800166c: b2d1 uxtb r1, r2
800166e: 4a08 ldr r2, [pc, #32] @ (8001690 <serial_number_task+0x114>)
8001670: 54d1 strb r1, [r2, r3]
tx_len = 0x1B;
8001672: 4b06 ldr r3, [pc, #24] @ (800168c <serial_number_task+0x110>)
8001674: 221b movs r2, #27
8001676: 701a strb r2, [r3, #0]
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
8001678: 4b04 ldr r3, [pc, #16] @ (800168c <serial_number_task+0x110>)
800167a: 781b ldrb r3, [r3, #0]
800167c: 461a mov r2, r3
800167e: 2364 movs r3, #100 @ 0x64
8001680: 4903 ldr r1, [pc, #12] @ (8001690 <serial_number_task+0x114>)
8001682: 4809 ldr r0, [pc, #36] @ (80016a8 <serial_number_task+0x12c>)
8001684: f004 ff42 bl 800650c <HAL_UART_Transmit>
}
8001688: bf00 nop
800168a: bd80 pop {r7, pc}
800168c: 20000290 .word 0x20000290
8001690: 20000270 .word 0x20000270
8001694: 20000291 .word 0x20000291
8001698: 20000004 .word 0x20000004
800169c: 20000248 .word 0x20000248
80016a0: 20000000 .word 0x20000000
80016a4: 20000298 .word 0x20000298
80016a8: 200001b4 .word 0x200001b4
080016ac <adc_task>:
/* ADC task */
void adc_task (void)
{
80016ac: b580 push {r7, lr}
80016ae: af00 add r7, sp, #0
HAL_ADC_Start(&hadc2);
80016b0: 4811 ldr r0, [pc, #68] @ (80016f8 <adc_task+0x4c>)
80016b2: f000 ffef bl 8002694 <HAL_ADC_Start>
HAL_ADC_PollForConversion(&hadc2, 500);
80016b6: f44f 71fa mov.w r1, #500 @ 0x1f4
80016ba: 480f ldr r0, [pc, #60] @ (80016f8 <adc_task+0x4c>)
80016bc: f001 f8da bl 8002874 <HAL_ADC_PollForConversion>
vout_adc_val = HAL_ADC_GetValue(&hadc2);
80016c0: 480d ldr r0, [pc, #52] @ (80016f8 <adc_task+0x4c>)
80016c2: f001 f9af bl 8002a24 <HAL_ADC_GetValue>
80016c6: 4603 mov r3, r0
80016c8: b29a uxth r2, r3
80016ca: 4b0c ldr r3, [pc, #48] @ (80016fc <adc_task+0x50>)
80016cc: 801a strh r2, [r3, #0]
HAL_ADC_Start(&hadc2);
80016ce: 480a ldr r0, [pc, #40] @ (80016f8 <adc_task+0x4c>)
80016d0: f000 ffe0 bl 8002694 <HAL_ADC_Start>
HAL_ADC_PollForConversion(&hadc2, 500);
80016d4: f44f 71fa mov.w r1, #500 @ 0x1f4
80016d8: 4807 ldr r0, [pc, #28] @ (80016f8 <adc_task+0x4c>)
80016da: f001 f8cb bl 8002874 <HAL_ADC_PollForConversion>
vin_adc_val = HAL_ADC_GetValue(&hadc2);
80016de: 4806 ldr r0, [pc, #24] @ (80016f8 <adc_task+0x4c>)
80016e0: f001 f9a0 bl 8002a24 <HAL_ADC_GetValue>
80016e4: 4603 mov r3, r0
80016e6: b29a uxth r2, r3
80016e8: 4b05 ldr r3, [pc, #20] @ (8001700 <adc_task+0x54>)
80016ea: 801a strh r2, [r3, #0]
HAL_ADC_Stop(&hadc2);
80016ec: 4802 ldr r0, [pc, #8] @ (80016f8 <adc_task+0x4c>)
80016ee: f001 f88d bl 800280c <HAL_ADC_Stop>
}
80016f2: bf00 nop
80016f4: bd80 pop {r7, pc}
80016f6: bf00 nop
80016f8: 200000b0 .word 0x200000b0
80016fc: 200002a4 .word 0x200002a4
8001700: 200002a2 .word 0x200002a2
08001704 <power_switch>:
/* Power switch function */
void power_switch (uint8_t state)
{
8001704: b580 push {r7, lr}
8001706: b082 sub sp, #8
8001708: af00 add r7, sp, #0
800170a: 4603 mov r3, r0
800170c: 71fb strb r3, [r7, #7]
if (state == 1)
800170e: 79fb ldrb r3, [r7, #7]
8001710: 2b01 cmp r3, #1
8001712: d109 bne.n 8001728 <power_switch+0x24>
{
vset_task_flag = 0xFF;
8001714: 4b0b ldr r3, [pc, #44] @ (8001744 <power_switch+0x40>)
8001716: 22ff movs r2, #255 @ 0xff
8001718: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);
800171a: 2201 movs r2, #1
800171c: f44f 7180 mov.w r1, #256 @ 0x100
8001720: 4809 ldr r0, [pc, #36] @ (8001748 <power_switch+0x44>)
8001722: f002 fbc9 bl 8003eb8 <HAL_GPIO_WritePin>
else
{
vset_task_flag = 0x00;
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
}
}
8001726: e008 b.n 800173a <power_switch+0x36>
vset_task_flag = 0x00;
8001728: 4b06 ldr r3, [pc, #24] @ (8001744 <power_switch+0x40>)
800172a: 2200 movs r2, #0
800172c: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
800172e: 2200 movs r2, #0
8001730: f44f 7180 mov.w r1, #256 @ 0x100
8001734: 4804 ldr r0, [pc, #16] @ (8001748 <power_switch+0x44>)
8001736: f002 fbbf bl 8003eb8 <HAL_GPIO_WritePin>
}
800173a: bf00 nop
800173c: 3708 adds r7, #8
800173e: 46bd mov sp, r7
8001740: bd80 pop {r7, pc}
8001742: bf00 nop
8001744: 200002b8 .word 0x200002b8
8001748: 48000400 .word 0x48000400
0800174c <HAL_UART_TxCpltCallback>:
/* UART Tx callback */
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
800174c: b480 push {r7}
800174e: b083 sub sp, #12
8001750: af00 add r7, sp, #0
8001752: 6078 str r0, [r7, #4]
/* Do nothing here for now */
}
8001754: bf00 nop
8001756: 370c adds r7, #12
8001758: 46bd mov sp, r7
800175a: f85d 7b04 ldr.w r7, [sp], #4
800175e: 4770 bx lr
08001760 <HAL_UART_RxCpltCallback>:
/* UART Rx callback */
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
8001760: b580 push {r7, lr}
8001762: b082 sub sp, #8
8001764: af00 add r7, sp, #0
8001766: 6078 str r0, [r7, #4]
/* If data received on UART */
if(huart->Instance==USART2)
8001768: 687b ldr r3, [r7, #4]
800176a: 681b ldr r3, [r3, #0]
800176c: 4a7e ldr r2, [pc, #504] @ (8001968 <HAL_UART_RxCpltCallback+0x208>)
800176e: 4293 cmp r3, r2
8001770: f040 80f6 bne.w 8001960 <HAL_UART_RxCpltCallback+0x200>
{
/* Act on received data */
switch (rx_counter)
8001774: 4b7d ldr r3, [pc, #500] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
8001776: 781b ldrb r3, [r3, #0]
8001778: 2b05 cmp r3, #5
800177a: f200 80e7 bhi.w 800194c <HAL_UART_RxCpltCallback+0x1ec>
800177e: a201 add r2, pc, #4 @ (adr r2, 8001784 <HAL_UART_RxCpltCallback+0x24>)
8001780: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001784: 0800179d .word 0x0800179d
8001788: 080017b5 .word 0x080017b5
800178c: 080017e3 .word 0x080017e3
8001790: 080017ff .word 0x080017ff
8001794: 0800183b .word 0x0800183b
8001798: 08001851 .word 0x08001851
{
case 0x00:
/* Check to see if first sync byte has been received */
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
800179c: 4b74 ldr r3, [pc, #464] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
800179e: 781b ldrb r3, [r3, #0]
80017a0: 2b41 cmp r3, #65 @ 0x41
80017a2: f040 80d5 bne.w 8001950 <HAL_UART_RxCpltCallback+0x1f0>
{
/* Got it, so now wait for the second sync byte */
rx_counter++;
80017a6: 4b71 ldr r3, [pc, #452] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017a8: 781b ldrb r3, [r3, #0]
80017aa: 3301 adds r3, #1
80017ac: b2da uxtb r2, r3
80017ae: 4b6f ldr r3, [pc, #444] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017b0: 701a strb r2, [r3, #0]
}
break;
80017b2: e0cd b.n 8001950 <HAL_UART_RxCpltCallback+0x1f0>
case 0x01:
/* Check to see if second sync byte has been received */
if (rx_hold_buffer[0] == IN_SYNC_BYTE_2)
80017b4: 4b6e ldr r3, [pc, #440] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
80017b6: 781b ldrb r3, [r3, #0]
80017b8: 2b52 cmp r3, #82 @ 0x52
80017ba: d106 bne.n 80017ca <HAL_UART_RxCpltCallback+0x6a>
{
/* Got it, so now wait for the data byte */
rx_counter++;
80017bc: 4b6b ldr r3, [pc, #428] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017be: 781b ldrb r3, [r3, #0]
80017c0: 3301 adds r3, #1
80017c2: b2da uxtb r2, r3
80017c4: 4b69 ldr r3, [pc, #420] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017c6: 701a strb r2, [r3, #0]
{
rx_counter = 0x00;
}
}
break;
80017c8: e0c5 b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
80017ca: 4b69 ldr r3, [pc, #420] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
80017cc: 781b ldrb r3, [r3, #0]
80017ce: 2b41 cmp r3, #65 @ 0x41
80017d0: d103 bne.n 80017da <HAL_UART_RxCpltCallback+0x7a>
rx_counter = 0x01;
80017d2: 4b66 ldr r3, [pc, #408] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017d4: 2201 movs r2, #1
80017d6: 701a strb r2, [r3, #0]
break;
80017d8: e0bd b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
rx_counter = 0x00;
80017da: 4b64 ldr r3, [pc, #400] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017dc: 2200 movs r2, #0
80017de: 701a strb r2, [r3, #0]
break;
80017e0: e0b9 b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
case 0x02:
/* Get rx length and reset counter */
rx_len = rx_hold_buffer[0];
80017e2: 4b63 ldr r3, [pc, #396] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
80017e4: 781a ldrb r2, [r3, #0]
80017e6: 4b63 ldr r3, [pc, #396] @ (8001974 <HAL_UART_RxCpltCallback+0x214>)
80017e8: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
80017ea: 4b63 ldr r3, [pc, #396] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
80017ec: 2200 movs r2, #0
80017ee: 701a strb r2, [r3, #0]
rx_counter++;
80017f0: 4b5e ldr r3, [pc, #376] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017f2: 781b ldrb r3, [r3, #0]
80017f4: 3301 adds r3, #1
80017f6: b2da uxtb r2, r3
80017f8: 4b5c ldr r3, [pc, #368] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80017fa: 701a strb r2, [r3, #0]
break;
80017fc: e0ab b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
case 0x03:
/* Store entire length of Data bytes */
/* Increase count */
rx_len_counter++;
80017fe: 4b5e ldr r3, [pc, #376] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
8001800: 781b ldrb r3, [r3, #0]
8001802: 3301 adds r3, #1
8001804: b2da uxtb r2, r3
8001806: 4b5c ldr r3, [pc, #368] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
8001808: 701a strb r2, [r3, #0]
/* Store data */
rx_buffer[rx_len_counter - 1] = rx_hold_buffer[0];
800180a: 4b5b ldr r3, [pc, #364] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
800180c: 781b ldrb r3, [r3, #0]
800180e: 3b01 subs r3, #1
8001810: 4a57 ldr r2, [pc, #348] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
8001812: 7811 ldrb r1, [r2, #0]
8001814: 4a59 ldr r2, [pc, #356] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
8001816: 54d1 strb r1, [r2, r3]
/* Check to see if we have all the expected data bytes */
/* If so, then move on the CRC */
if (rx_len_counter == rx_len)
8001818: 4b57 ldr r3, [pc, #348] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
800181a: 781a ldrb r2, [r3, #0]
800181c: 4b55 ldr r3, [pc, #340] @ (8001974 <HAL_UART_RxCpltCallback+0x214>)
800181e: 781b ldrb r3, [r3, #0]
8001820: 429a cmp r2, r3
8001822: f040 8097 bne.w 8001954 <HAL_UART_RxCpltCallback+0x1f4>
{
rx_counter++;
8001826: 4b51 ldr r3, [pc, #324] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
8001828: 781b ldrb r3, [r3, #0]
800182a: 3301 adds r3, #1
800182c: b2da uxtb r2, r3
800182e: 4b4f ldr r3, [pc, #316] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
8001830: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
8001832: 4b51 ldr r3, [pc, #324] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
8001834: 2200 movs r2, #0
8001836: 701a strb r2, [r3, #0]
}
break;
8001838: e08c b.n 8001954 <HAL_UART_RxCpltCallback+0x1f4>
case 0x04:
/* Store Rx checksum byte #1 */
rx_checksum_hold_1 = rx_hold_buffer[0];
800183a: 4b4d ldr r3, [pc, #308] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
800183c: 781a ldrb r2, [r3, #0]
800183e: 4b50 ldr r3, [pc, #320] @ (8001980 <HAL_UART_RxCpltCallback+0x220>)
8001840: 701a strb r2, [r3, #0]
rx_counter++;
8001842: 4b4a ldr r3, [pc, #296] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
8001844: 781b ldrb r3, [r3, #0]
8001846: 3301 adds r3, #1
8001848: b2da uxtb r2, r3
800184a: 4b48 ldr r3, [pc, #288] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
800184c: 701a strb r2, [r3, #0]
break;
800184e: e082 b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
case 0x05:
/* Store Rx checksum byte #2, reset and calculate checksum */
rx_checksum_hold_2 = rx_hold_buffer[0];
8001850: 4b47 ldr r3, [pc, #284] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
8001852: 781a ldrb r2, [r3, #0]
8001854: 4b4b ldr r3, [pc, #300] @ (8001984 <HAL_UART_RxCpltCallback+0x224>)
8001856: 701a strb r2, [r3, #0]
rx_checksum_hold = (rx_checksum_hold_1 << 8) | rx_checksum_hold_2;
8001858: 4b49 ldr r3, [pc, #292] @ (8001980 <HAL_UART_RxCpltCallback+0x220>)
800185a: 781b ldrb r3, [r3, #0]
800185c: b21b sxth r3, r3
800185e: 021b lsls r3, r3, #8
8001860: b21a sxth r2, r3
8001862: 4b48 ldr r3, [pc, #288] @ (8001984 <HAL_UART_RxCpltCallback+0x224>)
8001864: 781b ldrb r3, [r3, #0]
8001866: b21b sxth r3, r3
8001868: 4313 orrs r3, r2
800186a: b21b sxth r3, r3
800186c: b29a uxth r2, r3
800186e: 4b46 ldr r3, [pc, #280] @ (8001988 <HAL_UART_RxCpltCallback+0x228>)
8001870: 801a strh r2, [r3, #0]
rx_checksum = 0;
8001872: 4b46 ldr r3, [pc, #280] @ (800198c <HAL_UART_RxCpltCallback+0x22c>)
8001874: 2200 movs r2, #0
8001876: 801a strh r2, [r3, #0]
/* Need to apply to all data bits */
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
8001878: 4b3f ldr r3, [pc, #252] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
800187a: 2200 movs r2, #0
800187c: 701a strb r2, [r3, #0]
800187e: e011 b.n 80018a4 <HAL_UART_RxCpltCallback+0x144>
{
rx_checksum += rx_buffer[rx_len_counter];
8001880: 4b3d ldr r3, [pc, #244] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
8001882: 781b ldrb r3, [r3, #0]
8001884: 461a mov r2, r3
8001886: 4b3d ldr r3, [pc, #244] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
8001888: 5c9b ldrb r3, [r3, r2]
800188a: 461a mov r2, r3
800188c: 4b3f ldr r3, [pc, #252] @ (800198c <HAL_UART_RxCpltCallback+0x22c>)
800188e: 881b ldrh r3, [r3, #0]
8001890: 4413 add r3, r2
8001892: b29a uxth r2, r3
8001894: 4b3d ldr r3, [pc, #244] @ (800198c <HAL_UART_RxCpltCallback+0x22c>)
8001896: 801a strh r2, [r3, #0]
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
8001898: 4b37 ldr r3, [pc, #220] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
800189a: 781b ldrb r3, [r3, #0]
800189c: 3301 adds r3, #1
800189e: b2da uxtb r2, r3
80018a0: 4b35 ldr r3, [pc, #212] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
80018a2: 701a strb r2, [r3, #0]
80018a4: 4b34 ldr r3, [pc, #208] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
80018a6: 781a ldrb r2, [r3, #0]
80018a8: 4b32 ldr r3, [pc, #200] @ (8001974 <HAL_UART_RxCpltCallback+0x214>)
80018aa: 781b ldrb r3, [r3, #0]
80018ac: 429a cmp r2, r3
80018ae: d3e7 bcc.n 8001880 <HAL_UART_RxCpltCallback+0x120>
}
rx_len = 0x00;
80018b0: 4b30 ldr r3, [pc, #192] @ (8001974 <HAL_UART_RxCpltCallback+0x214>)
80018b2: 2200 movs r2, #0
80018b4: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
80018b6: 4b30 ldr r3, [pc, #192] @ (8001978 <HAL_UART_RxCpltCallback+0x218>)
80018b8: 2200 movs r2, #0
80018ba: 701a strb r2, [r3, #0]
rx_checksum = ~rx_checksum;
80018bc: 4b33 ldr r3, [pc, #204] @ (800198c <HAL_UART_RxCpltCallback+0x22c>)
80018be: 881b ldrh r3, [r3, #0]
80018c0: 43db mvns r3, r3
80018c2: b29a uxth r2, r3
80018c4: 4b31 ldr r3, [pc, #196] @ (800198c <HAL_UART_RxCpltCallback+0x22c>)
80018c6: 801a strh r2, [r3, #0]
/* If checksum calculated equals the received checksum of packet then we got a good packet */
if (rx_checksum == rx_checksum_hold)
80018c8: 4b30 ldr r3, [pc, #192] @ (800198c <HAL_UART_RxCpltCallback+0x22c>)
80018ca: 881a ldrh r2, [r3, #0]
80018cc: 4b2e ldr r3, [pc, #184] @ (8001988 <HAL_UART_RxCpltCallback+0x228>)
80018ce: 881b ldrh r3, [r3, #0]
80018d0: 429a cmp r2, r3
80018d2: d135 bne.n 8001940 <HAL_UART_RxCpltCallback+0x1e0>
{
/* Rx is finished, so reset count to wait for another first sync byte (also act on command/data)*/
rx_counter = 0x00;
80018d4: 4b25 ldr r3, [pc, #148] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
80018d6: 2200 movs r2, #0
80018d8: 701a strb r2, [r3, #0]
command = rx_buffer[0];
80018da: 4b28 ldr r3, [pc, #160] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
80018dc: 781a ldrb r2, [r3, #0]
80018de: 4b2c ldr r3, [pc, #176] @ (8001990 <HAL_UART_RxCpltCallback+0x230>)
80018e0: 701a strb r2, [r3, #0]
switch (command)
80018e2: 4b2b ldr r3, [pc, #172] @ (8001990 <HAL_UART_RxCpltCallback+0x230>)
80018e4: 781b ldrb r3, [r3, #0]
80018e6: 2b56 cmp r3, #86 @ 0x56
80018e8: d022 beq.n 8001930 <HAL_UART_RxCpltCallback+0x1d0>
80018ea: 2b56 cmp r3, #86 @ 0x56
80018ec: dc2c bgt.n 8001948 <HAL_UART_RxCpltCallback+0x1e8>
80018ee: 2b49 cmp r3, #73 @ 0x49
80018f0: d022 beq.n 8001938 <HAL_UART_RxCpltCallback+0x1d8>
80018f2: 2b53 cmp r3, #83 @ 0x53
80018f4: d128 bne.n 8001948 <HAL_UART_RxCpltCallback+0x1e8>
{
/* 'S' - Set power output state */
case 0x53:
power_state_value = rx_buffer[1];
80018f6: 4b21 ldr r3, [pc, #132] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
80018f8: 785a ldrb r2, [r3, #1]
80018fa: 4b26 ldr r3, [pc, #152] @ (8001994 <HAL_UART_RxCpltCallback+0x234>)
80018fc: 701a strb r2, [r3, #0]
v_target = ((uint32_t)rx_buffer[2] << 24) | ((uint32_t)rx_buffer[3] << 16) | ((uint32_t)rx_buffer[4] << 8) | ((uint32_t)rx_buffer[5]);
80018fe: 4b1f ldr r3, [pc, #124] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
8001900: 789b ldrb r3, [r3, #2]
8001902: 061a lsls r2, r3, #24
8001904: 4b1d ldr r3, [pc, #116] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
8001906: 78db ldrb r3, [r3, #3]
8001908: 041b lsls r3, r3, #16
800190a: 431a orrs r2, r3
800190c: 4b1b ldr r3, [pc, #108] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
800190e: 791b ldrb r3, [r3, #4]
8001910: 021b lsls r3, r3, #8
8001912: 4313 orrs r3, r2
8001914: 4a19 ldr r2, [pc, #100] @ (800197c <HAL_UART_RxCpltCallback+0x21c>)
8001916: 7952 ldrb r2, [r2, #5]
8001918: 4313 orrs r3, r2
800191a: 4a1f ldr r2, [pc, #124] @ (8001998 <HAL_UART_RxCpltCallback+0x238>)
800191c: 6013 str r3, [r2, #0]
MA_Init(&movavFilter);
800191e: 481f ldr r0, [pc, #124] @ (800199c <HAL_UART_RxCpltCallback+0x23c>)
8001920: f7ff fca4 bl 800126c <MA_Init>
power_switch(power_state_value);
8001924: 4b1b ldr r3, [pc, #108] @ (8001994 <HAL_UART_RxCpltCallback+0x234>)
8001926: 781b ldrb r3, [r3, #0]
8001928: 4618 mov r0, r3
800192a: f7ff feeb bl 8001704 <power_switch>
break;
800192e: e00c b.n 800194a <HAL_UART_RxCpltCallback+0x1ea>
/* 'V' - Get voltages (both input and output) */
case 0x56:
adc_task_flag = 0xff;
8001930: 4b1b ldr r3, [pc, #108] @ (80019a0 <HAL_UART_RxCpltCallback+0x240>)
8001932: 22ff movs r2, #255 @ 0xff
8001934: 701a strb r2, [r3, #0]
break;
8001936: e008 b.n 800194a <HAL_UART_RxCpltCallback+0x1ea>
/* 'I' - Get serial number information */
case 0x49:
serial_number_flag = 0xff;
8001938: 4b1a ldr r3, [pc, #104] @ (80019a4 <HAL_UART_RxCpltCallback+0x244>)
800193a: 22ff movs r2, #255 @ 0xff
800193c: 701a strb r2, [r3, #0]
break;
800193e: e004 b.n 800194a <HAL_UART_RxCpltCallback+0x1ea>
/* Bad packet received */
else
{
/* Rx is finished, so reset count to wait for another first sync byte (bad packet so no flag)*/
rx_counter = 0x00;
8001940: 4b0a ldr r3, [pc, #40] @ (800196c <HAL_UART_RxCpltCallback+0x20c>)
8001942: 2200 movs r2, #0
8001944: 701a strb r2, [r3, #0]
}
break;
8001946: e006 b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
break;
8001948: bf00 nop
break;
800194a: e004 b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
/* Default case - NOT USED!*/
default:
break;
800194c: bf00 nop
800194e: e002 b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
break;
8001950: bf00 nop
8001952: e000 b.n 8001956 <HAL_UART_RxCpltCallback+0x1f6>
break;
8001954: bf00 nop
}
/* Reset interrupts */
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
8001956: 2201 movs r2, #1
8001958: 4905 ldr r1, [pc, #20] @ (8001970 <HAL_UART_RxCpltCallback+0x210>)
800195a: 4813 ldr r0, [pc, #76] @ (80019a8 <HAL_UART_RxCpltCallback+0x248>)
800195c: f004 fe64 bl 8006628 <HAL_UART_Receive_IT>
}
}
8001960: bf00 nop
8001962: 3708 adds r7, #8
8001964: 46bd mov sp, r7
8001966: bd80 pop {r7, pc}
8001968: 40004400 .word 0x40004400
800196c: 20000292 .word 0x20000292
8001970: 2000024c .word 0x2000024c
8001974: 20000293 .word 0x20000293
8001978: 20000294 .word 0x20000294
800197c: 20000250 .word 0x20000250
8001980: 2000029a .word 0x2000029a
8001984: 2000029b .word 0x2000029b
8001988: 2000029c .word 0x2000029c
800198c: 20000296 .word 0x20000296
8001990: 2000029f .word 0x2000029f
8001994: 2000029e .word 0x2000029e
8001998: 200002b4 .word 0x200002b4
800199c: 200002bc .word 0x200002bc
80019a0: 200002a0 .word 0x200002a0
80019a4: 200002b9 .word 0x200002b9
80019a8: 200001b4 .word 0x200001b4
080019ac <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80019ac: b480 push {r7}
80019ae: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80019b0: b672 cpsid i
}
80019b2: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80019b4: bf00 nop
80019b6: e7fd b.n 80019b4 <Error_Handler+0x8>
080019b8 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80019b8: b580 push {r7, lr}
80019ba: b082 sub sp, #8
80019bc: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80019be: 4b0f ldr r3, [pc, #60] @ (80019fc <HAL_MspInit+0x44>)
80019c0: 6e1b ldr r3, [r3, #96] @ 0x60
80019c2: 4a0e ldr r2, [pc, #56] @ (80019fc <HAL_MspInit+0x44>)
80019c4: f043 0301 orr.w r3, r3, #1
80019c8: 6613 str r3, [r2, #96] @ 0x60
80019ca: 4b0c ldr r3, [pc, #48] @ (80019fc <HAL_MspInit+0x44>)
80019cc: 6e1b ldr r3, [r3, #96] @ 0x60
80019ce: f003 0301 and.w r3, r3, #1
80019d2: 607b str r3, [r7, #4]
80019d4: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80019d6: 4b09 ldr r3, [pc, #36] @ (80019fc <HAL_MspInit+0x44>)
80019d8: 6d9b ldr r3, [r3, #88] @ 0x58
80019da: 4a08 ldr r2, [pc, #32] @ (80019fc <HAL_MspInit+0x44>)
80019dc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80019e0: 6593 str r3, [r2, #88] @ 0x58
80019e2: 4b06 ldr r3, [pc, #24] @ (80019fc <HAL_MspInit+0x44>)
80019e4: 6d9b ldr r3, [r3, #88] @ 0x58
80019e6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80019ea: 603b str r3, [r7, #0]
80019ec: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
*/
HAL_PWREx_DisableUCPDDeadBattery();
80019ee: f002 fb1f bl 8004030 <HAL_PWREx_DisableUCPDDeadBattery>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80019f2: bf00 nop
80019f4: 3708 adds r7, #8
80019f6: 46bd mov sp, r7
80019f8: bd80 pop {r7, pc}
80019fa: bf00 nop
80019fc: 40021000 .word 0x40021000
08001a00 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8001a00: b580 push {r7, lr}
8001a02: b09c sub sp, #112 @ 0x70
8001a04: af00 add r7, sp, #0
8001a06: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001a08: f107 035c add.w r3, r7, #92 @ 0x5c
8001a0c: 2200 movs r2, #0
8001a0e: 601a str r2, [r3, #0]
8001a10: 605a str r2, [r3, #4]
8001a12: 609a str r2, [r3, #8]
8001a14: 60da str r2, [r3, #12]
8001a16: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001a18: f107 0318 add.w r3, r7, #24
8001a1c: 2244 movs r2, #68 @ 0x44
8001a1e: 2100 movs r1, #0
8001a20: 4618 mov r0, r3
8001a22: f006 fe33 bl 800868c <memset>
if(hadc->Instance==ADC1)
8001a26: 687b ldr r3, [r7, #4]
8001a28: 681b ldr r3, [r3, #0]
8001a2a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8001a2e: d125 bne.n 8001a7c <HAL_ADC_MspInit+0x7c>
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
8001a30: f44f 4300 mov.w r3, #32768 @ 0x8000
8001a34: 61bb str r3, [r7, #24]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
8001a36: f04f 5300 mov.w r3, #536870912 @ 0x20000000
8001a3a: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001a3c: f107 0318 add.w r3, r7, #24
8001a40: 4618 mov r0, r3
8001a42: f003 f833 bl 8004aac <HAL_RCCEx_PeriphCLKConfig>
8001a46: 4603 mov r3, r0
8001a48: 2b00 cmp r3, #0
8001a4a: d001 beq.n 8001a50 <HAL_ADC_MspInit+0x50>
{
Error_Handler();
8001a4c: f7ff ffae bl 80019ac <Error_Handler>
}
/* Peripheral clock enable */
HAL_RCC_ADC12_CLK_ENABLED++;
8001a50: 4b2e ldr r3, [pc, #184] @ (8001b0c <HAL_ADC_MspInit+0x10c>)
8001a52: 681b ldr r3, [r3, #0]
8001a54: 3301 adds r3, #1
8001a56: 4a2d ldr r2, [pc, #180] @ (8001b0c <HAL_ADC_MspInit+0x10c>)
8001a58: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8001a5a: 4b2c ldr r3, [pc, #176] @ (8001b0c <HAL_ADC_MspInit+0x10c>)
8001a5c: 681b ldr r3, [r3, #0]
8001a5e: 2b01 cmp r3, #1
8001a60: d14f bne.n 8001b02 <HAL_ADC_MspInit+0x102>
__HAL_RCC_ADC12_CLK_ENABLE();
8001a62: 4b2b ldr r3, [pc, #172] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001a64: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a66: 4a2a ldr r2, [pc, #168] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001a68: f443 5300 orr.w r3, r3, #8192 @ 0x2000
8001a6c: 64d3 str r3, [r2, #76] @ 0x4c
8001a6e: 4b28 ldr r3, [pc, #160] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001a70: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a72: f403 5300 and.w r3, r3, #8192 @ 0x2000
8001a76: 617b str r3, [r7, #20]
8001a78: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
8001a7a: e042 b.n 8001b02 <HAL_ADC_MspInit+0x102>
else if(hadc->Instance==ADC2)
8001a7c: 687b ldr r3, [r7, #4]
8001a7e: 681b ldr r3, [r3, #0]
8001a80: 4a24 ldr r2, [pc, #144] @ (8001b14 <HAL_ADC_MspInit+0x114>)
8001a82: 4293 cmp r3, r2
8001a84: d13d bne.n 8001b02 <HAL_ADC_MspInit+0x102>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
8001a86: f44f 4300 mov.w r3, #32768 @ 0x8000
8001a8a: 61bb str r3, [r7, #24]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
8001a8c: f04f 5300 mov.w r3, #536870912 @ 0x20000000
8001a90: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001a92: f107 0318 add.w r3, r7, #24
8001a96: 4618 mov r0, r3
8001a98: f003 f808 bl 8004aac <HAL_RCCEx_PeriphCLKConfig>
8001a9c: 4603 mov r3, r0
8001a9e: 2b00 cmp r3, #0
8001aa0: d001 beq.n 8001aa6 <HAL_ADC_MspInit+0xa6>
Error_Handler();
8001aa2: f7ff ff83 bl 80019ac <Error_Handler>
HAL_RCC_ADC12_CLK_ENABLED++;
8001aa6: 4b19 ldr r3, [pc, #100] @ (8001b0c <HAL_ADC_MspInit+0x10c>)
8001aa8: 681b ldr r3, [r3, #0]
8001aaa: 3301 adds r3, #1
8001aac: 4a17 ldr r2, [pc, #92] @ (8001b0c <HAL_ADC_MspInit+0x10c>)
8001aae: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8001ab0: 4b16 ldr r3, [pc, #88] @ (8001b0c <HAL_ADC_MspInit+0x10c>)
8001ab2: 681b ldr r3, [r3, #0]
8001ab4: 2b01 cmp r3, #1
8001ab6: d10b bne.n 8001ad0 <HAL_ADC_MspInit+0xd0>
__HAL_RCC_ADC12_CLK_ENABLE();
8001ab8: 4b15 ldr r3, [pc, #84] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001aba: 6cdb ldr r3, [r3, #76] @ 0x4c
8001abc: 4a14 ldr r2, [pc, #80] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001abe: f443 5300 orr.w r3, r3, #8192 @ 0x2000
8001ac2: 64d3 str r3, [r2, #76] @ 0x4c
8001ac4: 4b12 ldr r3, [pc, #72] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001ac6: 6cdb ldr r3, [r3, #76] @ 0x4c
8001ac8: f403 5300 and.w r3, r3, #8192 @ 0x2000
8001acc: 613b str r3, [r7, #16]
8001ace: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001ad0: 4b0f ldr r3, [pc, #60] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001ad2: 6cdb ldr r3, [r3, #76] @ 0x4c
8001ad4: 4a0e ldr r2, [pc, #56] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001ad6: f043 0301 orr.w r3, r3, #1
8001ada: 64d3 str r3, [r2, #76] @ 0x4c
8001adc: 4b0c ldr r3, [pc, #48] @ (8001b10 <HAL_ADC_MspInit+0x110>)
8001ade: 6cdb ldr r3, [r3, #76] @ 0x4c
8001ae0: f003 0301 and.w r3, r3, #1
8001ae4: 60fb str r3, [r7, #12]
8001ae6: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = VIN_Pin|VOUT_Pin;
8001ae8: 23c0 movs r3, #192 @ 0xc0
8001aea: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001aec: 2303 movs r3, #3
8001aee: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001af0: 2300 movs r3, #0
8001af2: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001af4: f107 035c add.w r3, r7, #92 @ 0x5c
8001af8: 4619 mov r1, r3
8001afa: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001afe: f002 f859 bl 8003bb4 <HAL_GPIO_Init>
}
8001b02: bf00 nop
8001b04: 3770 adds r7, #112 @ 0x70
8001b06: 46bd mov sp, r7
8001b08: bd80 pop {r7, pc}
8001b0a: bf00 nop
8001b0c: 200003c4 .word 0x200003c4
8001b10: 40021000 .word 0x40021000
8001b14: 50000100 .word 0x50000100
08001b18 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001b18: b580 push {r7, lr}
8001b1a: b084 sub sp, #16
8001b1c: af00 add r7, sp, #0
8001b1e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
8001b20: 687b ldr r3, [r7, #4]
8001b22: 681b ldr r3, [r3, #0]
8001b24: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001b28: d114 bne.n 8001b54 <HAL_TIM_Base_MspInit+0x3c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001b2a: 4b15 ldr r3, [pc, #84] @ (8001b80 <HAL_TIM_Base_MspInit+0x68>)
8001b2c: 6d9b ldr r3, [r3, #88] @ 0x58
8001b2e: 4a14 ldr r2, [pc, #80] @ (8001b80 <HAL_TIM_Base_MspInit+0x68>)
8001b30: f043 0301 orr.w r3, r3, #1
8001b34: 6593 str r3, [r2, #88] @ 0x58
8001b36: 4b12 ldr r3, [pc, #72] @ (8001b80 <HAL_TIM_Base_MspInit+0x68>)
8001b38: 6d9b ldr r3, [r3, #88] @ 0x58
8001b3a: f003 0301 and.w r3, r3, #1
8001b3e: 60fb str r3, [r7, #12]
8001b40: 68fb ldr r3, [r7, #12]
/* TIM2 interrupt Init */
HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
8001b42: 2200 movs r2, #0
8001b44: 2100 movs r1, #0
8001b46: 201c movs r0, #28
8001b48: f001 ff3f bl 80039ca <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM2_IRQn);
8001b4c: 201c movs r0, #28
8001b4e: f001 ff56 bl 80039fe <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM16_MspInit 1 */
/* USER CODE END TIM16_MspInit 1 */
}
}
8001b52: e010 b.n 8001b76 <HAL_TIM_Base_MspInit+0x5e>
else if(htim_base->Instance==TIM16)
8001b54: 687b ldr r3, [r7, #4]
8001b56: 681b ldr r3, [r3, #0]
8001b58: 4a0a ldr r2, [pc, #40] @ (8001b84 <HAL_TIM_Base_MspInit+0x6c>)
8001b5a: 4293 cmp r3, r2
8001b5c: d10b bne.n 8001b76 <HAL_TIM_Base_MspInit+0x5e>
__HAL_RCC_TIM16_CLK_ENABLE();
8001b5e: 4b08 ldr r3, [pc, #32] @ (8001b80 <HAL_TIM_Base_MspInit+0x68>)
8001b60: 6e1b ldr r3, [r3, #96] @ 0x60
8001b62: 4a07 ldr r2, [pc, #28] @ (8001b80 <HAL_TIM_Base_MspInit+0x68>)
8001b64: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001b68: 6613 str r3, [r2, #96] @ 0x60
8001b6a: 4b05 ldr r3, [pc, #20] @ (8001b80 <HAL_TIM_Base_MspInit+0x68>)
8001b6c: 6e1b ldr r3, [r3, #96] @ 0x60
8001b6e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001b72: 60bb str r3, [r7, #8]
8001b74: 68bb ldr r3, [r7, #8]
}
8001b76: bf00 nop
8001b78: 3710 adds r7, #16
8001b7a: 46bd mov sp, r7
8001b7c: bd80 pop {r7, pc}
8001b7e: bf00 nop
8001b80: 40021000 .word 0x40021000
8001b84: 40014400 .word 0x40014400
08001b88 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001b88: b580 push {r7, lr}
8001b8a: b088 sub sp, #32
8001b8c: af00 add r7, sp, #0
8001b8e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001b90: f107 030c add.w r3, r7, #12
8001b94: 2200 movs r2, #0
8001b96: 601a str r2, [r3, #0]
8001b98: 605a str r2, [r3, #4]
8001b9a: 609a str r2, [r3, #8]
8001b9c: 60da str r2, [r3, #12]
8001b9e: 611a str r2, [r3, #16]
if(htim->Instance==TIM16)
8001ba0: 687b ldr r3, [r7, #4]
8001ba2: 681b ldr r3, [r3, #0]
8001ba4: 4a12 ldr r2, [pc, #72] @ (8001bf0 <HAL_TIM_MspPostInit+0x68>)
8001ba6: 4293 cmp r3, r2
8001ba8: d11d bne.n 8001be6 <HAL_TIM_MspPostInit+0x5e>
{
/* USER CODE BEGIN TIM16_MspPostInit 0 */
/* USER CODE END TIM16_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001baa: 4b12 ldr r3, [pc, #72] @ (8001bf4 <HAL_TIM_MspPostInit+0x6c>)
8001bac: 6cdb ldr r3, [r3, #76] @ 0x4c
8001bae: 4a11 ldr r2, [pc, #68] @ (8001bf4 <HAL_TIM_MspPostInit+0x6c>)
8001bb0: f043 0301 orr.w r3, r3, #1
8001bb4: 64d3 str r3, [r2, #76] @ 0x4c
8001bb6: 4b0f ldr r3, [pc, #60] @ (8001bf4 <HAL_TIM_MspPostInit+0x6c>)
8001bb8: 6cdb ldr r3, [r3, #76] @ 0x4c
8001bba: f003 0301 and.w r3, r3, #1
8001bbe: 60bb str r3, [r7, #8]
8001bc0: 68bb ldr r3, [r7, #8]
/**TIM16 GPIO Configuration
PA12 ------> TIM16_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_12;
8001bc2: f44f 5380 mov.w r3, #4096 @ 0x1000
8001bc6: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bc8: 2302 movs r3, #2
8001bca: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bcc: 2300 movs r3, #0
8001bce: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001bd0: 2300 movs r3, #0
8001bd2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM16;
8001bd4: 2301 movs r3, #1
8001bd6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001bd8: f107 030c add.w r3, r7, #12
8001bdc: 4619 mov r1, r3
8001bde: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001be2: f001 ffe7 bl 8003bb4 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM16_MspPostInit 1 */
/* USER CODE END TIM16_MspPostInit 1 */
}
}
8001be6: bf00 nop
8001be8: 3720 adds r7, #32
8001bea: 46bd mov sp, r7
8001bec: bd80 pop {r7, pc}
8001bee: bf00 nop
8001bf0: 40014400 .word 0x40014400
8001bf4: 40021000 .word 0x40021000
08001bf8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001bf8: b580 push {r7, lr}
8001bfa: b09a sub sp, #104 @ 0x68
8001bfc: af00 add r7, sp, #0
8001bfe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001c00: f107 0354 add.w r3, r7, #84 @ 0x54
8001c04: 2200 movs r2, #0
8001c06: 601a str r2, [r3, #0]
8001c08: 605a str r2, [r3, #4]
8001c0a: 609a str r2, [r3, #8]
8001c0c: 60da str r2, [r3, #12]
8001c0e: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001c10: f107 0310 add.w r3, r7, #16
8001c14: 2244 movs r2, #68 @ 0x44
8001c16: 2100 movs r1, #0
8001c18: 4618 mov r0, r3
8001c1a: f006 fd37 bl 800868c <memset>
if(huart->Instance==USART2)
8001c1e: 687b ldr r3, [r7, #4]
8001c20: 681b ldr r3, [r3, #0]
8001c22: 4a23 ldr r2, [pc, #140] @ (8001cb0 <HAL_UART_MspInit+0xb8>)
8001c24: 4293 cmp r3, r2
8001c26: d13e bne.n 8001ca6 <HAL_UART_MspInit+0xae>
/* USER CODE END USART2_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
8001c28: 2302 movs r3, #2
8001c2a: 613b str r3, [r7, #16]
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
8001c2c: 2300 movs r3, #0
8001c2e: 61bb str r3, [r7, #24]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001c30: f107 0310 add.w r3, r7, #16
8001c34: 4618 mov r0, r3
8001c36: f002 ff39 bl 8004aac <HAL_RCCEx_PeriphCLKConfig>
8001c3a: 4603 mov r3, r0
8001c3c: 2b00 cmp r3, #0
8001c3e: d001 beq.n 8001c44 <HAL_UART_MspInit+0x4c>
{
Error_Handler();
8001c40: f7ff feb4 bl 80019ac <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
8001c44: 4b1b ldr r3, [pc, #108] @ (8001cb4 <HAL_UART_MspInit+0xbc>)
8001c46: 6d9b ldr r3, [r3, #88] @ 0x58
8001c48: 4a1a ldr r2, [pc, #104] @ (8001cb4 <HAL_UART_MspInit+0xbc>)
8001c4a: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001c4e: 6593 str r3, [r2, #88] @ 0x58
8001c50: 4b18 ldr r3, [pc, #96] @ (8001cb4 <HAL_UART_MspInit+0xbc>)
8001c52: 6d9b ldr r3, [r3, #88] @ 0x58
8001c54: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001c58: 60fb str r3, [r7, #12]
8001c5a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001c5c: 4b15 ldr r3, [pc, #84] @ (8001cb4 <HAL_UART_MspInit+0xbc>)
8001c5e: 6cdb ldr r3, [r3, #76] @ 0x4c
8001c60: 4a14 ldr r2, [pc, #80] @ (8001cb4 <HAL_UART_MspInit+0xbc>)
8001c62: f043 0301 orr.w r3, r3, #1
8001c66: 64d3 str r3, [r2, #76] @ 0x4c
8001c68: 4b12 ldr r3, [pc, #72] @ (8001cb4 <HAL_UART_MspInit+0xbc>)
8001c6a: 6cdb ldr r3, [r3, #76] @ 0x4c
8001c6c: f003 0301 and.w r3, r3, #1
8001c70: 60bb str r3, [r7, #8]
8001c72: 68bb ldr r3, [r7, #8]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin;
8001c74: 230c movs r3, #12
8001c76: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c78: 2302 movs r3, #2
8001c7a: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c7c: 2300 movs r3, #0
8001c7e: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001c80: 2300 movs r3, #0
8001c82: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8001c84: 2307 movs r3, #7
8001c86: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001c88: f107 0354 add.w r3, r7, #84 @ 0x54
8001c8c: 4619 mov r1, r3
8001c8e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001c92: f001 ff8f bl 8003bb4 <HAL_GPIO_Init>
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
8001c96: 2200 movs r2, #0
8001c98: 2100 movs r1, #0
8001c9a: 2026 movs r0, #38 @ 0x26
8001c9c: f001 fe95 bl 80039ca <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
8001ca0: 2026 movs r0, #38 @ 0x26
8001ca2: f001 feac bl 80039fe <HAL_NVIC_EnableIRQ>
/* USER CODE END USART2_MspInit 1 */
}
}
8001ca6: bf00 nop
8001ca8: 3768 adds r7, #104 @ 0x68
8001caa: 46bd mov sp, r7
8001cac: bd80 pop {r7, pc}
8001cae: bf00 nop
8001cb0: 40004400 .word 0x40004400
8001cb4: 40021000 .word 0x40021000
08001cb8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001cb8: b480 push {r7}
8001cba: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001cbc: bf00 nop
8001cbe: e7fd b.n 8001cbc <NMI_Handler+0x4>
08001cc0 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001cc0: b480 push {r7}
8001cc2: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001cc4: bf00 nop
8001cc6: e7fd b.n 8001cc4 <HardFault_Handler+0x4>
08001cc8 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001cc8: b480 push {r7}
8001cca: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001ccc: bf00 nop
8001cce: e7fd b.n 8001ccc <MemManage_Handler+0x4>
08001cd0 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001cd0: b480 push {r7}
8001cd2: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001cd4: bf00 nop
8001cd6: e7fd b.n 8001cd4 <BusFault_Handler+0x4>
08001cd8 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001cd8: b480 push {r7}
8001cda: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001cdc: bf00 nop
8001cde: e7fd b.n 8001cdc <UsageFault_Handler+0x4>
08001ce0 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001ce0: b480 push {r7}
8001ce2: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001ce4: bf00 nop
8001ce6: 46bd mov sp, r7
8001ce8: f85d 7b04 ldr.w r7, [sp], #4
8001cec: 4770 bx lr
08001cee <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001cee: b480 push {r7}
8001cf0: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001cf2: bf00 nop
8001cf4: 46bd mov sp, r7
8001cf6: f85d 7b04 ldr.w r7, [sp], #4
8001cfa: 4770 bx lr
08001cfc <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001cfc: b480 push {r7}
8001cfe: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001d00: bf00 nop
8001d02: 46bd mov sp, r7
8001d04: f85d 7b04 ldr.w r7, [sp], #4
8001d08: 4770 bx lr
08001d0a <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001d0a: b580 push {r7, lr}
8001d0c: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001d0e: f000 f8a5 bl 8001e5c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001d12: bf00 nop
8001d14: bd80 pop {r7, pc}
...
08001d18 <TIM2_IRQHandler>:
/**
* @brief This function handles TIM2 global interrupt.
*/
void TIM2_IRQHandler(void)
{
8001d18: b580 push {r7, lr}
8001d1a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_IRQn 0 */
/* USER CODE END TIM2_IRQn 0 */
HAL_TIM_IRQHandler(&htim2);
8001d1c: 4802 ldr r0, [pc, #8] @ (8001d28 <TIM2_IRQHandler+0x10>)
8001d1e: f003 fa6d bl 80051fc <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM2_IRQn 1 */
/* USER CODE END TIM2_IRQn 1 */
}
8001d22: bf00 nop
8001d24: bd80 pop {r7, pc}
8001d26: bf00 nop
8001d28: 2000011c .word 0x2000011c
08001d2c <USART2_IRQHandler>:
/**
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
*/
void USART2_IRQHandler(void)
{
8001d2c: b580 push {r7, lr}
8001d2e: af00 add r7, sp, #0
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
8001d30: 4802 ldr r0, [pc, #8] @ (8001d3c <USART2_IRQHandler+0x10>)
8001d32: f004 fcc5 bl 80066c0 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
8001d36: bf00 nop
8001d38: bd80 pop {r7, pc}
8001d3a: bf00 nop
8001d3c: 200001b4 .word 0x200001b4
08001d40 <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
8001d40: b480 push {r7}
8001d42: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
8001d44: 4b06 ldr r3, [pc, #24] @ (8001d60 <SystemInit+0x20>)
8001d46: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8001d4a: 4a05 ldr r2, [pc, #20] @ (8001d60 <SystemInit+0x20>)
8001d4c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8001d50: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001d54: bf00 nop
8001d56: 46bd mov sp, r7
8001d58: f85d 7b04 ldr.w r7, [sp], #4
8001d5c: 4770 bx lr
8001d5e: bf00 nop
8001d60: e000ed00 .word 0xe000ed00
08001d64 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8001d64: 480d ldr r0, [pc, #52] @ (8001d9c <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8001d66: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8001d68: f7ff ffea bl 8001d40 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001d6c: 480c ldr r0, [pc, #48] @ (8001da0 <LoopForever+0x6>)
ldr r1, =_edata
8001d6e: 490d ldr r1, [pc, #52] @ (8001da4 <LoopForever+0xa>)
ldr r2, =_sidata
8001d70: 4a0d ldr r2, [pc, #52] @ (8001da8 <LoopForever+0xe>)
movs r3, #0
8001d72: 2300 movs r3, #0
b LoopCopyDataInit
8001d74: e002 b.n 8001d7c <LoopCopyDataInit>
08001d76 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001d76: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001d78: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001d7a: 3304 adds r3, #4
08001d7c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001d7c: 18c4 adds r4, r0, r3
cmp r4, r1
8001d7e: 428c cmp r4, r1
bcc CopyDataInit
8001d80: d3f9 bcc.n 8001d76 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001d82: 4a0a ldr r2, [pc, #40] @ (8001dac <LoopForever+0x12>)
ldr r4, =_ebss
8001d84: 4c0a ldr r4, [pc, #40] @ (8001db0 <LoopForever+0x16>)
movs r3, #0
8001d86: 2300 movs r3, #0
b LoopFillZerobss
8001d88: e001 b.n 8001d8e <LoopFillZerobss>
08001d8a <FillZerobss>:
FillZerobss:
str r3, [r2]
8001d8a: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001d8c: 3204 adds r2, #4
08001d8e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001d8e: 42a2 cmp r2, r4
bcc FillZerobss
8001d90: d3fb bcc.n 8001d8a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001d92: f006 fc83 bl 800869c <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001d96: f7fe fedb bl 8000b50 <main>
08001d9a <LoopForever>:
LoopForever:
b LoopForever
8001d9a: e7fe b.n 8001d9a <LoopForever>
ldr r0, =_estack
8001d9c: 20008000 .word 0x20008000
ldr r0, =_sdata
8001da0: 20000000 .word 0x20000000
ldr r1, =_edata
8001da4: 20000028 .word 0x20000028
ldr r2, =_sidata
8001da8: 0800874c .word 0x0800874c
ldr r2, =_sbss
8001dac: 20000028 .word 0x20000028
ldr r4, =_ebss
8001db0: 200003cc .word 0x200003cc
08001db4 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001db4: e7fe b.n 8001db4 <ADC1_2_IRQHandler>
08001db6 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001db6: b580 push {r7, lr}
8001db8: b082 sub sp, #8
8001dba: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001dbc: 2300 movs r3, #0
8001dbe: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001dc0: 2003 movs r0, #3
8001dc2: f001 fdf7 bl 80039b4 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001dc6: 2000 movs r0, #0
8001dc8: f000 f80e bl 8001de8 <HAL_InitTick>
8001dcc: 4603 mov r3, r0
8001dce: 2b00 cmp r3, #0
8001dd0: d002 beq.n 8001dd8 <HAL_Init+0x22>
{
status = HAL_ERROR;
8001dd2: 2301 movs r3, #1
8001dd4: 71fb strb r3, [r7, #7]
8001dd6: e001 b.n 8001ddc <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001dd8: f7ff fdee bl 80019b8 <HAL_MspInit>
}
/* Return function status */
return status;
8001ddc: 79fb ldrb r3, [r7, #7]
}
8001dde: 4618 mov r0, r3
8001de0: 3708 adds r7, #8
8001de2: 46bd mov sp, r7
8001de4: bd80 pop {r7, pc}
...
08001de8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001de8: b580 push {r7, lr}
8001dea: b084 sub sp, #16
8001dec: af00 add r7, sp, #0
8001dee: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001df0: 2300 movs r3, #0
8001df2: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8001df4: 4b16 ldr r3, [pc, #88] @ (8001e50 <HAL_InitTick+0x68>)
8001df6: 681b ldr r3, [r3, #0]
8001df8: 2b00 cmp r3, #0
8001dfa: d022 beq.n 8001e42 <HAL_InitTick+0x5a>
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8001dfc: 4b15 ldr r3, [pc, #84] @ (8001e54 <HAL_InitTick+0x6c>)
8001dfe: 681a ldr r2, [r3, #0]
8001e00: 4b13 ldr r3, [pc, #76] @ (8001e50 <HAL_InitTick+0x68>)
8001e02: 681b ldr r3, [r3, #0]
8001e04: f44f 717a mov.w r1, #1000 @ 0x3e8
8001e08: fbb1 f3f3 udiv r3, r1, r3
8001e0c: fbb2 f3f3 udiv r3, r2, r3
8001e10: 4618 mov r0, r3
8001e12: f001 fe02 bl 8003a1a <HAL_SYSTICK_Config>
8001e16: 4603 mov r3, r0
8001e18: 2b00 cmp r3, #0
8001e1a: d10f bne.n 8001e3c <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001e1c: 687b ldr r3, [r7, #4]
8001e1e: 2b0f cmp r3, #15
8001e20: d809 bhi.n 8001e36 <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001e22: 2200 movs r2, #0
8001e24: 6879 ldr r1, [r7, #4]
8001e26: f04f 30ff mov.w r0, #4294967295
8001e2a: f001 fdce bl 80039ca <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001e2e: 4a0a ldr r2, [pc, #40] @ (8001e58 <HAL_InitTick+0x70>)
8001e30: 687b ldr r3, [r7, #4]
8001e32: 6013 str r3, [r2, #0]
8001e34: e007 b.n 8001e46 <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8001e36: 2301 movs r3, #1
8001e38: 73fb strb r3, [r7, #15]
8001e3a: e004 b.n 8001e46 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001e3c: 2301 movs r3, #1
8001e3e: 73fb strb r3, [r7, #15]
8001e40: e001 b.n 8001e46 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001e42: 2301 movs r3, #1
8001e44: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001e46: 7bfb ldrb r3, [r7, #15]
}
8001e48: 4618 mov r0, r3
8001e4a: 3710 adds r7, #16
8001e4c: 46bd mov sp, r7
8001e4e: bd80 pop {r7, pc}
8001e50: 20000024 .word 0x20000024
8001e54: 2000001c .word 0x2000001c
8001e58: 20000020 .word 0x20000020
08001e5c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001e5c: b480 push {r7}
8001e5e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001e60: 4b05 ldr r3, [pc, #20] @ (8001e78 <HAL_IncTick+0x1c>)
8001e62: 681a ldr r2, [r3, #0]
8001e64: 4b05 ldr r3, [pc, #20] @ (8001e7c <HAL_IncTick+0x20>)
8001e66: 681b ldr r3, [r3, #0]
8001e68: 4413 add r3, r2
8001e6a: 4a03 ldr r2, [pc, #12] @ (8001e78 <HAL_IncTick+0x1c>)
8001e6c: 6013 str r3, [r2, #0]
}
8001e6e: bf00 nop
8001e70: 46bd mov sp, r7
8001e72: f85d 7b04 ldr.w r7, [sp], #4
8001e76: 4770 bx lr
8001e78: 200003c8 .word 0x200003c8
8001e7c: 20000024 .word 0x20000024
08001e80 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001e80: b480 push {r7}
8001e82: af00 add r7, sp, #0
return uwTick;
8001e84: 4b03 ldr r3, [pc, #12] @ (8001e94 <HAL_GetTick+0x14>)
8001e86: 681b ldr r3, [r3, #0]
}
8001e88: 4618 mov r0, r3
8001e8a: 46bd mov sp, r7
8001e8c: f85d 7b04 ldr.w r7, [sp], #4
8001e90: 4770 bx lr
8001e92: bf00 nop
8001e94: 200003c8 .word 0x200003c8
08001e98 <LL_ADC_SetCommonClock>:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
8001e98: b480 push {r7}
8001e9a: b083 sub sp, #12
8001e9c: af00 add r7, sp, #0
8001e9e: 6078 str r0, [r7, #4]
8001ea0: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 689b ldr r3, [r3, #8]
8001ea6: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000
8001eaa: 683b ldr r3, [r7, #0]
8001eac: 431a orrs r2, r3
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 609a str r2, [r3, #8]
}
8001eb2: bf00 nop
8001eb4: 370c adds r7, #12
8001eb6: 46bd mov sp, r7
8001eb8: f85d 7b04 ldr.w r7, [sp], #4
8001ebc: 4770 bx lr
08001ebe <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
8001ebe: b480 push {r7}
8001ec0: b083 sub sp, #12
8001ec2: af00 add r7, sp, #0
8001ec4: 6078 str r0, [r7, #4]
8001ec6: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
8001ec8: 687b ldr r3, [r7, #4]
8001eca: 689b ldr r3, [r3, #8]
8001ecc: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000
8001ed0: 683b ldr r3, [r7, #0]
8001ed2: 431a orrs r2, r3
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 609a str r2, [r3, #8]
}
8001ed8: bf00 nop
8001eda: 370c adds r7, #12
8001edc: 46bd mov sp, r7
8001ede: f85d 7b04 ldr.w r7, [sp], #4
8001ee2: 4770 bx lr
08001ee4 <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8001ee4: b480 push {r7}
8001ee6: b083 sub sp, #12
8001ee8: af00 add r7, sp, #0
8001eea: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
8001eec: 687b ldr r3, [r7, #4]
8001eee: 689b ldr r3, [r3, #8]
8001ef0: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000
}
8001ef4: 4618 mov r0, r3
8001ef6: 370c adds r7, #12
8001ef8: 46bd mov sp, r7
8001efa: f85d 7b04 ldr.w r7, [sp], #4
8001efe: 4770 bx lr
08001f00 <LL_ADC_SetOffset>:
* (fADC) to convert in 12-bit resolution.\n
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
8001f00: b480 push {r7}
8001f02: b087 sub sp, #28
8001f04: af00 add r7, sp, #0
8001f06: 60f8 str r0, [r7, #12]
8001f08: 60b9 str r1, [r7, #8]
8001f0a: 607a str r2, [r7, #4]
8001f0c: 603b str r3, [r7, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001f0e: 68fb ldr r3, [r7, #12]
8001f10: 3360 adds r3, #96 @ 0x60
8001f12: 461a mov r2, r3
8001f14: 68bb ldr r3, [r7, #8]
8001f16: 009b lsls r3, r3, #2
8001f18: 4413 add r3, r2
8001f1a: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001f1c: 697b ldr r3, [r7, #20]
8001f1e: 681a ldr r2, [r3, #0]
8001f20: 4b08 ldr r3, [pc, #32] @ (8001f44 <LL_ADC_SetOffset+0x44>)
8001f22: 4013 ands r3, r2
8001f24: 687a ldr r2, [r7, #4]
8001f26: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000
8001f2a: 683a ldr r2, [r7, #0]
8001f2c: 430a orrs r2, r1
8001f2e: 4313 orrs r3, r2
8001f30: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
8001f34: 697b ldr r3, [r7, #20]
8001f36: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
}
8001f38: bf00 nop
8001f3a: 371c adds r7, #28
8001f3c: 46bd mov sp, r7
8001f3e: f85d 7b04 ldr.w r7, [sp], #4
8001f42: 4770 bx lr
8001f44: 03fff000 .word 0x03fff000
08001f48 <LL_ADC_GetOffsetChannel>:
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
8001f48: b480 push {r7}
8001f4a: b085 sub sp, #20
8001f4c: af00 add r7, sp, #0
8001f4e: 6078 str r0, [r7, #4]
8001f50: 6039 str r1, [r7, #0]
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001f52: 687b ldr r3, [r7, #4]
8001f54: 3360 adds r3, #96 @ 0x60
8001f56: 461a mov r2, r3
8001f58: 683b ldr r3, [r7, #0]
8001f5a: 009b lsls r3, r3, #2
8001f5c: 4413 add r3, r2
8001f5e: 60fb str r3, [r7, #12]
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
8001f60: 68fb ldr r3, [r7, #12]
8001f62: 681b ldr r3, [r3, #0]
8001f64: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
}
8001f68: 4618 mov r0, r3
8001f6a: 3714 adds r7, #20
8001f6c: 46bd mov sp, r7
8001f6e: f85d 7b04 ldr.w r7, [sp], #4
8001f72: 4770 bx lr
08001f74 <LL_ADC_SetOffsetState>:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
8001f74: b480 push {r7}
8001f76: b087 sub sp, #28
8001f78: af00 add r7, sp, #0
8001f7a: 60f8 str r0, [r7, #12]
8001f7c: 60b9 str r1, [r7, #8]
8001f7e: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001f80: 68fb ldr r3, [r7, #12]
8001f82: 3360 adds r3, #96 @ 0x60
8001f84: 461a mov r2, r3
8001f86: 68bb ldr r3, [r7, #8]
8001f88: 009b lsls r3, r3, #2
8001f8a: 4413 add r3, r2
8001f8c: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001f8e: 697b ldr r3, [r7, #20]
8001f90: 681b ldr r3, [r3, #0]
8001f92: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8001f96: 687b ldr r3, [r7, #4]
8001f98: 431a orrs r2, r3
8001f9a: 697b ldr r3, [r7, #20]
8001f9c: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN,
OffsetState);
}
8001f9e: bf00 nop
8001fa0: 371c adds r7, #28
8001fa2: 46bd mov sp, r7
8001fa4: f85d 7b04 ldr.w r7, [sp], #4
8001fa8: 4770 bx lr
08001faa <LL_ADC_SetOffsetSign>:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
8001faa: b480 push {r7}
8001fac: b087 sub sp, #28
8001fae: af00 add r7, sp, #0
8001fb0: 60f8 str r0, [r7, #12]
8001fb2: 60b9 str r1, [r7, #8]
8001fb4: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001fb6: 68fb ldr r3, [r7, #12]
8001fb8: 3360 adds r3, #96 @ 0x60
8001fba: 461a mov r2, r3
8001fbc: 68bb ldr r3, [r7, #8]
8001fbe: 009b lsls r3, r3, #2
8001fc0: 4413 add r3, r2
8001fc2: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001fc4: 697b ldr r3, [r7, #20]
8001fc6: 681b ldr r3, [r3, #0]
8001fc8: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
8001fcc: 687b ldr r3, [r7, #4]
8001fce: 431a orrs r2, r3
8001fd0: 697b ldr r3, [r7, #20]
8001fd2: 601a str r2, [r3, #0]
ADC_OFR1_OFFSETPOS,
OffsetSign);
}
8001fd4: bf00 nop
8001fd6: 371c adds r7, #28
8001fd8: 46bd mov sp, r7
8001fda: f85d 7b04 ldr.w r7, [sp], #4
8001fde: 4770 bx lr
08001fe0 <LL_ADC_SetOffsetSaturation>:
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
{
8001fe0: b480 push {r7}
8001fe2: b087 sub sp, #28
8001fe4: af00 add r7, sp, #0
8001fe6: 60f8 str r0, [r7, #12]
8001fe8: 60b9 str r1, [r7, #8]
8001fea: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001fec: 68fb ldr r3, [r7, #12]
8001fee: 3360 adds r3, #96 @ 0x60
8001ff0: 461a mov r2, r3
8001ff2: 68bb ldr r3, [r7, #8]
8001ff4: 009b lsls r3, r3, #2
8001ff6: 4413 add r3, r2
8001ff8: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001ffa: 697b ldr r3, [r7, #20]
8001ffc: 681b ldr r3, [r3, #0]
8001ffe: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
8002002: 687b ldr r3, [r7, #4]
8002004: 431a orrs r2, r3
8002006: 697b ldr r3, [r7, #20]
8002008: 601a str r2, [r3, #0]
ADC_OFR1_SATEN,
OffsetSaturation);
}
800200a: bf00 nop
800200c: 371c adds r7, #28
800200e: 46bd mov sp, r7
8002010: f85d 7b04 ldr.w r7, [sp], #4
8002014: 4770 bx lr
08002016 <LL_ADC_SetSamplingTimeCommonConfig>:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
{
8002016: b480 push {r7}
8002018: b083 sub sp, #12
800201a: af00 add r7, sp, #0
800201c: 6078 str r0, [r7, #4]
800201e: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
8002020: 687b ldr r3, [r7, #4]
8002022: 695b ldr r3, [r3, #20]
8002024: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8002028: 683b ldr r3, [r7, #0]
800202a: 431a orrs r2, r3
800202c: 687b ldr r3, [r7, #4]
800202e: 615a str r2, [r3, #20]
}
8002030: bf00 nop
8002032: 370c adds r7, #12
8002034: 46bd mov sp, r7
8002036: f85d 7b04 ldr.w r7, [sp], #4
800203a: 4770 bx lr
0800203c <LL_ADC_REG_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
{
800203c: b480 push {r7}
800203e: b083 sub sp, #12
8002040: af00 add r7, sp, #0
8002042: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
8002044: 687b ldr r3, [r7, #4]
8002046: 68db ldr r3, [r3, #12]
8002048: f403 6340 and.w r3, r3, #3072 @ 0xc00
800204c: 2b00 cmp r3, #0
800204e: d101 bne.n 8002054 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
8002050: 2301 movs r3, #1
8002052: e000 b.n 8002056 <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
8002054: 2300 movs r3, #0
}
8002056: 4618 mov r0, r3
8002058: 370c adds r7, #12
800205a: 46bd mov sp, r7
800205c: f85d 7b04 ldr.w r7, [sp], #4
8002060: 4770 bx lr
08002062 <LL_ADC_REG_SetSequencerRanks>:
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
* (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
8002062: b480 push {r7}
8002064: b087 sub sp, #28
8002066: af00 add r7, sp, #0
8002068: 60f8 str r0, [r7, #12]
800206a: 60b9 str r1, [r7, #8]
800206c: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
800206e: 68fb ldr r3, [r7, #12]
8002070: 3330 adds r3, #48 @ 0x30
8002072: 461a mov r2, r3
8002074: 68bb ldr r3, [r7, #8]
8002076: 0a1b lsrs r3, r3, #8
8002078: 009b lsls r3, r3, #2
800207a: f003 030c and.w r3, r3, #12
800207e: 4413 add r3, r2
8002080: 617b str r3, [r7, #20]
((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
8002082: 697b ldr r3, [r7, #20]
8002084: 681a ldr r2, [r3, #0]
8002086: 68bb ldr r3, [r7, #8]
8002088: f003 031f and.w r3, r3, #31
800208c: 211f movs r1, #31
800208e: fa01 f303 lsl.w r3, r1, r3
8002092: 43db mvns r3, r3
8002094: 401a ands r2, r3
8002096: 687b ldr r3, [r7, #4]
8002098: 0e9b lsrs r3, r3, #26
800209a: f003 011f and.w r1, r3, #31
800209e: 68bb ldr r3, [r7, #8]
80020a0: f003 031f and.w r3, r3, #31
80020a4: fa01 f303 lsl.w r3, r1, r3
80020a8: 431a orrs r2, r3
80020aa: 697b ldr r3, [r7, #20]
80020ac: 601a str r2, [r3, #0]
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<< (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
80020ae: bf00 nop
80020b0: 371c adds r7, #28
80020b2: 46bd mov sp, r7
80020b4: f85d 7b04 ldr.w r7, [sp], #4
80020b8: 4770 bx lr
080020ba <LL_ADC_SetChannelSamplingTime>:
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
80020ba: b480 push {r7}
80020bc: b087 sub sp, #28
80020be: af00 add r7, sp, #0
80020c0: 60f8 str r0, [r7, #12]
80020c2: 60b9 str r1, [r7, #8]
80020c4: 607a str r2, [r7, #4]
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
80020c6: 68fb ldr r3, [r7, #12]
80020c8: 3314 adds r3, #20
80020ca: 461a mov r2, r3
80020cc: 68bb ldr r3, [r7, #8]
80020ce: 0e5b lsrs r3, r3, #25
80020d0: 009b lsls r3, r3, #2
80020d2: f003 0304 and.w r3, r3, #4
80020d6: 4413 add r3, r2
80020d8: 617b str r3, [r7, #20]
((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
80020da: 697b ldr r3, [r7, #20]
80020dc: 681a ldr r2, [r3, #0]
80020de: 68bb ldr r3, [r7, #8]
80020e0: 0d1b lsrs r3, r3, #20
80020e2: f003 031f and.w r3, r3, #31
80020e6: 2107 movs r1, #7
80020e8: fa01 f303 lsl.w r3, r1, r3
80020ec: 43db mvns r3, r3
80020ee: 401a ands r2, r3
80020f0: 68bb ldr r3, [r7, #8]
80020f2: 0d1b lsrs r3, r3, #20
80020f4: f003 031f and.w r3, r3, #31
80020f8: 6879 ldr r1, [r7, #4]
80020fa: fa01 f303 lsl.w r3, r1, r3
80020fe: 431a orrs r2, r3
8002100: 697b ldr r3, [r7, #20]
8002102: 601a str r2, [r3, #0]
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
8002104: bf00 nop
8002106: 371c adds r7, #28
8002108: 46bd mov sp, r7
800210a: f85d 7b04 ldr.w r7, [sp], #4
800210e: 4770 bx lr
08002110 <LL_ADC_SetChannelSingleDiff>:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
8002110: b480 push {r7}
8002112: b085 sub sp, #20
8002114: af00 add r7, sp, #0
8002116: 60f8 str r0, [r7, #12]
8002118: 60b9 str r1, [r7, #8]
800211a: 607a str r2, [r7, #4]
/* Bits of channels in single or differential mode are set only for */
/* differential mode (for single mode, mask of bits allowed to be set is */
/* shifted out of range of bits of channels in single or differential mode. */
MODIFY_REG(ADCx->DIFSEL,
800211c: 68fb ldr r3, [r7, #12]
800211e: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0
8002122: 68bb ldr r3, [r7, #8]
8002124: f3c3 0312 ubfx r3, r3, #0, #19
8002128: 43db mvns r3, r3
800212a: 401a ands r2, r3
800212c: 687b ldr r3, [r7, #4]
800212e: f003 0318 and.w r3, r3, #24
8002132: 4908 ldr r1, [pc, #32] @ (8002154 <LL_ADC_SetChannelSingleDiff+0x44>)
8002134: 40d9 lsrs r1, r3
8002136: 68bb ldr r3, [r7, #8]
8002138: 400b ands r3, r1
800213a: f3c3 0312 ubfx r3, r3, #0, #19
800213e: 431a orrs r2, r3
8002140: 68fb ldr r3, [r7, #12]
8002142: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
& (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
}
8002146: bf00 nop
8002148: 3714 adds r7, #20
800214a: 46bd mov sp, r7
800214c: f85d 7b04 ldr.w r7, [sp], #4
8002150: 4770 bx lr
8002152: bf00 nop
8002154: 0007ffff .word 0x0007ffff
08002158 <LL_ADC_GetMultimode>:
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8002158: b480 push {r7}
800215a: b083 sub sp, #12
800215c: af00 add r7, sp, #0
800215e: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
8002160: 687b ldr r3, [r7, #4]
8002162: 689b ldr r3, [r3, #8]
8002164: f003 031f and.w r3, r3, #31
}
8002168: 4618 mov r0, r3
800216a: 370c adds r7, #12
800216c: 46bd mov sp, r7
800216e: f85d 7b04 ldr.w r7, [sp], #4
8002172: 4770 bx lr
08002174 <LL_ADC_GetMultiDMATransfer>:
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8002174: b480 push {r7}
8002176: b083 sub sp, #12
8002178: af00 add r7, sp, #0
800217a: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
800217c: 687b ldr r3, [r7, #4]
800217e: 689b ldr r3, [r3, #8]
8002180: f403 4360 and.w r3, r3, #57344 @ 0xe000
}
8002184: 4618 mov r0, r3
8002186: 370c adds r7, #12
8002188: 46bd mov sp, r7
800218a: f85d 7b04 ldr.w r7, [sp], #4
800218e: 4770 bx lr
08002190 <LL_ADC_DisableDeepPowerDown>:
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
8002190: b480 push {r7}
8002192: b083 sub sp, #12
8002194: af00 add r7, sp, #0
8002196: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
8002198: 687b ldr r3, [r7, #4]
800219a: 689b ldr r3, [r3, #8]
800219c: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000
80021a0: f023 033f bic.w r3, r3, #63 @ 0x3f
80021a4: 687a ldr r2, [r7, #4]
80021a6: 6093 str r3, [r2, #8]
}
80021a8: bf00 nop
80021aa: 370c adds r7, #12
80021ac: 46bd mov sp, r7
80021ae: f85d 7b04 ldr.w r7, [sp], #4
80021b2: 4770 bx lr
080021b4 <LL_ADC_IsDeepPowerDownEnabled>:
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
{
80021b4: b480 push {r7}
80021b6: b083 sub sp, #12
80021b8: af00 add r7, sp, #0
80021ba: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
80021bc: 687b ldr r3, [r7, #4]
80021be: 689b ldr r3, [r3, #8]
80021c0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80021c4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80021c8: d101 bne.n 80021ce <LL_ADC_IsDeepPowerDownEnabled+0x1a>
80021ca: 2301 movs r3, #1
80021cc: e000 b.n 80021d0 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
80021ce: 2300 movs r3, #0
}
80021d0: 4618 mov r0, r3
80021d2: 370c adds r7, #12
80021d4: 46bd mov sp, r7
80021d6: f85d 7b04 ldr.w r7, [sp], #4
80021da: 4770 bx lr
080021dc <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
80021dc: b480 push {r7}
80021de: b083 sub sp, #12
80021e0: af00 add r7, sp, #0
80021e2: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
80021e4: 687b ldr r3, [r7, #4]
80021e6: 689b ldr r3, [r3, #8]
80021e8: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000
80021ec: f023 033f bic.w r3, r3, #63 @ 0x3f
80021f0: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000
80021f4: 687b ldr r3, [r7, #4]
80021f6: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
80021f8: bf00 nop
80021fa: 370c adds r7, #12
80021fc: 46bd mov sp, r7
80021fe: f85d 7b04 ldr.w r7, [sp], #4
8002202: 4770 bx lr
08002204 <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
{
8002204: b480 push {r7}
8002206: b083 sub sp, #12
8002208: af00 add r7, sp, #0
800220a: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
800220c: 687b ldr r3, [r7, #4]
800220e: 689b ldr r3, [r3, #8]
8002210: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002214: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8002218: d101 bne.n 800221e <LL_ADC_IsInternalRegulatorEnabled+0x1a>
800221a: 2301 movs r3, #1
800221c: e000 b.n 8002220 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
800221e: 2300 movs r3, #0
}
8002220: 4618 mov r0, r3
8002222: 370c adds r7, #12
8002224: 46bd mov sp, r7
8002226: f85d 7b04 ldr.w r7, [sp], #4
800222a: 4770 bx lr
0800222c <LL_ADC_Enable>:
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
800222c: b480 push {r7}
800222e: b083 sub sp, #12
8002230: af00 add r7, sp, #0
8002232: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8002234: 687b ldr r3, [r7, #4]
8002236: 689b ldr r3, [r3, #8]
8002238: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
800223c: f023 033f bic.w r3, r3, #63 @ 0x3f
8002240: f043 0201 orr.w r2, r3, #1
8002244: 687b ldr r3, [r7, #4]
8002246: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
8002248: bf00 nop
800224a: 370c adds r7, #12
800224c: 46bd mov sp, r7
800224e: f85d 7b04 ldr.w r7, [sp], #4
8002252: 4770 bx lr
08002254 <LL_ADC_Disable>:
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
8002254: b480 push {r7}
8002256: b083 sub sp, #12
8002258: af00 add r7, sp, #0
800225a: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
800225c: 687b ldr r3, [r7, #4]
800225e: 689b ldr r3, [r3, #8]
8002260: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8002264: f023 033f bic.w r3, r3, #63 @ 0x3f
8002268: f043 0202 orr.w r2, r3, #2
800226c: 687b ldr r3, [r7, #4]
800226e: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADDIS);
}
8002270: bf00 nop
8002272: 370c adds r7, #12
8002274: 46bd mov sp, r7
8002276: f85d 7b04 ldr.w r7, [sp], #4
800227a: 4770 bx lr
0800227c <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
{
800227c: b480 push {r7}
800227e: b083 sub sp, #12
8002280: af00 add r7, sp, #0
8002282: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8002284: 687b ldr r3, [r7, #4]
8002286: 689b ldr r3, [r3, #8]
8002288: f003 0301 and.w r3, r3, #1
800228c: 2b01 cmp r3, #1
800228e: d101 bne.n 8002294 <LL_ADC_IsEnabled+0x18>
8002290: 2301 movs r3, #1
8002292: e000 b.n 8002296 <LL_ADC_IsEnabled+0x1a>
8002294: 2300 movs r3, #0
}
8002296: 4618 mov r0, r3
8002298: 370c adds r7, #12
800229a: 46bd mov sp, r7
800229c: f85d 7b04 ldr.w r7, [sp], #4
80022a0: 4770 bx lr
080022a2 <LL_ADC_IsDisableOngoing>:
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
{
80022a2: b480 push {r7}
80022a4: b083 sub sp, #12
80022a6: af00 add r7, sp, #0
80022a8: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
80022aa: 687b ldr r3, [r7, #4]
80022ac: 689b ldr r3, [r3, #8]
80022ae: f003 0302 and.w r3, r3, #2
80022b2: 2b02 cmp r3, #2
80022b4: d101 bne.n 80022ba <LL_ADC_IsDisableOngoing+0x18>
80022b6: 2301 movs r3, #1
80022b8: e000 b.n 80022bc <LL_ADC_IsDisableOngoing+0x1a>
80022ba: 2300 movs r3, #0
}
80022bc: 4618 mov r0, r3
80022be: 370c adds r7, #12
80022c0: 46bd mov sp, r7
80022c2: f85d 7b04 ldr.w r7, [sp], #4
80022c6: 4770 bx lr
080022c8 <LL_ADC_REG_StartConversion>:
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
80022c8: b480 push {r7}
80022ca: b083 sub sp, #12
80022cc: af00 add r7, sp, #0
80022ce: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
80022d0: 687b ldr r3, [r7, #4]
80022d2: 689b ldr r3, [r3, #8]
80022d4: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
80022d8: f023 033f bic.w r3, r3, #63 @ 0x3f
80022dc: f043 0204 orr.w r2, r3, #4
80022e0: 687b ldr r3, [r7, #4]
80022e2: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
80022e4: bf00 nop
80022e6: 370c adds r7, #12
80022e8: 46bd mov sp, r7
80022ea: f85d 7b04 ldr.w r7, [sp], #4
80022ee: 4770 bx lr
080022f0 <LL_ADC_REG_StopConversion>:
* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
{
80022f0: b480 push {r7}
80022f2: b083 sub sp, #12
80022f4: af00 add r7, sp, #0
80022f6: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
80022f8: 687b ldr r3, [r7, #4]
80022fa: 689b ldr r3, [r3, #8]
80022fc: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8002300: f023 033f bic.w r3, r3, #63 @ 0x3f
8002304: f043 0210 orr.w r2, r3, #16
8002308: 687b ldr r3, [r7, #4]
800230a: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTP);
}
800230c: bf00 nop
800230e: 370c adds r7, #12
8002310: 46bd mov sp, r7
8002312: f85d 7b04 ldr.w r7, [sp], #4
8002316: 4770 bx lr
08002318 <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
8002318: b480 push {r7}
800231a: b083 sub sp, #12
800231c: af00 add r7, sp, #0
800231e: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8002320: 687b ldr r3, [r7, #4]
8002322: 689b ldr r3, [r3, #8]
8002324: f003 0304 and.w r3, r3, #4
8002328: 2b04 cmp r3, #4
800232a: d101 bne.n 8002330 <LL_ADC_REG_IsConversionOngoing+0x18>
800232c: 2301 movs r3, #1
800232e: e000 b.n 8002332 <LL_ADC_REG_IsConversionOngoing+0x1a>
8002330: 2300 movs r3, #0
}
8002332: 4618 mov r0, r3
8002334: 370c adds r7, #12
8002336: 46bd mov sp, r7
8002338: f85d 7b04 ldr.w r7, [sp], #4
800233c: 4770 bx lr
0800233e <LL_ADC_INJ_StopConversion>:
* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
{
800233e: b480 push {r7}
8002340: b083 sub sp, #12
8002342: af00 add r7, sp, #0
8002344: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8002346: 687b ldr r3, [r7, #4]
8002348: 689b ldr r3, [r3, #8]
800234a: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
800234e: f023 033f bic.w r3, r3, #63 @ 0x3f
8002352: f043 0220 orr.w r2, r3, #32
8002356: 687b ldr r3, [r7, #4]
8002358: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_JADSTP);
}
800235a: bf00 nop
800235c: 370c adds r7, #12
800235e: 46bd mov sp, r7
8002360: f85d 7b04 ldr.w r7, [sp], #4
8002364: 4770 bx lr
08002366 <LL_ADC_INJ_IsConversionOngoing>:
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
8002366: b480 push {r7}
8002368: b083 sub sp, #12
800236a: af00 add r7, sp, #0
800236c: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
800236e: 687b ldr r3, [r7, #4]
8002370: 689b ldr r3, [r3, #8]
8002372: f003 0308 and.w r3, r3, #8
8002376: 2b08 cmp r3, #8
8002378: d101 bne.n 800237e <LL_ADC_INJ_IsConversionOngoing+0x18>
800237a: 2301 movs r3, #1
800237c: e000 b.n 8002380 <LL_ADC_INJ_IsConversionOngoing+0x1a>
800237e: 2300 movs r3, #0
}
8002380: 4618 mov r0, r3
8002382: 370c adds r7, #12
8002384: 46bd mov sp, r7
8002386: f85d 7b04 ldr.w r7, [sp], #4
800238a: 4770 bx lr
0800238c <HAL_ADC_Init>:
* without disabling the other ADCs.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
800238c: b590 push {r4, r7, lr}
800238e: b089 sub sp, #36 @ 0x24
8002390: af00 add r7, sp, #0
8002392: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002394: 2300 movs r3, #0
8002396: 77fb strb r3, [r7, #31]
uint32_t tmp_cfgr;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0UL;
8002398: 2300 movs r3, #0
800239a: 60fb str r3, [r7, #12]
/* Check ADC handle */
if (hadc == NULL)
800239c: 687b ldr r3, [r7, #4]
800239e: 2b00 cmp r3, #0
80023a0: d101 bne.n 80023a6 <HAL_ADC_Init+0x1a>
{
return HAL_ERROR;
80023a2: 2301 movs r3, #1
80023a4: e167 b.n 8002676 <HAL_ADC_Init+0x2ea>
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
80023a6: 687b ldr r3, [r7, #4]
80023a8: 695b ldr r3, [r3, #20]
80023aa: 2b00 cmp r3, #0
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
80023ac: 687b ldr r3, [r7, #4]
80023ae: 6ddb ldr r3, [r3, #92] @ 0x5c
80023b0: 2b00 cmp r3, #0
80023b2: d109 bne.n 80023c8 <HAL_ADC_Init+0x3c>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80023b4: 6878 ldr r0, [r7, #4]
80023b6: f7ff fb23 bl 8001a00 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
80023ba: 687b ldr r3, [r7, #4]
80023bc: 2200 movs r2, #0
80023be: 661a str r2, [r3, #96] @ 0x60
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
80023c0: 687b ldr r3, [r7, #4]
80023c2: 2200 movs r2, #0
80023c4: f883 2058 strb.w r2, [r3, #88] @ 0x58
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
80023c8: 687b ldr r3, [r7, #4]
80023ca: 681b ldr r3, [r3, #0]
80023cc: 4618 mov r0, r3
80023ce: f7ff fef1 bl 80021b4 <LL_ADC_IsDeepPowerDownEnabled>
80023d2: 4603 mov r3, r0
80023d4: 2b00 cmp r3, #0
80023d6: d004 beq.n 80023e2 <HAL_ADC_Init+0x56>
{
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
80023d8: 687b ldr r3, [r7, #4]
80023da: 681b ldr r3, [r3, #0]
80023dc: 4618 mov r0, r3
80023de: f7ff fed7 bl 8002190 <LL_ADC_DisableDeepPowerDown>
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
80023e2: 687b ldr r3, [r7, #4]
80023e4: 681b ldr r3, [r3, #0]
80023e6: 4618 mov r0, r3
80023e8: f7ff ff0c bl 8002204 <LL_ADC_IsInternalRegulatorEnabled>
80023ec: 4603 mov r3, r0
80023ee: 2b00 cmp r3, #0
80023f0: d115 bne.n 800241e <HAL_ADC_Init+0x92>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
80023f2: 687b ldr r3, [r7, #4]
80023f4: 681b ldr r3, [r3, #0]
80023f6: 4618 mov r0, r3
80023f8: f7ff fef0 bl 80021dc <LL_ADC_EnableInternalRegulator>
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
80023fc: 4ba0 ldr r3, [pc, #640] @ (8002680 <HAL_ADC_Init+0x2f4>)
80023fe: 681b ldr r3, [r3, #0]
8002400: 099b lsrs r3, r3, #6
8002402: 4aa0 ldr r2, [pc, #640] @ (8002684 <HAL_ADC_Init+0x2f8>)
8002404: fba2 2303 umull r2, r3, r2, r3
8002408: 099b lsrs r3, r3, #6
800240a: 3301 adds r3, #1
800240c: 005b lsls r3, r3, #1
800240e: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002410: e002 b.n 8002418 <HAL_ADC_Init+0x8c>
{
wait_loop_index--;
8002412: 68fb ldr r3, [r7, #12]
8002414: 3b01 subs r3, #1
8002416: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002418: 68fb ldr r3, [r7, #12]
800241a: 2b00 cmp r3, #0
800241c: d1f9 bne.n 8002412 <HAL_ADC_Init+0x86>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
800241e: 687b ldr r3, [r7, #4]
8002420: 681b ldr r3, [r3, #0]
8002422: 4618 mov r0, r3
8002424: f7ff feee bl 8002204 <LL_ADC_IsInternalRegulatorEnabled>
8002428: 4603 mov r3, r0
800242a: 2b00 cmp r3, #0
800242c: d10d bne.n 800244a <HAL_ADC_Init+0xbe>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800242e: 687b ldr r3, [r7, #4]
8002430: 6ddb ldr r3, [r3, #92] @ 0x5c
8002432: f043 0210 orr.w r2, r3, #16
8002436: 687b ldr r3, [r7, #4]
8002438: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800243a: 687b ldr r3, [r7, #4]
800243c: 6e1b ldr r3, [r3, #96] @ 0x60
800243e: f043 0201 orr.w r2, r3, #1
8002442: 687b ldr r3, [r7, #4]
8002444: 661a str r2, [r3, #96] @ 0x60
tmp_hal_status = HAL_ERROR;
8002446: 2301 movs r3, #1
8002448: 77fb strb r3, [r7, #31]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
800244a: 687b ldr r3, [r7, #4]
800244c: 681b ldr r3, [r3, #0]
800244e: 4618 mov r0, r3
8002450: f7ff ff62 bl 8002318 <LL_ADC_REG_IsConversionOngoing>
8002454: 6178 str r0, [r7, #20]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8002456: 687b ldr r3, [r7, #4]
8002458: 6ddb ldr r3, [r3, #92] @ 0x5c
800245a: f003 0310 and.w r3, r3, #16
800245e: 2b00 cmp r3, #0
8002460: f040 8100 bne.w 8002664 <HAL_ADC_Init+0x2d8>
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
8002464: 697b ldr r3, [r7, #20]
8002466: 2b00 cmp r3, #0
8002468: f040 80fc bne.w 8002664 <HAL_ADC_Init+0x2d8>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800246c: 687b ldr r3, [r7, #4]
800246e: 6ddb ldr r3, [r3, #92] @ 0x5c
8002470: f423 7381 bic.w r3, r3, #258 @ 0x102
8002474: f043 0202 orr.w r2, r3, #2
8002478: 687b ldr r3, [r7, #4]
800247a: 65da str r2, [r3, #92] @ 0x5c
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
800247c: 687b ldr r3, [r7, #4]
800247e: 681b ldr r3, [r3, #0]
8002480: 4618 mov r0, r3
8002482: f7ff fefb bl 800227c <LL_ADC_IsEnabled>
8002486: 4603 mov r3, r0
8002488: 2b00 cmp r3, #0
800248a: d111 bne.n 80024b0 <HAL_ADC_Init+0x124>
{
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
800248c: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
8002490: f7ff fef4 bl 800227c <LL_ADC_IsEnabled>
8002494: 4604 mov r4, r0
8002496: 487c ldr r0, [pc, #496] @ (8002688 <HAL_ADC_Init+0x2fc>)
8002498: f7ff fef0 bl 800227c <LL_ADC_IsEnabled>
800249c: 4603 mov r3, r0
800249e: 4323 orrs r3, r4
80024a0: 2b00 cmp r3, #0
80024a2: d105 bne.n 80024b0 <HAL_ADC_Init+0x124>
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
/* HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
80024a4: 687b ldr r3, [r7, #4]
80024a6: 685b ldr r3, [r3, #4]
80024a8: 4619 mov r1, r3
80024aa: 4878 ldr r0, [pc, #480] @ (800268c <HAL_ADC_Init+0x300>)
80024ac: f7ff fcf4 bl 8001e98 <LL_ADC_SetCommonClock>
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* - continuous conversion mode Init.ContinuousConvMode */
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80024b0: 687b ldr r3, [r7, #4]
80024b2: 7f5b ldrb r3, [r3, #29]
80024b4: 035a lsls r2, r3, #13
hadc->Init.Overrun |
80024b6: 687b ldr r3, [r7, #4]
80024b8: 6bdb ldr r3, [r3, #60] @ 0x3c
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80024ba: 431a orrs r2, r3
hadc->Init.DataAlign |
80024bc: 687b ldr r3, [r7, #4]
80024be: 68db ldr r3, [r3, #12]
hadc->Init.Overrun |
80024c0: 431a orrs r2, r3
hadc->Init.Resolution |
80024c2: 687b ldr r3, [r7, #4]
80024c4: 689b ldr r3, [r3, #8]
hadc->Init.DataAlign |
80024c6: 431a orrs r2, r3
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
80024c8: 687b ldr r3, [r7, #4]
80024ca: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80024ce: 041b lsls r3, r3, #16
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80024d0: 4313 orrs r3, r2
80024d2: 61bb str r3, [r7, #24]
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80024d4: 687b ldr r3, [r7, #4]
80024d6: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
80024da: 2b01 cmp r3, #1
80024dc: d106 bne.n 80024ec <HAL_ADC_Init+0x160>
{
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
80024de: 687b ldr r3, [r7, #4]
80024e0: 6a9b ldr r3, [r3, #40] @ 0x28
80024e2: 3b01 subs r3, #1
80024e4: 045b lsls r3, r3, #17
80024e6: 69ba ldr r2, [r7, #24]
80024e8: 4313 orrs r3, r2
80024ea: 61bb str r3, [r7, #24]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
80024ec: 687b ldr r3, [r7, #4]
80024ee: 6adb ldr r3, [r3, #44] @ 0x2c
80024f0: 2b00 cmp r3, #0
80024f2: d009 beq.n 8002508 <HAL_ADC_Init+0x17c>
{
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
80024f4: 687b ldr r3, [r7, #4]
80024f6: 6adb ldr r3, [r3, #44] @ 0x2c
80024f8: f403 7278 and.w r2, r3, #992 @ 0x3e0
| hadc->Init.ExternalTrigConvEdge
80024fc: 687b ldr r3, [r7, #4]
80024fe: 6b1b ldr r3, [r3, #48] @ 0x30
8002500: 4313 orrs r3, r2
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8002502: 69ba ldr r2, [r7, #24]
8002504: 4313 orrs r3, r2
8002506: 61bb str r3, [r7, #24]
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
8002508: 687b ldr r3, [r7, #4]
800250a: 681b ldr r3, [r3, #0]
800250c: 68da ldr r2, [r3, #12]
800250e: 4b60 ldr r3, [pc, #384] @ (8002690 <HAL_ADC_Init+0x304>)
8002510: 4013 ands r3, r2
8002512: 687a ldr r2, [r7, #4]
8002514: 6812 ldr r2, [r2, #0]
8002516: 69b9 ldr r1, [r7, #24]
8002518: 430b orrs r3, r1
800251a: 60d3 str r3, [r2, #12]
/* Configuration of sampling mode */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
800251c: 687b ldr r3, [r7, #4]
800251e: 681b ldr r3, [r3, #0]
8002520: 691b ldr r3, [r3, #16]
8002522: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000
8002526: 687b ldr r3, [r7, #4]
8002528: 6b5a ldr r2, [r3, #52] @ 0x34
800252a: 687b ldr r3, [r7, #4]
800252c: 681b ldr r3, [r3, #0]
800252e: 430a orrs r2, r1
8002530: 611a str r2, [r3, #16]
/* conversion on going on regular and injected groups: */
/* - Gain Compensation Init.GainCompensation */
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002532: 687b ldr r3, [r7, #4]
8002534: 681b ldr r3, [r3, #0]
8002536: 4618 mov r0, r3
8002538: f7ff ff15 bl 8002366 <LL_ADC_INJ_IsConversionOngoing>
800253c: 6138 str r0, [r7, #16]
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
800253e: 697b ldr r3, [r7, #20]
8002540: 2b00 cmp r3, #0
8002542: d16d bne.n 8002620 <HAL_ADC_Init+0x294>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8002544: 693b ldr r3, [r7, #16]
8002546: 2b00 cmp r3, #0
8002548: d16a bne.n 8002620 <HAL_ADC_Init+0x294>
)
{
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800254a: 687b ldr r3, [r7, #4]
800254c: 7f1b ldrb r3, [r3, #28]
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
800254e: 039a lsls r2, r3, #14
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
8002550: 687b ldr r3, [r7, #4]
8002552: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8002556: 005b lsls r3, r3, #1
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
8002558: 4313 orrs r3, r2
800255a: 61bb str r3, [r7, #24]
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
800255c: 687b ldr r3, [r7, #4]
800255e: 681b ldr r3, [r3, #0]
8002560: 68db ldr r3, [r3, #12]
8002562: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8002566: f023 0302 bic.w r3, r3, #2
800256a: 687a ldr r2, [r7, #4]
800256c: 6812 ldr r2, [r2, #0]
800256e: 69b9 ldr r1, [r7, #24]
8002570: 430b orrs r3, r1
8002572: 60d3 str r3, [r2, #12]
if (hadc->Init.GainCompensation != 0UL)
8002574: 687b ldr r3, [r7, #4]
8002576: 691b ldr r3, [r3, #16]
8002578: 2b00 cmp r3, #0
800257a: d017 beq.n 80025ac <HAL_ADC_Init+0x220>
{
SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
800257c: 687b ldr r3, [r7, #4]
800257e: 681b ldr r3, [r3, #0]
8002580: 691a ldr r2, [r3, #16]
8002582: 687b ldr r3, [r7, #4]
8002584: 681b ldr r3, [r3, #0]
8002586: f442 3280 orr.w r2, r2, #65536 @ 0x10000
800258a: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
800258c: 687b ldr r3, [r7, #4]
800258e: 681b ldr r3, [r3, #0]
8002590: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
8002594: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8002598: f023 033f bic.w r3, r3, #63 @ 0x3f
800259c: 687a ldr r2, [r7, #4]
800259e: 6911 ldr r1, [r2, #16]
80025a0: 687a ldr r2, [r7, #4]
80025a2: 6812 ldr r2, [r2, #0]
80025a4: 430b orrs r3, r1
80025a6: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
80025aa: e013 b.n 80025d4 <HAL_ADC_Init+0x248>
}
else
{
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
80025ac: 687b ldr r3, [r7, #4]
80025ae: 681b ldr r3, [r3, #0]
80025b0: 691a ldr r2, [r3, #16]
80025b2: 687b ldr r3, [r7, #4]
80025b4: 681b ldr r3, [r3, #0]
80025b6: f422 3280 bic.w r2, r2, #65536 @ 0x10000
80025ba: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
80025bc: 687b ldr r3, [r7, #4]
80025be: 681b ldr r3, [r3, #0]
80025c0: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
80025c4: 687a ldr r2, [r7, #4]
80025c6: 6812 ldr r2, [r2, #0]
80025c8: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
80025cc: f023 033f bic.w r3, r3, #63 @ 0x3f
80025d0: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
}
if (hadc->Init.OversamplingMode == ENABLE)
80025d4: 687b ldr r3, [r7, #4]
80025d6: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80025da: 2b01 cmp r3, #1
80025dc: d118 bne.n 8002610 <HAL_ADC_Init+0x284>
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2,
80025de: 687b ldr r3, [r7, #4]
80025e0: 681b ldr r3, [r3, #0]
80025e2: 691b ldr r3, [r3, #16]
80025e4: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
80025e8: f023 0304 bic.w r3, r3, #4
80025ec: 687a ldr r2, [r7, #4]
80025ee: 6c51 ldr r1, [r2, #68] @ 0x44
80025f0: 687a ldr r2, [r7, #4]
80025f2: 6c92 ldr r2, [r2, #72] @ 0x48
80025f4: 4311 orrs r1, r2
80025f6: 687a ldr r2, [r7, #4]
80025f8: 6cd2 ldr r2, [r2, #76] @ 0x4c
80025fa: 4311 orrs r1, r2
80025fc: 687a ldr r2, [r7, #4]
80025fe: 6d12 ldr r2, [r2, #80] @ 0x50
8002600: 430a orrs r2, r1
8002602: 431a orrs r2, r3
8002604: 687b ldr r3, [r7, #4]
8002606: 681b ldr r3, [r3, #0]
8002608: f042 0201 orr.w r2, r2, #1
800260c: 611a str r2, [r3, #16]
800260e: e007 b.n 8002620 <HAL_ADC_Init+0x294>
);
}
else
{
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
8002610: 687b ldr r3, [r7, #4]
8002612: 681b ldr r3, [r3, #0]
8002614: 691a ldr r2, [r3, #16]
8002616: 687b ldr r3, [r7, #4]
8002618: 681b ldr r3, [r3, #0]
800261a: f022 0201 bic.w r2, r2, #1
800261e: 611a str r2, [r3, #16]
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8002620: 687b ldr r3, [r7, #4]
8002622: 695b ldr r3, [r3, #20]
8002624: 2b01 cmp r3, #1
8002626: d10c bne.n 8002642 <HAL_ADC_Init+0x2b6>
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
8002628: 687b ldr r3, [r7, #4]
800262a: 681b ldr r3, [r3, #0]
800262c: 6b1b ldr r3, [r3, #48] @ 0x30
800262e: f023 010f bic.w r1, r3, #15
8002632: 687b ldr r3, [r7, #4]
8002634: 6a1b ldr r3, [r3, #32]
8002636: 1e5a subs r2, r3, #1
8002638: 687b ldr r3, [r7, #4]
800263a: 681b ldr r3, [r3, #0]
800263c: 430a orrs r2, r1
800263e: 631a str r2, [r3, #48] @ 0x30
8002640: e007 b.n 8002652 <HAL_ADC_Init+0x2c6>
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
8002642: 687b ldr r3, [r7, #4]
8002644: 681b ldr r3, [r3, #0]
8002646: 6b1a ldr r2, [r3, #48] @ 0x30
8002648: 687b ldr r3, [r7, #4]
800264a: 681b ldr r3, [r3, #0]
800264c: f022 020f bic.w r2, r2, #15
8002650: 631a str r2, [r3, #48] @ 0x30
}
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
8002652: 687b ldr r3, [r7, #4]
8002654: 6ddb ldr r3, [r3, #92] @ 0x5c
8002656: f023 0303 bic.w r3, r3, #3
800265a: f043 0201 orr.w r2, r3, #1
800265e: 687b ldr r3, [r7, #4]
8002660: 65da str r2, [r3, #92] @ 0x5c
8002662: e007 b.n 8002674 <HAL_ADC_Init+0x2e8>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002664: 687b ldr r3, [r7, #4]
8002666: 6ddb ldr r3, [r3, #92] @ 0x5c
8002668: f043 0210 orr.w r2, r3, #16
800266c: 687b ldr r3, [r7, #4]
800266e: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8002670: 2301 movs r3, #1
8002672: 77fb strb r3, [r7, #31]
}
/* Return function status */
return tmp_hal_status;
8002674: 7ffb ldrb r3, [r7, #31]
}
8002676: 4618 mov r0, r3
8002678: 3724 adds r7, #36 @ 0x24
800267a: 46bd mov sp, r7
800267c: bd90 pop {r4, r7, pc}
800267e: bf00 nop
8002680: 2000001c .word 0x2000001c
8002684: 053e2d63 .word 0x053e2d63
8002688: 50000100 .word 0x50000100
800268c: 50000300 .word 0x50000300
8002690: fff04007 .word 0xfff04007
08002694 <HAL_ADC_Start>:
* if ADC is master, ADC is enabled and multimode conversion is started.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
{
8002694: b580 push {r7, lr}
8002696: b086 sub sp, #24
8002698: af00 add r7, sp, #0
800269a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
800269c: 4859 ldr r0, [pc, #356] @ (8002804 <HAL_ADC_Start+0x170>)
800269e: f7ff fd5b bl 8002158 <LL_ADC_GetMultimode>
80026a2: 6138 str r0, [r7, #16]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80026a4: 687b ldr r3, [r7, #4]
80026a6: 681b ldr r3, [r3, #0]
80026a8: 4618 mov r0, r3
80026aa: f7ff fe35 bl 8002318 <LL_ADC_REG_IsConversionOngoing>
80026ae: 4603 mov r3, r0
80026b0: 2b00 cmp r3, #0
80026b2: f040 809f bne.w 80027f4 <HAL_ADC_Start+0x160>
{
/* Process locked */
__HAL_LOCK(hadc);
80026b6: 687b ldr r3, [r7, #4]
80026b8: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
80026bc: 2b01 cmp r3, #1
80026be: d101 bne.n 80026c4 <HAL_ADC_Start+0x30>
80026c0: 2302 movs r3, #2
80026c2: e09a b.n 80027fa <HAL_ADC_Start+0x166>
80026c4: 687b ldr r3, [r7, #4]
80026c6: 2201 movs r2, #1
80026c8: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
80026cc: 6878 ldr r0, [r7, #4]
80026ce: f000 fe63 bl 8003398 <ADC_Enable>
80026d2: 4603 mov r3, r0
80026d4: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
80026d6: 7dfb ldrb r3, [r7, #23]
80026d8: 2b00 cmp r3, #0
80026da: f040 8086 bne.w 80027ea <HAL_ADC_Start+0x156>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
80026de: 687b ldr r3, [r7, #4]
80026e0: 6ddb ldr r3, [r3, #92] @ 0x5c
80026e2: f423 6370 bic.w r3, r3, #3840 @ 0xf00
80026e6: f023 0301 bic.w r3, r3, #1
80026ea: f443 7280 orr.w r2, r3, #256 @ 0x100
80026ee: 687b ldr r3, [r7, #4]
80026f0: 65da str r2, [r3, #92] @ 0x5c
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
80026f2: 687b ldr r3, [r7, #4]
80026f4: 681b ldr r3, [r3, #0]
80026f6: 4a44 ldr r2, [pc, #272] @ (8002808 <HAL_ADC_Start+0x174>)
80026f8: 4293 cmp r3, r2
80026fa: d002 beq.n 8002702 <HAL_ADC_Start+0x6e>
80026fc: 687b ldr r3, [r7, #4]
80026fe: 681b ldr r3, [r3, #0]
8002700: e001 b.n 8002706 <HAL_ADC_Start+0x72>
8002702: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8002706: 687a ldr r2, [r7, #4]
8002708: 6812 ldr r2, [r2, #0]
800270a: 4293 cmp r3, r2
800270c: d002 beq.n 8002714 <HAL_ADC_Start+0x80>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
800270e: 693b ldr r3, [r7, #16]
8002710: 2b00 cmp r3, #0
8002712: d105 bne.n 8002720 <HAL_ADC_Start+0x8c>
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8002714: 687b ldr r3, [r7, #4]
8002716: 6ddb ldr r3, [r3, #92] @ 0x5c
8002718: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
800271c: 687b ldr r3, [r7, #4]
800271e: 65da str r2, [r3, #92] @ 0x5c
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8002720: 687b ldr r3, [r7, #4]
8002722: 6ddb ldr r3, [r3, #92] @ 0x5c
8002724: f403 5380 and.w r3, r3, #4096 @ 0x1000
8002728: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800272c: d106 bne.n 800273c <HAL_ADC_Start+0xa8>
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
800272e: 687b ldr r3, [r7, #4]
8002730: 6e1b ldr r3, [r3, #96] @ 0x60
8002732: f023 0206 bic.w r2, r3, #6
8002736: 687b ldr r3, [r7, #4]
8002738: 661a str r2, [r3, #96] @ 0x60
800273a: e002 b.n 8002742 <HAL_ADC_Start+0xae>
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
800273c: 687b ldr r3, [r7, #4]
800273e: 2200 movs r2, #0
8002740: 661a str r2, [r3, #96] @ 0x60
}
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
8002742: 687b ldr r3, [r7, #4]
8002744: 681b ldr r3, [r3, #0]
8002746: 221c movs r2, #28
8002748: 601a str r2, [r3, #0]
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
800274a: 687b ldr r3, [r7, #4]
800274c: 2200 movs r2, #0
800274e: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Case of multimode enabled (when multimode feature is available): */
/* - if ADC is slave and dual regular conversions are enabled, ADC is */
/* enabled only (conversion is not started), */
/* - if ADC is master, ADC is enabled and conversion is started. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8002752: 687b ldr r3, [r7, #4]
8002754: 681b ldr r3, [r3, #0]
8002756: 4a2c ldr r2, [pc, #176] @ (8002808 <HAL_ADC_Start+0x174>)
8002758: 4293 cmp r3, r2
800275a: d002 beq.n 8002762 <HAL_ADC_Start+0xce>
800275c: 687b ldr r3, [r7, #4]
800275e: 681b ldr r3, [r3, #0]
8002760: e001 b.n 8002766 <HAL_ADC_Start+0xd2>
8002762: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8002766: 687a ldr r2, [r7, #4]
8002768: 6812 ldr r2, [r2, #0]
800276a: 4293 cmp r3, r2
800276c: d008 beq.n 8002780 <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
800276e: 693b ldr r3, [r7, #16]
8002770: 2b00 cmp r3, #0
8002772: d005 beq.n 8002780 <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
8002774: 693b ldr r3, [r7, #16]
8002776: 2b05 cmp r3, #5
8002778: d002 beq.n 8002780 <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
800277a: 693b ldr r3, [r7, #16]
800277c: 2b09 cmp r3, #9
800277e: d114 bne.n 80027aa <HAL_ADC_Start+0x116>
)
{
/* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
8002780: 687b ldr r3, [r7, #4]
8002782: 681b ldr r3, [r3, #0]
8002784: 68db ldr r3, [r3, #12]
8002786: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800278a: 2b00 cmp r3, #0
800278c: d007 beq.n 800279e <HAL_ADC_Start+0x10a>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
800278e: 687b ldr r3, [r7, #4]
8002790: 6ddb ldr r3, [r3, #92] @ 0x5c
8002792: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8002796: f443 5280 orr.w r2, r3, #4096 @ 0x1000
800279a: 687b ldr r3, [r7, #4]
800279c: 65da str r2, [r3, #92] @ 0x5c
}
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
800279e: 687b ldr r3, [r7, #4]
80027a0: 681b ldr r3, [r3, #0]
80027a2: 4618 mov r0, r3
80027a4: f7ff fd90 bl 80022c8 <LL_ADC_REG_StartConversion>
80027a8: e026 b.n 80027f8 <HAL_ADC_Start+0x164>
}
else
{
/* ADC instance is a multimode slave instance with multimode regular conversions enabled */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
80027aa: 687b ldr r3, [r7, #4]
80027ac: 6ddb ldr r3, [r3, #92] @ 0x5c
80027ae: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
80027b2: 687b ldr r3, [r7, #4]
80027b4: 65da str r2, [r3, #92] @ 0x5c
/* if Master ADC JAUTO bit is set, update Slave State in setting
HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
80027b6: 687b ldr r3, [r7, #4]
80027b8: 681b ldr r3, [r3, #0]
80027ba: 4a13 ldr r2, [pc, #76] @ (8002808 <HAL_ADC_Start+0x174>)
80027bc: 4293 cmp r3, r2
80027be: d002 beq.n 80027c6 <HAL_ADC_Start+0x132>
80027c0: 687b ldr r3, [r7, #4]
80027c2: 681b ldr r3, [r3, #0]
80027c4: e001 b.n 80027ca <HAL_ADC_Start+0x136>
80027c6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
80027ca: 60fb str r3, [r7, #12]
if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
80027cc: 68fb ldr r3, [r7, #12]
80027ce: 68db ldr r3, [r3, #12]
80027d0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80027d4: 2b00 cmp r3, #0
80027d6: d00f beq.n 80027f8 <HAL_ADC_Start+0x164>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
80027d8: 687b ldr r3, [r7, #4]
80027da: 6ddb ldr r3, [r3, #92] @ 0x5c
80027dc: f423 5340 bic.w r3, r3, #12288 @ 0x3000
80027e0: f443 5280 orr.w r2, r3, #4096 @ 0x1000
80027e4: 687b ldr r3, [r7, #4]
80027e6: 65da str r2, [r3, #92] @ 0x5c
80027e8: e006 b.n 80027f8 <HAL_ADC_Start+0x164>
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
80027ea: 687b ldr r3, [r7, #4]
80027ec: 2200 movs r2, #0
80027ee: f883 2058 strb.w r2, [r3, #88] @ 0x58
80027f2: e001 b.n 80027f8 <HAL_ADC_Start+0x164>
}
}
else
{
tmp_hal_status = HAL_BUSY;
80027f4: 2302 movs r3, #2
80027f6: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
80027f8: 7dfb ldrb r3, [r7, #23]
}
80027fa: 4618 mov r0, r3
80027fc: 3718 adds r7, #24
80027fe: 46bd mov sp, r7
8002800: bd80 pop {r7, pc}
8002802: bf00 nop
8002804: 50000300 .word 0x50000300
8002808: 50000100 .word 0x50000100
0800280c <HAL_ADC_Stop>:
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
{
800280c: b580 push {r7, lr}
800280e: b084 sub sp, #16
8002810: af00 add r7, sp, #0
8002812: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
8002814: 687b ldr r3, [r7, #4]
8002816: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
800281a: 2b01 cmp r3, #1
800281c: d101 bne.n 8002822 <HAL_ADC_Stop+0x16>
800281e: 2302 movs r3, #2
8002820: e023 b.n 800286a <HAL_ADC_Stop+0x5e>
8002822: 687b ldr r3, [r7, #4]
8002824: 2201 movs r2, #1
8002826: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
800282a: 2103 movs r1, #3
800282c: 6878 ldr r0, [r7, #4]
800282e: f000 fcf7 bl 8003220 <ADC_ConversionStop>
8002832: 4603 mov r3, r0
8002834: 73fb strb r3, [r7, #15]
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
8002836: 7bfb ldrb r3, [r7, #15]
8002838: 2b00 cmp r3, #0
800283a: d111 bne.n 8002860 <HAL_ADC_Stop+0x54>
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
800283c: 6878 ldr r0, [r7, #4]
800283e: f000 fe31 bl 80034a4 <ADC_Disable>
8002842: 4603 mov r3, r0
8002844: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
8002846: 7bfb ldrb r3, [r7, #15]
8002848: 2b00 cmp r3, #0
800284a: d109 bne.n 8002860 <HAL_ADC_Stop+0x54>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800284c: 687b ldr r3, [r7, #4]
800284e: 6ddb ldr r3, [r3, #92] @ 0x5c
8002850: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8002854: f023 0301 bic.w r3, r3, #1
8002858: f043 0201 orr.w r2, r3, #1
800285c: 687b ldr r3, [r7, #4]
800285e: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_READY);
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002860: 687b ldr r3, [r7, #4]
8002862: 2200 movs r2, #0
8002864: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
8002868: 7bfb ldrb r3, [r7, #15]
}
800286a: 4618 mov r0, r3
800286c: 3710 adds r7, #16
800286e: 46bd mov sp, r7
8002870: bd80 pop {r7, pc}
...
08002874 <HAL_ADC_PollForConversion>:
* @param hadc ADC handle
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
8002874: b580 push {r7, lr}
8002876: b088 sub sp, #32
8002878: af00 add r7, sp, #0
800287a: 6078 str r0, [r7, #4]
800287c: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t tmp_Flag_End;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
800287e: 4867 ldr r0, [pc, #412] @ (8002a1c <HAL_ADC_PollForConversion+0x1a8>)
8002880: f7ff fc6a bl 8002158 <LL_ADC_GetMultimode>
8002884: 6178 str r0, [r7, #20]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* If end of conversion selected to end of sequence conversions */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
8002886: 687b ldr r3, [r7, #4]
8002888: 699b ldr r3, [r3, #24]
800288a: 2b08 cmp r3, #8
800288c: d102 bne.n 8002894 <HAL_ADC_PollForConversion+0x20>
{
tmp_Flag_End = ADC_FLAG_EOS;
800288e: 2308 movs r3, #8
8002890: 61fb str r3, [r7, #28]
8002892: e02a b.n 80028ea <HAL_ADC_PollForConversion+0x76>
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8002894: 697b ldr r3, [r7, #20]
8002896: 2b00 cmp r3, #0
8002898: d005 beq.n 80028a6 <HAL_ADC_PollForConversion+0x32>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
800289a: 697b ldr r3, [r7, #20]
800289c: 2b05 cmp r3, #5
800289e: d002 beq.n 80028a6 <HAL_ADC_PollForConversion+0x32>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
80028a0: 697b ldr r3, [r7, #20]
80028a2: 2b09 cmp r3, #9
80028a4: d111 bne.n 80028ca <HAL_ADC_PollForConversion+0x56>
)
{
/* Check ADC DMA mode in independent mode on ADC group regular */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
80028a6: 687b ldr r3, [r7, #4]
80028a8: 681b ldr r3, [r3, #0]
80028aa: 68db ldr r3, [r3, #12]
80028ac: f003 0301 and.w r3, r3, #1
80028b0: 2b00 cmp r3, #0
80028b2: d007 beq.n 80028c4 <HAL_ADC_PollForConversion+0x50>
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80028b4: 687b ldr r3, [r7, #4]
80028b6: 6ddb ldr r3, [r3, #92] @ 0x5c
80028b8: f043 0220 orr.w r2, r3, #32
80028bc: 687b ldr r3, [r7, #4]
80028be: 65da str r2, [r3, #92] @ 0x5c
return HAL_ERROR;
80028c0: 2301 movs r3, #1
80028c2: e0a6 b.n 8002a12 <HAL_ADC_PollForConversion+0x19e>
}
else
{
tmp_Flag_End = (ADC_FLAG_EOC);
80028c4: 2304 movs r3, #4
80028c6: 61fb str r3, [r7, #28]
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
80028c8: e00f b.n 80028ea <HAL_ADC_PollForConversion+0x76>
}
}
else
{
/* Check ADC DMA mode in multimode on ADC group regular */
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
80028ca: 4854 ldr r0, [pc, #336] @ (8002a1c <HAL_ADC_PollForConversion+0x1a8>)
80028cc: f7ff fc52 bl 8002174 <LL_ADC_GetMultiDMATransfer>
80028d0: 4603 mov r3, r0
80028d2: 2b00 cmp r3, #0
80028d4: d007 beq.n 80028e6 <HAL_ADC_PollForConversion+0x72>
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80028d6: 687b ldr r3, [r7, #4]
80028d8: 6ddb ldr r3, [r3, #92] @ 0x5c
80028da: f043 0220 orr.w r2, r3, #32
80028de: 687b ldr r3, [r7, #4]
80028e0: 65da str r2, [r3, #92] @ 0x5c
return HAL_ERROR;
80028e2: 2301 movs r3, #1
80028e4: e095 b.n 8002a12 <HAL_ADC_PollForConversion+0x19e>
}
else
{
tmp_Flag_End = (ADC_FLAG_EOC);
80028e6: 2304 movs r3, #4
80028e8: 61fb str r3, [r7, #28]
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
/* Get tick count */
tickstart = HAL_GetTick();
80028ea: f7ff fac9 bl 8001e80 <HAL_GetTick>
80028ee: 6138 str r0, [r7, #16]
/* Wait until End of unitary conversion or sequence conversions flag is raised */
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
80028f0: e021 b.n 8002936 <HAL_ADC_PollForConversion+0xc2>
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
80028f2: 683b ldr r3, [r7, #0]
80028f4: f1b3 3fff cmp.w r3, #4294967295
80028f8: d01d beq.n 8002936 <HAL_ADC_PollForConversion+0xc2>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
80028fa: f7ff fac1 bl 8001e80 <HAL_GetTick>
80028fe: 4602 mov r2, r0
8002900: 693b ldr r3, [r7, #16]
8002902: 1ad3 subs r3, r2, r3
8002904: 683a ldr r2, [r7, #0]
8002906: 429a cmp r2, r3
8002908: d302 bcc.n 8002910 <HAL_ADC_PollForConversion+0x9c>
800290a: 683b ldr r3, [r7, #0]
800290c: 2b00 cmp r3, #0
800290e: d112 bne.n 8002936 <HAL_ADC_PollForConversion+0xc2>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
8002910: 687b ldr r3, [r7, #4]
8002912: 681b ldr r3, [r3, #0]
8002914: 681a ldr r2, [r3, #0]
8002916: 69fb ldr r3, [r7, #28]
8002918: 4013 ands r3, r2
800291a: 2b00 cmp r3, #0
800291c: d10b bne.n 8002936 <HAL_ADC_PollForConversion+0xc2>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
800291e: 687b ldr r3, [r7, #4]
8002920: 6ddb ldr r3, [r3, #92] @ 0x5c
8002922: f043 0204 orr.w r2, r3, #4
8002926: 687b ldr r3, [r7, #4]
8002928: 65da str r2, [r3, #92] @ 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
800292a: 687b ldr r3, [r7, #4]
800292c: 2200 movs r2, #0
800292e: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_TIMEOUT;
8002932: 2303 movs r3, #3
8002934: e06d b.n 8002a12 <HAL_ADC_PollForConversion+0x19e>
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
8002936: 687b ldr r3, [r7, #4]
8002938: 681b ldr r3, [r3, #0]
800293a: 681a ldr r2, [r3, #0]
800293c: 69fb ldr r3, [r7, #28]
800293e: 4013 ands r3, r2
8002940: 2b00 cmp r3, #0
8002942: d0d6 beq.n 80028f2 <HAL_ADC_PollForConversion+0x7e>
}
}
}
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8002944: 687b ldr r3, [r7, #4]
8002946: 6ddb ldr r3, [r3, #92] @ 0x5c
8002948: f443 7200 orr.w r2, r3, #512 @ 0x200
800294c: 687b ldr r3, [r7, #4]
800294e: 65da str r2, [r3, #92] @ 0x5c
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
8002950: 687b ldr r3, [r7, #4]
8002952: 681b ldr r3, [r3, #0]
8002954: 4618 mov r0, r3
8002956: f7ff fb71 bl 800203c <LL_ADC_REG_IsTriggerSourceSWStart>
800295a: 4603 mov r3, r0
800295c: 2b00 cmp r3, #0
800295e: d01c beq.n 800299a <HAL_ADC_PollForConversion+0x126>
&& (hadc->Init.ContinuousConvMode == DISABLE)
8002960: 687b ldr r3, [r7, #4]
8002962: 7f5b ldrb r3, [r3, #29]
8002964: 2b00 cmp r3, #0
8002966: d118 bne.n 800299a <HAL_ADC_PollForConversion+0x126>
)
{
/* Check whether end of sequence is reached */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
8002968: 687b ldr r3, [r7, #4]
800296a: 681b ldr r3, [r3, #0]
800296c: 681b ldr r3, [r3, #0]
800296e: f003 0308 and.w r3, r3, #8
8002972: 2b08 cmp r3, #8
8002974: d111 bne.n 800299a <HAL_ADC_PollForConversion+0x126>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8002976: 687b ldr r3, [r7, #4]
8002978: 6ddb ldr r3, [r3, #92] @ 0x5c
800297a: f423 7280 bic.w r2, r3, #256 @ 0x100
800297e: 687b ldr r3, [r7, #4]
8002980: 65da str r2, [r3, #92] @ 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
8002982: 687b ldr r3, [r7, #4]
8002984: 6ddb ldr r3, [r3, #92] @ 0x5c
8002986: f403 5380 and.w r3, r3, #4096 @ 0x1000
800298a: 2b00 cmp r3, #0
800298c: d105 bne.n 800299a <HAL_ADC_PollForConversion+0x126>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
800298e: 687b ldr r3, [r7, #4]
8002990: 6ddb ldr r3, [r3, #92] @ 0x5c
8002992: f043 0201 orr.w r2, r3, #1
8002996: 687b ldr r3, [r7, #4]
8002998: 65da str r2, [r3, #92] @ 0x5c
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
800299a: 687b ldr r3, [r7, #4]
800299c: 681b ldr r3, [r3, #0]
800299e: 4a20 ldr r2, [pc, #128] @ (8002a20 <HAL_ADC_PollForConversion+0x1ac>)
80029a0: 4293 cmp r3, r2
80029a2: d002 beq.n 80029aa <HAL_ADC_PollForConversion+0x136>
80029a4: 687b ldr r3, [r7, #4]
80029a6: 681b ldr r3, [r3, #0]
80029a8: e001 b.n 80029ae <HAL_ADC_PollForConversion+0x13a>
80029aa: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
80029ae: 687a ldr r2, [r7, #4]
80029b0: 6812 ldr r2, [r2, #0]
80029b2: 4293 cmp r3, r2
80029b4: d008 beq.n 80029c8 <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
80029b6: 697b ldr r3, [r7, #20]
80029b8: 2b00 cmp r3, #0
80029ba: d005 beq.n 80029c8 <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
80029bc: 697b ldr r3, [r7, #20]
80029be: 2b05 cmp r3, #5
80029c0: d002 beq.n 80029c8 <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
80029c2: 697b ldr r3, [r7, #20]
80029c4: 2b09 cmp r3, #9
80029c6: d104 bne.n 80029d2 <HAL_ADC_PollForConversion+0x15e>
)
{
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
80029c8: 687b ldr r3, [r7, #4]
80029ca: 681b ldr r3, [r3, #0]
80029cc: 68db ldr r3, [r3, #12]
80029ce: 61bb str r3, [r7, #24]
80029d0: e00d b.n 80029ee <HAL_ADC_PollForConversion+0x17a>
}
else
{
/* Retrieve Master ADC CFGR register */
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
80029d2: 687b ldr r3, [r7, #4]
80029d4: 681b ldr r3, [r3, #0]
80029d6: 4a12 ldr r2, [pc, #72] @ (8002a20 <HAL_ADC_PollForConversion+0x1ac>)
80029d8: 4293 cmp r3, r2
80029da: d002 beq.n 80029e2 <HAL_ADC_PollForConversion+0x16e>
80029dc: 687b ldr r3, [r7, #4]
80029de: 681b ldr r3, [r3, #0]
80029e0: e001 b.n 80029e6 <HAL_ADC_PollForConversion+0x172>
80029e2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
80029e6: 60fb str r3, [r7, #12]
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
80029e8: 68fb ldr r3, [r7, #12]
80029ea: 68db ldr r3, [r3, #12]
80029ec: 61bb str r3, [r7, #24]
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear polled flag */
if (tmp_Flag_End == ADC_FLAG_EOS)
80029ee: 69fb ldr r3, [r7, #28]
80029f0: 2b08 cmp r3, #8
80029f2: d104 bne.n 80029fe <HAL_ADC_PollForConversion+0x18a>
{
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
80029f4: 687b ldr r3, [r7, #4]
80029f6: 681b ldr r3, [r3, #0]
80029f8: 2208 movs r2, #8
80029fa: 601a str r2, [r3, #0]
80029fc: e008 b.n 8002a10 <HAL_ADC_PollForConversion+0x19c>
else
{
/* Clear end of conversion EOC flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
80029fe: 69bb ldr r3, [r7, #24]
8002a00: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002a04: 2b00 cmp r3, #0
8002a06: d103 bne.n 8002a10 <HAL_ADC_PollForConversion+0x19c>
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
8002a08: 687b ldr r3, [r7, #4]
8002a0a: 681b ldr r3, [r3, #0]
8002a0c: 220c movs r2, #12
8002a0e: 601a str r2, [r3, #0]
}
}
/* Return function status */
return HAL_OK;
8002a10: 2300 movs r3, #0
}
8002a12: 4618 mov r0, r3
8002a14: 3720 adds r7, #32
8002a16: 46bd mov sp, r7
8002a18: bd80 pop {r7, pc}
8002a1a: bf00 nop
8002a1c: 50000300 .word 0x50000300
8002a20: 50000100 .word 0x50000100
08002a24 <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
{
8002a24: b480 push {r7}
8002a26: b083 sub sp, #12
8002a28: af00 add r7, sp, #0
8002a2a: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
8002a2c: 687b ldr r3, [r7, #4]
8002a2e: 681b ldr r3, [r3, #0]
8002a30: 6c1b ldr r3, [r3, #64] @ 0x40
}
8002a32: 4618 mov r0, r3
8002a34: 370c adds r7, #12
8002a36: 46bd mov sp, r7
8002a38: f85d 7b04 ldr.w r7, [sp], #4
8002a3c: 4770 bx lr
...
08002a40 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
{
8002a40: b580 push {r7, lr}
8002a42: b0b6 sub sp, #216 @ 0xd8
8002a44: af00 add r7, sp, #0
8002a46: 6078 str r0, [r7, #4]
8002a48: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002a4a: 2300 movs r3, #0
8002a4c: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
8002a50: 2300 movs r3, #0
8002a52: 60fb str r3, [r7, #12]
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
}
/* Process locked */
__HAL_LOCK(hadc);
8002a54: 687b ldr r3, [r7, #4]
8002a56: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8002a5a: 2b01 cmp r3, #1
8002a5c: d101 bne.n 8002a62 <HAL_ADC_ConfigChannel+0x22>
8002a5e: 2302 movs r3, #2
8002a60: e3c8 b.n 80031f4 <HAL_ADC_ConfigChannel+0x7b4>
8002a62: 687b ldr r3, [r7, #4]
8002a64: 2201 movs r2, #1
8002a66: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002a6a: 687b ldr r3, [r7, #4]
8002a6c: 681b ldr r3, [r3, #0]
8002a6e: 4618 mov r0, r3
8002a70: f7ff fc52 bl 8002318 <LL_ADC_REG_IsConversionOngoing>
8002a74: 4603 mov r3, r0
8002a76: 2b00 cmp r3, #0
8002a78: f040 83ad bne.w 80031d6 <HAL_ADC_ConfigChannel+0x796>
{
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
8002a7c: 687b ldr r3, [r7, #4]
8002a7e: 6818 ldr r0, [r3, #0]
8002a80: 683b ldr r3, [r7, #0]
8002a82: 6859 ldr r1, [r3, #4]
8002a84: 683b ldr r3, [r7, #0]
8002a86: 681b ldr r3, [r3, #0]
8002a88: 461a mov r2, r3
8002a8a: f7ff faea bl 8002062 <LL_ADC_REG_SetSequencerRanks>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8002a8e: 687b ldr r3, [r7, #4]
8002a90: 681b ldr r3, [r3, #0]
8002a92: 4618 mov r0, r3
8002a94: f7ff fc40 bl 8002318 <LL_ADC_REG_IsConversionOngoing>
8002a98: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002a9c: 687b ldr r3, [r7, #4]
8002a9e: 681b ldr r3, [r3, #0]
8002aa0: 4618 mov r0, r3
8002aa2: f7ff fc60 bl 8002366 <LL_ADC_INJ_IsConversionOngoing>
8002aa6: f8c7 00cc str.w r0, [r7, #204] @ 0xcc
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8002aaa: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
8002aae: 2b00 cmp r3, #0
8002ab0: f040 81d9 bne.w 8002e66 <HAL_ADC_ConfigChannel+0x426>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8002ab4: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8002ab8: 2b00 cmp r3, #0
8002aba: f040 81d4 bne.w 8002e66 <HAL_ADC_ConfigChannel+0x426>
)
{
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
8002abe: 683b ldr r3, [r7, #0]
8002ac0: 689b ldr r3, [r3, #8]
8002ac2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8002ac6: d10f bne.n 8002ae8 <HAL_ADC_ConfigChannel+0xa8>
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
8002ac8: 687b ldr r3, [r7, #4]
8002aca: 6818 ldr r0, [r3, #0]
8002acc: 683b ldr r3, [r7, #0]
8002ace: 681b ldr r3, [r3, #0]
8002ad0: 2200 movs r2, #0
8002ad2: 4619 mov r1, r3
8002ad4: f7ff faf1 bl 80020ba <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
8002ad8: 687b ldr r3, [r7, #4]
8002ada: 681b ldr r3, [r3, #0]
8002adc: f04f 4100 mov.w r1, #2147483648 @ 0x80000000
8002ae0: 4618 mov r0, r3
8002ae2: f7ff fa98 bl 8002016 <LL_ADC_SetSamplingTimeCommonConfig>
8002ae6: e00e b.n 8002b06 <HAL_ADC_ConfigChannel+0xc6>
}
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
8002ae8: 687b ldr r3, [r7, #4]
8002aea: 6818 ldr r0, [r3, #0]
8002aec: 683b ldr r3, [r7, #0]
8002aee: 6819 ldr r1, [r3, #0]
8002af0: 683b ldr r3, [r7, #0]
8002af2: 689b ldr r3, [r3, #8]
8002af4: 461a mov r2, r3
8002af6: f7ff fae0 bl 80020ba <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
8002afa: 687b ldr r3, [r7, #4]
8002afc: 681b ldr r3, [r3, #0]
8002afe: 2100 movs r1, #0
8002b00: 4618 mov r0, r3
8002b02: f7ff fa88 bl 8002016 <LL_ADC_SetSamplingTimeCommonConfig>
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
8002b06: 683b ldr r3, [r7, #0]
8002b08: 695a ldr r2, [r3, #20]
8002b0a: 687b ldr r3, [r7, #4]
8002b0c: 681b ldr r3, [r3, #0]
8002b0e: 68db ldr r3, [r3, #12]
8002b10: 08db lsrs r3, r3, #3
8002b12: f003 0303 and.w r3, r3, #3
8002b16: 005b lsls r3, r3, #1
8002b18: fa02 f303 lsl.w r3, r2, r3
8002b1c: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
8002b20: 683b ldr r3, [r7, #0]
8002b22: 691b ldr r3, [r3, #16]
8002b24: 2b04 cmp r3, #4
8002b26: d022 beq.n 8002b6e <HAL_ADC_ConfigChannel+0x12e>
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
8002b28: 687b ldr r3, [r7, #4]
8002b2a: 6818 ldr r0, [r3, #0]
8002b2c: 683b ldr r3, [r7, #0]
8002b2e: 6919 ldr r1, [r3, #16]
8002b30: 683b ldr r3, [r7, #0]
8002b32: 681a ldr r2, [r3, #0]
8002b34: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8002b38: f7ff f9e2 bl 8001f00 <LL_ADC_SetOffset>
assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
/* Set ADC selected offset sign & saturation */
LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
8002b3c: 687b ldr r3, [r7, #4]
8002b3e: 6818 ldr r0, [r3, #0]
8002b40: 683b ldr r3, [r7, #0]
8002b42: 6919 ldr r1, [r3, #16]
8002b44: 683b ldr r3, [r7, #0]
8002b46: 699b ldr r3, [r3, #24]
8002b48: 461a mov r2, r3
8002b4a: f7ff fa2e bl 8001faa <LL_ADC_SetOffsetSign>
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
8002b4e: 687b ldr r3, [r7, #4]
8002b50: 6818 ldr r0, [r3, #0]
8002b52: 683b ldr r3, [r7, #0]
8002b54: 6919 ldr r1, [r3, #16]
(pConfig->OffsetSaturation == ENABLE) ?
8002b56: 683b ldr r3, [r7, #0]
8002b58: 7f1b ldrb r3, [r3, #28]
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
8002b5a: 2b01 cmp r3, #1
8002b5c: d102 bne.n 8002b64 <HAL_ADC_ConfigChannel+0x124>
8002b5e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002b62: e000 b.n 8002b66 <HAL_ADC_ConfigChannel+0x126>
8002b64: 2300 movs r3, #0
8002b66: 461a mov r2, r3
8002b68: f7ff fa3a bl 8001fe0 <LL_ADC_SetOffsetSaturation>
8002b6c: e17b b.n 8002e66 <HAL_ADC_ConfigChannel+0x426>
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
8002b6e: 687b ldr r3, [r7, #4]
8002b70: 681b ldr r3, [r3, #0]
8002b72: 2100 movs r1, #0
8002b74: 4618 mov r0, r3
8002b76: f7ff f9e7 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002b7a: 4603 mov r3, r0
8002b7c: f3c3 0312 ubfx r3, r3, #0, #19
8002b80: 2b00 cmp r3, #0
8002b82: d10a bne.n 8002b9a <HAL_ADC_ConfigChannel+0x15a>
8002b84: 687b ldr r3, [r7, #4]
8002b86: 681b ldr r3, [r3, #0]
8002b88: 2100 movs r1, #0
8002b8a: 4618 mov r0, r3
8002b8c: f7ff f9dc bl 8001f48 <LL_ADC_GetOffsetChannel>
8002b90: 4603 mov r3, r0
8002b92: 0e9b lsrs r3, r3, #26
8002b94: f003 021f and.w r2, r3, #31
8002b98: e01e b.n 8002bd8 <HAL_ADC_ConfigChannel+0x198>
8002b9a: 687b ldr r3, [r7, #4]
8002b9c: 681b ldr r3, [r3, #0]
8002b9e: 2100 movs r1, #0
8002ba0: 4618 mov r0, r3
8002ba2: f7ff f9d1 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002ba6: 4603 mov r3, r0
8002ba8: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002bac: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8002bb0: fa93 f3a3 rbit r3, r3
8002bb4: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8002bb8: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002bbc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
8002bc0: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8002bc4: 2b00 cmp r3, #0
8002bc6: d101 bne.n 8002bcc <HAL_ADC_ConfigChannel+0x18c>
{
return 32U;
8002bc8: 2320 movs r3, #32
8002bca: e004 b.n 8002bd6 <HAL_ADC_ConfigChannel+0x196>
}
return __builtin_clz(value);
8002bcc: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8002bd0: fab3 f383 clz r3, r3
8002bd4: b2db uxtb r3, r3
8002bd6: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002bd8: 683b ldr r3, [r7, #0]
8002bda: 681b ldr r3, [r3, #0]
8002bdc: f3c3 0312 ubfx r3, r3, #0, #19
8002be0: 2b00 cmp r3, #0
8002be2: d105 bne.n 8002bf0 <HAL_ADC_ConfigChannel+0x1b0>
8002be4: 683b ldr r3, [r7, #0]
8002be6: 681b ldr r3, [r3, #0]
8002be8: 0e9b lsrs r3, r3, #26
8002bea: f003 031f and.w r3, r3, #31
8002bee: e018 b.n 8002c22 <HAL_ADC_ConfigChannel+0x1e2>
8002bf0: 683b ldr r3, [r7, #0]
8002bf2: 681b ldr r3, [r3, #0]
8002bf4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002bf8: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
8002bfc: fa93 f3a3 rbit r3, r3
8002c00: f8c7 30ac str.w r3, [r7, #172] @ 0xac
return result;
8002c04: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8002c08: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
if (value == 0U)
8002c0c: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8002c10: 2b00 cmp r3, #0
8002c12: d101 bne.n 8002c18 <HAL_ADC_ConfigChannel+0x1d8>
return 32U;
8002c14: 2320 movs r3, #32
8002c16: e004 b.n 8002c22 <HAL_ADC_ConfigChannel+0x1e2>
return __builtin_clz(value);
8002c18: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8002c1c: fab3 f383 clz r3, r3
8002c20: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
8002c22: 429a cmp r2, r3
8002c24: d106 bne.n 8002c34 <HAL_ADC_ConfigChannel+0x1f4>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
8002c26: 687b ldr r3, [r7, #4]
8002c28: 681b ldr r3, [r3, #0]
8002c2a: 2200 movs r2, #0
8002c2c: 2100 movs r1, #0
8002c2e: 4618 mov r0, r3
8002c30: f7ff f9a0 bl 8001f74 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002c34: 687b ldr r3, [r7, #4]
8002c36: 681b ldr r3, [r3, #0]
8002c38: 2101 movs r1, #1
8002c3a: 4618 mov r0, r3
8002c3c: f7ff f984 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002c40: 4603 mov r3, r0
8002c42: f3c3 0312 ubfx r3, r3, #0, #19
8002c46: 2b00 cmp r3, #0
8002c48: d10a bne.n 8002c60 <HAL_ADC_ConfigChannel+0x220>
8002c4a: 687b ldr r3, [r7, #4]
8002c4c: 681b ldr r3, [r3, #0]
8002c4e: 2101 movs r1, #1
8002c50: 4618 mov r0, r3
8002c52: f7ff f979 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002c56: 4603 mov r3, r0
8002c58: 0e9b lsrs r3, r3, #26
8002c5a: f003 021f and.w r2, r3, #31
8002c5e: e01e b.n 8002c9e <HAL_ADC_ConfigChannel+0x25e>
8002c60: 687b ldr r3, [r7, #4]
8002c62: 681b ldr r3, [r3, #0]
8002c64: 2101 movs r1, #1
8002c66: 4618 mov r0, r3
8002c68: f7ff f96e bl 8001f48 <LL_ADC_GetOffsetChannel>
8002c6c: 4603 mov r3, r0
8002c6e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c72: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8002c76: fa93 f3a3 rbit r3, r3
8002c7a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return result;
8002c7e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8002c82: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
if (value == 0U)
8002c86: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8002c8a: 2b00 cmp r3, #0
8002c8c: d101 bne.n 8002c92 <HAL_ADC_ConfigChannel+0x252>
return 32U;
8002c8e: 2320 movs r3, #32
8002c90: e004 b.n 8002c9c <HAL_ADC_ConfigChannel+0x25c>
return __builtin_clz(value);
8002c92: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8002c96: fab3 f383 clz r3, r3
8002c9a: b2db uxtb r3, r3
8002c9c: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002c9e: 683b ldr r3, [r7, #0]
8002ca0: 681b ldr r3, [r3, #0]
8002ca2: f3c3 0312 ubfx r3, r3, #0, #19
8002ca6: 2b00 cmp r3, #0
8002ca8: d105 bne.n 8002cb6 <HAL_ADC_ConfigChannel+0x276>
8002caa: 683b ldr r3, [r7, #0]
8002cac: 681b ldr r3, [r3, #0]
8002cae: 0e9b lsrs r3, r3, #26
8002cb0: f003 031f and.w r3, r3, #31
8002cb4: e018 b.n 8002ce8 <HAL_ADC_ConfigChannel+0x2a8>
8002cb6: 683b ldr r3, [r7, #0]
8002cb8: 681b ldr r3, [r3, #0]
8002cba: f8c7 3098 str.w r3, [r7, #152] @ 0x98
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002cbe: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8002cc2: fa93 f3a3 rbit r3, r3
8002cc6: f8c7 3094 str.w r3, [r7, #148] @ 0x94
return result;
8002cca: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
8002cce: f8c7 309c str.w r3, [r7, #156] @ 0x9c
if (value == 0U)
8002cd2: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8002cd6: 2b00 cmp r3, #0
8002cd8: d101 bne.n 8002cde <HAL_ADC_ConfigChannel+0x29e>
return 32U;
8002cda: 2320 movs r3, #32
8002cdc: e004 b.n 8002ce8 <HAL_ADC_ConfigChannel+0x2a8>
return __builtin_clz(value);
8002cde: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8002ce2: fab3 f383 clz r3, r3
8002ce6: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002ce8: 429a cmp r2, r3
8002cea: d106 bne.n 8002cfa <HAL_ADC_ConfigChannel+0x2ba>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
8002cec: 687b ldr r3, [r7, #4]
8002cee: 681b ldr r3, [r3, #0]
8002cf0: 2200 movs r2, #0
8002cf2: 2101 movs r1, #1
8002cf4: 4618 mov r0, r3
8002cf6: f7ff f93d bl 8001f74 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002cfa: 687b ldr r3, [r7, #4]
8002cfc: 681b ldr r3, [r3, #0]
8002cfe: 2102 movs r1, #2
8002d00: 4618 mov r0, r3
8002d02: f7ff f921 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002d06: 4603 mov r3, r0
8002d08: f3c3 0312 ubfx r3, r3, #0, #19
8002d0c: 2b00 cmp r3, #0
8002d0e: d10a bne.n 8002d26 <HAL_ADC_ConfigChannel+0x2e6>
8002d10: 687b ldr r3, [r7, #4]
8002d12: 681b ldr r3, [r3, #0]
8002d14: 2102 movs r1, #2
8002d16: 4618 mov r0, r3
8002d18: f7ff f916 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002d1c: 4603 mov r3, r0
8002d1e: 0e9b lsrs r3, r3, #26
8002d20: f003 021f and.w r2, r3, #31
8002d24: e01e b.n 8002d64 <HAL_ADC_ConfigChannel+0x324>
8002d26: 687b ldr r3, [r7, #4]
8002d28: 681b ldr r3, [r3, #0]
8002d2a: 2102 movs r1, #2
8002d2c: 4618 mov r0, r3
8002d2e: f7ff f90b bl 8001f48 <LL_ADC_GetOffsetChannel>
8002d32: 4603 mov r3, r0
8002d34: f8c7 308c str.w r3, [r7, #140] @ 0x8c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d38: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002d3c: fa93 f3a3 rbit r3, r3
8002d40: f8c7 3088 str.w r3, [r7, #136] @ 0x88
return result;
8002d44: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8002d48: f8c7 3090 str.w r3, [r7, #144] @ 0x90
if (value == 0U)
8002d4c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8002d50: 2b00 cmp r3, #0
8002d52: d101 bne.n 8002d58 <HAL_ADC_ConfigChannel+0x318>
return 32U;
8002d54: 2320 movs r3, #32
8002d56: e004 b.n 8002d62 <HAL_ADC_ConfigChannel+0x322>
return __builtin_clz(value);
8002d58: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8002d5c: fab3 f383 clz r3, r3
8002d60: b2db uxtb r3, r3
8002d62: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002d64: 683b ldr r3, [r7, #0]
8002d66: 681b ldr r3, [r3, #0]
8002d68: f3c3 0312 ubfx r3, r3, #0, #19
8002d6c: 2b00 cmp r3, #0
8002d6e: d105 bne.n 8002d7c <HAL_ADC_ConfigChannel+0x33c>
8002d70: 683b ldr r3, [r7, #0]
8002d72: 681b ldr r3, [r3, #0]
8002d74: 0e9b lsrs r3, r3, #26
8002d76: f003 031f and.w r3, r3, #31
8002d7a: e016 b.n 8002daa <HAL_ADC_ConfigChannel+0x36a>
8002d7c: 683b ldr r3, [r7, #0]
8002d7e: 681b ldr r3, [r3, #0]
8002d80: f8c7 3080 str.w r3, [r7, #128] @ 0x80
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d84: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002d88: fa93 f3a3 rbit r3, r3
8002d8c: 67fb str r3, [r7, #124] @ 0x7c
return result;
8002d8e: 6ffb ldr r3, [r7, #124] @ 0x7c
8002d90: f8c7 3084 str.w r3, [r7, #132] @ 0x84
if (value == 0U)
8002d94: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8002d98: 2b00 cmp r3, #0
8002d9a: d101 bne.n 8002da0 <HAL_ADC_ConfigChannel+0x360>
return 32U;
8002d9c: 2320 movs r3, #32
8002d9e: e004 b.n 8002daa <HAL_ADC_ConfigChannel+0x36a>
return __builtin_clz(value);
8002da0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8002da4: fab3 f383 clz r3, r3
8002da8: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002daa: 429a cmp r2, r3
8002dac: d106 bne.n 8002dbc <HAL_ADC_ConfigChannel+0x37c>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
8002dae: 687b ldr r3, [r7, #4]
8002db0: 681b ldr r3, [r3, #0]
8002db2: 2200 movs r2, #0
8002db4: 2102 movs r1, #2
8002db6: 4618 mov r0, r3
8002db8: f7ff f8dc bl 8001f74 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002dbc: 687b ldr r3, [r7, #4]
8002dbe: 681b ldr r3, [r3, #0]
8002dc0: 2103 movs r1, #3
8002dc2: 4618 mov r0, r3
8002dc4: f7ff f8c0 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002dc8: 4603 mov r3, r0
8002dca: f3c3 0312 ubfx r3, r3, #0, #19
8002dce: 2b00 cmp r3, #0
8002dd0: d10a bne.n 8002de8 <HAL_ADC_ConfigChannel+0x3a8>
8002dd2: 687b ldr r3, [r7, #4]
8002dd4: 681b ldr r3, [r3, #0]
8002dd6: 2103 movs r1, #3
8002dd8: 4618 mov r0, r3
8002dda: f7ff f8b5 bl 8001f48 <LL_ADC_GetOffsetChannel>
8002dde: 4603 mov r3, r0
8002de0: 0e9b lsrs r3, r3, #26
8002de2: f003 021f and.w r2, r3, #31
8002de6: e017 b.n 8002e18 <HAL_ADC_ConfigChannel+0x3d8>
8002de8: 687b ldr r3, [r7, #4]
8002dea: 681b ldr r3, [r3, #0]
8002dec: 2103 movs r1, #3
8002dee: 4618 mov r0, r3
8002df0: f7ff f8aa bl 8001f48 <LL_ADC_GetOffsetChannel>
8002df4: 4603 mov r3, r0
8002df6: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002df8: 6f7b ldr r3, [r7, #116] @ 0x74
8002dfa: fa93 f3a3 rbit r3, r3
8002dfe: 673b str r3, [r7, #112] @ 0x70
return result;
8002e00: 6f3b ldr r3, [r7, #112] @ 0x70
8002e02: 67bb str r3, [r7, #120] @ 0x78
if (value == 0U)
8002e04: 6fbb ldr r3, [r7, #120] @ 0x78
8002e06: 2b00 cmp r3, #0
8002e08: d101 bne.n 8002e0e <HAL_ADC_ConfigChannel+0x3ce>
return 32U;
8002e0a: 2320 movs r3, #32
8002e0c: e003 b.n 8002e16 <HAL_ADC_ConfigChannel+0x3d6>
return __builtin_clz(value);
8002e0e: 6fbb ldr r3, [r7, #120] @ 0x78
8002e10: fab3 f383 clz r3, r3
8002e14: b2db uxtb r3, r3
8002e16: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002e18: 683b ldr r3, [r7, #0]
8002e1a: 681b ldr r3, [r3, #0]
8002e1c: f3c3 0312 ubfx r3, r3, #0, #19
8002e20: 2b00 cmp r3, #0
8002e22: d105 bne.n 8002e30 <HAL_ADC_ConfigChannel+0x3f0>
8002e24: 683b ldr r3, [r7, #0]
8002e26: 681b ldr r3, [r3, #0]
8002e28: 0e9b lsrs r3, r3, #26
8002e2a: f003 031f and.w r3, r3, #31
8002e2e: e011 b.n 8002e54 <HAL_ADC_ConfigChannel+0x414>
8002e30: 683b ldr r3, [r7, #0]
8002e32: 681b ldr r3, [r3, #0]
8002e34: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e36: 6ebb ldr r3, [r7, #104] @ 0x68
8002e38: fa93 f3a3 rbit r3, r3
8002e3c: 667b str r3, [r7, #100] @ 0x64
return result;
8002e3e: 6e7b ldr r3, [r7, #100] @ 0x64
8002e40: 66fb str r3, [r7, #108] @ 0x6c
if (value == 0U)
8002e42: 6efb ldr r3, [r7, #108] @ 0x6c
8002e44: 2b00 cmp r3, #0
8002e46: d101 bne.n 8002e4c <HAL_ADC_ConfigChannel+0x40c>
return 32U;
8002e48: 2320 movs r3, #32
8002e4a: e003 b.n 8002e54 <HAL_ADC_ConfigChannel+0x414>
return __builtin_clz(value);
8002e4c: 6efb ldr r3, [r7, #108] @ 0x6c
8002e4e: fab3 f383 clz r3, r3
8002e52: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002e54: 429a cmp r2, r3
8002e56: d106 bne.n 8002e66 <HAL_ADC_ConfigChannel+0x426>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
8002e58: 687b ldr r3, [r7, #4]
8002e5a: 681b ldr r3, [r3, #0]
8002e5c: 2200 movs r2, #0
8002e5e: 2103 movs r1, #3
8002e60: 4618 mov r0, r3
8002e62: f7ff f887 bl 8001f74 <LL_ADC_SetOffsetState>
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002e66: 687b ldr r3, [r7, #4]
8002e68: 681b ldr r3, [r3, #0]
8002e6a: 4618 mov r0, r3
8002e6c: f7ff fa06 bl 800227c <LL_ADC_IsEnabled>
8002e70: 4603 mov r3, r0
8002e72: 2b00 cmp r3, #0
8002e74: f040 8140 bne.w 80030f8 <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
8002e78: 687b ldr r3, [r7, #4]
8002e7a: 6818 ldr r0, [r3, #0]
8002e7c: 683b ldr r3, [r7, #0]
8002e7e: 6819 ldr r1, [r3, #0]
8002e80: 683b ldr r3, [r7, #0]
8002e82: 68db ldr r3, [r3, #12]
8002e84: 461a mov r2, r3
8002e86: f7ff f943 bl 8002110 <LL_ADC_SetChannelSingleDiff>
/* Configuration of differential mode */
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
8002e8a: 683b ldr r3, [r7, #0]
8002e8c: 68db ldr r3, [r3, #12]
8002e8e: 4a8f ldr r2, [pc, #572] @ (80030cc <HAL_ADC_ConfigChannel+0x68c>)
8002e90: 4293 cmp r3, r2
8002e92: f040 8131 bne.w 80030f8 <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002e96: 687b ldr r3, [r7, #4]
8002e98: 6818 ldr r0, [r3, #0]
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002e9a: 683b ldr r3, [r7, #0]
8002e9c: 681b ldr r3, [r3, #0]
8002e9e: f3c3 0312 ubfx r3, r3, #0, #19
8002ea2: 2b00 cmp r3, #0
8002ea4: d10b bne.n 8002ebe <HAL_ADC_ConfigChannel+0x47e>
8002ea6: 683b ldr r3, [r7, #0]
8002ea8: 681b ldr r3, [r3, #0]
8002eaa: 0e9b lsrs r3, r3, #26
8002eac: 3301 adds r3, #1
8002eae: f003 031f and.w r3, r3, #31
8002eb2: 2b09 cmp r3, #9
8002eb4: bf94 ite ls
8002eb6: 2301 movls r3, #1
8002eb8: 2300 movhi r3, #0
8002eba: b2db uxtb r3, r3
8002ebc: e019 b.n 8002ef2 <HAL_ADC_ConfigChannel+0x4b2>
8002ebe: 683b ldr r3, [r7, #0]
8002ec0: 681b ldr r3, [r3, #0]
8002ec2: 65fb str r3, [r7, #92] @ 0x5c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ec4: 6dfb ldr r3, [r7, #92] @ 0x5c
8002ec6: fa93 f3a3 rbit r3, r3
8002eca: 65bb str r3, [r7, #88] @ 0x58
return result;
8002ecc: 6dbb ldr r3, [r7, #88] @ 0x58
8002ece: 663b str r3, [r7, #96] @ 0x60
if (value == 0U)
8002ed0: 6e3b ldr r3, [r7, #96] @ 0x60
8002ed2: 2b00 cmp r3, #0
8002ed4: d101 bne.n 8002eda <HAL_ADC_ConfigChannel+0x49a>
return 32U;
8002ed6: 2320 movs r3, #32
8002ed8: e003 b.n 8002ee2 <HAL_ADC_ConfigChannel+0x4a2>
return __builtin_clz(value);
8002eda: 6e3b ldr r3, [r7, #96] @ 0x60
8002edc: fab3 f383 clz r3, r3
8002ee0: b2db uxtb r3, r3
8002ee2: 3301 adds r3, #1
8002ee4: f003 031f and.w r3, r3, #31
8002ee8: 2b09 cmp r3, #9
8002eea: bf94 ite ls
8002eec: 2301 movls r3, #1
8002eee: 2300 movhi r3, #0
8002ef0: b2db uxtb r3, r3
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002ef2: 2b00 cmp r3, #0
8002ef4: d079 beq.n 8002fea <HAL_ADC_ConfigChannel+0x5aa>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002ef6: 683b ldr r3, [r7, #0]
8002ef8: 681b ldr r3, [r3, #0]
8002efa: f3c3 0312 ubfx r3, r3, #0, #19
8002efe: 2b00 cmp r3, #0
8002f00: d107 bne.n 8002f12 <HAL_ADC_ConfigChannel+0x4d2>
8002f02: 683b ldr r3, [r7, #0]
8002f04: 681b ldr r3, [r3, #0]
8002f06: 0e9b lsrs r3, r3, #26
8002f08: 3301 adds r3, #1
8002f0a: 069b lsls r3, r3, #26
8002f0c: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002f10: e015 b.n 8002f3e <HAL_ADC_ConfigChannel+0x4fe>
8002f12: 683b ldr r3, [r7, #0]
8002f14: 681b ldr r3, [r3, #0]
8002f16: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f18: 6d3b ldr r3, [r7, #80] @ 0x50
8002f1a: fa93 f3a3 rbit r3, r3
8002f1e: 64fb str r3, [r7, #76] @ 0x4c
return result;
8002f20: 6cfb ldr r3, [r7, #76] @ 0x4c
8002f22: 657b str r3, [r7, #84] @ 0x54
if (value == 0U)
8002f24: 6d7b ldr r3, [r7, #84] @ 0x54
8002f26: 2b00 cmp r3, #0
8002f28: d101 bne.n 8002f2e <HAL_ADC_ConfigChannel+0x4ee>
return 32U;
8002f2a: 2320 movs r3, #32
8002f2c: e003 b.n 8002f36 <HAL_ADC_ConfigChannel+0x4f6>
return __builtin_clz(value);
8002f2e: 6d7b ldr r3, [r7, #84] @ 0x54
8002f30: fab3 f383 clz r3, r3
8002f34: b2db uxtb r3, r3
8002f36: 3301 adds r3, #1
8002f38: 069b lsls r3, r3, #26
8002f3a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002f3e: 683b ldr r3, [r7, #0]
8002f40: 681b ldr r3, [r3, #0]
8002f42: f3c3 0312 ubfx r3, r3, #0, #19
8002f46: 2b00 cmp r3, #0
8002f48: d109 bne.n 8002f5e <HAL_ADC_ConfigChannel+0x51e>
8002f4a: 683b ldr r3, [r7, #0]
8002f4c: 681b ldr r3, [r3, #0]
8002f4e: 0e9b lsrs r3, r3, #26
8002f50: 3301 adds r3, #1
8002f52: f003 031f and.w r3, r3, #31
8002f56: 2101 movs r1, #1
8002f58: fa01 f303 lsl.w r3, r1, r3
8002f5c: e017 b.n 8002f8e <HAL_ADC_ConfigChannel+0x54e>
8002f5e: 683b ldr r3, [r7, #0]
8002f60: 681b ldr r3, [r3, #0]
8002f62: 647b str r3, [r7, #68] @ 0x44
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f64: 6c7b ldr r3, [r7, #68] @ 0x44
8002f66: fa93 f3a3 rbit r3, r3
8002f6a: 643b str r3, [r7, #64] @ 0x40
return result;
8002f6c: 6c3b ldr r3, [r7, #64] @ 0x40
8002f6e: 64bb str r3, [r7, #72] @ 0x48
if (value == 0U)
8002f70: 6cbb ldr r3, [r7, #72] @ 0x48
8002f72: 2b00 cmp r3, #0
8002f74: d101 bne.n 8002f7a <HAL_ADC_ConfigChannel+0x53a>
return 32U;
8002f76: 2320 movs r3, #32
8002f78: e003 b.n 8002f82 <HAL_ADC_ConfigChannel+0x542>
return __builtin_clz(value);
8002f7a: 6cbb ldr r3, [r7, #72] @ 0x48
8002f7c: fab3 f383 clz r3, r3
8002f80: b2db uxtb r3, r3
8002f82: 3301 adds r3, #1
8002f84: f003 031f and.w r3, r3, #31
8002f88: 2101 movs r1, #1
8002f8a: fa01 f303 lsl.w r3, r1, r3
8002f8e: ea42 0103 orr.w r1, r2, r3
8002f92: 683b ldr r3, [r7, #0]
8002f94: 681b ldr r3, [r3, #0]
8002f96: f3c3 0312 ubfx r3, r3, #0, #19
8002f9a: 2b00 cmp r3, #0
8002f9c: d10a bne.n 8002fb4 <HAL_ADC_ConfigChannel+0x574>
8002f9e: 683b ldr r3, [r7, #0]
8002fa0: 681b ldr r3, [r3, #0]
8002fa2: 0e9b lsrs r3, r3, #26
8002fa4: 3301 adds r3, #1
8002fa6: f003 021f and.w r2, r3, #31
8002faa: 4613 mov r3, r2
8002fac: 005b lsls r3, r3, #1
8002fae: 4413 add r3, r2
8002fb0: 051b lsls r3, r3, #20
8002fb2: e018 b.n 8002fe6 <HAL_ADC_ConfigChannel+0x5a6>
8002fb4: 683b ldr r3, [r7, #0]
8002fb6: 681b ldr r3, [r3, #0]
8002fb8: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002fba: 6bbb ldr r3, [r7, #56] @ 0x38
8002fbc: fa93 f3a3 rbit r3, r3
8002fc0: 637b str r3, [r7, #52] @ 0x34
return result;
8002fc2: 6b7b ldr r3, [r7, #52] @ 0x34
8002fc4: 63fb str r3, [r7, #60] @ 0x3c
if (value == 0U)
8002fc6: 6bfb ldr r3, [r7, #60] @ 0x3c
8002fc8: 2b00 cmp r3, #0
8002fca: d101 bne.n 8002fd0 <HAL_ADC_ConfigChannel+0x590>
return 32U;
8002fcc: 2320 movs r3, #32
8002fce: e003 b.n 8002fd8 <HAL_ADC_ConfigChannel+0x598>
return __builtin_clz(value);
8002fd0: 6bfb ldr r3, [r7, #60] @ 0x3c
8002fd2: fab3 f383 clz r3, r3
8002fd6: b2db uxtb r3, r3
8002fd8: 3301 adds r3, #1
8002fda: f003 021f and.w r2, r3, #31
8002fde: 4613 mov r3, r2
8002fe0: 005b lsls r3, r3, #1
8002fe2: 4413 add r3, r2
8002fe4: 051b lsls r3, r3, #20
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002fe6: 430b orrs r3, r1
8002fe8: e081 b.n 80030ee <HAL_ADC_ConfigChannel+0x6ae>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002fea: 683b ldr r3, [r7, #0]
8002fec: 681b ldr r3, [r3, #0]
8002fee: f3c3 0312 ubfx r3, r3, #0, #19
8002ff2: 2b00 cmp r3, #0
8002ff4: d107 bne.n 8003006 <HAL_ADC_ConfigChannel+0x5c6>
8002ff6: 683b ldr r3, [r7, #0]
8002ff8: 681b ldr r3, [r3, #0]
8002ffa: 0e9b lsrs r3, r3, #26
8002ffc: 3301 adds r3, #1
8002ffe: 069b lsls r3, r3, #26
8003000: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8003004: e015 b.n 8003032 <HAL_ADC_ConfigChannel+0x5f2>
8003006: 683b ldr r3, [r7, #0]
8003008: 681b ldr r3, [r3, #0]
800300a: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800300c: 6afb ldr r3, [r7, #44] @ 0x2c
800300e: fa93 f3a3 rbit r3, r3
8003012: 62bb str r3, [r7, #40] @ 0x28
return result;
8003014: 6abb ldr r3, [r7, #40] @ 0x28
8003016: 633b str r3, [r7, #48] @ 0x30
if (value == 0U)
8003018: 6b3b ldr r3, [r7, #48] @ 0x30
800301a: 2b00 cmp r3, #0
800301c: d101 bne.n 8003022 <HAL_ADC_ConfigChannel+0x5e2>
return 32U;
800301e: 2320 movs r3, #32
8003020: e003 b.n 800302a <HAL_ADC_ConfigChannel+0x5ea>
return __builtin_clz(value);
8003022: 6b3b ldr r3, [r7, #48] @ 0x30
8003024: fab3 f383 clz r3, r3
8003028: b2db uxtb r3, r3
800302a: 3301 adds r3, #1
800302c: 069b lsls r3, r3, #26
800302e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8003032: 683b ldr r3, [r7, #0]
8003034: 681b ldr r3, [r3, #0]
8003036: f3c3 0312 ubfx r3, r3, #0, #19
800303a: 2b00 cmp r3, #0
800303c: d109 bne.n 8003052 <HAL_ADC_ConfigChannel+0x612>
800303e: 683b ldr r3, [r7, #0]
8003040: 681b ldr r3, [r3, #0]
8003042: 0e9b lsrs r3, r3, #26
8003044: 3301 adds r3, #1
8003046: f003 031f and.w r3, r3, #31
800304a: 2101 movs r1, #1
800304c: fa01 f303 lsl.w r3, r1, r3
8003050: e017 b.n 8003082 <HAL_ADC_ConfigChannel+0x642>
8003052: 683b ldr r3, [r7, #0]
8003054: 681b ldr r3, [r3, #0]
8003056: 623b str r3, [r7, #32]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003058: 6a3b ldr r3, [r7, #32]
800305a: fa93 f3a3 rbit r3, r3
800305e: 61fb str r3, [r7, #28]
return result;
8003060: 69fb ldr r3, [r7, #28]
8003062: 627b str r3, [r7, #36] @ 0x24
if (value == 0U)
8003064: 6a7b ldr r3, [r7, #36] @ 0x24
8003066: 2b00 cmp r3, #0
8003068: d101 bne.n 800306e <HAL_ADC_ConfigChannel+0x62e>
return 32U;
800306a: 2320 movs r3, #32
800306c: e003 b.n 8003076 <HAL_ADC_ConfigChannel+0x636>
return __builtin_clz(value);
800306e: 6a7b ldr r3, [r7, #36] @ 0x24
8003070: fab3 f383 clz r3, r3
8003074: b2db uxtb r3, r3
8003076: 3301 adds r3, #1
8003078: f003 031f and.w r3, r3, #31
800307c: 2101 movs r1, #1
800307e: fa01 f303 lsl.w r3, r1, r3
8003082: ea42 0103 orr.w r1, r2, r3
8003086: 683b ldr r3, [r7, #0]
8003088: 681b ldr r3, [r3, #0]
800308a: f3c3 0312 ubfx r3, r3, #0, #19
800308e: 2b00 cmp r3, #0
8003090: d10d bne.n 80030ae <HAL_ADC_ConfigChannel+0x66e>
8003092: 683b ldr r3, [r7, #0]
8003094: 681b ldr r3, [r3, #0]
8003096: 0e9b lsrs r3, r3, #26
8003098: 3301 adds r3, #1
800309a: f003 021f and.w r2, r3, #31
800309e: 4613 mov r3, r2
80030a0: 005b lsls r3, r3, #1
80030a2: 4413 add r3, r2
80030a4: 3b1e subs r3, #30
80030a6: 051b lsls r3, r3, #20
80030a8: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
80030ac: e01e b.n 80030ec <HAL_ADC_ConfigChannel+0x6ac>
80030ae: 683b ldr r3, [r7, #0]
80030b0: 681b ldr r3, [r3, #0]
80030b2: 617b str r3, [r7, #20]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80030b4: 697b ldr r3, [r7, #20]
80030b6: fa93 f3a3 rbit r3, r3
80030ba: 613b str r3, [r7, #16]
return result;
80030bc: 693b ldr r3, [r7, #16]
80030be: 61bb str r3, [r7, #24]
if (value == 0U)
80030c0: 69bb ldr r3, [r7, #24]
80030c2: 2b00 cmp r3, #0
80030c4: d104 bne.n 80030d0 <HAL_ADC_ConfigChannel+0x690>
return 32U;
80030c6: 2320 movs r3, #32
80030c8: e006 b.n 80030d8 <HAL_ADC_ConfigChannel+0x698>
80030ca: bf00 nop
80030cc: 407f0000 .word 0x407f0000
return __builtin_clz(value);
80030d0: 69bb ldr r3, [r7, #24]
80030d2: fab3 f383 clz r3, r3
80030d6: b2db uxtb r3, r3
80030d8: 3301 adds r3, #1
80030da: f003 021f and.w r2, r3, #31
80030de: 4613 mov r3, r2
80030e0: 005b lsls r3, r3, #1
80030e2: 4413 add r3, r2
80030e4: 3b1e subs r3, #30
80030e6: 051b lsls r3, r3, #20
80030e8: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
LL_ADC_SetChannelSamplingTime(hadc->Instance,
80030ec: 430b orrs r3, r1
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+ 1UL) & 0x1FUL)),
pConfig->SamplingTime);
80030ee: 683a ldr r2, [r7, #0]
80030f0: 6892 ldr r2, [r2, #8]
LL_ADC_SetChannelSamplingTime(hadc->Instance,
80030f2: 4619 mov r1, r3
80030f4: f7fe ffe1 bl 80020ba <LL_ADC_SetChannelSamplingTime>
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
80030f8: 683b ldr r3, [r7, #0]
80030fa: 681a ldr r2, [r3, #0]
80030fc: 4b3f ldr r3, [pc, #252] @ (80031fc <HAL_ADC_ConfigChannel+0x7bc>)
80030fe: 4013 ands r3, r2
8003100: 2b00 cmp r3, #0
8003102: d071 beq.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8003104: 483e ldr r0, [pc, #248] @ (8003200 <HAL_ADC_ConfigChannel+0x7c0>)
8003106: f7fe feed bl 8001ee4 <LL_ADC_GetCommonPathInternalCh>
800310a: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
800310e: 683b ldr r3, [r7, #0]
8003110: 681b ldr r3, [r3, #0]
8003112: 4a3c ldr r2, [pc, #240] @ (8003204 <HAL_ADC_ConfigChannel+0x7c4>)
8003114: 4293 cmp r3, r2
8003116: d004 beq.n 8003122 <HAL_ADC_ConfigChannel+0x6e2>
8003118: 683b ldr r3, [r7, #0]
800311a: 681b ldr r3, [r3, #0]
800311c: 4a3a ldr r2, [pc, #232] @ (8003208 <HAL_ADC_ConfigChannel+0x7c8>)
800311e: 4293 cmp r3, r2
8003120: d127 bne.n 8003172 <HAL_ADC_ConfigChannel+0x732>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8003122: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8003126: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800312a: 2b00 cmp r3, #0
800312c: d121 bne.n 8003172 <HAL_ADC_ConfigChannel+0x732>
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
800312e: 687b ldr r3, [r7, #4]
8003130: 681b ldr r3, [r3, #0]
8003132: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8003136: d157 bne.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8003138: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
800313c: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8003140: 4619 mov r1, r3
8003142: 482f ldr r0, [pc, #188] @ (8003200 <HAL_ADC_ConfigChannel+0x7c0>)
8003144: f7fe febb bl 8001ebe <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8003148: 4b30 ldr r3, [pc, #192] @ (800320c <HAL_ADC_ConfigChannel+0x7cc>)
800314a: 681b ldr r3, [r3, #0]
800314c: 099b lsrs r3, r3, #6
800314e: 4a30 ldr r2, [pc, #192] @ (8003210 <HAL_ADC_ConfigChannel+0x7d0>)
8003150: fba2 2303 umull r2, r3, r2, r3
8003154: 099b lsrs r3, r3, #6
8003156: 1c5a adds r2, r3, #1
8003158: 4613 mov r3, r2
800315a: 005b lsls r3, r3, #1
800315c: 4413 add r3, r2
800315e: 009b lsls r3, r3, #2
8003160: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8003162: e002 b.n 800316a <HAL_ADC_ConfigChannel+0x72a>
{
wait_loop_index--;
8003164: 68fb ldr r3, [r7, #12]
8003166: 3b01 subs r3, #1
8003168: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
800316a: 68fb ldr r3, [r7, #12]
800316c: 2b00 cmp r3, #0
800316e: d1f9 bne.n 8003164 <HAL_ADC_ConfigChannel+0x724>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8003170: e03a b.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
}
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
8003172: 683b ldr r3, [r7, #0]
8003174: 681b ldr r3, [r3, #0]
8003176: 4a27 ldr r2, [pc, #156] @ (8003214 <HAL_ADC_ConfigChannel+0x7d4>)
8003178: 4293 cmp r3, r2
800317a: d113 bne.n 80031a4 <HAL_ADC_ConfigChannel+0x764>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
800317c: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8003180: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8003184: 2b00 cmp r3, #0
8003186: d10d bne.n 80031a4 <HAL_ADC_ConfigChannel+0x764>
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8003188: 687b ldr r3, [r7, #4]
800318a: 681b ldr r3, [r3, #0]
800318c: 4a22 ldr r2, [pc, #136] @ (8003218 <HAL_ADC_ConfigChannel+0x7d8>)
800318e: 4293 cmp r3, r2
8003190: d02a beq.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8003192: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8003196: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800319a: 4619 mov r1, r3
800319c: 4818 ldr r0, [pc, #96] @ (8003200 <HAL_ADC_ConfigChannel+0x7c0>)
800319e: f7fe fe8e bl 8001ebe <LL_ADC_SetCommonPathInternalCh>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
80031a2: e021 b.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
80031a4: 683b ldr r3, [r7, #0]
80031a6: 681b ldr r3, [r3, #0]
80031a8: 4a1c ldr r2, [pc, #112] @ (800321c <HAL_ADC_ConfigChannel+0x7dc>)
80031aa: 4293 cmp r3, r2
80031ac: d11c bne.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
80031ae: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
80031b2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
80031b6: 2b00 cmp r3, #0
80031b8: d116 bne.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
{
if (ADC_VREFINT_INSTANCE(hadc))
80031ba: 687b ldr r3, [r7, #4]
80031bc: 681b ldr r3, [r3, #0]
80031be: 4a16 ldr r2, [pc, #88] @ (8003218 <HAL_ADC_ConfigChannel+0x7d8>)
80031c0: 4293 cmp r3, r2
80031c2: d011 beq.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
80031c4: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
80031c8: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
80031cc: 4619 mov r1, r3
80031ce: 480c ldr r0, [pc, #48] @ (8003200 <HAL_ADC_ConfigChannel+0x7c0>)
80031d0: f7fe fe75 bl 8001ebe <LL_ADC_SetCommonPathInternalCh>
80031d4: e008 b.n 80031e8 <HAL_ADC_ConfigChannel+0x7a8>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80031d6: 687b ldr r3, [r7, #4]
80031d8: 6ddb ldr r3, [r3, #92] @ 0x5c
80031da: f043 0220 orr.w r2, r3, #32
80031de: 687b ldr r3, [r7, #4]
80031e0: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
80031e2: 2301 movs r3, #1
80031e4: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80031e8: 687b ldr r3, [r7, #4]
80031ea: 2200 movs r2, #0
80031ec: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
80031f0: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7
}
80031f4: 4618 mov r0, r3
80031f6: 37d8 adds r7, #216 @ 0xd8
80031f8: 46bd mov sp, r7
80031fa: bd80 pop {r7, pc}
80031fc: 80080000 .word 0x80080000
8003200: 50000300 .word 0x50000300
8003204: c3210000 .word 0xc3210000
8003208: 90c00010 .word 0x90c00010
800320c: 2000001c .word 0x2000001c
8003210: 053e2d63 .word 0x053e2d63
8003214: c7520000 .word 0xc7520000
8003218: 50000100 .word 0x50000100
800321c: cb840000 .word 0xcb840000
08003220 <ADC_ConversionStop>:
* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
{
8003220: b580 push {r7, lr}
8003222: b088 sub sp, #32
8003224: af00 add r7, sp, #0
8003226: 6078 str r0, [r7, #4]
8003228: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t Conversion_Timeout_CPU_cycles = 0UL;
800322a: 2300 movs r3, #0
800322c: 61fb str r3, [r7, #28]
uint32_t conversion_group_reassigned = ConversionGroup;
800322e: 683b ldr r3, [r7, #0]
8003230: 61bb str r3, [r7, #24]
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
/* Verification if ADC is not already stopped (on regular and injected */
/* groups) to bypass this function if not needed. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8003232: 687b ldr r3, [r7, #4]
8003234: 681b ldr r3, [r3, #0]
8003236: 4618 mov r0, r3
8003238: f7ff f86e bl 8002318 <LL_ADC_REG_IsConversionOngoing>
800323c: 6138 str r0, [r7, #16]
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
800323e: 687b ldr r3, [r7, #4]
8003240: 681b ldr r3, [r3, #0]
8003242: 4618 mov r0, r3
8003244: f7ff f88f bl 8002366 <LL_ADC_INJ_IsConversionOngoing>
8003248: 60f8 str r0, [r7, #12]
if ((tmp_adc_is_conversion_on_going_regular != 0UL)
800324a: 693b ldr r3, [r7, #16]
800324c: 2b00 cmp r3, #0
800324e: d103 bne.n 8003258 <ADC_ConversionStop+0x38>
|| (tmp_adc_is_conversion_on_going_injected != 0UL)
8003250: 68fb ldr r3, [r7, #12]
8003252: 2b00 cmp r3, #0
8003254: f000 8098 beq.w 8003388 <ADC_ConversionStop+0x168>
/* auto-delay mode. */
/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
/* injected group stop ADC_CR_JADSTP). */
/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
/* (see reference manual). */
if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
8003258: 687b ldr r3, [r7, #4]
800325a: 681b ldr r3, [r3, #0]
800325c: 68db ldr r3, [r3, #12]
800325e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003262: 2b00 cmp r3, #0
8003264: d02a beq.n 80032bc <ADC_ConversionStop+0x9c>
&& (hadc->Init.ContinuousConvMode == ENABLE)
8003266: 687b ldr r3, [r7, #4]
8003268: 7f5b ldrb r3, [r3, #29]
800326a: 2b01 cmp r3, #1
800326c: d126 bne.n 80032bc <ADC_ConversionStop+0x9c>
&& (hadc->Init.LowPowerAutoWait == ENABLE)
800326e: 687b ldr r3, [r7, #4]
8003270: 7f1b ldrb r3, [r3, #28]
8003272: 2b01 cmp r3, #1
8003274: d122 bne.n 80032bc <ADC_ConversionStop+0x9c>
)
{
/* Use stop of regular group */
conversion_group_reassigned = ADC_REGULAR_GROUP;
8003276: 2301 movs r3, #1
8003278: 61bb str r3, [r7, #24]
/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
800327a: e014 b.n 80032a6 <ADC_ConversionStop+0x86>
{
if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
800327c: 69fb ldr r3, [r7, #28]
800327e: 4a45 ldr r2, [pc, #276] @ (8003394 <ADC_ConversionStop+0x174>)
8003280: 4293 cmp r3, r2
8003282: d90d bls.n 80032a0 <ADC_ConversionStop+0x80>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003284: 687b ldr r3, [r7, #4]
8003286: 6ddb ldr r3, [r3, #92] @ 0x5c
8003288: f043 0210 orr.w r2, r3, #16
800328c: 687b ldr r3, [r7, #4]
800328e: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003290: 687b ldr r3, [r7, #4]
8003292: 6e1b ldr r3, [r3, #96] @ 0x60
8003294: f043 0201 orr.w r2, r3, #1
8003298: 687b ldr r3, [r7, #4]
800329a: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
800329c: 2301 movs r3, #1
800329e: e074 b.n 800338a <ADC_ConversionStop+0x16a>
}
Conversion_Timeout_CPU_cycles ++;
80032a0: 69fb ldr r3, [r7, #28]
80032a2: 3301 adds r3, #1
80032a4: 61fb str r3, [r7, #28]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
80032a6: 687b ldr r3, [r7, #4]
80032a8: 681b ldr r3, [r3, #0]
80032aa: 681b ldr r3, [r3, #0]
80032ac: f003 0340 and.w r3, r3, #64 @ 0x40
80032b0: 2b40 cmp r3, #64 @ 0x40
80032b2: d1e3 bne.n 800327c <ADC_ConversionStop+0x5c>
}
/* Clear JEOS */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
80032b4: 687b ldr r3, [r7, #4]
80032b6: 681b ldr r3, [r3, #0]
80032b8: 2240 movs r2, #64 @ 0x40
80032ba: 601a str r2, [r3, #0]
}
/* Stop potential conversion on going on ADC group regular */
if (conversion_group_reassigned != ADC_INJECTED_GROUP)
80032bc: 69bb ldr r3, [r7, #24]
80032be: 2b02 cmp r3, #2
80032c0: d014 beq.n 80032ec <ADC_ConversionStop+0xcc>
{
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
80032c2: 687b ldr r3, [r7, #4]
80032c4: 681b ldr r3, [r3, #0]
80032c6: 4618 mov r0, r3
80032c8: f7ff f826 bl 8002318 <LL_ADC_REG_IsConversionOngoing>
80032cc: 4603 mov r3, r0
80032ce: 2b00 cmp r3, #0
80032d0: d00c beq.n 80032ec <ADC_ConversionStop+0xcc>
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
80032d2: 687b ldr r3, [r7, #4]
80032d4: 681b ldr r3, [r3, #0]
80032d6: 4618 mov r0, r3
80032d8: f7fe ffe3 bl 80022a2 <LL_ADC_IsDisableOngoing>
80032dc: 4603 mov r3, r0
80032de: 2b00 cmp r3, #0
80032e0: d104 bne.n 80032ec <ADC_ConversionStop+0xcc>
{
/* Stop ADC group regular conversion */
LL_ADC_REG_StopConversion(hadc->Instance);
80032e2: 687b ldr r3, [r7, #4]
80032e4: 681b ldr r3, [r3, #0]
80032e6: 4618 mov r0, r3
80032e8: f7ff f802 bl 80022f0 <LL_ADC_REG_StopConversion>
}
}
}
/* Stop potential conversion on going on ADC group injected */
if (conversion_group_reassigned != ADC_REGULAR_GROUP)
80032ec: 69bb ldr r3, [r7, #24]
80032ee: 2b01 cmp r3, #1
80032f0: d014 beq.n 800331c <ADC_ConversionStop+0xfc>
{
/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
80032f2: 687b ldr r3, [r7, #4]
80032f4: 681b ldr r3, [r3, #0]
80032f6: 4618 mov r0, r3
80032f8: f7ff f835 bl 8002366 <LL_ADC_INJ_IsConversionOngoing>
80032fc: 4603 mov r3, r0
80032fe: 2b00 cmp r3, #0
8003300: d00c beq.n 800331c <ADC_ConversionStop+0xfc>
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
8003302: 687b ldr r3, [r7, #4]
8003304: 681b ldr r3, [r3, #0]
8003306: 4618 mov r0, r3
8003308: f7fe ffcb bl 80022a2 <LL_ADC_IsDisableOngoing>
800330c: 4603 mov r3, r0
800330e: 2b00 cmp r3, #0
8003310: d104 bne.n 800331c <ADC_ConversionStop+0xfc>
{
/* Stop ADC group injected conversion */
LL_ADC_INJ_StopConversion(hadc->Instance);
8003312: 687b ldr r3, [r7, #4]
8003314: 681b ldr r3, [r3, #0]
8003316: 4618 mov r0, r3
8003318: f7ff f811 bl 800233e <LL_ADC_INJ_StopConversion>
}
}
}
/* Selection of start and stop bits with respect to the regular or injected group */
switch (conversion_group_reassigned)
800331c: 69bb ldr r3, [r7, #24]
800331e: 2b02 cmp r3, #2
8003320: d005 beq.n 800332e <ADC_ConversionStop+0x10e>
8003322: 69bb ldr r3, [r7, #24]
8003324: 2b03 cmp r3, #3
8003326: d105 bne.n 8003334 <ADC_ConversionStop+0x114>
{
case ADC_REGULAR_INJECTED_GROUP:
tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
8003328: 230c movs r3, #12
800332a: 617b str r3, [r7, #20]
break;
800332c: e005 b.n 800333a <ADC_ConversionStop+0x11a>
case ADC_INJECTED_GROUP:
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
800332e: 2308 movs r3, #8
8003330: 617b str r3, [r7, #20]
break;
8003332: e002 b.n 800333a <ADC_ConversionStop+0x11a>
/* Case ADC_REGULAR_GROUP only*/
default:
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
8003334: 2304 movs r3, #4
8003336: 617b str r3, [r7, #20]
break;
8003338: bf00 nop
}
/* Wait for conversion effectively stopped */
tickstart = HAL_GetTick();
800333a: f7fe fda1 bl 8001e80 <HAL_GetTick>
800333e: 60b8 str r0, [r7, #8]
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
8003340: e01b b.n 800337a <ADC_ConversionStop+0x15a>
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
8003342: f7fe fd9d bl 8001e80 <HAL_GetTick>
8003346: 4602 mov r2, r0
8003348: 68bb ldr r3, [r7, #8]
800334a: 1ad3 subs r3, r2, r3
800334c: 2b05 cmp r3, #5
800334e: d914 bls.n 800337a <ADC_ConversionStop+0x15a>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
8003350: 687b ldr r3, [r7, #4]
8003352: 681b ldr r3, [r3, #0]
8003354: 689a ldr r2, [r3, #8]
8003356: 697b ldr r3, [r7, #20]
8003358: 4013 ands r3, r2
800335a: 2b00 cmp r3, #0
800335c: d00d beq.n 800337a <ADC_ConversionStop+0x15a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800335e: 687b ldr r3, [r7, #4]
8003360: 6ddb ldr r3, [r3, #92] @ 0x5c
8003362: f043 0210 orr.w r2, r3, #16
8003366: 687b ldr r3, [r7, #4]
8003368: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800336a: 687b ldr r3, [r7, #4]
800336c: 6e1b ldr r3, [r3, #96] @ 0x60
800336e: f043 0201 orr.w r2, r3, #1
8003372: 687b ldr r3, [r7, #4]
8003374: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8003376: 2301 movs r3, #1
8003378: e007 b.n 800338a <ADC_ConversionStop+0x16a>
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
800337a: 687b ldr r3, [r7, #4]
800337c: 681b ldr r3, [r3, #0]
800337e: 689a ldr r2, [r3, #8]
8003380: 697b ldr r3, [r7, #20]
8003382: 4013 ands r3, r2
8003384: 2b00 cmp r3, #0
8003386: d1dc bne.n 8003342 <ADC_ConversionStop+0x122>
}
}
/* Return HAL status */
return HAL_OK;
8003388: 2300 movs r3, #0
}
800338a: 4618 mov r0, r3
800338c: 3720 adds r7, #32
800338e: 46bd mov sp, r7
8003390: bd80 pop {r7, pc}
8003392: bf00 nop
8003394: a33fffff .word 0xa33fffff
08003398 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
8003398: b580 push {r7, lr}
800339a: b084 sub sp, #16
800339c: af00 add r7, sp, #0
800339e: 6078 str r0, [r7, #4]
uint32_t tickstart;
__IO uint32_t wait_loop_index = 0UL;
80033a0: 2300 movs r3, #0
80033a2: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80033a4: 687b ldr r3, [r7, #4]
80033a6: 681b ldr r3, [r3, #0]
80033a8: 4618 mov r0, r3
80033aa: f7fe ff67 bl 800227c <LL_ADC_IsEnabled>
80033ae: 4603 mov r3, r0
80033b0: 2b00 cmp r3, #0
80033b2: d169 bne.n 8003488 <ADC_Enable+0xf0>
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
80033b4: 687b ldr r3, [r7, #4]
80033b6: 681b ldr r3, [r3, #0]
80033b8: 689a ldr r2, [r3, #8]
80033ba: 4b36 ldr r3, [pc, #216] @ (8003494 <ADC_Enable+0xfc>)
80033bc: 4013 ands r3, r2
80033be: 2b00 cmp r3, #0
80033c0: d00d beq.n 80033de <ADC_Enable+0x46>
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80033c2: 687b ldr r3, [r7, #4]
80033c4: 6ddb ldr r3, [r3, #92] @ 0x5c
80033c6: f043 0210 orr.w r2, r3, #16
80033ca: 687b ldr r3, [r7, #4]
80033cc: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80033ce: 687b ldr r3, [r7, #4]
80033d0: 6e1b ldr r3, [r3, #96] @ 0x60
80033d2: f043 0201 orr.w r2, r3, #1
80033d6: 687b ldr r3, [r7, #4]
80033d8: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
80033da: 2301 movs r3, #1
80033dc: e055 b.n 800348a <ADC_Enable+0xf2>
}
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
80033de: 687b ldr r3, [r7, #4]
80033e0: 681b ldr r3, [r3, #0]
80033e2: 4618 mov r0, r3
80033e4: f7fe ff22 bl 800222c <LL_ADC_Enable>
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
80033e8: 482b ldr r0, [pc, #172] @ (8003498 <ADC_Enable+0x100>)
80033ea: f7fe fd7b bl 8001ee4 <LL_ADC_GetCommonPathInternalCh>
80033ee: 4603 mov r3, r0
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
80033f0: f403 0300 and.w r3, r3, #8388608 @ 0x800000
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
80033f4: 2b00 cmp r3, #0
80033f6: d013 beq.n 8003420 <ADC_Enable+0x88>
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
80033f8: 4b28 ldr r3, [pc, #160] @ (800349c <ADC_Enable+0x104>)
80033fa: 681b ldr r3, [r3, #0]
80033fc: 099b lsrs r3, r3, #6
80033fe: 4a28 ldr r2, [pc, #160] @ (80034a0 <ADC_Enable+0x108>)
8003400: fba2 2303 umull r2, r3, r2, r3
8003404: 099b lsrs r3, r3, #6
8003406: 1c5a adds r2, r3, #1
8003408: 4613 mov r3, r2
800340a: 005b lsls r3, r3, #1
800340c: 4413 add r3, r2
800340e: 009b lsls r3, r3, #2
8003410: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8003412: e002 b.n 800341a <ADC_Enable+0x82>
{
wait_loop_index--;
8003414: 68bb ldr r3, [r7, #8]
8003416: 3b01 subs r3, #1
8003418: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
800341a: 68bb ldr r3, [r7, #8]
800341c: 2b00 cmp r3, #0
800341e: d1f9 bne.n 8003414 <ADC_Enable+0x7c>
}
}
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
8003420: f7fe fd2e bl 8001e80 <HAL_GetTick>
8003424: 60f8 str r0, [r7, #12]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8003426: e028 b.n 800347a <ADC_Enable+0xe2>
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8003428: 687b ldr r3, [r7, #4]
800342a: 681b ldr r3, [r3, #0]
800342c: 4618 mov r0, r3
800342e: f7fe ff25 bl 800227c <LL_ADC_IsEnabled>
8003432: 4603 mov r3, r0
8003434: 2b00 cmp r3, #0
8003436: d104 bne.n 8003442 <ADC_Enable+0xaa>
{
LL_ADC_Enable(hadc->Instance);
8003438: 687b ldr r3, [r7, #4]
800343a: 681b ldr r3, [r3, #0]
800343c: 4618 mov r0, r3
800343e: f7fe fef5 bl 800222c <LL_ADC_Enable>
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
8003442: f7fe fd1d bl 8001e80 <HAL_GetTick>
8003446: 4602 mov r2, r0
8003448: 68fb ldr r3, [r7, #12]
800344a: 1ad3 subs r3, r2, r3
800344c: 2b02 cmp r3, #2
800344e: d914 bls.n 800347a <ADC_Enable+0xe2>
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8003450: 687b ldr r3, [r7, #4]
8003452: 681b ldr r3, [r3, #0]
8003454: 681b ldr r3, [r3, #0]
8003456: f003 0301 and.w r3, r3, #1
800345a: 2b01 cmp r3, #1
800345c: d00d beq.n 800347a <ADC_Enable+0xe2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800345e: 687b ldr r3, [r7, #4]
8003460: 6ddb ldr r3, [r3, #92] @ 0x5c
8003462: f043 0210 orr.w r2, r3, #16
8003466: 687b ldr r3, [r7, #4]
8003468: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800346a: 687b ldr r3, [r7, #4]
800346c: 6e1b ldr r3, [r3, #96] @ 0x60
800346e: f043 0201 orr.w r2, r3, #1
8003472: 687b ldr r3, [r7, #4]
8003474: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8003476: 2301 movs r3, #1
8003478: e007 b.n 800348a <ADC_Enable+0xf2>
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
800347a: 687b ldr r3, [r7, #4]
800347c: 681b ldr r3, [r3, #0]
800347e: 681b ldr r3, [r3, #0]
8003480: f003 0301 and.w r3, r3, #1
8003484: 2b01 cmp r3, #1
8003486: d1cf bne.n 8003428 <ADC_Enable+0x90>
}
}
}
/* Return HAL status */
return HAL_OK;
8003488: 2300 movs r3, #0
}
800348a: 4618 mov r0, r3
800348c: 3710 adds r7, #16
800348e: 46bd mov sp, r7
8003490: bd80 pop {r7, pc}
8003492: bf00 nop
8003494: 8000003f .word 0x8000003f
8003498: 50000300 .word 0x50000300
800349c: 2000001c .word 0x2000001c
80034a0: 053e2d63 .word 0x053e2d63
080034a4 <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
80034a4: b580 push {r7, lr}
80034a6: b084 sub sp, #16
80034a8: af00 add r7, sp, #0
80034aa: 6078 str r0, [r7, #4]
uint32_t tickstart;
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
80034ac: 687b ldr r3, [r7, #4]
80034ae: 681b ldr r3, [r3, #0]
80034b0: 4618 mov r0, r3
80034b2: f7fe fef6 bl 80022a2 <LL_ADC_IsDisableOngoing>
80034b6: 60f8 str r0, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
80034b8: 687b ldr r3, [r7, #4]
80034ba: 681b ldr r3, [r3, #0]
80034bc: 4618 mov r0, r3
80034be: f7fe fedd bl 800227c <LL_ADC_IsEnabled>
80034c2: 4603 mov r3, r0
80034c4: 2b00 cmp r3, #0
80034c6: d047 beq.n 8003558 <ADC_Disable+0xb4>
&& (tmp_adc_is_disable_on_going == 0UL)
80034c8: 68fb ldr r3, [r7, #12]
80034ca: 2b00 cmp r3, #0
80034cc: d144 bne.n 8003558 <ADC_Disable+0xb4>
)
{
/* Check if conditions to disable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
80034ce: 687b ldr r3, [r7, #4]
80034d0: 681b ldr r3, [r3, #0]
80034d2: 689b ldr r3, [r3, #8]
80034d4: f003 030d and.w r3, r3, #13
80034d8: 2b01 cmp r3, #1
80034da: d10c bne.n 80034f6 <ADC_Disable+0x52>
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
80034dc: 687b ldr r3, [r7, #4]
80034de: 681b ldr r3, [r3, #0]
80034e0: 4618 mov r0, r3
80034e2: f7fe feb7 bl 8002254 <LL_ADC_Disable>
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
80034e6: 687b ldr r3, [r7, #4]
80034e8: 681b ldr r3, [r3, #0]
80034ea: 2203 movs r2, #3
80034ec: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
80034ee: f7fe fcc7 bl 8001e80 <HAL_GetTick>
80034f2: 60b8 str r0, [r7, #8]
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
80034f4: e029 b.n 800354a <ADC_Disable+0xa6>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80034f6: 687b ldr r3, [r7, #4]
80034f8: 6ddb ldr r3, [r3, #92] @ 0x5c
80034fa: f043 0210 orr.w r2, r3, #16
80034fe: 687b ldr r3, [r7, #4]
8003500: 65da str r2, [r3, #92] @ 0x5c
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003502: 687b ldr r3, [r7, #4]
8003504: 6e1b ldr r3, [r3, #96] @ 0x60
8003506: f043 0201 orr.w r2, r3, #1
800350a: 687b ldr r3, [r7, #4]
800350c: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
800350e: 2301 movs r3, #1
8003510: e023 b.n 800355a <ADC_Disable+0xb6>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8003512: f7fe fcb5 bl 8001e80 <HAL_GetTick>
8003516: 4602 mov r2, r0
8003518: 68bb ldr r3, [r7, #8]
800351a: 1ad3 subs r3, r2, r3
800351c: 2b02 cmp r3, #2
800351e: d914 bls.n 800354a <ADC_Disable+0xa6>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8003520: 687b ldr r3, [r7, #4]
8003522: 681b ldr r3, [r3, #0]
8003524: 689b ldr r3, [r3, #8]
8003526: f003 0301 and.w r3, r3, #1
800352a: 2b00 cmp r3, #0
800352c: d00d beq.n 800354a <ADC_Disable+0xa6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800352e: 687b ldr r3, [r7, #4]
8003530: 6ddb ldr r3, [r3, #92] @ 0x5c
8003532: f043 0210 orr.w r2, r3, #16
8003536: 687b ldr r3, [r7, #4]
8003538: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800353a: 687b ldr r3, [r7, #4]
800353c: 6e1b ldr r3, [r3, #96] @ 0x60
800353e: f043 0201 orr.w r2, r3, #1
8003542: 687b ldr r3, [r7, #4]
8003544: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8003546: 2301 movs r3, #1
8003548: e007 b.n 800355a <ADC_Disable+0xb6>
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
800354a: 687b ldr r3, [r7, #4]
800354c: 681b ldr r3, [r3, #0]
800354e: 689b ldr r3, [r3, #8]
8003550: f003 0301 and.w r3, r3, #1
8003554: 2b00 cmp r3, #0
8003556: d1dc bne.n 8003512 <ADC_Disable+0x6e>
}
}
}
/* Return HAL status */
return HAL_OK;
8003558: 2300 movs r3, #0
}
800355a: 4618 mov r0, r3
800355c: 3710 adds r7, #16
800355e: 46bd mov sp, r7
8003560: bd80 pop {r7, pc}
08003562 <LL_ADC_IsEnabled>:
{
8003562: b480 push {r7}
8003564: b083 sub sp, #12
8003566: af00 add r7, sp, #0
8003568: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
800356a: 687b ldr r3, [r7, #4]
800356c: 689b ldr r3, [r3, #8]
800356e: f003 0301 and.w r3, r3, #1
8003572: 2b01 cmp r3, #1
8003574: d101 bne.n 800357a <LL_ADC_IsEnabled+0x18>
8003576: 2301 movs r3, #1
8003578: e000 b.n 800357c <LL_ADC_IsEnabled+0x1a>
800357a: 2300 movs r3, #0
}
800357c: 4618 mov r0, r3
800357e: 370c adds r7, #12
8003580: 46bd mov sp, r7
8003582: f85d 7b04 ldr.w r7, [sp], #4
8003586: 4770 bx lr
08003588 <LL_ADC_StartCalibration>:
{
8003588: b480 push {r7}
800358a: b083 sub sp, #12
800358c: af00 add r7, sp, #0
800358e: 6078 str r0, [r7, #4]
8003590: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->CR,
8003592: 687b ldr r3, [r7, #4]
8003594: 689b ldr r3, [r3, #8]
8003596: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000
800359a: f023 033f bic.w r3, r3, #63 @ 0x3f
800359e: 683a ldr r2, [r7, #0]
80035a0: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
80035a4: 4313 orrs r3, r2
80035a6: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
80035aa: 687b ldr r3, [r7, #4]
80035ac: 609a str r2, [r3, #8]
}
80035ae: bf00 nop
80035b0: 370c adds r7, #12
80035b2: 46bd mov sp, r7
80035b4: f85d 7b04 ldr.w r7, [sp], #4
80035b8: 4770 bx lr
080035ba <LL_ADC_IsCalibrationOnGoing>:
{
80035ba: b480 push {r7}
80035bc: b083 sub sp, #12
80035be: af00 add r7, sp, #0
80035c0: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
80035c2: 687b ldr r3, [r7, #4]
80035c4: 689b ldr r3, [r3, #8]
80035c6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80035ca: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80035ce: d101 bne.n 80035d4 <LL_ADC_IsCalibrationOnGoing+0x1a>
80035d0: 2301 movs r3, #1
80035d2: e000 b.n 80035d6 <LL_ADC_IsCalibrationOnGoing+0x1c>
80035d4: 2300 movs r3, #0
}
80035d6: 4618 mov r0, r3
80035d8: 370c adds r7, #12
80035da: 46bd mov sp, r7
80035dc: f85d 7b04 ldr.w r7, [sp], #4
80035e0: 4770 bx lr
080035e2 <LL_ADC_REG_IsConversionOngoing>:
{
80035e2: b480 push {r7}
80035e4: b083 sub sp, #12
80035e6: af00 add r7, sp, #0
80035e8: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
80035ea: 687b ldr r3, [r7, #4]
80035ec: 689b ldr r3, [r3, #8]
80035ee: f003 0304 and.w r3, r3, #4
80035f2: 2b04 cmp r3, #4
80035f4: d101 bne.n 80035fa <LL_ADC_REG_IsConversionOngoing+0x18>
80035f6: 2301 movs r3, #1
80035f8: e000 b.n 80035fc <LL_ADC_REG_IsConversionOngoing+0x1a>
80035fa: 2300 movs r3, #0
}
80035fc: 4618 mov r0, r3
80035fe: 370c adds r7, #12
8003600: 46bd mov sp, r7
8003602: f85d 7b04 ldr.w r7, [sp], #4
8003606: 4770 bx lr
08003608 <HAL_ADCEx_Calibration_Start>:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
8003608: b580 push {r7, lr}
800360a: b084 sub sp, #16
800360c: af00 add r7, sp, #0
800360e: 6078 str r0, [r7, #4]
8003610: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
8003612: 2300 movs r3, #0
8003614: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Process locked */
__HAL_LOCK(hadc);
8003616: 687b ldr r3, [r7, #4]
8003618: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
800361c: 2b01 cmp r3, #1
800361e: d101 bne.n 8003624 <HAL_ADCEx_Calibration_Start+0x1c>
8003620: 2302 movs r3, #2
8003622: e04d b.n 80036c0 <HAL_ADCEx_Calibration_Start+0xb8>
8003624: 687b ldr r3, [r7, #4]
8003626: 2201 movs r2, #1
8003628: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Calibration prerequisite: ADC must be disabled. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
800362c: 6878 ldr r0, [r7, #4]
800362e: f7ff ff39 bl 80034a4 <ADC_Disable>
8003632: 4603 mov r3, r0
8003634: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
8003636: 7bfb ldrb r3, [r7, #15]
8003638: 2b00 cmp r3, #0
800363a: d136 bne.n 80036aa <HAL_ADCEx_Calibration_Start+0xa2>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800363c: 687b ldr r3, [r7, #4]
800363e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003640: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8003644: f023 0302 bic.w r3, r3, #2
8003648: f043 0202 orr.w r2, r3, #2
800364c: 687b ldr r3, [r7, #4]
800364e: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration in mode single-ended or differential */
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
8003650: 687b ldr r3, [r7, #4]
8003652: 681b ldr r3, [r3, #0]
8003654: 6839 ldr r1, [r7, #0]
8003656: 4618 mov r0, r3
8003658: f7ff ff96 bl 8003588 <LL_ADC_StartCalibration>
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
800365c: e014 b.n 8003688 <HAL_ADCEx_Calibration_Start+0x80>
{
wait_loop_index++;
800365e: 68bb ldr r3, [r7, #8]
8003660: 3301 adds r3, #1
8003662: 60bb str r3, [r7, #8]
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
8003664: 68bb ldr r3, [r7, #8]
8003666: 4a18 ldr r2, [pc, #96] @ (80036c8 <HAL_ADCEx_Calibration_Start+0xc0>)
8003668: 4293 cmp r3, r2
800366a: d90d bls.n 8003688 <HAL_ADCEx_Calibration_Start+0x80>
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
800366c: 687b ldr r3, [r7, #4]
800366e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003670: f023 0312 bic.w r3, r3, #18
8003674: f043 0210 orr.w r2, r3, #16
8003678: 687b ldr r3, [r7, #4]
800367a: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Process unlocked */
__HAL_UNLOCK(hadc);
800367c: 687b ldr r3, [r7, #4]
800367e: 2200 movs r2, #0
8003680: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
8003684: 2301 movs r3, #1
8003686: e01b b.n 80036c0 <HAL_ADCEx_Calibration_Start+0xb8>
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8003688: 687b ldr r3, [r7, #4]
800368a: 681b ldr r3, [r3, #0]
800368c: 4618 mov r0, r3
800368e: f7ff ff94 bl 80035ba <LL_ADC_IsCalibrationOnGoing>
8003692: 4603 mov r3, r0
8003694: 2b00 cmp r3, #0
8003696: d1e2 bne.n 800365e <HAL_ADCEx_Calibration_Start+0x56>
}
}
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8003698: 687b ldr r3, [r7, #4]
800369a: 6ddb ldr r3, [r3, #92] @ 0x5c
800369c: f023 0303 bic.w r3, r3, #3
80036a0: f043 0201 orr.w r2, r3, #1
80036a4: 687b ldr r3, [r7, #4]
80036a6: 65da str r2, [r3, #92] @ 0x5c
80036a8: e005 b.n 80036b6 <HAL_ADCEx_Calibration_Start+0xae>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80036aa: 687b ldr r3, [r7, #4]
80036ac: 6ddb ldr r3, [r3, #92] @ 0x5c
80036ae: f043 0210 orr.w r2, r3, #16
80036b2: 687b ldr r3, [r7, #4]
80036b4: 65da str r2, [r3, #92] @ 0x5c
/* Note: No need to update variable "tmp_hal_status" here: already set */
/* to state "HAL_ERROR" by function disabling the ADC. */
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80036b6: 687b ldr r3, [r7, #4]
80036b8: 2200 movs r2, #0
80036ba: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
80036be: 7bfb ldrb r3, [r7, #15]
}
80036c0: 4618 mov r0, r3
80036c2: 3710 adds r7, #16
80036c4: 46bd mov sp, r7
80036c6: bd80 pop {r7, pc}
80036c8: 0004de01 .word 0x0004de01
080036cc <HAL_ADCEx_MultiModeConfigChannel>:
* @param hadc Master ADC handle
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
{
80036cc: b590 push {r4, r7, lr}
80036ce: b0a1 sub sp, #132 @ 0x84
80036d0: af00 add r7, sp, #0
80036d2: 6078 str r0, [r7, #4]
80036d4: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80036d6: 2300 movs r3, #0
80036d8: f887 307f strb.w r3, [r7, #127] @ 0x7f
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
80036dc: 687b ldr r3, [r7, #4]
80036de: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
80036e2: 2b01 cmp r3, #1
80036e4: d101 bne.n 80036ea <HAL_ADCEx_MultiModeConfigChannel+0x1e>
80036e6: 2302 movs r3, #2
80036e8: e08b b.n 8003802 <HAL_ADCEx_MultiModeConfigChannel+0x136>
80036ea: 687b ldr r3, [r7, #4]
80036ec: 2201 movs r2, #1
80036ee: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
80036f2: 2300 movs r3, #0
80036f4: 667b str r3, [r7, #100] @ 0x64
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
80036f6: 2300 movs r3, #0
80036f8: 66bb str r3, [r7, #104] @ 0x68
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
80036fa: 687b ldr r3, [r7, #4]
80036fc: 681b ldr r3, [r3, #0]
80036fe: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8003702: d102 bne.n 800370a <HAL_ADCEx_MultiModeConfigChannel+0x3e>
8003704: 4b41 ldr r3, [pc, #260] @ (800380c <HAL_ADCEx_MultiModeConfigChannel+0x140>)
8003706: 60bb str r3, [r7, #8]
8003708: e001 b.n 800370e <HAL_ADCEx_MultiModeConfigChannel+0x42>
800370a: 2300 movs r3, #0
800370c: 60bb str r3, [r7, #8]
if (tmp_hadc_slave.Instance == NULL)
800370e: 68bb ldr r3, [r7, #8]
8003710: 2b00 cmp r3, #0
8003712: d10b bne.n 800372c <HAL_ADCEx_MultiModeConfigChannel+0x60>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003714: 687b ldr r3, [r7, #4]
8003716: 6ddb ldr r3, [r3, #92] @ 0x5c
8003718: f043 0220 orr.w r2, r3, #32
800371c: 687b ldr r3, [r7, #4]
800371e: 65da str r2, [r3, #92] @ 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003720: 687b ldr r3, [r7, #4]
8003722: 2200 movs r2, #0
8003724: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
8003728: 2301 movs r3, #1
800372a: e06a b.n 8003802 <HAL_ADCEx_MultiModeConfigChannel+0x136>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
800372c: 68bb ldr r3, [r7, #8]
800372e: 4618 mov r0, r3
8003730: f7ff ff57 bl 80035e2 <LL_ADC_REG_IsConversionOngoing>
8003734: 67b8 str r0, [r7, #120] @ 0x78
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8003736: 687b ldr r3, [r7, #4]
8003738: 681b ldr r3, [r3, #0]
800373a: 4618 mov r0, r3
800373c: f7ff ff51 bl 80035e2 <LL_ADC_REG_IsConversionOngoing>
8003740: 4603 mov r3, r0
8003742: 2b00 cmp r3, #0
8003744: d14c bne.n 80037e0 <HAL_ADCEx_MultiModeConfigChannel+0x114>
&& (tmp_hadc_slave_conversion_on_going == 0UL))
8003746: 6fbb ldr r3, [r7, #120] @ 0x78
8003748: 2b00 cmp r3, #0
800374a: d149 bne.n 80037e0 <HAL_ADCEx_MultiModeConfigChannel+0x114>
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
800374c: 4b30 ldr r3, [pc, #192] @ (8003810 <HAL_ADCEx_MultiModeConfigChannel+0x144>)
800374e: 677b str r3, [r7, #116] @ 0x74
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003750: 683b ldr r3, [r7, #0]
8003752: 681b ldr r3, [r3, #0]
8003754: 2b00 cmp r3, #0
8003756: d028 beq.n 80037aa <HAL_ADCEx_MultiModeConfigChannel+0xde>
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
8003758: 6f7b ldr r3, [r7, #116] @ 0x74
800375a: 689b ldr r3, [r3, #8]
800375c: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8003760: 683b ldr r3, [r7, #0]
8003762: 6859 ldr r1, [r3, #4]
8003764: 687b ldr r3, [r7, #4]
8003766: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
800376a: 035b lsls r3, r3, #13
800376c: 430b orrs r3, r1
800376e: 431a orrs r2, r3
8003770: 6f7b ldr r3, [r7, #116] @ 0x74
8003772: 609a str r2, [r3, #8]
/* from 1 to 10 clock cycles for 10 bits, */
/* from 1 to 8 clock cycles for 8 bits */
/* from 1 to 6 clock cycles for 6 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8003774: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
8003778: f7ff fef3 bl 8003562 <LL_ADC_IsEnabled>
800377c: 4604 mov r4, r0
800377e: 4823 ldr r0, [pc, #140] @ (800380c <HAL_ADCEx_MultiModeConfigChannel+0x140>)
8003780: f7ff feef bl 8003562 <LL_ADC_IsEnabled>
8003784: 4603 mov r3, r0
8003786: 4323 orrs r3, r4
8003788: 2b00 cmp r3, #0
800378a: d133 bne.n 80037f4 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
MODIFY_REG(tmpADC_Common->CCR,
800378c: 6f7b ldr r3, [r7, #116] @ 0x74
800378e: 689b ldr r3, [r3, #8]
8003790: f423 6371 bic.w r3, r3, #3856 @ 0xf10
8003794: f023 030f bic.w r3, r3, #15
8003798: 683a ldr r2, [r7, #0]
800379a: 6811 ldr r1, [r2, #0]
800379c: 683a ldr r2, [r7, #0]
800379e: 6892 ldr r2, [r2, #8]
80037a0: 430a orrs r2, r1
80037a2: 431a orrs r2, r3
80037a4: 6f7b ldr r3, [r7, #116] @ 0x74
80037a6: 609a str r2, [r3, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
80037a8: e024 b.n 80037f4 <HAL_ADCEx_MultiModeConfigChannel+0x128>
);
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
80037aa: 6f7b ldr r3, [r7, #116] @ 0x74
80037ac: 689b ldr r3, [r3, #8]
80037ae: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80037b2: 6f7b ldr r3, [r7, #116] @ 0x74
80037b4: 609a str r2, [r3, #8]
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80037b6: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
80037ba: f7ff fed2 bl 8003562 <LL_ADC_IsEnabled>
80037be: 4604 mov r4, r0
80037c0: 4812 ldr r0, [pc, #72] @ (800380c <HAL_ADCEx_MultiModeConfigChannel+0x140>)
80037c2: f7ff fece bl 8003562 <LL_ADC_IsEnabled>
80037c6: 4603 mov r3, r0
80037c8: 4323 orrs r3, r4
80037ca: 2b00 cmp r3, #0
80037cc: d112 bne.n 80037f4 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
80037ce: 6f7b ldr r3, [r7, #116] @ 0x74
80037d0: 689b ldr r3, [r3, #8]
80037d2: f423 6371 bic.w r3, r3, #3856 @ 0xf10
80037d6: f023 030f bic.w r3, r3, #15
80037da: 6f7a ldr r2, [r7, #116] @ 0x74
80037dc: 6093 str r3, [r2, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
80037de: e009 b.n 80037f4 <HAL_ADCEx_MultiModeConfigChannel+0x128>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80037e0: 687b ldr r3, [r7, #4]
80037e2: 6ddb ldr r3, [r3, #92] @ 0x5c
80037e4: f043 0220 orr.w r2, r3, #32
80037e8: 687b ldr r3, [r7, #4]
80037ea: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
80037ec: 2301 movs r3, #1
80037ee: f887 307f strb.w r3, [r7, #127] @ 0x7f
80037f2: e000 b.n 80037f6 <HAL_ADCEx_MultiModeConfigChannel+0x12a>
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
80037f4: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80037f6: 687b ldr r3, [r7, #4]
80037f8: 2200 movs r2, #0
80037fa: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
80037fe: f897 307f ldrb.w r3, [r7, #127] @ 0x7f
}
8003802: 4618 mov r0, r3
8003804: 3784 adds r7, #132 @ 0x84
8003806: 46bd mov sp, r7
8003808: bd90 pop {r4, r7, pc}
800380a: bf00 nop
800380c: 50000100 .word 0x50000100
8003810: 50000300 .word 0x50000300
08003814 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003814: b480 push {r7}
8003816: b085 sub sp, #20
8003818: af00 add r7, sp, #0
800381a: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800381c: 687b ldr r3, [r7, #4]
800381e: f003 0307 and.w r3, r3, #7
8003822: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8003824: 4b0c ldr r3, [pc, #48] @ (8003858 <__NVIC_SetPriorityGrouping+0x44>)
8003826: 68db ldr r3, [r3, #12]
8003828: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800382a: 68ba ldr r2, [r7, #8]
800382c: f64f 03ff movw r3, #63743 @ 0xf8ff
8003830: 4013 ands r3, r2
8003832: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8003834: 68fb ldr r3, [r7, #12]
8003836: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8003838: 68bb ldr r3, [r7, #8]
800383a: 4313 orrs r3, r2
reg_value = (reg_value |
800383c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003840: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003844: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8003846: 4a04 ldr r2, [pc, #16] @ (8003858 <__NVIC_SetPriorityGrouping+0x44>)
8003848: 68bb ldr r3, [r7, #8]
800384a: 60d3 str r3, [r2, #12]
}
800384c: bf00 nop
800384e: 3714 adds r7, #20
8003850: 46bd mov sp, r7
8003852: f85d 7b04 ldr.w r7, [sp], #4
8003856: 4770 bx lr
8003858: e000ed00 .word 0xe000ed00
0800385c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800385c: b480 push {r7}
800385e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8003860: 4b04 ldr r3, [pc, #16] @ (8003874 <__NVIC_GetPriorityGrouping+0x18>)
8003862: 68db ldr r3, [r3, #12]
8003864: 0a1b lsrs r3, r3, #8
8003866: f003 0307 and.w r3, r3, #7
}
800386a: 4618 mov r0, r3
800386c: 46bd mov sp, r7
800386e: f85d 7b04 ldr.w r7, [sp], #4
8003872: 4770 bx lr
8003874: e000ed00 .word 0xe000ed00
08003878 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003878: b480 push {r7}
800387a: b083 sub sp, #12
800387c: af00 add r7, sp, #0
800387e: 4603 mov r3, r0
8003880: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003882: f997 3007 ldrsb.w r3, [r7, #7]
8003886: 2b00 cmp r3, #0
8003888: db0b blt.n 80038a2 <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800388a: 79fb ldrb r3, [r7, #7]
800388c: f003 021f and.w r2, r3, #31
8003890: 4907 ldr r1, [pc, #28] @ (80038b0 <__NVIC_EnableIRQ+0x38>)
8003892: f997 3007 ldrsb.w r3, [r7, #7]
8003896: 095b lsrs r3, r3, #5
8003898: 2001 movs r0, #1
800389a: fa00 f202 lsl.w r2, r0, r2
800389e: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
80038a2: bf00 nop
80038a4: 370c adds r7, #12
80038a6: 46bd mov sp, r7
80038a8: f85d 7b04 ldr.w r7, [sp], #4
80038ac: 4770 bx lr
80038ae: bf00 nop
80038b0: e000e100 .word 0xe000e100
080038b4 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80038b4: b480 push {r7}
80038b6: b083 sub sp, #12
80038b8: af00 add r7, sp, #0
80038ba: 4603 mov r3, r0
80038bc: 6039 str r1, [r7, #0]
80038be: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80038c0: f997 3007 ldrsb.w r3, [r7, #7]
80038c4: 2b00 cmp r3, #0
80038c6: db0a blt.n 80038de <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80038c8: 683b ldr r3, [r7, #0]
80038ca: b2da uxtb r2, r3
80038cc: 490c ldr r1, [pc, #48] @ (8003900 <__NVIC_SetPriority+0x4c>)
80038ce: f997 3007 ldrsb.w r3, [r7, #7]
80038d2: 0112 lsls r2, r2, #4
80038d4: b2d2 uxtb r2, r2
80038d6: 440b add r3, r1
80038d8: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80038dc: e00a b.n 80038f4 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80038de: 683b ldr r3, [r7, #0]
80038e0: b2da uxtb r2, r3
80038e2: 4908 ldr r1, [pc, #32] @ (8003904 <__NVIC_SetPriority+0x50>)
80038e4: 79fb ldrb r3, [r7, #7]
80038e6: f003 030f and.w r3, r3, #15
80038ea: 3b04 subs r3, #4
80038ec: 0112 lsls r2, r2, #4
80038ee: b2d2 uxtb r2, r2
80038f0: 440b add r3, r1
80038f2: 761a strb r2, [r3, #24]
}
80038f4: bf00 nop
80038f6: 370c adds r7, #12
80038f8: 46bd mov sp, r7
80038fa: f85d 7b04 ldr.w r7, [sp], #4
80038fe: 4770 bx lr
8003900: e000e100 .word 0xe000e100
8003904: e000ed00 .word 0xe000ed00
08003908 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003908: b480 push {r7}
800390a: b089 sub sp, #36 @ 0x24
800390c: af00 add r7, sp, #0
800390e: 60f8 str r0, [r7, #12]
8003910: 60b9 str r1, [r7, #8]
8003912: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003914: 68fb ldr r3, [r7, #12]
8003916: f003 0307 and.w r3, r3, #7
800391a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
800391c: 69fb ldr r3, [r7, #28]
800391e: f1c3 0307 rsb r3, r3, #7
8003922: 2b04 cmp r3, #4
8003924: bf28 it cs
8003926: 2304 movcs r3, #4
8003928: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800392a: 69fb ldr r3, [r7, #28]
800392c: 3304 adds r3, #4
800392e: 2b06 cmp r3, #6
8003930: d902 bls.n 8003938 <NVIC_EncodePriority+0x30>
8003932: 69fb ldr r3, [r7, #28]
8003934: 3b03 subs r3, #3
8003936: e000 b.n 800393a <NVIC_EncodePriority+0x32>
8003938: 2300 movs r3, #0
800393a: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800393c: f04f 32ff mov.w r2, #4294967295
8003940: 69bb ldr r3, [r7, #24]
8003942: fa02 f303 lsl.w r3, r2, r3
8003946: 43da mvns r2, r3
8003948: 68bb ldr r3, [r7, #8]
800394a: 401a ands r2, r3
800394c: 697b ldr r3, [r7, #20]
800394e: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8003950: f04f 31ff mov.w r1, #4294967295
8003954: 697b ldr r3, [r7, #20]
8003956: fa01 f303 lsl.w r3, r1, r3
800395a: 43d9 mvns r1, r3
800395c: 687b ldr r3, [r7, #4]
800395e: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003960: 4313 orrs r3, r2
);
}
8003962: 4618 mov r0, r3
8003964: 3724 adds r7, #36 @ 0x24
8003966: 46bd mov sp, r7
8003968: f85d 7b04 ldr.w r7, [sp], #4
800396c: 4770 bx lr
...
08003970 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8003970: b580 push {r7, lr}
8003972: b082 sub sp, #8
8003974: af00 add r7, sp, #0
8003976: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003978: 687b ldr r3, [r7, #4]
800397a: 3b01 subs r3, #1
800397c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8003980: d301 bcc.n 8003986 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8003982: 2301 movs r3, #1
8003984: e00f b.n 80039a6 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8003986: 4a0a ldr r2, [pc, #40] @ (80039b0 <SysTick_Config+0x40>)
8003988: 687b ldr r3, [r7, #4]
800398a: 3b01 subs r3, #1
800398c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800398e: 210f movs r1, #15
8003990: f04f 30ff mov.w r0, #4294967295
8003994: f7ff ff8e bl 80038b4 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003998: 4b05 ldr r3, [pc, #20] @ (80039b0 <SysTick_Config+0x40>)
800399a: 2200 movs r2, #0
800399c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800399e: 4b04 ldr r3, [pc, #16] @ (80039b0 <SysTick_Config+0x40>)
80039a0: 2207 movs r2, #7
80039a2: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80039a4: 2300 movs r3, #0
}
80039a6: 4618 mov r0, r3
80039a8: 3708 adds r7, #8
80039aa: 46bd mov sp, r7
80039ac: bd80 pop {r7, pc}
80039ae: bf00 nop
80039b0: e000e010 .word 0xe000e010
080039b4 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80039b4: b580 push {r7, lr}
80039b6: b082 sub sp, #8
80039b8: af00 add r7, sp, #0
80039ba: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80039bc: 6878 ldr r0, [r7, #4]
80039be: f7ff ff29 bl 8003814 <__NVIC_SetPriorityGrouping>
}
80039c2: bf00 nop
80039c4: 3708 adds r7, #8
80039c6: 46bd mov sp, r7
80039c8: bd80 pop {r7, pc}
080039ca <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80039ca: b580 push {r7, lr}
80039cc: b086 sub sp, #24
80039ce: af00 add r7, sp, #0
80039d0: 4603 mov r3, r0
80039d2: 60b9 str r1, [r7, #8]
80039d4: 607a str r2, [r7, #4]
80039d6: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80039d8: f7ff ff40 bl 800385c <__NVIC_GetPriorityGrouping>
80039dc: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80039de: 687a ldr r2, [r7, #4]
80039e0: 68b9 ldr r1, [r7, #8]
80039e2: 6978 ldr r0, [r7, #20]
80039e4: f7ff ff90 bl 8003908 <NVIC_EncodePriority>
80039e8: 4602 mov r2, r0
80039ea: f997 300f ldrsb.w r3, [r7, #15]
80039ee: 4611 mov r1, r2
80039f0: 4618 mov r0, r3
80039f2: f7ff ff5f bl 80038b4 <__NVIC_SetPriority>
}
80039f6: bf00 nop
80039f8: 3718 adds r7, #24
80039fa: 46bd mov sp, r7
80039fc: bd80 pop {r7, pc}
080039fe <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80039fe: b580 push {r7, lr}
8003a00: b082 sub sp, #8
8003a02: af00 add r7, sp, #0
8003a04: 4603 mov r3, r0
8003a06: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8003a08: f997 3007 ldrsb.w r3, [r7, #7]
8003a0c: 4618 mov r0, r3
8003a0e: f7ff ff33 bl 8003878 <__NVIC_EnableIRQ>
}
8003a12: bf00 nop
8003a14: 3708 adds r7, #8
8003a16: 46bd mov sp, r7
8003a18: bd80 pop {r7, pc}
08003a1a <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8003a1a: b580 push {r7, lr}
8003a1c: b082 sub sp, #8
8003a1e: af00 add r7, sp, #0
8003a20: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8003a22: 6878 ldr r0, [r7, #4]
8003a24: f7ff ffa4 bl 8003970 <SysTick_Config>
8003a28: 4603 mov r3, r0
}
8003a2a: 4618 mov r0, r3
8003a2c: 3708 adds r7, #8
8003a2e: 46bd mov sp, r7
8003a30: bd80 pop {r7, pc}
08003a32 <HAL_DMA_Abort>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8003a32: b480 push {r7}
8003a34: b085 sub sp, #20
8003a36: af00 add r7, sp, #0
8003a38: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003a3a: 2300 movs r3, #0
8003a3c: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
8003a3e: 687b ldr r3, [r7, #4]
8003a40: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8003a44: b2db uxtb r3, r3
8003a46: 2b02 cmp r3, #2
8003a48: d005 beq.n 8003a56 <HAL_DMA_Abort+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003a4a: 687b ldr r3, [r7, #4]
8003a4c: 2204 movs r2, #4
8003a4e: 63da str r2, [r3, #60] @ 0x3c
status = HAL_ERROR;
8003a50: 2301 movs r3, #1
8003a52: 73fb strb r3, [r7, #15]
8003a54: e037 b.n 8003ac6 <HAL_DMA_Abort+0x94>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003a56: 687b ldr r3, [r7, #4]
8003a58: 681b ldr r3, [r3, #0]
8003a5a: 681a ldr r2, [r3, #0]
8003a5c: 687b ldr r3, [r7, #4]
8003a5e: 681b ldr r3, [r3, #0]
8003a60: f022 020e bic.w r2, r2, #14
8003a64: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003a66: 687b ldr r3, [r7, #4]
8003a68: 6c9b ldr r3, [r3, #72] @ 0x48
8003a6a: 681a ldr r2, [r3, #0]
8003a6c: 687b ldr r3, [r7, #4]
8003a6e: 6c9b ldr r3, [r3, #72] @ 0x48
8003a70: f422 7280 bic.w r2, r2, #256 @ 0x100
8003a74: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003a76: 687b ldr r3, [r7, #4]
8003a78: 681b ldr r3, [r3, #0]
8003a7a: 681a ldr r2, [r3, #0]
8003a7c: 687b ldr r3, [r7, #4]
8003a7e: 681b ldr r3, [r3, #0]
8003a80: f022 0201 bic.w r2, r2, #1
8003a84: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
8003a86: 687b ldr r3, [r7, #4]
8003a88: 6c5b ldr r3, [r3, #68] @ 0x44
8003a8a: f003 021f and.w r2, r3, #31
8003a8e: 687b ldr r3, [r7, #4]
8003a90: 6c1b ldr r3, [r3, #64] @ 0x40
8003a92: 2101 movs r1, #1
8003a94: fa01 f202 lsl.w r2, r1, r2
8003a98: 605a str r2, [r3, #4]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003a9a: 687b ldr r3, [r7, #4]
8003a9c: 6cdb ldr r3, [r3, #76] @ 0x4c
8003a9e: 687a ldr r2, [r7, #4]
8003aa0: 6d12 ldr r2, [r2, #80] @ 0x50
8003aa2: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003aa4: 687b ldr r3, [r7, #4]
8003aa6: 6d5b ldr r3, [r3, #84] @ 0x54
8003aa8: 2b00 cmp r3, #0
8003aaa: d00c beq.n 8003ac6 <HAL_DMA_Abort+0x94>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8003aac: 687b ldr r3, [r7, #4]
8003aae: 6d5b ldr r3, [r3, #84] @ 0x54
8003ab0: 681a ldr r2, [r3, #0]
8003ab2: 687b ldr r3, [r7, #4]
8003ab4: 6d5b ldr r3, [r3, #84] @ 0x54
8003ab6: f422 7280 bic.w r2, r2, #256 @ 0x100
8003aba: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003abc: 687b ldr r3, [r7, #4]
8003abe: 6d9b ldr r3, [r3, #88] @ 0x58
8003ac0: 687a ldr r2, [r7, #4]
8003ac2: 6dd2 ldr r2, [r2, #92] @ 0x5c
8003ac4: 605a str r2, [r3, #4]
}
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003ac6: 687b ldr r3, [r7, #4]
8003ac8: 2201 movs r2, #1
8003aca: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003ace: 687b ldr r3, [r7, #4]
8003ad0: 2200 movs r2, #0
8003ad2: f883 2024 strb.w r2, [r3, #36] @ 0x24
return status;
8003ad6: 7bfb ldrb r3, [r7, #15]
}
8003ad8: 4618 mov r0, r3
8003ada: 3714 adds r7, #20
8003adc: 46bd mov sp, r7
8003ade: f85d 7b04 ldr.w r7, [sp], #4
8003ae2: 4770 bx lr
08003ae4 <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8003ae4: b580 push {r7, lr}
8003ae6: b084 sub sp, #16
8003ae8: af00 add r7, sp, #0
8003aea: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003aec: 2300 movs r3, #0
8003aee: 73fb strb r3, [r7, #15]
if (HAL_DMA_STATE_BUSY != hdma->State)
8003af0: 687b ldr r3, [r7, #4]
8003af2: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8003af6: b2db uxtb r3, r3
8003af8: 2b02 cmp r3, #2
8003afa: d00d beq.n 8003b18 <HAL_DMA_Abort_IT+0x34>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003afc: 687b ldr r3, [r7, #4]
8003afe: 2204 movs r2, #4
8003b00: 63da str r2, [r3, #60] @ 0x3c
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003b02: 687b ldr r3, [r7, #4]
8003b04: 2201 movs r2, #1
8003b06: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003b0a: 687b ldr r3, [r7, #4]
8003b0c: 2200 movs r2, #0
8003b0e: f883 2024 strb.w r2, [r3, #36] @ 0x24
status = HAL_ERROR;
8003b12: 2301 movs r3, #1
8003b14: 73fb strb r3, [r7, #15]
8003b16: e047 b.n 8003ba8 <HAL_DMA_Abort_IT+0xc4>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003b18: 687b ldr r3, [r7, #4]
8003b1a: 681b ldr r3, [r3, #0]
8003b1c: 681a ldr r2, [r3, #0]
8003b1e: 687b ldr r3, [r7, #4]
8003b20: 681b ldr r3, [r3, #0]
8003b22: f022 020e bic.w r2, r2, #14
8003b26: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003b28: 687b ldr r3, [r7, #4]
8003b2a: 681b ldr r3, [r3, #0]
8003b2c: 681a ldr r2, [r3, #0]
8003b2e: 687b ldr r3, [r7, #4]
8003b30: 681b ldr r3, [r3, #0]
8003b32: f022 0201 bic.w r2, r2, #1
8003b36: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003b38: 687b ldr r3, [r7, #4]
8003b3a: 6c9b ldr r3, [r3, #72] @ 0x48
8003b3c: 681a ldr r2, [r3, #0]
8003b3e: 687b ldr r3, [r7, #4]
8003b40: 6c9b ldr r3, [r3, #72] @ 0x48
8003b42: f422 7280 bic.w r2, r2, #256 @ 0x100
8003b46: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
8003b48: 687b ldr r3, [r7, #4]
8003b4a: 6c5b ldr r3, [r3, #68] @ 0x44
8003b4c: f003 021f and.w r2, r3, #31
8003b50: 687b ldr r3, [r7, #4]
8003b52: 6c1b ldr r3, [r3, #64] @ 0x40
8003b54: 2101 movs r1, #1
8003b56: fa01 f202 lsl.w r2, r1, r2
8003b5a: 605a str r2, [r3, #4]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003b5c: 687b ldr r3, [r7, #4]
8003b5e: 6cdb ldr r3, [r3, #76] @ 0x4c
8003b60: 687a ldr r2, [r7, #4]
8003b62: 6d12 ldr r2, [r2, #80] @ 0x50
8003b64: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003b66: 687b ldr r3, [r7, #4]
8003b68: 6d5b ldr r3, [r3, #84] @ 0x54
8003b6a: 2b00 cmp r3, #0
8003b6c: d00c beq.n 8003b88 <HAL_DMA_Abort_IT+0xa4>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8003b6e: 687b ldr r3, [r7, #4]
8003b70: 6d5b ldr r3, [r3, #84] @ 0x54
8003b72: 681a ldr r2, [r3, #0]
8003b74: 687b ldr r3, [r7, #4]
8003b76: 6d5b ldr r3, [r3, #84] @ 0x54
8003b78: f422 7280 bic.w r2, r2, #256 @ 0x100
8003b7c: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003b7e: 687b ldr r3, [r7, #4]
8003b80: 6d9b ldr r3, [r3, #88] @ 0x58
8003b82: 687a ldr r2, [r7, #4]
8003b84: 6dd2 ldr r2, [r2, #92] @ 0x5c
8003b86: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003b88: 687b ldr r3, [r7, #4]
8003b8a: 2201 movs r2, #1
8003b8c: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003b90: 687b ldr r3, [r7, #4]
8003b92: 2200 movs r2, #0
8003b94: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
8003b98: 687b ldr r3, [r7, #4]
8003b9a: 6b9b ldr r3, [r3, #56] @ 0x38
8003b9c: 2b00 cmp r3, #0
8003b9e: d003 beq.n 8003ba8 <HAL_DMA_Abort_IT+0xc4>
{
hdma->XferAbortCallback(hdma);
8003ba0: 687b ldr r3, [r7, #4]
8003ba2: 6b9b ldr r3, [r3, #56] @ 0x38
8003ba4: 6878 ldr r0, [r7, #4]
8003ba6: 4798 blx r3
}
}
return status;
8003ba8: 7bfb ldrb r3, [r7, #15]
}
8003baa: 4618 mov r0, r3
8003bac: 3710 adds r7, #16
8003bae: 46bd mov sp, r7
8003bb0: bd80 pop {r7, pc}
...
08003bb4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8003bb4: b480 push {r7}
8003bb6: b087 sub sp, #28
8003bb8: af00 add r7, sp, #0
8003bba: 6078 str r0, [r7, #4]
8003bbc: 6039 str r1, [r7, #0]
uint32_t position = 0x00U;
8003bbe: 2300 movs r3, #0
8003bc0: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0U)
8003bc2: e15a b.n 8003e7a <HAL_GPIO_Init+0x2c6>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8003bc4: 683b ldr r3, [r7, #0]
8003bc6: 681a ldr r2, [r3, #0]
8003bc8: 2101 movs r1, #1
8003bca: 697b ldr r3, [r7, #20]
8003bcc: fa01 f303 lsl.w r3, r1, r3
8003bd0: 4013 ands r3, r2
8003bd2: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8003bd4: 68fb ldr r3, [r7, #12]
8003bd6: 2b00 cmp r3, #0
8003bd8: f000 814c beq.w 8003e74 <HAL_GPIO_Init+0x2c0>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8003bdc: 683b ldr r3, [r7, #0]
8003bde: 685b ldr r3, [r3, #4]
8003be0: f003 0303 and.w r3, r3, #3
8003be4: 2b01 cmp r3, #1
8003be6: d005 beq.n 8003bf4 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8003be8: 683b ldr r3, [r7, #0]
8003bea: 685b ldr r3, [r3, #4]
8003bec: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8003bf0: 2b02 cmp r3, #2
8003bf2: d130 bne.n 8003c56 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8003bf4: 687b ldr r3, [r7, #4]
8003bf6: 689b ldr r3, [r3, #8]
8003bf8: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8003bfa: 697b ldr r3, [r7, #20]
8003bfc: 005b lsls r3, r3, #1
8003bfe: 2203 movs r2, #3
8003c00: fa02 f303 lsl.w r3, r2, r3
8003c04: 43db mvns r3, r3
8003c06: 693a ldr r2, [r7, #16]
8003c08: 4013 ands r3, r2
8003c0a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2U));
8003c0c: 683b ldr r3, [r7, #0]
8003c0e: 68da ldr r2, [r3, #12]
8003c10: 697b ldr r3, [r7, #20]
8003c12: 005b lsls r3, r3, #1
8003c14: fa02 f303 lsl.w r3, r2, r3
8003c18: 693a ldr r2, [r7, #16]
8003c1a: 4313 orrs r3, r2
8003c1c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8003c1e: 687b ldr r3, [r7, #4]
8003c20: 693a ldr r2, [r7, #16]
8003c22: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8003c24: 687b ldr r3, [r7, #4]
8003c26: 685b ldr r3, [r3, #4]
8003c28: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8003c2a: 2201 movs r2, #1
8003c2c: 697b ldr r3, [r7, #20]
8003c2e: fa02 f303 lsl.w r3, r2, r3
8003c32: 43db mvns r3, r3
8003c34: 693a ldr r2, [r7, #16]
8003c36: 4013 ands r3, r2
8003c38: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8003c3a: 683b ldr r3, [r7, #0]
8003c3c: 685b ldr r3, [r3, #4]
8003c3e: 091b lsrs r3, r3, #4
8003c40: f003 0201 and.w r2, r3, #1
8003c44: 697b ldr r3, [r7, #20]
8003c46: fa02 f303 lsl.w r3, r2, r3
8003c4a: 693a ldr r2, [r7, #16]
8003c4c: 4313 orrs r3, r2
8003c4e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8003c50: 687b ldr r3, [r7, #4]
8003c52: 693a ldr r2, [r7, #16]
8003c54: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8003c56: 683b ldr r3, [r7, #0]
8003c58: 685b ldr r3, [r3, #4]
8003c5a: f003 0303 and.w r3, r3, #3
8003c5e: 2b03 cmp r3, #3
8003c60: d017 beq.n 8003c92 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8003c62: 687b ldr r3, [r7, #4]
8003c64: 68db ldr r3, [r3, #12]
8003c66: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8003c68: 697b ldr r3, [r7, #20]
8003c6a: 005b lsls r3, r3, #1
8003c6c: 2203 movs r2, #3
8003c6e: fa02 f303 lsl.w r3, r2, r3
8003c72: 43db mvns r3, r3
8003c74: 693a ldr r2, [r7, #16]
8003c76: 4013 ands r3, r2
8003c78: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8003c7a: 683b ldr r3, [r7, #0]
8003c7c: 689a ldr r2, [r3, #8]
8003c7e: 697b ldr r3, [r7, #20]
8003c80: 005b lsls r3, r3, #1
8003c82: fa02 f303 lsl.w r3, r2, r3
8003c86: 693a ldr r2, [r7, #16]
8003c88: 4313 orrs r3, r2
8003c8a: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8003c8c: 687b ldr r3, [r7, #4]
8003c8e: 693a ldr r2, [r7, #16]
8003c90: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8003c92: 683b ldr r3, [r7, #0]
8003c94: 685b ldr r3, [r3, #4]
8003c96: f003 0303 and.w r3, r3, #3
8003c9a: 2b02 cmp r3, #2
8003c9c: d123 bne.n 8003ce6 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8003c9e: 697b ldr r3, [r7, #20]
8003ca0: 08da lsrs r2, r3, #3
8003ca2: 687b ldr r3, [r7, #4]
8003ca4: 3208 adds r2, #8
8003ca6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8003caa: 613b str r3, [r7, #16]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8003cac: 697b ldr r3, [r7, #20]
8003cae: f003 0307 and.w r3, r3, #7
8003cb2: 009b lsls r3, r3, #2
8003cb4: 220f movs r2, #15
8003cb6: fa02 f303 lsl.w r3, r2, r3
8003cba: 43db mvns r3, r3
8003cbc: 693a ldr r2, [r7, #16]
8003cbe: 4013 ands r3, r2
8003cc0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8003cc2: 683b ldr r3, [r7, #0]
8003cc4: 691a ldr r2, [r3, #16]
8003cc6: 697b ldr r3, [r7, #20]
8003cc8: f003 0307 and.w r3, r3, #7
8003ccc: 009b lsls r3, r3, #2
8003cce: fa02 f303 lsl.w r3, r2, r3
8003cd2: 693a ldr r2, [r7, #16]
8003cd4: 4313 orrs r3, r2
8003cd6: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3U] = temp;
8003cd8: 697b ldr r3, [r7, #20]
8003cda: 08da lsrs r2, r3, #3
8003cdc: 687b ldr r3, [r7, #4]
8003cde: 3208 adds r2, #8
8003ce0: 6939 ldr r1, [r7, #16]
8003ce2: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8003ce6: 687b ldr r3, [r7, #4]
8003ce8: 681b ldr r3, [r3, #0]
8003cea: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8003cec: 697b ldr r3, [r7, #20]
8003cee: 005b lsls r3, r3, #1
8003cf0: 2203 movs r2, #3
8003cf2: fa02 f303 lsl.w r3, r2, r3
8003cf6: 43db mvns r3, r3
8003cf8: 693a ldr r2, [r7, #16]
8003cfa: 4013 ands r3, r2
8003cfc: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8003cfe: 683b ldr r3, [r7, #0]
8003d00: 685b ldr r3, [r3, #4]
8003d02: f003 0203 and.w r2, r3, #3
8003d06: 697b ldr r3, [r7, #20]
8003d08: 005b lsls r3, r3, #1
8003d0a: fa02 f303 lsl.w r3, r2, r3
8003d0e: 693a ldr r2, [r7, #16]
8003d10: 4313 orrs r3, r2
8003d12: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8003d14: 687b ldr r3, [r7, #4]
8003d16: 693a ldr r2, [r7, #16]
8003d18: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8003d1a: 683b ldr r3, [r7, #0]
8003d1c: 685b ldr r3, [r3, #4]
8003d1e: f403 3340 and.w r3, r3, #196608 @ 0x30000
8003d22: 2b00 cmp r3, #0
8003d24: f000 80a6 beq.w 8003e74 <HAL_GPIO_Init+0x2c0>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003d28: 4b5b ldr r3, [pc, #364] @ (8003e98 <HAL_GPIO_Init+0x2e4>)
8003d2a: 6e1b ldr r3, [r3, #96] @ 0x60
8003d2c: 4a5a ldr r2, [pc, #360] @ (8003e98 <HAL_GPIO_Init+0x2e4>)
8003d2e: f043 0301 orr.w r3, r3, #1
8003d32: 6613 str r3, [r2, #96] @ 0x60
8003d34: 4b58 ldr r3, [pc, #352] @ (8003e98 <HAL_GPIO_Init+0x2e4>)
8003d36: 6e1b ldr r3, [r3, #96] @ 0x60
8003d38: f003 0301 and.w r3, r3, #1
8003d3c: 60bb str r3, [r7, #8]
8003d3e: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2U];
8003d40: 4a56 ldr r2, [pc, #344] @ (8003e9c <HAL_GPIO_Init+0x2e8>)
8003d42: 697b ldr r3, [r7, #20]
8003d44: 089b lsrs r3, r3, #2
8003d46: 3302 adds r3, #2
8003d48: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003d4c: 613b str r3, [r7, #16]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8003d4e: 697b ldr r3, [r7, #20]
8003d50: f003 0303 and.w r3, r3, #3
8003d54: 009b lsls r3, r3, #2
8003d56: 220f movs r2, #15
8003d58: fa02 f303 lsl.w r3, r2, r3
8003d5c: 43db mvns r3, r3
8003d5e: 693a ldr r2, [r7, #16]
8003d60: 4013 ands r3, r2
8003d62: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8003d64: 687b ldr r3, [r7, #4]
8003d66: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8003d6a: d01f beq.n 8003dac <HAL_GPIO_Init+0x1f8>
8003d6c: 687b ldr r3, [r7, #4]
8003d6e: 4a4c ldr r2, [pc, #304] @ (8003ea0 <HAL_GPIO_Init+0x2ec>)
8003d70: 4293 cmp r3, r2
8003d72: d019 beq.n 8003da8 <HAL_GPIO_Init+0x1f4>
8003d74: 687b ldr r3, [r7, #4]
8003d76: 4a4b ldr r2, [pc, #300] @ (8003ea4 <HAL_GPIO_Init+0x2f0>)
8003d78: 4293 cmp r3, r2
8003d7a: d013 beq.n 8003da4 <HAL_GPIO_Init+0x1f0>
8003d7c: 687b ldr r3, [r7, #4]
8003d7e: 4a4a ldr r2, [pc, #296] @ (8003ea8 <HAL_GPIO_Init+0x2f4>)
8003d80: 4293 cmp r3, r2
8003d82: d00d beq.n 8003da0 <HAL_GPIO_Init+0x1ec>
8003d84: 687b ldr r3, [r7, #4]
8003d86: 4a49 ldr r2, [pc, #292] @ (8003eac <HAL_GPIO_Init+0x2f8>)
8003d88: 4293 cmp r3, r2
8003d8a: d007 beq.n 8003d9c <HAL_GPIO_Init+0x1e8>
8003d8c: 687b ldr r3, [r7, #4]
8003d8e: 4a48 ldr r2, [pc, #288] @ (8003eb0 <HAL_GPIO_Init+0x2fc>)
8003d90: 4293 cmp r3, r2
8003d92: d101 bne.n 8003d98 <HAL_GPIO_Init+0x1e4>
8003d94: 2305 movs r3, #5
8003d96: e00a b.n 8003dae <HAL_GPIO_Init+0x1fa>
8003d98: 2306 movs r3, #6
8003d9a: e008 b.n 8003dae <HAL_GPIO_Init+0x1fa>
8003d9c: 2304 movs r3, #4
8003d9e: e006 b.n 8003dae <HAL_GPIO_Init+0x1fa>
8003da0: 2303 movs r3, #3
8003da2: e004 b.n 8003dae <HAL_GPIO_Init+0x1fa>
8003da4: 2302 movs r3, #2
8003da6: e002 b.n 8003dae <HAL_GPIO_Init+0x1fa>
8003da8: 2301 movs r3, #1
8003daa: e000 b.n 8003dae <HAL_GPIO_Init+0x1fa>
8003dac: 2300 movs r3, #0
8003dae: 697a ldr r2, [r7, #20]
8003db0: f002 0203 and.w r2, r2, #3
8003db4: 0092 lsls r2, r2, #2
8003db6: 4093 lsls r3, r2
8003db8: 693a ldr r2, [r7, #16]
8003dba: 4313 orrs r3, r2
8003dbc: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2U] = temp;
8003dbe: 4937 ldr r1, [pc, #220] @ (8003e9c <HAL_GPIO_Init+0x2e8>)
8003dc0: 697b ldr r3, [r7, #20]
8003dc2: 089b lsrs r3, r3, #2
8003dc4: 3302 adds r3, #2
8003dc6: 693a ldr r2, [r7, #16]
8003dc8: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8003dcc: 4b39 ldr r3, [pc, #228] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003dce: 689b ldr r3, [r3, #8]
8003dd0: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003dd2: 68fb ldr r3, [r7, #12]
8003dd4: 43db mvns r3, r3
8003dd6: 693a ldr r2, [r7, #16]
8003dd8: 4013 ands r3, r2
8003dda: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8003ddc: 683b ldr r3, [r7, #0]
8003dde: 685b ldr r3, [r3, #4]
8003de0: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003de4: 2b00 cmp r3, #0
8003de6: d003 beq.n 8003df0 <HAL_GPIO_Init+0x23c>
{
temp |= iocurrent;
8003de8: 693a ldr r2, [r7, #16]
8003dea: 68fb ldr r3, [r7, #12]
8003dec: 4313 orrs r3, r2
8003dee: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8003df0: 4a30 ldr r2, [pc, #192] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003df2: 693b ldr r3, [r7, #16]
8003df4: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8003df6: 4b2f ldr r3, [pc, #188] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003df8: 68db ldr r3, [r3, #12]
8003dfa: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003dfc: 68fb ldr r3, [r7, #12]
8003dfe: 43db mvns r3, r3
8003e00: 693a ldr r2, [r7, #16]
8003e02: 4013 ands r3, r2
8003e04: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8003e06: 683b ldr r3, [r7, #0]
8003e08: 685b ldr r3, [r3, #4]
8003e0a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8003e0e: 2b00 cmp r3, #0
8003e10: d003 beq.n 8003e1a <HAL_GPIO_Init+0x266>
{
temp |= iocurrent;
8003e12: 693a ldr r2, [r7, #16]
8003e14: 68fb ldr r3, [r7, #12]
8003e16: 4313 orrs r3, r2
8003e18: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8003e1a: 4a26 ldr r2, [pc, #152] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003e1c: 693b ldr r3, [r7, #16]
8003e1e: 60d3 str r3, [r2, #12]
temp = EXTI->EMR1;
8003e20: 4b24 ldr r3, [pc, #144] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003e22: 685b ldr r3, [r3, #4]
8003e24: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003e26: 68fb ldr r3, [r7, #12]
8003e28: 43db mvns r3, r3
8003e2a: 693a ldr r2, [r7, #16]
8003e2c: 4013 ands r3, r2
8003e2e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8003e30: 683b ldr r3, [r7, #0]
8003e32: 685b ldr r3, [r3, #4]
8003e34: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003e38: 2b00 cmp r3, #0
8003e3a: d003 beq.n 8003e44 <HAL_GPIO_Init+0x290>
{
temp |= iocurrent;
8003e3c: 693a ldr r2, [r7, #16]
8003e3e: 68fb ldr r3, [r7, #12]
8003e40: 4313 orrs r3, r2
8003e42: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8003e44: 4a1b ldr r2, [pc, #108] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003e46: 693b ldr r3, [r7, #16]
8003e48: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
8003e4a: 4b1a ldr r3, [pc, #104] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003e4c: 681b ldr r3, [r3, #0]
8003e4e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003e50: 68fb ldr r3, [r7, #12]
8003e52: 43db mvns r3, r3
8003e54: 693a ldr r2, [r7, #16]
8003e56: 4013 ands r3, r2
8003e58: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8003e5a: 683b ldr r3, [r7, #0]
8003e5c: 685b ldr r3, [r3, #4]
8003e5e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003e62: 2b00 cmp r3, #0
8003e64: d003 beq.n 8003e6e <HAL_GPIO_Init+0x2ba>
{
temp |= iocurrent;
8003e66: 693a ldr r2, [r7, #16]
8003e68: 68fb ldr r3, [r7, #12]
8003e6a: 4313 orrs r3, r2
8003e6c: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8003e6e: 4a11 ldr r2, [pc, #68] @ (8003eb4 <HAL_GPIO_Init+0x300>)
8003e70: 693b ldr r3, [r7, #16]
8003e72: 6013 str r3, [r2, #0]
}
}
position++;
8003e74: 697b ldr r3, [r7, #20]
8003e76: 3301 adds r3, #1
8003e78: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0U)
8003e7a: 683b ldr r3, [r7, #0]
8003e7c: 681a ldr r2, [r3, #0]
8003e7e: 697b ldr r3, [r7, #20]
8003e80: fa22 f303 lsr.w r3, r2, r3
8003e84: 2b00 cmp r3, #0
8003e86: f47f ae9d bne.w 8003bc4 <HAL_GPIO_Init+0x10>
}
}
8003e8a: bf00 nop
8003e8c: bf00 nop
8003e8e: 371c adds r7, #28
8003e90: 46bd mov sp, r7
8003e92: f85d 7b04 ldr.w r7, [sp], #4
8003e96: 4770 bx lr
8003e98: 40021000 .word 0x40021000
8003e9c: 40010000 .word 0x40010000
8003ea0: 48000400 .word 0x48000400
8003ea4: 48000800 .word 0x48000800
8003ea8: 48000c00 .word 0x48000c00
8003eac: 48001000 .word 0x48001000
8003eb0: 48001400 .word 0x48001400
8003eb4: 40010400 .word 0x40010400
08003eb8 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8003eb8: b480 push {r7}
8003eba: b083 sub sp, #12
8003ebc: af00 add r7, sp, #0
8003ebe: 6078 str r0, [r7, #4]
8003ec0: 460b mov r3, r1
8003ec2: 807b strh r3, [r7, #2]
8003ec4: 4613 mov r3, r2
8003ec6: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003ec8: 787b ldrb r3, [r7, #1]
8003eca: 2b00 cmp r3, #0
8003ecc: d003 beq.n 8003ed6 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8003ece: 887a ldrh r2, [r7, #2]
8003ed0: 687b ldr r3, [r7, #4]
8003ed2: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8003ed4: e002 b.n 8003edc <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8003ed6: 887a ldrh r2, [r7, #2]
8003ed8: 687b ldr r3, [r7, #4]
8003eda: 629a str r2, [r3, #40] @ 0x28
}
8003edc: bf00 nop
8003ede: 370c adds r7, #12
8003ee0: 46bd mov sp, r7
8003ee2: f85d 7b04 ldr.w r7, [sp], #4
8003ee6: 4770 bx lr
08003ee8 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8003ee8: b480 push {r7}
8003eea: b085 sub sp, #20
8003eec: af00 add r7, sp, #0
8003eee: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
8003ef0: 687b ldr r3, [r7, #4]
8003ef2: 2b00 cmp r3, #0
8003ef4: d141 bne.n 8003f7a <HAL_PWREx_ControlVoltageScaling+0x92>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8003ef6: 4b4b ldr r3, [pc, #300] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003ef8: 681b ldr r3, [r3, #0]
8003efa: f403 63c0 and.w r3, r3, #1536 @ 0x600
8003efe: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003f02: d131 bne.n 8003f68 <HAL_PWREx_ControlVoltageScaling+0x80>
{
/* Make sure Range 1 Boost is enabled */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003f04: 4b47 ldr r3, [pc, #284] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f06: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003f0a: 4a46 ldr r2, [pc, #280] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f0c: f423 7380 bic.w r3, r3, #256 @ 0x100
8003f10: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8003f14: 4b43 ldr r3, [pc, #268] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f16: 681b ldr r3, [r3, #0]
8003f18: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8003f1c: 4a41 ldr r2, [pc, #260] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f1e: f443 7300 orr.w r3, r3, #512 @ 0x200
8003f22: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8003f24: 4b40 ldr r3, [pc, #256] @ (8004028 <HAL_PWREx_ControlVoltageScaling+0x140>)
8003f26: 681b ldr r3, [r3, #0]
8003f28: 2232 movs r2, #50 @ 0x32
8003f2a: fb02 f303 mul.w r3, r2, r3
8003f2e: 4a3f ldr r2, [pc, #252] @ (800402c <HAL_PWREx_ControlVoltageScaling+0x144>)
8003f30: fba2 2303 umull r2, r3, r2, r3
8003f34: 0c9b lsrs r3, r3, #18
8003f36: 3301 adds r3, #1
8003f38: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003f3a: e002 b.n 8003f42 <HAL_PWREx_ControlVoltageScaling+0x5a>
{
wait_loop_index--;
8003f3c: 68fb ldr r3, [r7, #12]
8003f3e: 3b01 subs r3, #1
8003f40: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003f42: 4b38 ldr r3, [pc, #224] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f44: 695b ldr r3, [r3, #20]
8003f46: f403 6380 and.w r3, r3, #1024 @ 0x400
8003f4a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003f4e: d102 bne.n 8003f56 <HAL_PWREx_ControlVoltageScaling+0x6e>
8003f50: 68fb ldr r3, [r7, #12]
8003f52: 2b00 cmp r3, #0
8003f54: d1f2 bne.n 8003f3c <HAL_PWREx_ControlVoltageScaling+0x54>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8003f56: 4b33 ldr r3, [pc, #204] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f58: 695b ldr r3, [r3, #20]
8003f5a: f403 6380 and.w r3, r3, #1024 @ 0x400
8003f5e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003f62: d158 bne.n 8004016 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8003f64: 2303 movs r3, #3
8003f66: e057 b.n 8004018 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Enable Range 1 Boost (no issue if bit already reset) */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003f68: 4b2e ldr r3, [pc, #184] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f6a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003f6e: 4a2d ldr r2, [pc, #180] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f70: f423 7380 bic.w r3, r3, #256 @ 0x100
8003f74: f8c2 3080 str.w r3, [r2, #128] @ 0x80
8003f78: e04d b.n 8004016 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8003f7a: 687b ldr r3, [r7, #4]
8003f7c: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003f80: d141 bne.n 8004006 <HAL_PWREx_ControlVoltageScaling+0x11e>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8003f82: 4b28 ldr r3, [pc, #160] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f84: 681b ldr r3, [r3, #0]
8003f86: f403 63c0 and.w r3, r3, #1536 @ 0x600
8003f8a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003f8e: d131 bne.n 8003ff4 <HAL_PWREx_ControlVoltageScaling+0x10c>
{
/* Make sure Range 1 Boost is disabled */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003f90: 4b24 ldr r3, [pc, #144] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f92: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003f96: 4a23 ldr r2, [pc, #140] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f98: f443 7380 orr.w r3, r3, #256 @ 0x100
8003f9c: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8003fa0: 4b20 ldr r3, [pc, #128] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003fa2: 681b ldr r3, [r3, #0]
8003fa4: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8003fa8: 4a1e ldr r2, [pc, #120] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003faa: f443 7300 orr.w r3, r3, #512 @ 0x200
8003fae: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8003fb0: 4b1d ldr r3, [pc, #116] @ (8004028 <HAL_PWREx_ControlVoltageScaling+0x140>)
8003fb2: 681b ldr r3, [r3, #0]
8003fb4: 2232 movs r2, #50 @ 0x32
8003fb6: fb02 f303 mul.w r3, r2, r3
8003fba: 4a1c ldr r2, [pc, #112] @ (800402c <HAL_PWREx_ControlVoltageScaling+0x144>)
8003fbc: fba2 2303 umull r2, r3, r2, r3
8003fc0: 0c9b lsrs r3, r3, #18
8003fc2: 3301 adds r3, #1
8003fc4: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003fc6: e002 b.n 8003fce <HAL_PWREx_ControlVoltageScaling+0xe6>
{
wait_loop_index--;
8003fc8: 68fb ldr r3, [r7, #12]
8003fca: 3b01 subs r3, #1
8003fcc: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003fce: 4b15 ldr r3, [pc, #84] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003fd0: 695b ldr r3, [r3, #20]
8003fd2: f403 6380 and.w r3, r3, #1024 @ 0x400
8003fd6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003fda: d102 bne.n 8003fe2 <HAL_PWREx_ControlVoltageScaling+0xfa>
8003fdc: 68fb ldr r3, [r7, #12]
8003fde: 2b00 cmp r3, #0
8003fe0: d1f2 bne.n 8003fc8 <HAL_PWREx_ControlVoltageScaling+0xe0>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8003fe2: 4b10 ldr r3, [pc, #64] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003fe4: 695b ldr r3, [r3, #20]
8003fe6: f403 6380 and.w r3, r3, #1024 @ 0x400
8003fea: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003fee: d112 bne.n 8004016 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8003ff0: 2303 movs r3, #3
8003ff2: e011 b.n 8004018 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Disable Range 1 Boost (no issue if bit already set) */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003ff4: 4b0b ldr r3, [pc, #44] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003ff6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003ffa: 4a0a ldr r2, [pc, #40] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003ffc: f443 7380 orr.w r3, r3, #256 @ 0x100
8004000: f8c2 3080 str.w r3, [r2, #128] @ 0x80
8004004: e007 b.n 8004016 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8004006: 4b07 ldr r3, [pc, #28] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8004008: 681b ldr r3, [r3, #0]
800400a: f423 63c0 bic.w r3, r3, #1536 @ 0x600
800400e: 4a05 ldr r2, [pc, #20] @ (8004024 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8004010: f443 6380 orr.w r3, r3, #1024 @ 0x400
8004014: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
}
return HAL_OK;
8004016: 2300 movs r3, #0
}
8004018: 4618 mov r0, r3
800401a: 3714 adds r7, #20
800401c: 46bd mov sp, r7
800401e: f85d 7b04 ldr.w r7, [sp], #4
8004022: 4770 bx lr
8004024: 40007000 .word 0x40007000
8004028: 2000001c .word 0x2000001c
800402c: 431bde83 .word 0x431bde83
08004030 <HAL_PWREx_DisableUCPDDeadBattery>:
* or to hand over control to the UCPD (which should therefore be
* initialized before doing the disable).
* @retval None
*/
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
8004030: b480 push {r7}
8004032: af00 add r7, sp, #0
/* Write 1 to disable the USB Type-C dead battery pull-down behavior */
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
8004034: 4b05 ldr r3, [pc, #20] @ (800404c <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
8004036: 689b ldr r3, [r3, #8]
8004038: 4a04 ldr r2, [pc, #16] @ (800404c <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
800403a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
800403e: 6093 str r3, [r2, #8]
}
8004040: bf00 nop
8004042: 46bd mov sp, r7
8004044: f85d 7b04 ldr.w r7, [sp], #4
8004048: 4770 bx lr
800404a: bf00 nop
800404c: 40007000 .word 0x40007000
08004050 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8004050: b580 push {r7, lr}
8004052: b088 sub sp, #32
8004054: af00 add r7, sp, #0
8004056: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8004058: 687b ldr r3, [r7, #4]
800405a: 2b00 cmp r3, #0
800405c: d101 bne.n 8004062 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800405e: 2301 movs r3, #1
8004060: e2fe b.n 8004660 <HAL_RCC_OscConfig+0x610>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8004062: 687b ldr r3, [r7, #4]
8004064: 681b ldr r3, [r3, #0]
8004066: f003 0301 and.w r3, r3, #1
800406a: 2b00 cmp r3, #0
800406c: d075 beq.n 800415a <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800406e: 4b97 ldr r3, [pc, #604] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004070: 689b ldr r3, [r3, #8]
8004072: f003 030c and.w r3, r3, #12
8004076: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8004078: 4b94 ldr r3, [pc, #592] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
800407a: 68db ldr r3, [r3, #12]
800407c: f003 0303 and.w r3, r3, #3
8004080: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
8004082: 69bb ldr r3, [r7, #24]
8004084: 2b0c cmp r3, #12
8004086: d102 bne.n 800408e <HAL_RCC_OscConfig+0x3e>
8004088: 697b ldr r3, [r7, #20]
800408a: 2b03 cmp r3, #3
800408c: d002 beq.n 8004094 <HAL_RCC_OscConfig+0x44>
800408e: 69bb ldr r3, [r7, #24]
8004090: 2b08 cmp r3, #8
8004092: d10b bne.n 80040ac <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004094: 4b8d ldr r3, [pc, #564] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004096: 681b ldr r3, [r3, #0]
8004098: f403 3300 and.w r3, r3, #131072 @ 0x20000
800409c: 2b00 cmp r3, #0
800409e: d05b beq.n 8004158 <HAL_RCC_OscConfig+0x108>
80040a0: 687b ldr r3, [r7, #4]
80040a2: 685b ldr r3, [r3, #4]
80040a4: 2b00 cmp r3, #0
80040a6: d157 bne.n 8004158 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80040a8: 2301 movs r3, #1
80040aa: e2d9 b.n 8004660 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80040ac: 687b ldr r3, [r7, #4]
80040ae: 685b ldr r3, [r3, #4]
80040b0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80040b4: d106 bne.n 80040c4 <HAL_RCC_OscConfig+0x74>
80040b6: 4b85 ldr r3, [pc, #532] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040b8: 681b ldr r3, [r3, #0]
80040ba: 4a84 ldr r2, [pc, #528] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040bc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80040c0: 6013 str r3, [r2, #0]
80040c2: e01d b.n 8004100 <HAL_RCC_OscConfig+0xb0>
80040c4: 687b ldr r3, [r7, #4]
80040c6: 685b ldr r3, [r3, #4]
80040c8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
80040cc: d10c bne.n 80040e8 <HAL_RCC_OscConfig+0x98>
80040ce: 4b7f ldr r3, [pc, #508] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040d0: 681b ldr r3, [r3, #0]
80040d2: 4a7e ldr r2, [pc, #504] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040d4: f443 2380 orr.w r3, r3, #262144 @ 0x40000
80040d8: 6013 str r3, [r2, #0]
80040da: 4b7c ldr r3, [pc, #496] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040dc: 681b ldr r3, [r3, #0]
80040de: 4a7b ldr r2, [pc, #492] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040e0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80040e4: 6013 str r3, [r2, #0]
80040e6: e00b b.n 8004100 <HAL_RCC_OscConfig+0xb0>
80040e8: 4b78 ldr r3, [pc, #480] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040ea: 681b ldr r3, [r3, #0]
80040ec: 4a77 ldr r2, [pc, #476] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040ee: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80040f2: 6013 str r3, [r2, #0]
80040f4: 4b75 ldr r3, [pc, #468] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040f6: 681b ldr r3, [r3, #0]
80040f8: 4a74 ldr r2, [pc, #464] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80040fa: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80040fe: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8004100: 687b ldr r3, [r7, #4]
8004102: 685b ldr r3, [r3, #4]
8004104: 2b00 cmp r3, #0
8004106: d013 beq.n 8004130 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004108: f7fd feba bl 8001e80 <HAL_GetTick>
800410c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800410e: e008 b.n 8004122 <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004110: f7fd feb6 bl 8001e80 <HAL_GetTick>
8004114: 4602 mov r2, r0
8004116: 693b ldr r3, [r7, #16]
8004118: 1ad3 subs r3, r2, r3
800411a: 2b64 cmp r3, #100 @ 0x64
800411c: d901 bls.n 8004122 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
800411e: 2303 movs r3, #3
8004120: e29e b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8004122: 4b6a ldr r3, [pc, #424] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004124: 681b ldr r3, [r3, #0]
8004126: f403 3300 and.w r3, r3, #131072 @ 0x20000
800412a: 2b00 cmp r3, #0
800412c: d0f0 beq.n 8004110 <HAL_RCC_OscConfig+0xc0>
800412e: e014 b.n 800415a <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004130: f7fd fea6 bl 8001e80 <HAL_GetTick>
8004134: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8004136: e008 b.n 800414a <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004138: f7fd fea2 bl 8001e80 <HAL_GetTick>
800413c: 4602 mov r2, r0
800413e: 693b ldr r3, [r7, #16]
8004140: 1ad3 subs r3, r2, r3
8004142: 2b64 cmp r3, #100 @ 0x64
8004144: d901 bls.n 800414a <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8004146: 2303 movs r3, #3
8004148: e28a b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
800414a: 4b60 ldr r3, [pc, #384] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
800414c: 681b ldr r3, [r3, #0]
800414e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004152: 2b00 cmp r3, #0
8004154: d1f0 bne.n 8004138 <HAL_RCC_OscConfig+0xe8>
8004156: e000 b.n 800415a <HAL_RCC_OscConfig+0x10a>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004158: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800415a: 687b ldr r3, [r7, #4]
800415c: 681b ldr r3, [r3, #0]
800415e: f003 0302 and.w r3, r3, #2
8004162: 2b00 cmp r3, #0
8004164: d075 beq.n 8004252 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8004166: 4b59 ldr r3, [pc, #356] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004168: 689b ldr r3, [r3, #8]
800416a: f003 030c and.w r3, r3, #12
800416e: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8004170: 4b56 ldr r3, [pc, #344] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004172: 68db ldr r3, [r3, #12]
8004174: f003 0303 and.w r3, r3, #3
8004178: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
800417a: 69bb ldr r3, [r7, #24]
800417c: 2b0c cmp r3, #12
800417e: d102 bne.n 8004186 <HAL_RCC_OscConfig+0x136>
8004180: 697b ldr r3, [r7, #20]
8004182: 2b02 cmp r3, #2
8004184: d002 beq.n 800418c <HAL_RCC_OscConfig+0x13c>
8004186: 69bb ldr r3, [r7, #24]
8004188: 2b04 cmp r3, #4
800418a: d11f bne.n 80041cc <HAL_RCC_OscConfig+0x17c>
{
/* When HSI is used as system clock it will not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
800418c: 4b4f ldr r3, [pc, #316] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
800418e: 681b ldr r3, [r3, #0]
8004190: f403 6380 and.w r3, r3, #1024 @ 0x400
8004194: 2b00 cmp r3, #0
8004196: d005 beq.n 80041a4 <HAL_RCC_OscConfig+0x154>
8004198: 687b ldr r3, [r7, #4]
800419a: 68db ldr r3, [r3, #12]
800419c: 2b00 cmp r3, #0
800419e: d101 bne.n 80041a4 <HAL_RCC_OscConfig+0x154>
{
return HAL_ERROR;
80041a0: 2301 movs r3, #1
80041a2: e25d b.n 8004660 <HAL_RCC_OscConfig+0x610>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80041a4: 4b49 ldr r3, [pc, #292] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80041a6: 685b ldr r3, [r3, #4]
80041a8: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
80041ac: 687b ldr r3, [r7, #4]
80041ae: 691b ldr r3, [r3, #16]
80041b0: 061b lsls r3, r3, #24
80041b2: 4946 ldr r1, [pc, #280] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80041b4: 4313 orrs r3, r2
80041b6: 604b str r3, [r1, #4]
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
80041b8: 4b45 ldr r3, [pc, #276] @ (80042d0 <HAL_RCC_OscConfig+0x280>)
80041ba: 681b ldr r3, [r3, #0]
80041bc: 4618 mov r0, r3
80041be: f7fd fe13 bl 8001de8 <HAL_InitTick>
80041c2: 4603 mov r3, r0
80041c4: 2b00 cmp r3, #0
80041c6: d043 beq.n 8004250 <HAL_RCC_OscConfig+0x200>
{
return HAL_ERROR;
80041c8: 2301 movs r3, #1
80041ca: e249 b.n 8004660 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80041cc: 687b ldr r3, [r7, #4]
80041ce: 68db ldr r3, [r3, #12]
80041d0: 2b00 cmp r3, #0
80041d2: d023 beq.n 800421c <HAL_RCC_OscConfig+0x1cc>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80041d4: 4b3d ldr r3, [pc, #244] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80041d6: 681b ldr r3, [r3, #0]
80041d8: 4a3c ldr r2, [pc, #240] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80041da: f443 7380 orr.w r3, r3, #256 @ 0x100
80041de: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80041e0: f7fd fe4e bl 8001e80 <HAL_GetTick>
80041e4: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80041e6: e008 b.n 80041fa <HAL_RCC_OscConfig+0x1aa>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80041e8: f7fd fe4a bl 8001e80 <HAL_GetTick>
80041ec: 4602 mov r2, r0
80041ee: 693b ldr r3, [r7, #16]
80041f0: 1ad3 subs r3, r2, r3
80041f2: 2b02 cmp r3, #2
80041f4: d901 bls.n 80041fa <HAL_RCC_OscConfig+0x1aa>
{
return HAL_TIMEOUT;
80041f6: 2303 movs r3, #3
80041f8: e232 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80041fa: 4b34 ldr r3, [pc, #208] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80041fc: 681b ldr r3, [r3, #0]
80041fe: f403 6380 and.w r3, r3, #1024 @ 0x400
8004202: 2b00 cmp r3, #0
8004204: d0f0 beq.n 80041e8 <HAL_RCC_OscConfig+0x198>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8004206: 4b31 ldr r3, [pc, #196] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004208: 685b ldr r3, [r3, #4]
800420a: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
800420e: 687b ldr r3, [r7, #4]
8004210: 691b ldr r3, [r3, #16]
8004212: 061b lsls r3, r3, #24
8004214: 492d ldr r1, [pc, #180] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004216: 4313 orrs r3, r2
8004218: 604b str r3, [r1, #4]
800421a: e01a b.n 8004252 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800421c: 4b2b ldr r3, [pc, #172] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
800421e: 681b ldr r3, [r3, #0]
8004220: 4a2a ldr r2, [pc, #168] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004222: f423 7380 bic.w r3, r3, #256 @ 0x100
8004226: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004228: f7fd fe2a bl 8001e80 <HAL_GetTick>
800422c: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
800422e: e008 b.n 8004242 <HAL_RCC_OscConfig+0x1f2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8004230: f7fd fe26 bl 8001e80 <HAL_GetTick>
8004234: 4602 mov r2, r0
8004236: 693b ldr r3, [r7, #16]
8004238: 1ad3 subs r3, r2, r3
800423a: 2b02 cmp r3, #2
800423c: d901 bls.n 8004242 <HAL_RCC_OscConfig+0x1f2>
{
return HAL_TIMEOUT;
800423e: 2303 movs r3, #3
8004240: e20e b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8004242: 4b22 ldr r3, [pc, #136] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004244: 681b ldr r3, [r3, #0]
8004246: f403 6380 and.w r3, r3, #1024 @ 0x400
800424a: 2b00 cmp r3, #0
800424c: d1f0 bne.n 8004230 <HAL_RCC_OscConfig+0x1e0>
800424e: e000 b.n 8004252 <HAL_RCC_OscConfig+0x202>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8004250: bf00 nop
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8004252: 687b ldr r3, [r7, #4]
8004254: 681b ldr r3, [r3, #0]
8004256: f003 0308 and.w r3, r3, #8
800425a: 2b00 cmp r3, #0
800425c: d041 beq.n 80042e2 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
800425e: 687b ldr r3, [r7, #4]
8004260: 695b ldr r3, [r3, #20]
8004262: 2b00 cmp r3, #0
8004264: d01c beq.n 80042a0 <HAL_RCC_OscConfig+0x250>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8004266: 4b19 ldr r3, [pc, #100] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004268: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800426c: 4a17 ldr r2, [pc, #92] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
800426e: f043 0301 orr.w r3, r3, #1
8004272: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004276: f7fd fe03 bl 8001e80 <HAL_GetTick>
800427a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
800427c: e008 b.n 8004290 <HAL_RCC_OscConfig+0x240>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800427e: f7fd fdff bl 8001e80 <HAL_GetTick>
8004282: 4602 mov r2, r0
8004284: 693b ldr r3, [r7, #16]
8004286: 1ad3 subs r3, r2, r3
8004288: 2b02 cmp r3, #2
800428a: d901 bls.n 8004290 <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
800428c: 2303 movs r3, #3
800428e: e1e7 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8004290: 4b0e ldr r3, [pc, #56] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
8004292: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8004296: f003 0302 and.w r3, r3, #2
800429a: 2b00 cmp r3, #0
800429c: d0ef beq.n 800427e <HAL_RCC_OscConfig+0x22e>
800429e: e020 b.n 80042e2 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80042a0: 4b0a ldr r3, [pc, #40] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80042a2: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80042a6: 4a09 ldr r2, [pc, #36] @ (80042cc <HAL_RCC_OscConfig+0x27c>)
80042a8: f023 0301 bic.w r3, r3, #1
80042ac: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80042b0: f7fd fde6 bl 8001e80 <HAL_GetTick>
80042b4: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80042b6: e00d b.n 80042d4 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80042b8: f7fd fde2 bl 8001e80 <HAL_GetTick>
80042bc: 4602 mov r2, r0
80042be: 693b ldr r3, [r7, #16]
80042c0: 1ad3 subs r3, r2, r3
80042c2: 2b02 cmp r3, #2
80042c4: d906 bls.n 80042d4 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
80042c6: 2303 movs r3, #3
80042c8: e1ca b.n 8004660 <HAL_RCC_OscConfig+0x610>
80042ca: bf00 nop
80042cc: 40021000 .word 0x40021000
80042d0: 20000020 .word 0x20000020
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80042d4: 4b8c ldr r3, [pc, #560] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80042d6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80042da: f003 0302 and.w r3, r3, #2
80042de: 2b00 cmp r3, #0
80042e0: d1ea bne.n 80042b8 <HAL_RCC_OscConfig+0x268>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80042e2: 687b ldr r3, [r7, #4]
80042e4: 681b ldr r3, [r3, #0]
80042e6: f003 0304 and.w r3, r3, #4
80042ea: 2b00 cmp r3, #0
80042ec: f000 80a6 beq.w 800443c <HAL_RCC_OscConfig+0x3ec>
{
FlagStatus pwrclkchanged = RESET;
80042f0: 2300 movs r3, #0
80042f2: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain if necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
80042f4: 4b84 ldr r3, [pc, #528] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80042f6: 6d9b ldr r3, [r3, #88] @ 0x58
80042f8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80042fc: 2b00 cmp r3, #0
80042fe: d101 bne.n 8004304 <HAL_RCC_OscConfig+0x2b4>
8004300: 2301 movs r3, #1
8004302: e000 b.n 8004306 <HAL_RCC_OscConfig+0x2b6>
8004304: 2300 movs r3, #0
8004306: 2b00 cmp r3, #0
8004308: d00d beq.n 8004326 <HAL_RCC_OscConfig+0x2d6>
{
__HAL_RCC_PWR_CLK_ENABLE();
800430a: 4b7f ldr r3, [pc, #508] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
800430c: 6d9b ldr r3, [r3, #88] @ 0x58
800430e: 4a7e ldr r2, [pc, #504] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004310: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004314: 6593 str r3, [r2, #88] @ 0x58
8004316: 4b7c ldr r3, [pc, #496] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004318: 6d9b ldr r3, [r3, #88] @ 0x58
800431a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800431e: 60fb str r3, [r7, #12]
8004320: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8004322: 2301 movs r3, #1
8004324: 77fb strb r3, [r7, #31]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8004326: 4b79 ldr r3, [pc, #484] @ (800450c <HAL_RCC_OscConfig+0x4bc>)
8004328: 681b ldr r3, [r3, #0]
800432a: f403 7380 and.w r3, r3, #256 @ 0x100
800432e: 2b00 cmp r3, #0
8004330: d118 bne.n 8004364 <HAL_RCC_OscConfig+0x314>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8004332: 4b76 ldr r3, [pc, #472] @ (800450c <HAL_RCC_OscConfig+0x4bc>)
8004334: 681b ldr r3, [r3, #0]
8004336: 4a75 ldr r2, [pc, #468] @ (800450c <HAL_RCC_OscConfig+0x4bc>)
8004338: f443 7380 orr.w r3, r3, #256 @ 0x100
800433c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800433e: f7fd fd9f bl 8001e80 <HAL_GetTick>
8004342: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8004344: e008 b.n 8004358 <HAL_RCC_OscConfig+0x308>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004346: f7fd fd9b bl 8001e80 <HAL_GetTick>
800434a: 4602 mov r2, r0
800434c: 693b ldr r3, [r7, #16]
800434e: 1ad3 subs r3, r2, r3
8004350: 2b02 cmp r3, #2
8004352: d901 bls.n 8004358 <HAL_RCC_OscConfig+0x308>
{
return HAL_TIMEOUT;
8004354: 2303 movs r3, #3
8004356: e183 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8004358: 4b6c ldr r3, [pc, #432] @ (800450c <HAL_RCC_OscConfig+0x4bc>)
800435a: 681b ldr r3, [r3, #0]
800435c: f403 7380 and.w r3, r3, #256 @ 0x100
8004360: 2b00 cmp r3, #0
8004362: d0f0 beq.n 8004346 <HAL_RCC_OscConfig+0x2f6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8004364: 687b ldr r3, [r7, #4]
8004366: 689b ldr r3, [r3, #8]
8004368: 2b01 cmp r3, #1
800436a: d108 bne.n 800437e <HAL_RCC_OscConfig+0x32e>
800436c: 4b66 ldr r3, [pc, #408] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
800436e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004372: 4a65 ldr r2, [pc, #404] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004374: f043 0301 orr.w r3, r3, #1
8004378: f8c2 3090 str.w r3, [r2, #144] @ 0x90
800437c: e024 b.n 80043c8 <HAL_RCC_OscConfig+0x378>
800437e: 687b ldr r3, [r7, #4]
8004380: 689b ldr r3, [r3, #8]
8004382: 2b05 cmp r3, #5
8004384: d110 bne.n 80043a8 <HAL_RCC_OscConfig+0x358>
8004386: 4b60 ldr r3, [pc, #384] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004388: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800438c: 4a5e ldr r2, [pc, #376] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
800438e: f043 0304 orr.w r3, r3, #4
8004392: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8004396: 4b5c ldr r3, [pc, #368] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004398: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800439c: 4a5a ldr r2, [pc, #360] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
800439e: f043 0301 orr.w r3, r3, #1
80043a2: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80043a6: e00f b.n 80043c8 <HAL_RCC_OscConfig+0x378>
80043a8: 4b57 ldr r3, [pc, #348] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80043aa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80043ae: 4a56 ldr r2, [pc, #344] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80043b0: f023 0301 bic.w r3, r3, #1
80043b4: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80043b8: 4b53 ldr r3, [pc, #332] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80043ba: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80043be: 4a52 ldr r2, [pc, #328] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80043c0: f023 0304 bic.w r3, r3, #4
80043c4: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80043c8: 687b ldr r3, [r7, #4]
80043ca: 689b ldr r3, [r3, #8]
80043cc: 2b00 cmp r3, #0
80043ce: d016 beq.n 80043fe <HAL_RCC_OscConfig+0x3ae>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80043d0: f7fd fd56 bl 8001e80 <HAL_GetTick>
80043d4: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80043d6: e00a b.n 80043ee <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80043d8: f7fd fd52 bl 8001e80 <HAL_GetTick>
80043dc: 4602 mov r2, r0
80043de: 693b ldr r3, [r7, #16]
80043e0: 1ad3 subs r3, r2, r3
80043e2: f241 3288 movw r2, #5000 @ 0x1388
80043e6: 4293 cmp r3, r2
80043e8: d901 bls.n 80043ee <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
80043ea: 2303 movs r3, #3
80043ec: e138 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
80043ee: 4b46 ldr r3, [pc, #280] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80043f0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80043f4: f003 0302 and.w r3, r3, #2
80043f8: 2b00 cmp r3, #0
80043fa: d0ed beq.n 80043d8 <HAL_RCC_OscConfig+0x388>
80043fc: e015 b.n 800442a <HAL_RCC_OscConfig+0x3da>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80043fe: f7fd fd3f bl 8001e80 <HAL_GetTick>
8004402: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8004404: e00a b.n 800441c <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004406: f7fd fd3b bl 8001e80 <HAL_GetTick>
800440a: 4602 mov r2, r0
800440c: 693b ldr r3, [r7, #16]
800440e: 1ad3 subs r3, r2, r3
8004410: f241 3288 movw r2, #5000 @ 0x1388
8004414: 4293 cmp r3, r2
8004416: d901 bls.n 800441c <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
8004418: 2303 movs r3, #3
800441a: e121 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
800441c: 4b3a ldr r3, [pc, #232] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
800441e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004422: f003 0302 and.w r3, r3, #2
8004426: 2b00 cmp r3, #0
8004428: d1ed bne.n 8004406 <HAL_RCC_OscConfig+0x3b6>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
800442a: 7ffb ldrb r3, [r7, #31]
800442c: 2b01 cmp r3, #1
800442e: d105 bne.n 800443c <HAL_RCC_OscConfig+0x3ec>
{
__HAL_RCC_PWR_CLK_DISABLE();
8004430: 4b35 ldr r3, [pc, #212] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004432: 6d9b ldr r3, [r3, #88] @ 0x58
8004434: 4a34 ldr r2, [pc, #208] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004436: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800443a: 6593 str r3, [r2, #88] @ 0x58
}
}
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
800443c: 687b ldr r3, [r7, #4]
800443e: 681b ldr r3, [r3, #0]
8004440: f003 0320 and.w r3, r3, #32
8004444: 2b00 cmp r3, #0
8004446: d03c beq.n 80044c2 <HAL_RCC_OscConfig+0x472>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
8004448: 687b ldr r3, [r7, #4]
800444a: 699b ldr r3, [r3, #24]
800444c: 2b00 cmp r3, #0
800444e: d01c beq.n 800448a <HAL_RCC_OscConfig+0x43a>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8004450: 4b2d ldr r3, [pc, #180] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004452: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8004456: 4a2c ldr r2, [pc, #176] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004458: f043 0301 orr.w r3, r3, #1
800445c: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004460: f7fd fd0e bl 8001e80 <HAL_GetTick>
8004464: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8004466: e008 b.n 800447a <HAL_RCC_OscConfig+0x42a>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8004468: f7fd fd0a bl 8001e80 <HAL_GetTick>
800446c: 4602 mov r2, r0
800446e: 693b ldr r3, [r7, #16]
8004470: 1ad3 subs r3, r2, r3
8004472: 2b02 cmp r3, #2
8004474: d901 bls.n 800447a <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8004476: 2303 movs r3, #3
8004478: e0f2 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
800447a: 4b23 ldr r3, [pc, #140] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
800447c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8004480: f003 0302 and.w r3, r3, #2
8004484: 2b00 cmp r3, #0
8004486: d0ef beq.n 8004468 <HAL_RCC_OscConfig+0x418>
8004488: e01b b.n 80044c2 <HAL_RCC_OscConfig+0x472>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
800448a: 4b1f ldr r3, [pc, #124] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
800448c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8004490: 4a1d ldr r2, [pc, #116] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
8004492: f023 0301 bic.w r3, r3, #1
8004496: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
800449a: f7fd fcf1 bl 8001e80 <HAL_GetTick>
800449e: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
80044a0: e008 b.n 80044b4 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
80044a2: f7fd fced bl 8001e80 <HAL_GetTick>
80044a6: 4602 mov r2, r0
80044a8: 693b ldr r3, [r7, #16]
80044aa: 1ad3 subs r3, r2, r3
80044ac: 2b02 cmp r3, #2
80044ae: d901 bls.n 80044b4 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
80044b0: 2303 movs r3, #3
80044b2: e0d5 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
80044b4: 4b14 ldr r3, [pc, #80] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80044b6: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
80044ba: f003 0302 and.w r3, r3, #2
80044be: 2b00 cmp r3, #0
80044c0: d1ef bne.n 80044a2 <HAL_RCC_OscConfig+0x452>
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
80044c2: 687b ldr r3, [r7, #4]
80044c4: 69db ldr r3, [r3, #28]
80044c6: 2b00 cmp r3, #0
80044c8: f000 80c9 beq.w 800465e <HAL_RCC_OscConfig+0x60e>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
80044cc: 4b0e ldr r3, [pc, #56] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80044ce: 689b ldr r3, [r3, #8]
80044d0: f003 030c and.w r3, r3, #12
80044d4: 2b0c cmp r3, #12
80044d6: f000 8083 beq.w 80045e0 <HAL_RCC_OscConfig+0x590>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
80044da: 687b ldr r3, [r7, #4]
80044dc: 69db ldr r3, [r3, #28]
80044de: 2b02 cmp r3, #2
80044e0: d15e bne.n 80045a0 <HAL_RCC_OscConfig+0x550>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80044e2: 4b09 ldr r3, [pc, #36] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80044e4: 681b ldr r3, [r3, #0]
80044e6: 4a08 ldr r2, [pc, #32] @ (8004508 <HAL_RCC_OscConfig+0x4b8>)
80044e8: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80044ec: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80044ee: f7fd fcc7 bl 8001e80 <HAL_GetTick>
80044f2: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80044f4: e00c b.n 8004510 <HAL_RCC_OscConfig+0x4c0>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80044f6: f7fd fcc3 bl 8001e80 <HAL_GetTick>
80044fa: 4602 mov r2, r0
80044fc: 693b ldr r3, [r7, #16]
80044fe: 1ad3 subs r3, r2, r3
8004500: 2b02 cmp r3, #2
8004502: d905 bls.n 8004510 <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
8004504: 2303 movs r3, #3
8004506: e0ab b.n 8004660 <HAL_RCC_OscConfig+0x610>
8004508: 40021000 .word 0x40021000
800450c: 40007000 .word 0x40007000
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8004510: 4b55 ldr r3, [pc, #340] @ (8004668 <HAL_RCC_OscConfig+0x618>)
8004512: 681b ldr r3, [r3, #0]
8004514: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004518: 2b00 cmp r3, #0
800451a: d1ec bne.n 80044f6 <HAL_RCC_OscConfig+0x4a6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800451c: 4b52 ldr r3, [pc, #328] @ (8004668 <HAL_RCC_OscConfig+0x618>)
800451e: 68da ldr r2, [r3, #12]
8004520: 4b52 ldr r3, [pc, #328] @ (800466c <HAL_RCC_OscConfig+0x61c>)
8004522: 4013 ands r3, r2
8004524: 687a ldr r2, [r7, #4]
8004526: 6a11 ldr r1, [r2, #32]
8004528: 687a ldr r2, [r7, #4]
800452a: 6a52 ldr r2, [r2, #36] @ 0x24
800452c: 3a01 subs r2, #1
800452e: 0112 lsls r2, r2, #4
8004530: 4311 orrs r1, r2
8004532: 687a ldr r2, [r7, #4]
8004534: 6a92 ldr r2, [r2, #40] @ 0x28
8004536: 0212 lsls r2, r2, #8
8004538: 4311 orrs r1, r2
800453a: 687a ldr r2, [r7, #4]
800453c: 6b12 ldr r2, [r2, #48] @ 0x30
800453e: 0852 lsrs r2, r2, #1
8004540: 3a01 subs r2, #1
8004542: 0552 lsls r2, r2, #21
8004544: 4311 orrs r1, r2
8004546: 687a ldr r2, [r7, #4]
8004548: 6b52 ldr r2, [r2, #52] @ 0x34
800454a: 0852 lsrs r2, r2, #1
800454c: 3a01 subs r2, #1
800454e: 0652 lsls r2, r2, #25
8004550: 4311 orrs r1, r2
8004552: 687a ldr r2, [r7, #4]
8004554: 6ad2 ldr r2, [r2, #44] @ 0x2c
8004556: 06d2 lsls r2, r2, #27
8004558: 430a orrs r2, r1
800455a: 4943 ldr r1, [pc, #268] @ (8004668 <HAL_RCC_OscConfig+0x618>)
800455c: 4313 orrs r3, r2
800455e: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8004560: 4b41 ldr r3, [pc, #260] @ (8004668 <HAL_RCC_OscConfig+0x618>)
8004562: 681b ldr r3, [r3, #0]
8004564: 4a40 ldr r2, [pc, #256] @ (8004668 <HAL_RCC_OscConfig+0x618>)
8004566: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800456a: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
800456c: 4b3e ldr r3, [pc, #248] @ (8004668 <HAL_RCC_OscConfig+0x618>)
800456e: 68db ldr r3, [r3, #12]
8004570: 4a3d ldr r2, [pc, #244] @ (8004668 <HAL_RCC_OscConfig+0x618>)
8004572: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8004576: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004578: f7fd fc82 bl 8001e80 <HAL_GetTick>
800457c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800457e: e008 b.n 8004592 <HAL_RCC_OscConfig+0x542>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8004580: f7fd fc7e bl 8001e80 <HAL_GetTick>
8004584: 4602 mov r2, r0
8004586: 693b ldr r3, [r7, #16]
8004588: 1ad3 subs r3, r2, r3
800458a: 2b02 cmp r3, #2
800458c: d901 bls.n 8004592 <HAL_RCC_OscConfig+0x542>
{
return HAL_TIMEOUT;
800458e: 2303 movs r3, #3
8004590: e066 b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8004592: 4b35 ldr r3, [pc, #212] @ (8004668 <HAL_RCC_OscConfig+0x618>)
8004594: 681b ldr r3, [r3, #0]
8004596: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800459a: 2b00 cmp r3, #0
800459c: d0f0 beq.n 8004580 <HAL_RCC_OscConfig+0x530>
800459e: e05e b.n 800465e <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80045a0: 4b31 ldr r3, [pc, #196] @ (8004668 <HAL_RCC_OscConfig+0x618>)
80045a2: 681b ldr r3, [r3, #0]
80045a4: 4a30 ldr r2, [pc, #192] @ (8004668 <HAL_RCC_OscConfig+0x618>)
80045a6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80045aa: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80045ac: f7fd fc68 bl 8001e80 <HAL_GetTick>
80045b0: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80045b2: e008 b.n 80045c6 <HAL_RCC_OscConfig+0x576>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80045b4: f7fd fc64 bl 8001e80 <HAL_GetTick>
80045b8: 4602 mov r2, r0
80045ba: 693b ldr r3, [r7, #16]
80045bc: 1ad3 subs r3, r2, r3
80045be: 2b02 cmp r3, #2
80045c0: d901 bls.n 80045c6 <HAL_RCC_OscConfig+0x576>
{
return HAL_TIMEOUT;
80045c2: 2303 movs r3, #3
80045c4: e04c b.n 8004660 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80045c6: 4b28 ldr r3, [pc, #160] @ (8004668 <HAL_RCC_OscConfig+0x618>)
80045c8: 681b ldr r3, [r3, #0]
80045ca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80045ce: 2b00 cmp r3, #0
80045d0: d1f0 bne.n 80045b4 <HAL_RCC_OscConfig+0x564>
}
}
/* Unselect PLL clock source and disable outputs to save power */
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
80045d2: 4b25 ldr r3, [pc, #148] @ (8004668 <HAL_RCC_OscConfig+0x618>)
80045d4: 68da ldr r2, [r3, #12]
80045d6: 4924 ldr r1, [pc, #144] @ (8004668 <HAL_RCC_OscConfig+0x618>)
80045d8: 4b25 ldr r3, [pc, #148] @ (8004670 <HAL_RCC_OscConfig+0x620>)
80045da: 4013 ands r3, r2
80045dc: 60cb str r3, [r1, #12]
80045de: e03e b.n 800465e <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80045e0: 687b ldr r3, [r7, #4]
80045e2: 69db ldr r3, [r3, #28]
80045e4: 2b01 cmp r3, #1
80045e6: d101 bne.n 80045ec <HAL_RCC_OscConfig+0x59c>
{
return HAL_ERROR;
80045e8: 2301 movs r3, #1
80045ea: e039 b.n 8004660 <HAL_RCC_OscConfig+0x610>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
80045ec: 4b1e ldr r3, [pc, #120] @ (8004668 <HAL_RCC_OscConfig+0x618>)
80045ee: 68db ldr r3, [r3, #12]
80045f0: 617b str r3, [r7, #20]
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80045f2: 697b ldr r3, [r7, #20]
80045f4: f003 0203 and.w r2, r3, #3
80045f8: 687b ldr r3, [r7, #4]
80045fa: 6a1b ldr r3, [r3, #32]
80045fc: 429a cmp r2, r3
80045fe: d12c bne.n 800465a <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8004600: 697b ldr r3, [r7, #20]
8004602: f003 02f0 and.w r2, r3, #240 @ 0xf0
8004606: 687b ldr r3, [r7, #4]
8004608: 6a5b ldr r3, [r3, #36] @ 0x24
800460a: 3b01 subs r3, #1
800460c: 011b lsls r3, r3, #4
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800460e: 429a cmp r2, r3
8004610: d123 bne.n 800465a <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8004612: 697b ldr r3, [r7, #20]
8004614: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8004618: 687b ldr r3, [r7, #4]
800461a: 6a9b ldr r3, [r3, #40] @ 0x28
800461c: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
800461e: 429a cmp r2, r3
8004620: d11b bne.n 800465a <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8004622: 697b ldr r3, [r7, #20]
8004624: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000
8004628: 687b ldr r3, [r7, #4]
800462a: 6adb ldr r3, [r3, #44] @ 0x2c
800462c: 06db lsls r3, r3, #27
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
800462e: 429a cmp r2, r3
8004630: d113 bne.n 800465a <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8004632: 697b ldr r3, [r7, #20]
8004634: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
8004638: 687b ldr r3, [r7, #4]
800463a: 6b1b ldr r3, [r3, #48] @ 0x30
800463c: 085b lsrs r3, r3, #1
800463e: 3b01 subs r3, #1
8004640: 055b lsls r3, r3, #21
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8004642: 429a cmp r2, r3
8004644: d109 bne.n 800465a <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8004646: 697b ldr r3, [r7, #20]
8004648: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
800464c: 687b ldr r3, [r7, #4]
800464e: 6b5b ldr r3, [r3, #52] @ 0x34
8004650: 085b lsrs r3, r3, #1
8004652: 3b01 subs r3, #1
8004654: 065b lsls r3, r3, #25
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8004656: 429a cmp r2, r3
8004658: d001 beq.n 800465e <HAL_RCC_OscConfig+0x60e>
{
return HAL_ERROR;
800465a: 2301 movs r3, #1
800465c: e000 b.n 8004660 <HAL_RCC_OscConfig+0x610>
}
}
}
}
return HAL_OK;
800465e: 2300 movs r3, #0
}
8004660: 4618 mov r0, r3
8004662: 3720 adds r7, #32
8004664: 46bd mov sp, r7
8004666: bd80 pop {r7, pc}
8004668: 40021000 .word 0x40021000
800466c: 019f800c .word 0x019f800c
8004670: feeefffc .word 0xfeeefffc
08004674 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8004674: b580 push {r7, lr}
8004676: b086 sub sp, #24
8004678: af00 add r7, sp, #0
800467a: 6078 str r0, [r7, #4]
800467c: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t pllfreq;
uint32_t hpre = RCC_SYSCLK_DIV1;
800467e: 2300 movs r3, #0
8004680: 617b str r3, [r7, #20]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8004682: 687b ldr r3, [r7, #4]
8004684: 2b00 cmp r3, #0
8004686: d101 bne.n 800468c <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8004688: 2301 movs r3, #1
800468a: e11e b.n 80048ca <HAL_RCC_ClockConfig+0x256>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800468c: 4b91 ldr r3, [pc, #580] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
800468e: 681b ldr r3, [r3, #0]
8004690: f003 030f and.w r3, r3, #15
8004694: 683a ldr r2, [r7, #0]
8004696: 429a cmp r2, r3
8004698: d910 bls.n 80046bc <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800469a: 4b8e ldr r3, [pc, #568] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
800469c: 681b ldr r3, [r3, #0]
800469e: f023 020f bic.w r2, r3, #15
80046a2: 498c ldr r1, [pc, #560] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
80046a4: 683b ldr r3, [r7, #0]
80046a6: 4313 orrs r3, r2
80046a8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80046aa: 4b8a ldr r3, [pc, #552] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
80046ac: 681b ldr r3, [r3, #0]
80046ae: f003 030f and.w r3, r3, #15
80046b2: 683a ldr r2, [r7, #0]
80046b4: 429a cmp r2, r3
80046b6: d001 beq.n 80046bc <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
80046b8: 2301 movs r3, #1
80046ba: e106 b.n 80048ca <HAL_RCC_ClockConfig+0x256>
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80046bc: 687b ldr r3, [r7, #4]
80046be: 681b ldr r3, [r3, #0]
80046c0: f003 0301 and.w r3, r3, #1
80046c4: 2b00 cmp r3, #0
80046c6: d073 beq.n 80047b0 <HAL_RCC_ClockConfig+0x13c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80046c8: 687b ldr r3, [r7, #4]
80046ca: 685b ldr r3, [r3, #4]
80046cc: 2b03 cmp r3, #3
80046ce: d129 bne.n 8004724 <HAL_RCC_ClockConfig+0xb0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80046d0: 4b81 ldr r3, [pc, #516] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80046d2: 681b ldr r3, [r3, #0]
80046d4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80046d8: 2b00 cmp r3, #0
80046da: d101 bne.n 80046e0 <HAL_RCC_ClockConfig+0x6c>
{
return HAL_ERROR;
80046dc: 2301 movs r3, #1
80046de: e0f4 b.n 80048ca <HAL_RCC_ClockConfig+0x256>
}
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
/* Compute target PLL output frequency */
pllfreq = RCC_GetSysClockFreqFromPLLSource();
80046e0: f000 f99e bl 8004a20 <RCC_GetSysClockFreqFromPLLSource>
80046e4: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
if(pllfreq > 80000000U)
80046e6: 693b ldr r3, [r7, #16]
80046e8: 4a7c ldr r2, [pc, #496] @ (80048dc <HAL_RCC_ClockConfig+0x268>)
80046ea: 4293 cmp r3, r2
80046ec: d93f bls.n 800476e <HAL_RCC_ClockConfig+0xfa>
{
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
80046ee: 4b7a ldr r3, [pc, #488] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80046f0: 689b ldr r3, [r3, #8]
80046f2: f003 03f0 and.w r3, r3, #240 @ 0xf0
80046f6: 2b00 cmp r3, #0
80046f8: d009 beq.n 800470e <HAL_RCC_ClockConfig+0x9a>
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
80046fa: 687b ldr r3, [r7, #4]
80046fc: 681b ldr r3, [r3, #0]
80046fe: f003 0302 and.w r3, r3, #2
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8004702: 2b00 cmp r3, #0
8004704: d033 beq.n 800476e <HAL_RCC_ClockConfig+0xfa>
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
8004706: 687b ldr r3, [r7, #4]
8004708: 689b ldr r3, [r3, #8]
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
800470a: 2b00 cmp r3, #0
800470c: d12f bne.n 800476e <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
800470e: 4b72 ldr r3, [pc, #456] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
8004710: 689b ldr r3, [r3, #8]
8004712: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8004716: 4a70 ldr r2, [pc, #448] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
8004718: f043 0380 orr.w r3, r3, #128 @ 0x80
800471c: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
800471e: 2380 movs r3, #128 @ 0x80
8004720: 617b str r3, [r7, #20]
8004722: e024 b.n 800476e <HAL_RCC_ClockConfig+0xfa>
}
}
else
{
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8004724: 687b ldr r3, [r7, #4]
8004726: 685b ldr r3, [r3, #4]
8004728: 2b02 cmp r3, #2
800472a: d107 bne.n 800473c <HAL_RCC_ClockConfig+0xc8>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800472c: 4b6a ldr r3, [pc, #424] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800472e: 681b ldr r3, [r3, #0]
8004730: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004734: 2b00 cmp r3, #0
8004736: d109 bne.n 800474c <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8004738: 2301 movs r3, #1
800473a: e0c6 b.n 80048ca <HAL_RCC_ClockConfig+0x256>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800473c: 4b66 ldr r3, [pc, #408] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800473e: 681b ldr r3, [r3, #0]
8004740: f403 6380 and.w r3, r3, #1024 @ 0x400
8004744: 2b00 cmp r3, #0
8004746: d101 bne.n 800474c <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8004748: 2301 movs r3, #1
800474a: e0be b.n 80048ca <HAL_RCC_ClockConfig+0x256>
}
}
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
pllfreq = HAL_RCC_GetSysClockFreq();
800474c: f000 f8ce bl 80048ec <HAL_RCC_GetSysClockFreq>
8004750: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
if(pllfreq > 80000000U)
8004752: 693b ldr r3, [r7, #16]
8004754: 4a61 ldr r2, [pc, #388] @ (80048dc <HAL_RCC_ClockConfig+0x268>)
8004756: 4293 cmp r3, r2
8004758: d909 bls.n 800476e <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
800475a: 4b5f ldr r3, [pc, #380] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800475c: 689b ldr r3, [r3, #8]
800475e: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8004762: 4a5d ldr r2, [pc, #372] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
8004764: f043 0380 orr.w r3, r3, #128 @ 0x80
8004768: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
800476a: 2380 movs r3, #128 @ 0x80
800476c: 617b str r3, [r7, #20]
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
800476e: 4b5a ldr r3, [pc, #360] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
8004770: 689b ldr r3, [r3, #8]
8004772: f023 0203 bic.w r2, r3, #3
8004776: 687b ldr r3, [r7, #4]
8004778: 685b ldr r3, [r3, #4]
800477a: 4957 ldr r1, [pc, #348] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800477c: 4313 orrs r3, r2
800477e: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004780: f7fd fb7e bl 8001e80 <HAL_GetTick>
8004784: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004786: e00a b.n 800479e <HAL_RCC_ClockConfig+0x12a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004788: f7fd fb7a bl 8001e80 <HAL_GetTick>
800478c: 4602 mov r2, r0
800478e: 68fb ldr r3, [r7, #12]
8004790: 1ad3 subs r3, r2, r3
8004792: f241 3288 movw r2, #5000 @ 0x1388
8004796: 4293 cmp r3, r2
8004798: d901 bls.n 800479e <HAL_RCC_ClockConfig+0x12a>
{
return HAL_TIMEOUT;
800479a: 2303 movs r3, #3
800479c: e095 b.n 80048ca <HAL_RCC_ClockConfig+0x256>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800479e: 4b4e ldr r3, [pc, #312] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80047a0: 689b ldr r3, [r3, #8]
80047a2: f003 020c and.w r2, r3, #12
80047a6: 687b ldr r3, [r7, #4]
80047a8: 685b ldr r3, [r3, #4]
80047aa: 009b lsls r3, r3, #2
80047ac: 429a cmp r2, r3
80047ae: d1eb bne.n 8004788 <HAL_RCC_ClockConfig+0x114>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80047b0: 687b ldr r3, [r7, #4]
80047b2: 681b ldr r3, [r3, #0]
80047b4: f003 0302 and.w r3, r3, #2
80047b8: 2b00 cmp r3, #0
80047ba: d023 beq.n 8004804 <HAL_RCC_ClockConfig+0x190>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80047bc: 687b ldr r3, [r7, #4]
80047be: 681b ldr r3, [r3, #0]
80047c0: f003 0304 and.w r3, r3, #4
80047c4: 2b00 cmp r3, #0
80047c6: d005 beq.n 80047d4 <HAL_RCC_ClockConfig+0x160>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80047c8: 4b43 ldr r3, [pc, #268] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80047ca: 689b ldr r3, [r3, #8]
80047cc: 4a42 ldr r2, [pc, #264] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80047ce: f443 63e0 orr.w r3, r3, #1792 @ 0x700
80047d2: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80047d4: 687b ldr r3, [r7, #4]
80047d6: 681b ldr r3, [r3, #0]
80047d8: f003 0308 and.w r3, r3, #8
80047dc: 2b00 cmp r3, #0
80047de: d007 beq.n 80047f0 <HAL_RCC_ClockConfig+0x17c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
80047e0: 4b3d ldr r3, [pc, #244] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80047e2: 689b ldr r3, [r3, #8]
80047e4: f423 537c bic.w r3, r3, #16128 @ 0x3f00
80047e8: 4a3b ldr r2, [pc, #236] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80047ea: f443 63e0 orr.w r3, r3, #1792 @ 0x700
80047ee: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80047f0: 4b39 ldr r3, [pc, #228] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80047f2: 689b ldr r3, [r3, #8]
80047f4: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80047f8: 687b ldr r3, [r7, #4]
80047fa: 689b ldr r3, [r3, #8]
80047fc: 4936 ldr r1, [pc, #216] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80047fe: 4313 orrs r3, r2
8004800: 608b str r3, [r1, #8]
8004802: e008 b.n 8004816 <HAL_RCC_ClockConfig+0x1a2>
}
else
{
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
8004804: 697b ldr r3, [r7, #20]
8004806: 2b80 cmp r3, #128 @ 0x80
8004808: d105 bne.n 8004816 <HAL_RCC_ClockConfig+0x1a2>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
800480a: 4b33 ldr r3, [pc, #204] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800480c: 689b ldr r3, [r3, #8]
800480e: 4a32 ldr r2, [pc, #200] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
8004810: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8004814: 6093 str r3, [r2, #8]
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8004816: 4b2f ldr r3, [pc, #188] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
8004818: 681b ldr r3, [r3, #0]
800481a: f003 030f and.w r3, r3, #15
800481e: 683a ldr r2, [r7, #0]
8004820: 429a cmp r2, r3
8004822: d21d bcs.n 8004860 <HAL_RCC_ClockConfig+0x1ec>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004824: 4b2b ldr r3, [pc, #172] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
8004826: 681b ldr r3, [r3, #0]
8004828: f023 020f bic.w r2, r3, #15
800482c: 4929 ldr r1, [pc, #164] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
800482e: 683b ldr r3, [r7, #0]
8004830: 4313 orrs r3, r2
8004832: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8004834: f7fd fb24 bl 8001e80 <HAL_GetTick>
8004838: 60f8 str r0, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
800483a: e00a b.n 8004852 <HAL_RCC_ClockConfig+0x1de>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800483c: f7fd fb20 bl 8001e80 <HAL_GetTick>
8004840: 4602 mov r2, r0
8004842: 68fb ldr r3, [r7, #12]
8004844: 1ad3 subs r3, r2, r3
8004846: f241 3288 movw r2, #5000 @ 0x1388
800484a: 4293 cmp r3, r2
800484c: d901 bls.n 8004852 <HAL_RCC_ClockConfig+0x1de>
{
return HAL_TIMEOUT;
800484e: 2303 movs r3, #3
8004850: e03b b.n 80048ca <HAL_RCC_ClockConfig+0x256>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8004852: 4b20 ldr r3, [pc, #128] @ (80048d4 <HAL_RCC_ClockConfig+0x260>)
8004854: 681b ldr r3, [r3, #0]
8004856: f003 030f and.w r3, r3, #15
800485a: 683a ldr r2, [r7, #0]
800485c: 429a cmp r2, r3
800485e: d1ed bne.n 800483c <HAL_RCC_ClockConfig+0x1c8>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004860: 687b ldr r3, [r7, #4]
8004862: 681b ldr r3, [r3, #0]
8004864: f003 0304 and.w r3, r3, #4
8004868: 2b00 cmp r3, #0
800486a: d008 beq.n 800487e <HAL_RCC_ClockConfig+0x20a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
800486c: 4b1a ldr r3, [pc, #104] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800486e: 689b ldr r3, [r3, #8]
8004870: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8004874: 687b ldr r3, [r7, #4]
8004876: 68db ldr r3, [r3, #12]
8004878: 4917 ldr r1, [pc, #92] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800487a: 4313 orrs r3, r2
800487c: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800487e: 687b ldr r3, [r7, #4]
8004880: 681b ldr r3, [r3, #0]
8004882: f003 0308 and.w r3, r3, #8
8004886: 2b00 cmp r3, #0
8004888: d009 beq.n 800489e <HAL_RCC_ClockConfig+0x22a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
800488a: 4b13 ldr r3, [pc, #76] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800488c: 689b ldr r3, [r3, #8]
800488e: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8004892: 687b ldr r3, [r7, #4]
8004894: 691b ldr r3, [r3, #16]
8004896: 00db lsls r3, r3, #3
8004898: 490f ldr r1, [pc, #60] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
800489a: 4313 orrs r3, r2
800489c: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
800489e: f000 f825 bl 80048ec <HAL_RCC_GetSysClockFreq>
80048a2: 4602 mov r2, r0
80048a4: 4b0c ldr r3, [pc, #48] @ (80048d8 <HAL_RCC_ClockConfig+0x264>)
80048a6: 689b ldr r3, [r3, #8]
80048a8: 091b lsrs r3, r3, #4
80048aa: f003 030f and.w r3, r3, #15
80048ae: 490c ldr r1, [pc, #48] @ (80048e0 <HAL_RCC_ClockConfig+0x26c>)
80048b0: 5ccb ldrb r3, [r1, r3]
80048b2: f003 031f and.w r3, r3, #31
80048b6: fa22 f303 lsr.w r3, r2, r3
80048ba: 4a0a ldr r2, [pc, #40] @ (80048e4 <HAL_RCC_ClockConfig+0x270>)
80048bc: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
80048be: 4b0a ldr r3, [pc, #40] @ (80048e8 <HAL_RCC_ClockConfig+0x274>)
80048c0: 681b ldr r3, [r3, #0]
80048c2: 4618 mov r0, r3
80048c4: f7fd fa90 bl 8001de8 <HAL_InitTick>
80048c8: 4603 mov r3, r0
}
80048ca: 4618 mov r0, r3
80048cc: 3718 adds r7, #24
80048ce: 46bd mov sp, r7
80048d0: bd80 pop {r7, pc}
80048d2: bf00 nop
80048d4: 40022000 .word 0x40022000
80048d8: 40021000 .word 0x40021000
80048dc: 04c4b400 .word 0x04c4b400
80048e0: 080086fc .word 0x080086fc
80048e4: 2000001c .word 0x2000001c
80048e8: 20000020 .word 0x20000020
080048ec <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80048ec: b480 push {r7}
80048ee: b087 sub sp, #28
80048f0: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
80048f2: 4b2c ldr r3, [pc, #176] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
80048f4: 689b ldr r3, [r3, #8]
80048f6: f003 030c and.w r3, r3, #12
80048fa: 2b04 cmp r3, #4
80048fc: d102 bne.n 8004904 <HAL_RCC_GetSysClockFreq+0x18>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
80048fe: 4b2a ldr r3, [pc, #168] @ (80049a8 <HAL_RCC_GetSysClockFreq+0xbc>)
8004900: 613b str r3, [r7, #16]
8004902: e047 b.n 8004994 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
8004904: 4b27 ldr r3, [pc, #156] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
8004906: 689b ldr r3, [r3, #8]
8004908: f003 030c and.w r3, r3, #12
800490c: 2b08 cmp r3, #8
800490e: d102 bne.n 8004916 <HAL_RCC_GetSysClockFreq+0x2a>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8004910: 4b26 ldr r3, [pc, #152] @ (80049ac <HAL_RCC_GetSysClockFreq+0xc0>)
8004912: 613b str r3, [r7, #16]
8004914: e03e b.n 8004994 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
8004916: 4b23 ldr r3, [pc, #140] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
8004918: 689b ldr r3, [r3, #8]
800491a: f003 030c and.w r3, r3, #12
800491e: 2b0c cmp r3, #12
8004920: d136 bne.n 8004990 <HAL_RCC_GetSysClockFreq+0xa4>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8004922: 4b20 ldr r3, [pc, #128] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
8004924: 68db ldr r3, [r3, #12]
8004926: f003 0303 and.w r3, r3, #3
800492a: 60fb str r3, [r7, #12]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
800492c: 4b1d ldr r3, [pc, #116] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
800492e: 68db ldr r3, [r3, #12]
8004930: 091b lsrs r3, r3, #4
8004932: f003 030f and.w r3, r3, #15
8004936: 3301 adds r3, #1
8004938: 60bb str r3, [r7, #8]
switch (pllsource)
800493a: 68fb ldr r3, [r7, #12]
800493c: 2b03 cmp r3, #3
800493e: d10c bne.n 800495a <HAL_RCC_GetSysClockFreq+0x6e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8004940: 4a1a ldr r2, [pc, #104] @ (80049ac <HAL_RCC_GetSysClockFreq+0xc0>)
8004942: 68bb ldr r3, [r7, #8]
8004944: fbb2 f3f3 udiv r3, r2, r3
8004948: 4a16 ldr r2, [pc, #88] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
800494a: 68d2 ldr r2, [r2, #12]
800494c: 0a12 lsrs r2, r2, #8
800494e: f002 027f and.w r2, r2, #127 @ 0x7f
8004952: fb02 f303 mul.w r3, r2, r3
8004956: 617b str r3, [r7, #20]
break;
8004958: e00c b.n 8004974 <HAL_RCC_GetSysClockFreq+0x88>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
800495a: 4a13 ldr r2, [pc, #76] @ (80049a8 <HAL_RCC_GetSysClockFreq+0xbc>)
800495c: 68bb ldr r3, [r7, #8]
800495e: fbb2 f3f3 udiv r3, r2, r3
8004962: 4a10 ldr r2, [pc, #64] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
8004964: 68d2 ldr r2, [r2, #12]
8004966: 0a12 lsrs r2, r2, #8
8004968: f002 027f and.w r2, r2, #127 @ 0x7f
800496c: fb02 f303 mul.w r3, r2, r3
8004970: 617b str r3, [r7, #20]
break;
8004972: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8004974: 4b0b ldr r3, [pc, #44] @ (80049a4 <HAL_RCC_GetSysClockFreq+0xb8>)
8004976: 68db ldr r3, [r3, #12]
8004978: 0e5b lsrs r3, r3, #25
800497a: f003 0303 and.w r3, r3, #3
800497e: 3301 adds r3, #1
8004980: 005b lsls r3, r3, #1
8004982: 607b str r3, [r7, #4]
sysclockfreq = pllvco/pllr;
8004984: 697a ldr r2, [r7, #20]
8004986: 687b ldr r3, [r7, #4]
8004988: fbb2 f3f3 udiv r3, r2, r3
800498c: 613b str r3, [r7, #16]
800498e: e001 b.n 8004994 <HAL_RCC_GetSysClockFreq+0xa8>
}
else
{
sysclockfreq = 0U;
8004990: 2300 movs r3, #0
8004992: 613b str r3, [r7, #16]
}
return sysclockfreq;
8004994: 693b ldr r3, [r7, #16]
}
8004996: 4618 mov r0, r3
8004998: 371c adds r7, #28
800499a: 46bd mov sp, r7
800499c: f85d 7b04 ldr.w r7, [sp], #4
80049a0: 4770 bx lr
80049a2: bf00 nop
80049a4: 40021000 .word 0x40021000
80049a8: 00f42400 .word 0x00f42400
80049ac: 007a1200 .word 0x007a1200
080049b0 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80049b0: b480 push {r7}
80049b2: af00 add r7, sp, #0
return SystemCoreClock;
80049b4: 4b03 ldr r3, [pc, #12] @ (80049c4 <HAL_RCC_GetHCLKFreq+0x14>)
80049b6: 681b ldr r3, [r3, #0]
}
80049b8: 4618 mov r0, r3
80049ba: 46bd mov sp, r7
80049bc: f85d 7b04 ldr.w r7, [sp], #4
80049c0: 4770 bx lr
80049c2: bf00 nop
80049c4: 2000001c .word 0x2000001c
080049c8 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
80049c8: b580 push {r7, lr}
80049ca: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
80049cc: f7ff fff0 bl 80049b0 <HAL_RCC_GetHCLKFreq>
80049d0: 4602 mov r2, r0
80049d2: 4b06 ldr r3, [pc, #24] @ (80049ec <HAL_RCC_GetPCLK1Freq+0x24>)
80049d4: 689b ldr r3, [r3, #8]
80049d6: 0a1b lsrs r3, r3, #8
80049d8: f003 0307 and.w r3, r3, #7
80049dc: 4904 ldr r1, [pc, #16] @ (80049f0 <HAL_RCC_GetPCLK1Freq+0x28>)
80049de: 5ccb ldrb r3, [r1, r3]
80049e0: f003 031f and.w r3, r3, #31
80049e4: fa22 f303 lsr.w r3, r2, r3
}
80049e8: 4618 mov r0, r3
80049ea: bd80 pop {r7, pc}
80049ec: 40021000 .word 0x40021000
80049f0: 0800870c .word 0x0800870c
080049f4 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
80049f4: b580 push {r7, lr}
80049f6: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
80049f8: f7ff ffda bl 80049b0 <HAL_RCC_GetHCLKFreq>
80049fc: 4602 mov r2, r0
80049fe: 4b06 ldr r3, [pc, #24] @ (8004a18 <HAL_RCC_GetPCLK2Freq+0x24>)
8004a00: 689b ldr r3, [r3, #8]
8004a02: 0adb lsrs r3, r3, #11
8004a04: f003 0307 and.w r3, r3, #7
8004a08: 4904 ldr r1, [pc, #16] @ (8004a1c <HAL_RCC_GetPCLK2Freq+0x28>)
8004a0a: 5ccb ldrb r3, [r1, r3]
8004a0c: f003 031f and.w r3, r3, #31
8004a10: fa22 f303 lsr.w r3, r2, r3
}
8004a14: 4618 mov r0, r3
8004a16: bd80 pop {r7, pc}
8004a18: 40021000 .word 0x40021000
8004a1c: 0800870c .word 0x0800870c
08004a20 <RCC_GetSysClockFreqFromPLLSource>:
/**
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
* @retval SYSCLK frequency
*/
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
{
8004a20: b480 push {r7}
8004a22: b087 sub sp, #28
8004a24: af00 add r7, sp, #0
uint32_t sysclockfreq;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8004a26: 4b1e ldr r3, [pc, #120] @ (8004aa0 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8004a28: 68db ldr r3, [r3, #12]
8004a2a: f003 0303 and.w r3, r3, #3
8004a2e: 613b str r3, [r7, #16]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8004a30: 4b1b ldr r3, [pc, #108] @ (8004aa0 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8004a32: 68db ldr r3, [r3, #12]
8004a34: 091b lsrs r3, r3, #4
8004a36: f003 030f and.w r3, r3, #15
8004a3a: 3301 adds r3, #1
8004a3c: 60fb str r3, [r7, #12]
switch (pllsource)
8004a3e: 693b ldr r3, [r7, #16]
8004a40: 2b03 cmp r3, #3
8004a42: d10c bne.n 8004a5e <RCC_GetSysClockFreqFromPLLSource+0x3e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8004a44: 4a17 ldr r2, [pc, #92] @ (8004aa4 <RCC_GetSysClockFreqFromPLLSource+0x84>)
8004a46: 68fb ldr r3, [r7, #12]
8004a48: fbb2 f3f3 udiv r3, r2, r3
8004a4c: 4a14 ldr r2, [pc, #80] @ (8004aa0 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8004a4e: 68d2 ldr r2, [r2, #12]
8004a50: 0a12 lsrs r2, r2, #8
8004a52: f002 027f and.w r2, r2, #127 @ 0x7f
8004a56: fb02 f303 mul.w r3, r2, r3
8004a5a: 617b str r3, [r7, #20]
break;
8004a5c: e00c b.n 8004a78 <RCC_GetSysClockFreqFromPLLSource+0x58>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8004a5e: 4a12 ldr r2, [pc, #72] @ (8004aa8 <RCC_GetSysClockFreqFromPLLSource+0x88>)
8004a60: 68fb ldr r3, [r7, #12]
8004a62: fbb2 f3f3 udiv r3, r2, r3
8004a66: 4a0e ldr r2, [pc, #56] @ (8004aa0 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8004a68: 68d2 ldr r2, [r2, #12]
8004a6a: 0a12 lsrs r2, r2, #8
8004a6c: f002 027f and.w r2, r2, #127 @ 0x7f
8004a70: fb02 f303 mul.w r3, r2, r3
8004a74: 617b str r3, [r7, #20]
break;
8004a76: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8004a78: 4b09 ldr r3, [pc, #36] @ (8004aa0 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8004a7a: 68db ldr r3, [r3, #12]
8004a7c: 0e5b lsrs r3, r3, #25
8004a7e: f003 0303 and.w r3, r3, #3
8004a82: 3301 adds r3, #1
8004a84: 005b lsls r3, r3, #1
8004a86: 60bb str r3, [r7, #8]
sysclockfreq = pllvco/pllr;
8004a88: 697a ldr r2, [r7, #20]
8004a8a: 68bb ldr r3, [r7, #8]
8004a8c: fbb2 f3f3 udiv r3, r2, r3
8004a90: 607b str r3, [r7, #4]
return sysclockfreq;
8004a92: 687b ldr r3, [r7, #4]
}
8004a94: 4618 mov r0, r3
8004a96: 371c adds r7, #28
8004a98: 46bd mov sp, r7
8004a9a: f85d 7b04 ldr.w r7, [sp], #4
8004a9e: 4770 bx lr
8004aa0: 40021000 .word 0x40021000
8004aa4: 007a1200 .word 0x007a1200
8004aa8: 00f42400 .word 0x00f42400
08004aac <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8004aac: b580 push {r7, lr}
8004aae: b086 sub sp, #24
8004ab0: af00 add r7, sp, #0
8004ab2: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8004ab4: 2300 movs r3, #0
8004ab6: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8004ab8: 2300 movs r3, #0
8004aba: 74bb strb r3, [r7, #18]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8004abc: 687b ldr r3, [r7, #4]
8004abe: 681b ldr r3, [r3, #0]
8004ac0: f403 2300 and.w r3, r3, #524288 @ 0x80000
8004ac4: 2b00 cmp r3, #0
8004ac6: f000 8098 beq.w 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
FlagStatus pwrclkchanged = RESET;
8004aca: 2300 movs r3, #0
8004acc: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8004ace: 4b43 ldr r3, [pc, #268] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004ad0: 6d9b ldr r3, [r3, #88] @ 0x58
8004ad2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004ad6: 2b00 cmp r3, #0
8004ad8: d10d bne.n 8004af6 <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004ada: 4b40 ldr r3, [pc, #256] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004adc: 6d9b ldr r3, [r3, #88] @ 0x58
8004ade: 4a3f ldr r2, [pc, #252] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004ae0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004ae4: 6593 str r3, [r2, #88] @ 0x58
8004ae6: 4b3d ldr r3, [pc, #244] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004ae8: 6d9b ldr r3, [r3, #88] @ 0x58
8004aea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004aee: 60bb str r3, [r7, #8]
8004af0: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8004af2: 2301 movs r3, #1
8004af4: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8004af6: 4b3a ldr r3, [pc, #232] @ (8004be0 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004af8: 681b ldr r3, [r3, #0]
8004afa: 4a39 ldr r2, [pc, #228] @ (8004be0 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004afc: f443 7380 orr.w r3, r3, #256 @ 0x100
8004b00: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004b02: f7fd f9bd bl 8001e80 <HAL_GetTick>
8004b06: 60f8 str r0, [r7, #12]
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8004b08: e009 b.n 8004b1e <HAL_RCCEx_PeriphCLKConfig+0x72>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004b0a: f7fd f9b9 bl 8001e80 <HAL_GetTick>
8004b0e: 4602 mov r2, r0
8004b10: 68fb ldr r3, [r7, #12]
8004b12: 1ad3 subs r3, r2, r3
8004b14: 2b02 cmp r3, #2
8004b16: d902 bls.n 8004b1e <HAL_RCCEx_PeriphCLKConfig+0x72>
{
ret = HAL_TIMEOUT;
8004b18: 2303 movs r3, #3
8004b1a: 74fb strb r3, [r7, #19]
break;
8004b1c: e005 b.n 8004b2a <HAL_RCCEx_PeriphCLKConfig+0x7e>
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8004b1e: 4b30 ldr r3, [pc, #192] @ (8004be0 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004b20: 681b ldr r3, [r3, #0]
8004b22: f403 7380 and.w r3, r3, #256 @ 0x100
8004b26: 2b00 cmp r3, #0
8004b28: d0ef beq.n 8004b0a <HAL_RCCEx_PeriphCLKConfig+0x5e>
}
}
if(ret == HAL_OK)
8004b2a: 7cfb ldrb r3, [r7, #19]
8004b2c: 2b00 cmp r3, #0
8004b2e: d159 bne.n 8004be4 <HAL_RCCEx_PeriphCLKConfig+0x138>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8004b30: 4b2a ldr r3, [pc, #168] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b32: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004b36: f403 7340 and.w r3, r3, #768 @ 0x300
8004b3a: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8004b3c: 697b ldr r3, [r7, #20]
8004b3e: 2b00 cmp r3, #0
8004b40: d01e beq.n 8004b80 <HAL_RCCEx_PeriphCLKConfig+0xd4>
8004b42: 687b ldr r3, [r7, #4]
8004b44: 6c1b ldr r3, [r3, #64] @ 0x40
8004b46: 697a ldr r2, [r7, #20]
8004b48: 429a cmp r2, r3
8004b4a: d019 beq.n 8004b80 <HAL_RCCEx_PeriphCLKConfig+0xd4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8004b4c: 4b23 ldr r3, [pc, #140] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b4e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004b52: f423 7340 bic.w r3, r3, #768 @ 0x300
8004b56: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8004b58: 4b20 ldr r3, [pc, #128] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b5a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004b5e: 4a1f ldr r2, [pc, #124] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b60: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004b64: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8004b68: 4b1c ldr r3, [pc, #112] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b6a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004b6e: 4a1b ldr r2, [pc, #108] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b70: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004b74: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8004b78: 4a18 ldr r2, [pc, #96] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b7a: 697b ldr r3, [r7, #20]
8004b7c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8004b80: 697b ldr r3, [r7, #20]
8004b82: f003 0301 and.w r3, r3, #1
8004b86: 2b00 cmp r3, #0
8004b88: d016 beq.n 8004bb8 <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004b8a: f7fd f979 bl 8001e80 <HAL_GetTick>
8004b8e: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004b90: e00b b.n 8004baa <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004b92: f7fd f975 bl 8001e80 <HAL_GetTick>
8004b96: 4602 mov r2, r0
8004b98: 68fb ldr r3, [r7, #12]
8004b9a: 1ad3 subs r3, r2, r3
8004b9c: f241 3288 movw r2, #5000 @ 0x1388
8004ba0: 4293 cmp r3, r2
8004ba2: d902 bls.n 8004baa <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
ret = HAL_TIMEOUT;
8004ba4: 2303 movs r3, #3
8004ba6: 74fb strb r3, [r7, #19]
break;
8004ba8: e006 b.n 8004bb8 <HAL_RCCEx_PeriphCLKConfig+0x10c>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004baa: 4b0c ldr r3, [pc, #48] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004bac: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004bb0: f003 0302 and.w r3, r3, #2
8004bb4: 2b00 cmp r3, #0
8004bb6: d0ec beq.n 8004b92 <HAL_RCCEx_PeriphCLKConfig+0xe6>
}
}
}
if(ret == HAL_OK)
8004bb8: 7cfb ldrb r3, [r7, #19]
8004bba: 2b00 cmp r3, #0
8004bbc: d10b bne.n 8004bd6 <HAL_RCCEx_PeriphCLKConfig+0x12a>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8004bbe: 4b07 ldr r3, [pc, #28] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004bc0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004bc4: f423 7240 bic.w r2, r3, #768 @ 0x300
8004bc8: 687b ldr r3, [r7, #4]
8004bca: 6c1b ldr r3, [r3, #64] @ 0x40
8004bcc: 4903 ldr r1, [pc, #12] @ (8004bdc <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004bce: 4313 orrs r3, r2
8004bd0: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8004bd4: e008 b.n 8004be8 <HAL_RCCEx_PeriphCLKConfig+0x13c>
}
else
{
/* set overall return value */
status = ret;
8004bd6: 7cfb ldrb r3, [r7, #19]
8004bd8: 74bb strb r3, [r7, #18]
8004bda: e005 b.n 8004be8 <HAL_RCCEx_PeriphCLKConfig+0x13c>
8004bdc: 40021000 .word 0x40021000
8004be0: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8004be4: 7cfb ldrb r3, [r7, #19]
8004be6: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8004be8: 7c7b ldrb r3, [r7, #17]
8004bea: 2b01 cmp r3, #1
8004bec: d105 bne.n 8004bfa <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8004bee: 4ba6 ldr r3, [pc, #664] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004bf0: 6d9b ldr r3, [r3, #88] @ 0x58
8004bf2: 4aa5 ldr r2, [pc, #660] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004bf4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8004bf8: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8004bfa: 687b ldr r3, [r7, #4]
8004bfc: 681b ldr r3, [r3, #0]
8004bfe: f003 0301 and.w r3, r3, #1
8004c02: 2b00 cmp r3, #0
8004c04: d00a beq.n 8004c1c <HAL_RCCEx_PeriphCLKConfig+0x170>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8004c06: 4ba0 ldr r3, [pc, #640] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c08: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c0c: f023 0203 bic.w r2, r3, #3
8004c10: 687b ldr r3, [r7, #4]
8004c12: 685b ldr r3, [r3, #4]
8004c14: 499c ldr r1, [pc, #624] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c16: 4313 orrs r3, r2
8004c18: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8004c1c: 687b ldr r3, [r7, #4]
8004c1e: 681b ldr r3, [r3, #0]
8004c20: f003 0302 and.w r3, r3, #2
8004c24: 2b00 cmp r3, #0
8004c26: d00a beq.n 8004c3e <HAL_RCCEx_PeriphCLKConfig+0x192>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8004c28: 4b97 ldr r3, [pc, #604] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c2a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c2e: f023 020c bic.w r2, r3, #12
8004c32: 687b ldr r3, [r7, #4]
8004c34: 689b ldr r3, [r3, #8]
8004c36: 4994 ldr r1, [pc, #592] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c38: 4313 orrs r3, r2
8004c3a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8004c3e: 687b ldr r3, [r7, #4]
8004c40: 681b ldr r3, [r3, #0]
8004c42: f003 0304 and.w r3, r3, #4
8004c46: 2b00 cmp r3, #0
8004c48: d00a beq.n 8004c60 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8004c4a: 4b8f ldr r3, [pc, #572] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c4c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c50: f023 0230 bic.w r2, r3, #48 @ 0x30
8004c54: 687b ldr r3, [r7, #4]
8004c56: 68db ldr r3, [r3, #12]
8004c58: 498b ldr r1, [pc, #556] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c5a: 4313 orrs r3, r2
8004c5c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8004c60: 687b ldr r3, [r7, #4]
8004c62: 681b ldr r3, [r3, #0]
8004c64: f003 0308 and.w r3, r3, #8
8004c68: 2b00 cmp r3, #0
8004c6a: d00a beq.n 8004c82 <HAL_RCCEx_PeriphCLKConfig+0x1d6>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8004c6c: 4b86 ldr r3, [pc, #536] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c6e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c72: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8004c76: 687b ldr r3, [r7, #4]
8004c78: 691b ldr r3, [r3, #16]
8004c7a: 4983 ldr r1, [pc, #524] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c7c: 4313 orrs r3, r2
8004c7e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8004c82: 687b ldr r3, [r7, #4]
8004c84: 681b ldr r3, [r3, #0]
8004c86: f003 0320 and.w r3, r3, #32
8004c8a: 2b00 cmp r3, #0
8004c8c: d00a beq.n 8004ca4 <HAL_RCCEx_PeriphCLKConfig+0x1f8>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8004c8e: 4b7e ldr r3, [pc, #504] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c90: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c94: f423 6240 bic.w r2, r3, #3072 @ 0xc00
8004c98: 687b ldr r3, [r7, #4]
8004c9a: 695b ldr r3, [r3, #20]
8004c9c: 497a ldr r1, [pc, #488] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c9e: 4313 orrs r3, r2
8004ca0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8004ca4: 687b ldr r3, [r7, #4]
8004ca6: 681b ldr r3, [r3, #0]
8004ca8: f003 0340 and.w r3, r3, #64 @ 0x40
8004cac: 2b00 cmp r3, #0
8004cae: d00a beq.n 8004cc6 <HAL_RCCEx_PeriphCLKConfig+0x21a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8004cb0: 4b75 ldr r3, [pc, #468] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cb2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004cb6: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8004cba: 687b ldr r3, [r7, #4]
8004cbc: 699b ldr r3, [r3, #24]
8004cbe: 4972 ldr r1, [pc, #456] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cc0: 4313 orrs r3, r2
8004cc2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8004cc6: 687b ldr r3, [r7, #4]
8004cc8: 681b ldr r3, [r3, #0]
8004cca: f003 0380 and.w r3, r3, #128 @ 0x80
8004cce: 2b00 cmp r3, #0
8004cd0: d00a beq.n 8004ce8 <HAL_RCCEx_PeriphCLKConfig+0x23c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8004cd2: 4b6d ldr r3, [pc, #436] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cd4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004cd8: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8004cdc: 687b ldr r3, [r7, #4]
8004cde: 69db ldr r3, [r3, #28]
8004ce0: 4969 ldr r1, [pc, #420] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004ce2: 4313 orrs r3, r2
8004ce4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C3)
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8004ce8: 687b ldr r3, [r7, #4]
8004cea: 681b ldr r3, [r3, #0]
8004cec: f403 7380 and.w r3, r3, #256 @ 0x100
8004cf0: 2b00 cmp r3, #0
8004cf2: d00a beq.n 8004d0a <HAL_RCCEx_PeriphCLKConfig+0x25e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8004cf4: 4b64 ldr r3, [pc, #400] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cf6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004cfa: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8004cfe: 687b ldr r3, [r7, #4]
8004d00: 6a1b ldr r3, [r3, #32]
8004d02: 4961 ldr r1, [pc, #388] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d04: 4313 orrs r3, r2
8004d06: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* I2C4 */
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8004d0a: 687b ldr r3, [r7, #4]
8004d0c: 681b ldr r3, [r3, #0]
8004d0e: f403 7300 and.w r3, r3, #512 @ 0x200
8004d12: 2b00 cmp r3, #0
8004d14: d00a beq.n 8004d2c <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8004d16: 4b5c ldr r3, [pc, #368] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d18: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004d1c: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
8004d20: 687b ldr r3, [r7, #4]
8004d22: 6a5b ldr r3, [r3, #36] @ 0x24
8004d24: 4958 ldr r1, [pc, #352] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d26: 4313 orrs r3, r2
8004d28: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
8004d2c: 687b ldr r3, [r7, #4]
8004d2e: 681b ldr r3, [r3, #0]
8004d30: f403 6380 and.w r3, r3, #1024 @ 0x400
8004d34: 2b00 cmp r3, #0
8004d36: d015 beq.n 8004d64 <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure the SAI1 interface clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8004d38: 4b53 ldr r3, [pc, #332] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d3a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004d3e: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8004d42: 687b ldr r3, [r7, #4]
8004d44: 6a9b ldr r3, [r3, #40] @ 0x28
8004d46: 4950 ldr r1, [pc, #320] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d48: 4313 orrs r3, r2
8004d4a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
8004d4e: 687b ldr r3, [r7, #4]
8004d50: 6a9b ldr r3, [r3, #40] @ 0x28
8004d52: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004d56: d105 bne.n 8004d64 <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004d58: 4b4b ldr r3, [pc, #300] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d5a: 68db ldr r3, [r3, #12]
8004d5c: 4a4a ldr r2, [pc, #296] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d5e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004d62: 60d3 str r3, [r2, #12]
#endif /* SAI1 */
#if defined(SPI_I2S_SUPPORT)
/*-------------------------- I2S clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
8004d64: 687b ldr r3, [r7, #4]
8004d66: 681b ldr r3, [r3, #0]
8004d68: f403 6300 and.w r3, r3, #2048 @ 0x800
8004d6c: 2b00 cmp r3, #0
8004d6e: d015 beq.n 8004d9c <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S interface clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8004d70: 4b45 ldr r3, [pc, #276] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d72: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004d76: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8004d7a: 687b ldr r3, [r7, #4]
8004d7c: 6adb ldr r3, [r3, #44] @ 0x2c
8004d7e: 4942 ldr r1, [pc, #264] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d80: 4313 orrs r3, r2
8004d82: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
8004d86: 687b ldr r3, [r7, #4]
8004d88: 6adb ldr r3, [r3, #44] @ 0x2c
8004d8a: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8004d8e: d105 bne.n 8004d9c <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004d90: 4b3d ldr r3, [pc, #244] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d92: 68db ldr r3, [r3, #12]
8004d94: 4a3c ldr r2, [pc, #240] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d96: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004d9a: 60d3 str r3, [r2, #12]
#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/*-------------------------- FDCAN clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
8004d9c: 687b ldr r3, [r7, #4]
8004d9e: 681b ldr r3, [r3, #0]
8004da0: f403 5380 and.w r3, r3, #4096 @ 0x1000
8004da4: 2b00 cmp r3, #0
8004da6: d015 beq.n 8004dd4 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
/* Configure the FDCAN interface clock source */
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
8004da8: 4b37 ldr r3, [pc, #220] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004daa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004dae: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8004db2: 687b ldr r3, [r7, #4]
8004db4: 6b1b ldr r3, [r3, #48] @ 0x30
8004db6: 4934 ldr r1, [pc, #208] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004db8: 4313 orrs r3, r2
8004dba: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
8004dbe: 687b ldr r3, [r7, #4]
8004dc0: 6b1b ldr r3, [r3, #48] @ 0x30
8004dc2: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8004dc6: d105 bne.n 8004dd4 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004dc8: 4b2f ldr r3, [pc, #188] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004dca: 68db ldr r3, [r3, #12]
8004dcc: 4a2e ldr r2, [pc, #184] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004dce: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004dd2: 60d3 str r3, [r2, #12]
#endif /* FDCAN1 */
#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
8004dd4: 687b ldr r3, [r7, #4]
8004dd6: 681b ldr r3, [r3, #0]
8004dd8: f403 5300 and.w r3, r3, #8192 @ 0x2000
8004ddc: 2b00 cmp r3, #0
8004dde: d015 beq.n 8004e0c <HAL_RCCEx_PeriphCLKConfig+0x360>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8004de0: 4b29 ldr r3, [pc, #164] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004de2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004de6: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8004dea: 687b ldr r3, [r7, #4]
8004dec: 6b5b ldr r3, [r3, #52] @ 0x34
8004dee: 4926 ldr r1, [pc, #152] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004df0: 4313 orrs r3, r2
8004df2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
8004df6: 687b ldr r3, [r7, #4]
8004df8: 6b5b ldr r3, [r3, #52] @ 0x34
8004dfa: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8004dfe: d105 bne.n 8004e0c <HAL_RCCEx_PeriphCLKConfig+0x360>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004e00: 4b21 ldr r3, [pc, #132] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e02: 68db ldr r3, [r3, #12]
8004e04: 4a20 ldr r2, [pc, #128] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e06: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004e0a: 60d3 str r3, [r2, #12]
}
#endif /* USB */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
8004e0c: 687b ldr r3, [r7, #4]
8004e0e: 681b ldr r3, [r3, #0]
8004e10: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004e14: 2b00 cmp r3, #0
8004e16: d015 beq.n 8004e44 <HAL_RCCEx_PeriphCLKConfig+0x398>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
8004e18: 4b1b ldr r3, [pc, #108] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e1a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004e1e: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8004e22: 687b ldr r3, [r7, #4]
8004e24: 6b9b ldr r3, [r3, #56] @ 0x38
8004e26: 4918 ldr r1, [pc, #96] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e28: 4313 orrs r3, r2
8004e2a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
8004e2e: 687b ldr r3, [r7, #4]
8004e30: 6b9b ldr r3, [r3, #56] @ 0x38
8004e32: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8004e36: d105 bne.n 8004e44 <HAL_RCCEx_PeriphCLKConfig+0x398>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004e38: 4b13 ldr r3, [pc, #76] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e3a: 68db ldr r3, [r3, #12]
8004e3c: 4a12 ldr r2, [pc, #72] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e3e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004e42: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- ADC12 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
8004e44: 687b ldr r3, [r7, #4]
8004e46: 681b ldr r3, [r3, #0]
8004e48: f403 4300 and.w r3, r3, #32768 @ 0x8000
8004e4c: 2b00 cmp r3, #0
8004e4e: d015 beq.n 8004e7c <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Check the parameters */
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
/* Configure the ADC12 interface clock source */
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
8004e50: 4b0d ldr r3, [pc, #52] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e52: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004e56: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
8004e5a: 687b ldr r3, [r7, #4]
8004e5c: 6bdb ldr r3, [r3, #60] @ 0x3c
8004e5e: 490a ldr r1, [pc, #40] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e60: 4313 orrs r3, r2
8004e62: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
8004e66: 687b ldr r3, [r7, #4]
8004e68: 6bdb ldr r3, [r3, #60] @ 0x3c
8004e6a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8004e6e: d105 bne.n 8004e7c <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
8004e70: 4b05 ldr r3, [pc, #20] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e72: 68db ldr r3, [r3, #12]
8004e74: 4a04 ldr r2, [pc, #16] @ (8004e88 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004e76: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004e7a: 60d3 str r3, [r2, #12]
}
}
#endif /* QUADSPI */
return status;
8004e7c: 7cbb ldrb r3, [r7, #18]
}
8004e7e: 4618 mov r0, r3
8004e80: 3718 adds r7, #24
8004e82: 46bd mov sp, r7
8004e84: bd80 pop {r7, pc}
8004e86: bf00 nop
8004e88: 40021000 .word 0x40021000
08004e8c <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8004e8c: b580 push {r7, lr}
8004e8e: b082 sub sp, #8
8004e90: af00 add r7, sp, #0
8004e92: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004e94: 687b ldr r3, [r7, #4]
8004e96: 2b00 cmp r3, #0
8004e98: d101 bne.n 8004e9e <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8004e9a: 2301 movs r3, #1
8004e9c: e049 b.n 8004f32 <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8004e9e: 687b ldr r3, [r7, #4]
8004ea0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004ea4: b2db uxtb r3, r3
8004ea6: 2b00 cmp r3, #0
8004ea8: d106 bne.n 8004eb8 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8004eaa: 687b ldr r3, [r7, #4]
8004eac: 2200 movs r2, #0
8004eae: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8004eb2: 6878 ldr r0, [r7, #4]
8004eb4: f7fc fe30 bl 8001b18 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8004eb8: 687b ldr r3, [r7, #4]
8004eba: 2202 movs r2, #2
8004ebc: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8004ec0: 687b ldr r3, [r7, #4]
8004ec2: 681a ldr r2, [r3, #0]
8004ec4: 687b ldr r3, [r7, #4]
8004ec6: 3304 adds r3, #4
8004ec8: 4619 mov r1, r3
8004eca: 4610 mov r0, r2
8004ecc: f000 fd26 bl 800591c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8004ed0: 687b ldr r3, [r7, #4]
8004ed2: 2201 movs r2, #1
8004ed4: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004ed8: 687b ldr r3, [r7, #4]
8004eda: 2201 movs r2, #1
8004edc: f883 203e strb.w r2, [r3, #62] @ 0x3e
8004ee0: 687b ldr r3, [r7, #4]
8004ee2: 2201 movs r2, #1
8004ee4: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004ee8: 687b ldr r3, [r7, #4]
8004eea: 2201 movs r2, #1
8004eec: f883 2040 strb.w r2, [r3, #64] @ 0x40
8004ef0: 687b ldr r3, [r7, #4]
8004ef2: 2201 movs r2, #1
8004ef4: f883 2041 strb.w r2, [r3, #65] @ 0x41
8004ef8: 687b ldr r3, [r7, #4]
8004efa: 2201 movs r2, #1
8004efc: f883 2042 strb.w r2, [r3, #66] @ 0x42
8004f00: 687b ldr r3, [r7, #4]
8004f02: 2201 movs r2, #1
8004f04: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004f08: 687b ldr r3, [r7, #4]
8004f0a: 2201 movs r2, #1
8004f0c: f883 2044 strb.w r2, [r3, #68] @ 0x44
8004f10: 687b ldr r3, [r7, #4]
8004f12: 2201 movs r2, #1
8004f14: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004f18: 687b ldr r3, [r7, #4]
8004f1a: 2201 movs r2, #1
8004f1c: f883 2046 strb.w r2, [r3, #70] @ 0x46
8004f20: 687b ldr r3, [r7, #4]
8004f22: 2201 movs r2, #1
8004f24: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8004f28: 687b ldr r3, [r7, #4]
8004f2a: 2201 movs r2, #1
8004f2c: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8004f30: 2300 movs r3, #0
}
8004f32: 4618 mov r0, r3
8004f34: 3708 adds r7, #8
8004f36: 46bd mov sp, r7
8004f38: bd80 pop {r7, pc}
08004f3a <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8004f3a: b580 push {r7, lr}
8004f3c: b082 sub sp, #8
8004f3e: af00 add r7, sp, #0
8004f40: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004f42: 687b ldr r3, [r7, #4]
8004f44: 2b00 cmp r3, #0
8004f46: d101 bne.n 8004f4c <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8004f48: 2301 movs r3, #1
8004f4a: e049 b.n 8004fe0 <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8004f4c: 687b ldr r3, [r7, #4]
8004f4e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004f52: b2db uxtb r3, r3
8004f54: 2b00 cmp r3, #0
8004f56: d106 bne.n 8004f66 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8004f58: 687b ldr r3, [r7, #4]
8004f5a: 2200 movs r2, #0
8004f5c: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8004f60: 6878 ldr r0, [r7, #4]
8004f62: f000 f841 bl 8004fe8 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8004f66: 687b ldr r3, [r7, #4]
8004f68: 2202 movs r2, #2
8004f6a: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8004f6e: 687b ldr r3, [r7, #4]
8004f70: 681a ldr r2, [r3, #0]
8004f72: 687b ldr r3, [r7, #4]
8004f74: 3304 adds r3, #4
8004f76: 4619 mov r1, r3
8004f78: 4610 mov r0, r2
8004f7a: f000 fccf bl 800591c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8004f7e: 687b ldr r3, [r7, #4]
8004f80: 2201 movs r2, #1
8004f82: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004f86: 687b ldr r3, [r7, #4]
8004f88: 2201 movs r2, #1
8004f8a: f883 203e strb.w r2, [r3, #62] @ 0x3e
8004f8e: 687b ldr r3, [r7, #4]
8004f90: 2201 movs r2, #1
8004f92: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004f96: 687b ldr r3, [r7, #4]
8004f98: 2201 movs r2, #1
8004f9a: f883 2040 strb.w r2, [r3, #64] @ 0x40
8004f9e: 687b ldr r3, [r7, #4]
8004fa0: 2201 movs r2, #1
8004fa2: f883 2041 strb.w r2, [r3, #65] @ 0x41
8004fa6: 687b ldr r3, [r7, #4]
8004fa8: 2201 movs r2, #1
8004faa: f883 2042 strb.w r2, [r3, #66] @ 0x42
8004fae: 687b ldr r3, [r7, #4]
8004fb0: 2201 movs r2, #1
8004fb2: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004fb6: 687b ldr r3, [r7, #4]
8004fb8: 2201 movs r2, #1
8004fba: f883 2044 strb.w r2, [r3, #68] @ 0x44
8004fbe: 687b ldr r3, [r7, #4]
8004fc0: 2201 movs r2, #1
8004fc2: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004fc6: 687b ldr r3, [r7, #4]
8004fc8: 2201 movs r2, #1
8004fca: f883 2046 strb.w r2, [r3, #70] @ 0x46
8004fce: 687b ldr r3, [r7, #4]
8004fd0: 2201 movs r2, #1
8004fd2: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8004fd6: 687b ldr r3, [r7, #4]
8004fd8: 2201 movs r2, #1
8004fda: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8004fde: 2300 movs r3, #0
}
8004fe0: 4618 mov r0, r3
8004fe2: 3708 adds r7, #8
8004fe4: 46bd mov sp, r7
8004fe6: bd80 pop {r7, pc}
08004fe8 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8004fe8: b480 push {r7}
8004fea: b083 sub sp, #12
8004fec: af00 add r7, sp, #0
8004fee: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8004ff0: bf00 nop
8004ff2: 370c adds r7, #12
8004ff4: 46bd mov sp, r7
8004ff6: f85d 7b04 ldr.w r7, [sp], #4
8004ffa: 4770 bx lr
08004ffc <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8004ffc: b580 push {r7, lr}
8004ffe: b084 sub sp, #16
8005000: af00 add r7, sp, #0
8005002: 6078 str r0, [r7, #4]
8005004: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8005006: 683b ldr r3, [r7, #0]
8005008: 2b00 cmp r3, #0
800500a: d109 bne.n 8005020 <HAL_TIM_PWM_Start+0x24>
800500c: 687b ldr r3, [r7, #4]
800500e: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8005012: b2db uxtb r3, r3
8005014: 2b01 cmp r3, #1
8005016: bf14 ite ne
8005018: 2301 movne r3, #1
800501a: 2300 moveq r3, #0
800501c: b2db uxtb r3, r3
800501e: e03c b.n 800509a <HAL_TIM_PWM_Start+0x9e>
8005020: 683b ldr r3, [r7, #0]
8005022: 2b04 cmp r3, #4
8005024: d109 bne.n 800503a <HAL_TIM_PWM_Start+0x3e>
8005026: 687b ldr r3, [r7, #4]
8005028: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
800502c: b2db uxtb r3, r3
800502e: 2b01 cmp r3, #1
8005030: bf14 ite ne
8005032: 2301 movne r3, #1
8005034: 2300 moveq r3, #0
8005036: b2db uxtb r3, r3
8005038: e02f b.n 800509a <HAL_TIM_PWM_Start+0x9e>
800503a: 683b ldr r3, [r7, #0]
800503c: 2b08 cmp r3, #8
800503e: d109 bne.n 8005054 <HAL_TIM_PWM_Start+0x58>
8005040: 687b ldr r3, [r7, #4]
8005042: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8005046: b2db uxtb r3, r3
8005048: 2b01 cmp r3, #1
800504a: bf14 ite ne
800504c: 2301 movne r3, #1
800504e: 2300 moveq r3, #0
8005050: b2db uxtb r3, r3
8005052: e022 b.n 800509a <HAL_TIM_PWM_Start+0x9e>
8005054: 683b ldr r3, [r7, #0]
8005056: 2b0c cmp r3, #12
8005058: d109 bne.n 800506e <HAL_TIM_PWM_Start+0x72>
800505a: 687b ldr r3, [r7, #4]
800505c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005060: b2db uxtb r3, r3
8005062: 2b01 cmp r3, #1
8005064: bf14 ite ne
8005066: 2301 movne r3, #1
8005068: 2300 moveq r3, #0
800506a: b2db uxtb r3, r3
800506c: e015 b.n 800509a <HAL_TIM_PWM_Start+0x9e>
800506e: 683b ldr r3, [r7, #0]
8005070: 2b10 cmp r3, #16
8005072: d109 bne.n 8005088 <HAL_TIM_PWM_Start+0x8c>
8005074: 687b ldr r3, [r7, #4]
8005076: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
800507a: b2db uxtb r3, r3
800507c: 2b01 cmp r3, #1
800507e: bf14 ite ne
8005080: 2301 movne r3, #1
8005082: 2300 moveq r3, #0
8005084: b2db uxtb r3, r3
8005086: e008 b.n 800509a <HAL_TIM_PWM_Start+0x9e>
8005088: 687b ldr r3, [r7, #4]
800508a: f893 3043 ldrb.w r3, [r3, #67] @ 0x43
800508e: b2db uxtb r3, r3
8005090: 2b01 cmp r3, #1
8005092: bf14 ite ne
8005094: 2301 movne r3, #1
8005096: 2300 moveq r3, #0
8005098: b2db uxtb r3, r3
800509a: 2b00 cmp r3, #0
800509c: d001 beq.n 80050a2 <HAL_TIM_PWM_Start+0xa6>
{
return HAL_ERROR;
800509e: 2301 movs r3, #1
80050a0: e097 b.n 80051d2 <HAL_TIM_PWM_Start+0x1d6>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
80050a2: 683b ldr r3, [r7, #0]
80050a4: 2b00 cmp r3, #0
80050a6: d104 bne.n 80050b2 <HAL_TIM_PWM_Start+0xb6>
80050a8: 687b ldr r3, [r7, #4]
80050aa: 2202 movs r2, #2
80050ac: f883 203e strb.w r2, [r3, #62] @ 0x3e
80050b0: e023 b.n 80050fa <HAL_TIM_PWM_Start+0xfe>
80050b2: 683b ldr r3, [r7, #0]
80050b4: 2b04 cmp r3, #4
80050b6: d104 bne.n 80050c2 <HAL_TIM_PWM_Start+0xc6>
80050b8: 687b ldr r3, [r7, #4]
80050ba: 2202 movs r2, #2
80050bc: f883 203f strb.w r2, [r3, #63] @ 0x3f
80050c0: e01b b.n 80050fa <HAL_TIM_PWM_Start+0xfe>
80050c2: 683b ldr r3, [r7, #0]
80050c4: 2b08 cmp r3, #8
80050c6: d104 bne.n 80050d2 <HAL_TIM_PWM_Start+0xd6>
80050c8: 687b ldr r3, [r7, #4]
80050ca: 2202 movs r2, #2
80050cc: f883 2040 strb.w r2, [r3, #64] @ 0x40
80050d0: e013 b.n 80050fa <HAL_TIM_PWM_Start+0xfe>
80050d2: 683b ldr r3, [r7, #0]
80050d4: 2b0c cmp r3, #12
80050d6: d104 bne.n 80050e2 <HAL_TIM_PWM_Start+0xe6>
80050d8: 687b ldr r3, [r7, #4]
80050da: 2202 movs r2, #2
80050dc: f883 2041 strb.w r2, [r3, #65] @ 0x41
80050e0: e00b b.n 80050fa <HAL_TIM_PWM_Start+0xfe>
80050e2: 683b ldr r3, [r7, #0]
80050e4: 2b10 cmp r3, #16
80050e6: d104 bne.n 80050f2 <HAL_TIM_PWM_Start+0xf6>
80050e8: 687b ldr r3, [r7, #4]
80050ea: 2202 movs r2, #2
80050ec: f883 2042 strb.w r2, [r3, #66] @ 0x42
80050f0: e003 b.n 80050fa <HAL_TIM_PWM_Start+0xfe>
80050f2: 687b ldr r3, [r7, #4]
80050f4: 2202 movs r2, #2
80050f6: f883 2043 strb.w r2, [r3, #67] @ 0x43
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
80050fa: 687b ldr r3, [r7, #4]
80050fc: 681b ldr r3, [r3, #0]
80050fe: 2201 movs r2, #1
8005100: 6839 ldr r1, [r7, #0]
8005102: 4618 mov r0, r3
8005104: f001 f838 bl 8006178 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8005108: 687b ldr r3, [r7, #4]
800510a: 681b ldr r3, [r3, #0]
800510c: 4a33 ldr r2, [pc, #204] @ (80051dc <HAL_TIM_PWM_Start+0x1e0>)
800510e: 4293 cmp r3, r2
8005110: d013 beq.n 800513a <HAL_TIM_PWM_Start+0x13e>
8005112: 687b ldr r3, [r7, #4]
8005114: 681b ldr r3, [r3, #0]
8005116: 4a32 ldr r2, [pc, #200] @ (80051e0 <HAL_TIM_PWM_Start+0x1e4>)
8005118: 4293 cmp r3, r2
800511a: d00e beq.n 800513a <HAL_TIM_PWM_Start+0x13e>
800511c: 687b ldr r3, [r7, #4]
800511e: 681b ldr r3, [r3, #0]
8005120: 4a30 ldr r2, [pc, #192] @ (80051e4 <HAL_TIM_PWM_Start+0x1e8>)
8005122: 4293 cmp r3, r2
8005124: d009 beq.n 800513a <HAL_TIM_PWM_Start+0x13e>
8005126: 687b ldr r3, [r7, #4]
8005128: 681b ldr r3, [r3, #0]
800512a: 4a2f ldr r2, [pc, #188] @ (80051e8 <HAL_TIM_PWM_Start+0x1ec>)
800512c: 4293 cmp r3, r2
800512e: d004 beq.n 800513a <HAL_TIM_PWM_Start+0x13e>
8005130: 687b ldr r3, [r7, #4]
8005132: 681b ldr r3, [r3, #0]
8005134: 4a2d ldr r2, [pc, #180] @ (80051ec <HAL_TIM_PWM_Start+0x1f0>)
8005136: 4293 cmp r3, r2
8005138: d101 bne.n 800513e <HAL_TIM_PWM_Start+0x142>
800513a: 2301 movs r3, #1
800513c: e000 b.n 8005140 <HAL_TIM_PWM_Start+0x144>
800513e: 2300 movs r3, #0
8005140: 2b00 cmp r3, #0
8005142: d007 beq.n 8005154 <HAL_TIM_PWM_Start+0x158>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8005144: 687b ldr r3, [r7, #4]
8005146: 681b ldr r3, [r3, #0]
8005148: 6c5a ldr r2, [r3, #68] @ 0x44
800514a: 687b ldr r3, [r7, #4]
800514c: 681b ldr r3, [r3, #0]
800514e: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8005152: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005154: 687b ldr r3, [r7, #4]
8005156: 681b ldr r3, [r3, #0]
8005158: 4a20 ldr r2, [pc, #128] @ (80051dc <HAL_TIM_PWM_Start+0x1e0>)
800515a: 4293 cmp r3, r2
800515c: d018 beq.n 8005190 <HAL_TIM_PWM_Start+0x194>
800515e: 687b ldr r3, [r7, #4]
8005160: 681b ldr r3, [r3, #0]
8005162: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005166: d013 beq.n 8005190 <HAL_TIM_PWM_Start+0x194>
8005168: 687b ldr r3, [r7, #4]
800516a: 681b ldr r3, [r3, #0]
800516c: 4a20 ldr r2, [pc, #128] @ (80051f0 <HAL_TIM_PWM_Start+0x1f4>)
800516e: 4293 cmp r3, r2
8005170: d00e beq.n 8005190 <HAL_TIM_PWM_Start+0x194>
8005172: 687b ldr r3, [r7, #4]
8005174: 681b ldr r3, [r3, #0]
8005176: 4a1f ldr r2, [pc, #124] @ (80051f4 <HAL_TIM_PWM_Start+0x1f8>)
8005178: 4293 cmp r3, r2
800517a: d009 beq.n 8005190 <HAL_TIM_PWM_Start+0x194>
800517c: 687b ldr r3, [r7, #4]
800517e: 681b ldr r3, [r3, #0]
8005180: 4a17 ldr r2, [pc, #92] @ (80051e0 <HAL_TIM_PWM_Start+0x1e4>)
8005182: 4293 cmp r3, r2
8005184: d004 beq.n 8005190 <HAL_TIM_PWM_Start+0x194>
8005186: 687b ldr r3, [r7, #4]
8005188: 681b ldr r3, [r3, #0]
800518a: 4a16 ldr r2, [pc, #88] @ (80051e4 <HAL_TIM_PWM_Start+0x1e8>)
800518c: 4293 cmp r3, r2
800518e: d115 bne.n 80051bc <HAL_TIM_PWM_Start+0x1c0>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8005190: 687b ldr r3, [r7, #4]
8005192: 681b ldr r3, [r3, #0]
8005194: 689a ldr r2, [r3, #8]
8005196: 4b18 ldr r3, [pc, #96] @ (80051f8 <HAL_TIM_PWM_Start+0x1fc>)
8005198: 4013 ands r3, r2
800519a: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800519c: 68fb ldr r3, [r7, #12]
800519e: 2b06 cmp r3, #6
80051a0: d015 beq.n 80051ce <HAL_TIM_PWM_Start+0x1d2>
80051a2: 68fb ldr r3, [r7, #12]
80051a4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80051a8: d011 beq.n 80051ce <HAL_TIM_PWM_Start+0x1d2>
{
__HAL_TIM_ENABLE(htim);
80051aa: 687b ldr r3, [r7, #4]
80051ac: 681b ldr r3, [r3, #0]
80051ae: 681a ldr r2, [r3, #0]
80051b0: 687b ldr r3, [r7, #4]
80051b2: 681b ldr r3, [r3, #0]
80051b4: f042 0201 orr.w r2, r2, #1
80051b8: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80051ba: e008 b.n 80051ce <HAL_TIM_PWM_Start+0x1d2>
}
}
else
{
__HAL_TIM_ENABLE(htim);
80051bc: 687b ldr r3, [r7, #4]
80051be: 681b ldr r3, [r3, #0]
80051c0: 681a ldr r2, [r3, #0]
80051c2: 687b ldr r3, [r7, #4]
80051c4: 681b ldr r3, [r3, #0]
80051c6: f042 0201 orr.w r2, r2, #1
80051ca: 601a str r2, [r3, #0]
80051cc: e000 b.n 80051d0 <HAL_TIM_PWM_Start+0x1d4>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80051ce: bf00 nop
}
/* Return function status */
return HAL_OK;
80051d0: 2300 movs r3, #0
}
80051d2: 4618 mov r0, r3
80051d4: 3710 adds r7, #16
80051d6: 46bd mov sp, r7
80051d8: bd80 pop {r7, pc}
80051da: bf00 nop
80051dc: 40012c00 .word 0x40012c00
80051e0: 40013400 .word 0x40013400
80051e4: 40014000 .word 0x40014000
80051e8: 40014400 .word 0x40014400
80051ec: 40014800 .word 0x40014800
80051f0: 40000400 .word 0x40000400
80051f4: 40000800 .word 0x40000800
80051f8: 00010007 .word 0x00010007
080051fc <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
80051fc: b580 push {r7, lr}
80051fe: b084 sub sp, #16
8005200: af00 add r7, sp, #0
8005202: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8005204: 687b ldr r3, [r7, #4]
8005206: 681b ldr r3, [r3, #0]
8005208: 68db ldr r3, [r3, #12]
800520a: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
800520c: 687b ldr r3, [r7, #4]
800520e: 681b ldr r3, [r3, #0]
8005210: 691b ldr r3, [r3, #16]
8005212: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8005214: 68bb ldr r3, [r7, #8]
8005216: f003 0302 and.w r3, r3, #2
800521a: 2b00 cmp r3, #0
800521c: d020 beq.n 8005260 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800521e: 68fb ldr r3, [r7, #12]
8005220: f003 0302 and.w r3, r3, #2
8005224: 2b00 cmp r3, #0
8005226: d01b beq.n 8005260 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8005228: 687b ldr r3, [r7, #4]
800522a: 681b ldr r3, [r3, #0]
800522c: f06f 0202 mvn.w r2, #2
8005230: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8005232: 687b ldr r3, [r7, #4]
8005234: 2201 movs r2, #1
8005236: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8005238: 687b ldr r3, [r7, #4]
800523a: 681b ldr r3, [r3, #0]
800523c: 699b ldr r3, [r3, #24]
800523e: f003 0303 and.w r3, r3, #3
8005242: 2b00 cmp r3, #0
8005244: d003 beq.n 800524e <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005246: 6878 ldr r0, [r7, #4]
8005248: f000 fb4a bl 80058e0 <HAL_TIM_IC_CaptureCallback>
800524c: e005 b.n 800525a <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800524e: 6878 ldr r0, [r7, #4]
8005250: f000 fb3c bl 80058cc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005254: 6878 ldr r0, [r7, #4]
8005256: f000 fb4d bl 80058f4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800525a: 687b ldr r3, [r7, #4]
800525c: 2200 movs r2, #0
800525e: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8005260: 68bb ldr r3, [r7, #8]
8005262: f003 0304 and.w r3, r3, #4
8005266: 2b00 cmp r3, #0
8005268: d020 beq.n 80052ac <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
800526a: 68fb ldr r3, [r7, #12]
800526c: f003 0304 and.w r3, r3, #4
8005270: 2b00 cmp r3, #0
8005272: d01b beq.n 80052ac <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8005274: 687b ldr r3, [r7, #4]
8005276: 681b ldr r3, [r3, #0]
8005278: f06f 0204 mvn.w r2, #4
800527c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
800527e: 687b ldr r3, [r7, #4]
8005280: 2202 movs r2, #2
8005282: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8005284: 687b ldr r3, [r7, #4]
8005286: 681b ldr r3, [r3, #0]
8005288: 699b ldr r3, [r3, #24]
800528a: f403 7340 and.w r3, r3, #768 @ 0x300
800528e: 2b00 cmp r3, #0
8005290: d003 beq.n 800529a <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005292: 6878 ldr r0, [r7, #4]
8005294: f000 fb24 bl 80058e0 <HAL_TIM_IC_CaptureCallback>
8005298: e005 b.n 80052a6 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800529a: 6878 ldr r0, [r7, #4]
800529c: f000 fb16 bl 80058cc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80052a0: 6878 ldr r0, [r7, #4]
80052a2: f000 fb27 bl 80058f4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80052a6: 687b ldr r3, [r7, #4]
80052a8: 2200 movs r2, #0
80052aa: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80052ac: 68bb ldr r3, [r7, #8]
80052ae: f003 0308 and.w r3, r3, #8
80052b2: 2b00 cmp r3, #0
80052b4: d020 beq.n 80052f8 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80052b6: 68fb ldr r3, [r7, #12]
80052b8: f003 0308 and.w r3, r3, #8
80052bc: 2b00 cmp r3, #0
80052be: d01b beq.n 80052f8 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
80052c0: 687b ldr r3, [r7, #4]
80052c2: 681b ldr r3, [r3, #0]
80052c4: f06f 0208 mvn.w r2, #8
80052c8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
80052ca: 687b ldr r3, [r7, #4]
80052cc: 2204 movs r2, #4
80052ce: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
80052d0: 687b ldr r3, [r7, #4]
80052d2: 681b ldr r3, [r3, #0]
80052d4: 69db ldr r3, [r3, #28]
80052d6: f003 0303 and.w r3, r3, #3
80052da: 2b00 cmp r3, #0
80052dc: d003 beq.n 80052e6 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80052de: 6878 ldr r0, [r7, #4]
80052e0: f000 fafe bl 80058e0 <HAL_TIM_IC_CaptureCallback>
80052e4: e005 b.n 80052f2 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80052e6: 6878 ldr r0, [r7, #4]
80052e8: f000 faf0 bl 80058cc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80052ec: 6878 ldr r0, [r7, #4]
80052ee: f000 fb01 bl 80058f4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80052f2: 687b ldr r3, [r7, #4]
80052f4: 2200 movs r2, #0
80052f6: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
80052f8: 68bb ldr r3, [r7, #8]
80052fa: f003 0310 and.w r3, r3, #16
80052fe: 2b00 cmp r3, #0
8005300: d020 beq.n 8005344 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8005302: 68fb ldr r3, [r7, #12]
8005304: f003 0310 and.w r3, r3, #16
8005308: 2b00 cmp r3, #0
800530a: d01b beq.n 8005344 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
800530c: 687b ldr r3, [r7, #4]
800530e: 681b ldr r3, [r3, #0]
8005310: f06f 0210 mvn.w r2, #16
8005314: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8005316: 687b ldr r3, [r7, #4]
8005318: 2208 movs r2, #8
800531a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
800531c: 687b ldr r3, [r7, #4]
800531e: 681b ldr r3, [r3, #0]
8005320: 69db ldr r3, [r3, #28]
8005322: f403 7340 and.w r3, r3, #768 @ 0x300
8005326: 2b00 cmp r3, #0
8005328: d003 beq.n 8005332 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800532a: 6878 ldr r0, [r7, #4]
800532c: f000 fad8 bl 80058e0 <HAL_TIM_IC_CaptureCallback>
8005330: e005 b.n 800533e <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005332: 6878 ldr r0, [r7, #4]
8005334: f000 faca bl 80058cc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005338: 6878 ldr r0, [r7, #4]
800533a: f000 fadb bl 80058f4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800533e: 687b ldr r3, [r7, #4]
8005340: 2200 movs r2, #0
8005342: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8005344: 68bb ldr r3, [r7, #8]
8005346: f003 0301 and.w r3, r3, #1
800534a: 2b00 cmp r3, #0
800534c: d00c beq.n 8005368 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
800534e: 68fb ldr r3, [r7, #12]
8005350: f003 0301 and.w r3, r3, #1
8005354: 2b00 cmp r3, #0
8005356: d007 beq.n 8005368 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8005358: 687b ldr r3, [r7, #4]
800535a: 681b ldr r3, [r3, #0]
800535c: f06f 0201 mvn.w r2, #1
8005360: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8005362: 6878 ldr r0, [r7, #4]
8005364: f000 faa8 bl 80058b8 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8005368: 68bb ldr r3, [r7, #8]
800536a: f003 0380 and.w r3, r3, #128 @ 0x80
800536e: 2b00 cmp r3, #0
8005370: d104 bne.n 800537c <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
8005372: 68bb ldr r3, [r7, #8]
8005374: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8005378: 2b00 cmp r3, #0
800537a: d00c beq.n 8005396 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
800537c: 68fb ldr r3, [r7, #12]
800537e: f003 0380 and.w r3, r3, #128 @ 0x80
8005382: 2b00 cmp r3, #0
8005384: d007 beq.n 8005396 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8005386: 687b ldr r3, [r7, #4]
8005388: 681b ldr r3, [r3, #0]
800538a: f46f 5202 mvn.w r2, #8320 @ 0x2080
800538e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8005390: 6878 ldr r0, [r7, #4]
8005392: f001 f82f bl 80063f4 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8005396: 68bb ldr r3, [r7, #8]
8005398: f403 7380 and.w r3, r3, #256 @ 0x100
800539c: 2b00 cmp r3, #0
800539e: d00c beq.n 80053ba <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80053a0: 68fb ldr r3, [r7, #12]
80053a2: f003 0380 and.w r3, r3, #128 @ 0x80
80053a6: 2b00 cmp r3, #0
80053a8: d007 beq.n 80053ba <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
80053aa: 687b ldr r3, [r7, #4]
80053ac: 681b ldr r3, [r3, #0]
80053ae: f46f 7280 mvn.w r2, #256 @ 0x100
80053b2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
80053b4: 6878 ldr r0, [r7, #4]
80053b6: f001 f827 bl 8006408 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80053ba: 68bb ldr r3, [r7, #8]
80053bc: f003 0340 and.w r3, r3, #64 @ 0x40
80053c0: 2b00 cmp r3, #0
80053c2: d00c beq.n 80053de <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
80053c4: 68fb ldr r3, [r7, #12]
80053c6: f003 0340 and.w r3, r3, #64 @ 0x40
80053ca: 2b00 cmp r3, #0
80053cc: d007 beq.n 80053de <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80053ce: 687b ldr r3, [r7, #4]
80053d0: 681b ldr r3, [r3, #0]
80053d2: f06f 0240 mvn.w r2, #64 @ 0x40
80053d6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80053d8: 6878 ldr r0, [r7, #4]
80053da: f000 fa95 bl 8005908 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
80053de: 68bb ldr r3, [r7, #8]
80053e0: f003 0320 and.w r3, r3, #32
80053e4: 2b00 cmp r3, #0
80053e6: d00c beq.n 8005402 <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
80053e8: 68fb ldr r3, [r7, #12]
80053ea: f003 0320 and.w r3, r3, #32
80053ee: 2b00 cmp r3, #0
80053f0: d007 beq.n 8005402 <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
80053f2: 687b ldr r3, [r7, #4]
80053f4: 681b ldr r3, [r3, #0]
80053f6: f06f 0220 mvn.w r2, #32
80053fa: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
80053fc: 6878 ldr r0, [r7, #4]
80053fe: f000 ffef bl 80063e0 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Encoder index event */
if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
8005402: 68bb ldr r3, [r7, #8]
8005404: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8005408: 2b00 cmp r3, #0
800540a: d00c beq.n 8005426 <HAL_TIM_IRQHandler+0x22a>
{
if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
800540c: 68fb ldr r3, [r7, #12]
800540e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8005412: 2b00 cmp r3, #0
8005414: d007 beq.n 8005426 <HAL_TIM_IRQHandler+0x22a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
8005416: 687b ldr r3, [r7, #4]
8005418: 681b ldr r3, [r3, #0]
800541a: f46f 1280 mvn.w r2, #1048576 @ 0x100000
800541e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->EncoderIndexCallback(htim);
#else
HAL_TIMEx_EncoderIndexCallback(htim);
8005420: 6878 ldr r0, [r7, #4]
8005422: f000 fffb bl 800641c <HAL_TIMEx_EncoderIndexCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Direction change event */
if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
8005426: 68bb ldr r3, [r7, #8]
8005428: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800542c: 2b00 cmp r3, #0
800542e: d00c beq.n 800544a <HAL_TIM_IRQHandler+0x24e>
{
if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
8005430: 68fb ldr r3, [r7, #12]
8005432: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8005436: 2b00 cmp r3, #0
8005438: d007 beq.n 800544a <HAL_TIM_IRQHandler+0x24e>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
800543a: 687b ldr r3, [r7, #4]
800543c: 681b ldr r3, [r3, #0]
800543e: f46f 1200 mvn.w r2, #2097152 @ 0x200000
8005442: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->DirectionChangeCallback(htim);
#else
HAL_TIMEx_DirectionChangeCallback(htim);
8005444: 6878 ldr r0, [r7, #4]
8005446: f000 fff3 bl 8006430 <HAL_TIMEx_DirectionChangeCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Index error event */
if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
800544a: 68bb ldr r3, [r7, #8]
800544c: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8005450: 2b00 cmp r3, #0
8005452: d00c beq.n 800546e <HAL_TIM_IRQHandler+0x272>
{
if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
8005454: 68fb ldr r3, [r7, #12]
8005456: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800545a: 2b00 cmp r3, #0
800545c: d007 beq.n 800546e <HAL_TIM_IRQHandler+0x272>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
800545e: 687b ldr r3, [r7, #4]
8005460: 681b ldr r3, [r3, #0]
8005462: f46f 0280 mvn.w r2, #4194304 @ 0x400000
8005466: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IndexErrorCallback(htim);
#else
HAL_TIMEx_IndexErrorCallback(htim);
8005468: 6878 ldr r0, [r7, #4]
800546a: f000 ffeb bl 8006444 <HAL_TIMEx_IndexErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Transition error event */
if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
800546e: 68bb ldr r3, [r7, #8]
8005470: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8005474: 2b00 cmp r3, #0
8005476: d00c beq.n 8005492 <HAL_TIM_IRQHandler+0x296>
{
if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
8005478: 68fb ldr r3, [r7, #12]
800547a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800547e: 2b00 cmp r3, #0
8005480: d007 beq.n 8005492 <HAL_TIM_IRQHandler+0x296>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
8005482: 687b ldr r3, [r7, #4]
8005484: 681b ldr r3, [r3, #0]
8005486: f46f 0200 mvn.w r2, #8388608 @ 0x800000
800548a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TransitionErrorCallback(htim);
#else
HAL_TIMEx_TransitionErrorCallback(htim);
800548c: 6878 ldr r0, [r7, #4]
800548e: f000 ffe3 bl 8006458 <HAL_TIMEx_TransitionErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8005492: bf00 nop
8005494: 3710 adds r7, #16
8005496: 46bd mov sp, r7
8005498: bd80 pop {r7, pc}
...
0800549c <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
800549c: b580 push {r7, lr}
800549e: b086 sub sp, #24
80054a0: af00 add r7, sp, #0
80054a2: 60f8 str r0, [r7, #12]
80054a4: 60b9 str r1, [r7, #8]
80054a6: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80054a8: 2300 movs r3, #0
80054aa: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
80054ac: 68fb ldr r3, [r7, #12]
80054ae: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80054b2: 2b01 cmp r3, #1
80054b4: d101 bne.n 80054ba <HAL_TIM_PWM_ConfigChannel+0x1e>
80054b6: 2302 movs r3, #2
80054b8: e0ff b.n 80056ba <HAL_TIM_PWM_ConfigChannel+0x21e>
80054ba: 68fb ldr r3, [r7, #12]
80054bc: 2201 movs r2, #1
80054be: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
80054c2: 687b ldr r3, [r7, #4]
80054c4: 2b14 cmp r3, #20
80054c6: f200 80f0 bhi.w 80056aa <HAL_TIM_PWM_ConfigChannel+0x20e>
80054ca: a201 add r2, pc, #4 @ (adr r2, 80054d0 <HAL_TIM_PWM_ConfigChannel+0x34>)
80054cc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80054d0: 08005525 .word 0x08005525
80054d4: 080056ab .word 0x080056ab
80054d8: 080056ab .word 0x080056ab
80054dc: 080056ab .word 0x080056ab
80054e0: 08005565 .word 0x08005565
80054e4: 080056ab .word 0x080056ab
80054e8: 080056ab .word 0x080056ab
80054ec: 080056ab .word 0x080056ab
80054f0: 080055a7 .word 0x080055a7
80054f4: 080056ab .word 0x080056ab
80054f8: 080056ab .word 0x080056ab
80054fc: 080056ab .word 0x080056ab
8005500: 080055e7 .word 0x080055e7
8005504: 080056ab .word 0x080056ab
8005508: 080056ab .word 0x080056ab
800550c: 080056ab .word 0x080056ab
8005510: 08005629 .word 0x08005629
8005514: 080056ab .word 0x080056ab
8005518: 080056ab .word 0x080056ab
800551c: 080056ab .word 0x080056ab
8005520: 08005669 .word 0x08005669
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8005524: 68fb ldr r3, [r7, #12]
8005526: 681b ldr r3, [r3, #0]
8005528: 68b9 ldr r1, [r7, #8]
800552a: 4618 mov r0, r3
800552c: f000 fa92 bl 8005a54 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8005530: 68fb ldr r3, [r7, #12]
8005532: 681b ldr r3, [r3, #0]
8005534: 699a ldr r2, [r3, #24]
8005536: 68fb ldr r3, [r7, #12]
8005538: 681b ldr r3, [r3, #0]
800553a: f042 0208 orr.w r2, r2, #8
800553e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8005540: 68fb ldr r3, [r7, #12]
8005542: 681b ldr r3, [r3, #0]
8005544: 699a ldr r2, [r3, #24]
8005546: 68fb ldr r3, [r7, #12]
8005548: 681b ldr r3, [r3, #0]
800554a: f022 0204 bic.w r2, r2, #4
800554e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8005550: 68fb ldr r3, [r7, #12]
8005552: 681b ldr r3, [r3, #0]
8005554: 6999 ldr r1, [r3, #24]
8005556: 68bb ldr r3, [r7, #8]
8005558: 691a ldr r2, [r3, #16]
800555a: 68fb ldr r3, [r7, #12]
800555c: 681b ldr r3, [r3, #0]
800555e: 430a orrs r2, r1
8005560: 619a str r2, [r3, #24]
break;
8005562: e0a5 b.n 80056b0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8005564: 68fb ldr r3, [r7, #12]
8005566: 681b ldr r3, [r3, #0]
8005568: 68b9 ldr r1, [r7, #8]
800556a: 4618 mov r0, r3
800556c: f000 fb02 bl 8005b74 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8005570: 68fb ldr r3, [r7, #12]
8005572: 681b ldr r3, [r3, #0]
8005574: 699a ldr r2, [r3, #24]
8005576: 68fb ldr r3, [r7, #12]
8005578: 681b ldr r3, [r3, #0]
800557a: f442 6200 orr.w r2, r2, #2048 @ 0x800
800557e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8005580: 68fb ldr r3, [r7, #12]
8005582: 681b ldr r3, [r3, #0]
8005584: 699a ldr r2, [r3, #24]
8005586: 68fb ldr r3, [r7, #12]
8005588: 681b ldr r3, [r3, #0]
800558a: f422 6280 bic.w r2, r2, #1024 @ 0x400
800558e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8005590: 68fb ldr r3, [r7, #12]
8005592: 681b ldr r3, [r3, #0]
8005594: 6999 ldr r1, [r3, #24]
8005596: 68bb ldr r3, [r7, #8]
8005598: 691b ldr r3, [r3, #16]
800559a: 021a lsls r2, r3, #8
800559c: 68fb ldr r3, [r7, #12]
800559e: 681b ldr r3, [r3, #0]
80055a0: 430a orrs r2, r1
80055a2: 619a str r2, [r3, #24]
break;
80055a4: e084 b.n 80056b0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80055a6: 68fb ldr r3, [r7, #12]
80055a8: 681b ldr r3, [r3, #0]
80055aa: 68b9 ldr r1, [r7, #8]
80055ac: 4618 mov r0, r3
80055ae: f000 fb6b bl 8005c88 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80055b2: 68fb ldr r3, [r7, #12]
80055b4: 681b ldr r3, [r3, #0]
80055b6: 69da ldr r2, [r3, #28]
80055b8: 68fb ldr r3, [r7, #12]
80055ba: 681b ldr r3, [r3, #0]
80055bc: f042 0208 orr.w r2, r2, #8
80055c0: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80055c2: 68fb ldr r3, [r7, #12]
80055c4: 681b ldr r3, [r3, #0]
80055c6: 69da ldr r2, [r3, #28]
80055c8: 68fb ldr r3, [r7, #12]
80055ca: 681b ldr r3, [r3, #0]
80055cc: f022 0204 bic.w r2, r2, #4
80055d0: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
80055d2: 68fb ldr r3, [r7, #12]
80055d4: 681b ldr r3, [r3, #0]
80055d6: 69d9 ldr r1, [r3, #28]
80055d8: 68bb ldr r3, [r7, #8]
80055da: 691a ldr r2, [r3, #16]
80055dc: 68fb ldr r3, [r7, #12]
80055de: 681b ldr r3, [r3, #0]
80055e0: 430a orrs r2, r1
80055e2: 61da str r2, [r3, #28]
break;
80055e4: e064 b.n 80056b0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
80055e6: 68fb ldr r3, [r7, #12]
80055e8: 681b ldr r3, [r3, #0]
80055ea: 68b9 ldr r1, [r7, #8]
80055ec: 4618 mov r0, r3
80055ee: f000 fbd3 bl 8005d98 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
80055f2: 68fb ldr r3, [r7, #12]
80055f4: 681b ldr r3, [r3, #0]
80055f6: 69da ldr r2, [r3, #28]
80055f8: 68fb ldr r3, [r7, #12]
80055fa: 681b ldr r3, [r3, #0]
80055fc: f442 6200 orr.w r2, r2, #2048 @ 0x800
8005600: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8005602: 68fb ldr r3, [r7, #12]
8005604: 681b ldr r3, [r3, #0]
8005606: 69da ldr r2, [r3, #28]
8005608: 68fb ldr r3, [r7, #12]
800560a: 681b ldr r3, [r3, #0]
800560c: f422 6280 bic.w r2, r2, #1024 @ 0x400
8005610: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8005612: 68fb ldr r3, [r7, #12]
8005614: 681b ldr r3, [r3, #0]
8005616: 69d9 ldr r1, [r3, #28]
8005618: 68bb ldr r3, [r7, #8]
800561a: 691b ldr r3, [r3, #16]
800561c: 021a lsls r2, r3, #8
800561e: 68fb ldr r3, [r7, #12]
8005620: 681b ldr r3, [r3, #0]
8005622: 430a orrs r2, r1
8005624: 61da str r2, [r3, #28]
break;
8005626: e043 b.n 80056b0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8005628: 68fb ldr r3, [r7, #12]
800562a: 681b ldr r3, [r3, #0]
800562c: 68b9 ldr r1, [r7, #8]
800562e: 4618 mov r0, r3
8005630: f000 fc3c bl 8005eac <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8005634: 68fb ldr r3, [r7, #12]
8005636: 681b ldr r3, [r3, #0]
8005638: 6d1a ldr r2, [r3, #80] @ 0x50
800563a: 68fb ldr r3, [r7, #12]
800563c: 681b ldr r3, [r3, #0]
800563e: f042 0208 orr.w r2, r2, #8
8005642: 651a str r2, [r3, #80] @ 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8005644: 68fb ldr r3, [r7, #12]
8005646: 681b ldr r3, [r3, #0]
8005648: 6d1a ldr r2, [r3, #80] @ 0x50
800564a: 68fb ldr r3, [r7, #12]
800564c: 681b ldr r3, [r3, #0]
800564e: f022 0204 bic.w r2, r2, #4
8005652: 651a str r2, [r3, #80] @ 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8005654: 68fb ldr r3, [r7, #12]
8005656: 681b ldr r3, [r3, #0]
8005658: 6d19 ldr r1, [r3, #80] @ 0x50
800565a: 68bb ldr r3, [r7, #8]
800565c: 691a ldr r2, [r3, #16]
800565e: 68fb ldr r3, [r7, #12]
8005660: 681b ldr r3, [r3, #0]
8005662: 430a orrs r2, r1
8005664: 651a str r2, [r3, #80] @ 0x50
break;
8005666: e023 b.n 80056b0 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8005668: 68fb ldr r3, [r7, #12]
800566a: 681b ldr r3, [r3, #0]
800566c: 68b9 ldr r1, [r7, #8]
800566e: 4618 mov r0, r3
8005670: f000 fc80 bl 8005f74 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8005674: 68fb ldr r3, [r7, #12]
8005676: 681b ldr r3, [r3, #0]
8005678: 6d1a ldr r2, [r3, #80] @ 0x50
800567a: 68fb ldr r3, [r7, #12]
800567c: 681b ldr r3, [r3, #0]
800567e: f442 6200 orr.w r2, r2, #2048 @ 0x800
8005682: 651a str r2, [r3, #80] @ 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8005684: 68fb ldr r3, [r7, #12]
8005686: 681b ldr r3, [r3, #0]
8005688: 6d1a ldr r2, [r3, #80] @ 0x50
800568a: 68fb ldr r3, [r7, #12]
800568c: 681b ldr r3, [r3, #0]
800568e: f422 6280 bic.w r2, r2, #1024 @ 0x400
8005692: 651a str r2, [r3, #80] @ 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8005694: 68fb ldr r3, [r7, #12]
8005696: 681b ldr r3, [r3, #0]
8005698: 6d19 ldr r1, [r3, #80] @ 0x50
800569a: 68bb ldr r3, [r7, #8]
800569c: 691b ldr r3, [r3, #16]
800569e: 021a lsls r2, r3, #8
80056a0: 68fb ldr r3, [r7, #12]
80056a2: 681b ldr r3, [r3, #0]
80056a4: 430a orrs r2, r1
80056a6: 651a str r2, [r3, #80] @ 0x50
break;
80056a8: e002 b.n 80056b0 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
80056aa: 2301 movs r3, #1
80056ac: 75fb strb r3, [r7, #23]
break;
80056ae: bf00 nop
}
__HAL_UNLOCK(htim);
80056b0: 68fb ldr r3, [r7, #12]
80056b2: 2200 movs r2, #0
80056b4: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80056b8: 7dfb ldrb r3, [r7, #23]
}
80056ba: 4618 mov r0, r3
80056bc: 3718 adds r7, #24
80056be: 46bd mov sp, r7
80056c0: bd80 pop {r7, pc}
80056c2: bf00 nop
080056c4 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
80056c4: b580 push {r7, lr}
80056c6: b084 sub sp, #16
80056c8: af00 add r7, sp, #0
80056ca: 6078 str r0, [r7, #4]
80056cc: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
80056ce: 2300 movs r3, #0
80056d0: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
80056d2: 687b ldr r3, [r7, #4]
80056d4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80056d8: 2b01 cmp r3, #1
80056da: d101 bne.n 80056e0 <HAL_TIM_ConfigClockSource+0x1c>
80056dc: 2302 movs r3, #2
80056de: e0de b.n 800589e <HAL_TIM_ConfigClockSource+0x1da>
80056e0: 687b ldr r3, [r7, #4]
80056e2: 2201 movs r2, #1
80056e4: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
80056e8: 687b ldr r3, [r7, #4]
80056ea: 2202 movs r2, #2
80056ec: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80056f0: 687b ldr r3, [r7, #4]
80056f2: 681b ldr r3, [r3, #0]
80056f4: 689b ldr r3, [r3, #8]
80056f6: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
80056f8: 68bb ldr r3, [r7, #8]
80056fa: f423 1344 bic.w r3, r3, #3211264 @ 0x310000
80056fe: f023 0377 bic.w r3, r3, #119 @ 0x77
8005702: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005704: 68bb ldr r3, [r7, #8]
8005706: f423 437f bic.w r3, r3, #65280 @ 0xff00
800570a: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
800570c: 687b ldr r3, [r7, #4]
800570e: 681b ldr r3, [r3, #0]
8005710: 68ba ldr r2, [r7, #8]
8005712: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8005714: 683b ldr r3, [r7, #0]
8005716: 681b ldr r3, [r3, #0]
8005718: 4a63 ldr r2, [pc, #396] @ (80058a8 <HAL_TIM_ConfigClockSource+0x1e4>)
800571a: 4293 cmp r3, r2
800571c: f000 80a9 beq.w 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
8005720: 4a61 ldr r2, [pc, #388] @ (80058a8 <HAL_TIM_ConfigClockSource+0x1e4>)
8005722: 4293 cmp r3, r2
8005724: f200 80ae bhi.w 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005728: 4a60 ldr r2, [pc, #384] @ (80058ac <HAL_TIM_ConfigClockSource+0x1e8>)
800572a: 4293 cmp r3, r2
800572c: f000 80a1 beq.w 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
8005730: 4a5e ldr r2, [pc, #376] @ (80058ac <HAL_TIM_ConfigClockSource+0x1e8>)
8005732: 4293 cmp r3, r2
8005734: f200 80a6 bhi.w 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005738: 4a5d ldr r2, [pc, #372] @ (80058b0 <HAL_TIM_ConfigClockSource+0x1ec>)
800573a: 4293 cmp r3, r2
800573c: f000 8099 beq.w 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
8005740: 4a5b ldr r2, [pc, #364] @ (80058b0 <HAL_TIM_ConfigClockSource+0x1ec>)
8005742: 4293 cmp r3, r2
8005744: f200 809e bhi.w 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005748: 4a5a ldr r2, [pc, #360] @ (80058b4 <HAL_TIM_ConfigClockSource+0x1f0>)
800574a: 4293 cmp r3, r2
800574c: f000 8091 beq.w 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
8005750: 4a58 ldr r2, [pc, #352] @ (80058b4 <HAL_TIM_ConfigClockSource+0x1f0>)
8005752: 4293 cmp r3, r2
8005754: f200 8096 bhi.w 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005758: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
800575c: f000 8089 beq.w 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
8005760: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
8005764: f200 808e bhi.w 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005768: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800576c: d03e beq.n 80057ec <HAL_TIM_ConfigClockSource+0x128>
800576e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8005772: f200 8087 bhi.w 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005776: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800577a: f000 8086 beq.w 800588a <HAL_TIM_ConfigClockSource+0x1c6>
800577e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005782: d87f bhi.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005784: 2b70 cmp r3, #112 @ 0x70
8005786: d01a beq.n 80057be <HAL_TIM_ConfigClockSource+0xfa>
8005788: 2b70 cmp r3, #112 @ 0x70
800578a: d87b bhi.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
800578c: 2b60 cmp r3, #96 @ 0x60
800578e: d050 beq.n 8005832 <HAL_TIM_ConfigClockSource+0x16e>
8005790: 2b60 cmp r3, #96 @ 0x60
8005792: d877 bhi.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
8005794: 2b50 cmp r3, #80 @ 0x50
8005796: d03c beq.n 8005812 <HAL_TIM_ConfigClockSource+0x14e>
8005798: 2b50 cmp r3, #80 @ 0x50
800579a: d873 bhi.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
800579c: 2b40 cmp r3, #64 @ 0x40
800579e: d058 beq.n 8005852 <HAL_TIM_ConfigClockSource+0x18e>
80057a0: 2b40 cmp r3, #64 @ 0x40
80057a2: d86f bhi.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
80057a4: 2b30 cmp r3, #48 @ 0x30
80057a6: d064 beq.n 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
80057a8: 2b30 cmp r3, #48 @ 0x30
80057aa: d86b bhi.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
80057ac: 2b20 cmp r3, #32
80057ae: d060 beq.n 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
80057b0: 2b20 cmp r3, #32
80057b2: d867 bhi.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
80057b4: 2b00 cmp r3, #0
80057b6: d05c beq.n 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
80057b8: 2b10 cmp r3, #16
80057ba: d05a beq.n 8005872 <HAL_TIM_ConfigClockSource+0x1ae>
80057bc: e062 b.n 8005884 <HAL_TIM_ConfigClockSource+0x1c0>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80057be: 687b ldr r3, [r7, #4]
80057c0: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80057c2: 683b ldr r3, [r7, #0]
80057c4: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80057c6: 683b ldr r3, [r7, #0]
80057c8: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80057ca: 683b ldr r3, [r7, #0]
80057cc: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80057ce: f000 fcb3 bl 8006138 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
80057d2: 687b ldr r3, [r7, #4]
80057d4: 681b ldr r3, [r3, #0]
80057d6: 689b ldr r3, [r3, #8]
80057d8: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80057da: 68bb ldr r3, [r7, #8]
80057dc: f043 0377 orr.w r3, r3, #119 @ 0x77
80057e0: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80057e2: 687b ldr r3, [r7, #4]
80057e4: 681b ldr r3, [r3, #0]
80057e6: 68ba ldr r2, [r7, #8]
80057e8: 609a str r2, [r3, #8]
break;
80057ea: e04f b.n 800588c <HAL_TIM_ConfigClockSource+0x1c8>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80057ec: 687b ldr r3, [r7, #4]
80057ee: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80057f0: 683b ldr r3, [r7, #0]
80057f2: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80057f4: 683b ldr r3, [r7, #0]
80057f6: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80057f8: 683b ldr r3, [r7, #0]
80057fa: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80057fc: f000 fc9c bl 8006138 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8005800: 687b ldr r3, [r7, #4]
8005802: 681b ldr r3, [r3, #0]
8005804: 689a ldr r2, [r3, #8]
8005806: 687b ldr r3, [r7, #4]
8005808: 681b ldr r3, [r3, #0]
800580a: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800580e: 609a str r2, [r3, #8]
break;
8005810: e03c b.n 800588c <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005812: 687b ldr r3, [r7, #4]
8005814: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8005816: 683b ldr r3, [r7, #0]
8005818: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800581a: 683b ldr r3, [r7, #0]
800581c: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
800581e: 461a mov r2, r3
8005820: f000 fc0e bl 8006040 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8005824: 687b ldr r3, [r7, #4]
8005826: 681b ldr r3, [r3, #0]
8005828: 2150 movs r1, #80 @ 0x50
800582a: 4618 mov r0, r3
800582c: f000 fc67 bl 80060fe <TIM_ITRx_SetConfig>
break;
8005830: e02c b.n 800588c <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8005832: 687b ldr r3, [r7, #4]
8005834: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8005836: 683b ldr r3, [r7, #0]
8005838: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800583a: 683b ldr r3, [r7, #0]
800583c: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
800583e: 461a mov r2, r3
8005840: f000 fc2d bl 800609e <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8005844: 687b ldr r3, [r7, #4]
8005846: 681b ldr r3, [r3, #0]
8005848: 2160 movs r1, #96 @ 0x60
800584a: 4618 mov r0, r3
800584c: f000 fc57 bl 80060fe <TIM_ITRx_SetConfig>
break;
8005850: e01c b.n 800588c <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005852: 687b ldr r3, [r7, #4]
8005854: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8005856: 683b ldr r3, [r7, #0]
8005858: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800585a: 683b ldr r3, [r7, #0]
800585c: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
800585e: 461a mov r2, r3
8005860: f000 fbee bl 8006040 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8005864: 687b ldr r3, [r7, #4]
8005866: 681b ldr r3, [r3, #0]
8005868: 2140 movs r1, #64 @ 0x40
800586a: 4618 mov r0, r3
800586c: f000 fc47 bl 80060fe <TIM_ITRx_SetConfig>
break;
8005870: e00c b.n 800588c <HAL_TIM_ConfigClockSource+0x1c8>
case TIM_CLOCKSOURCE_ITR11:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8005872: 687b ldr r3, [r7, #4]
8005874: 681a ldr r2, [r3, #0]
8005876: 683b ldr r3, [r7, #0]
8005878: 681b ldr r3, [r3, #0]
800587a: 4619 mov r1, r3
800587c: 4610 mov r0, r2
800587e: f000 fc3e bl 80060fe <TIM_ITRx_SetConfig>
break;
8005882: e003 b.n 800588c <HAL_TIM_ConfigClockSource+0x1c8>
}
default:
status = HAL_ERROR;
8005884: 2301 movs r3, #1
8005886: 73fb strb r3, [r7, #15]
break;
8005888: e000 b.n 800588c <HAL_TIM_ConfigClockSource+0x1c8>
break;
800588a: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800588c: 687b ldr r3, [r7, #4]
800588e: 2201 movs r2, #1
8005890: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005894: 687b ldr r3, [r7, #4]
8005896: 2200 movs r2, #0
8005898: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
800589c: 7bfb ldrb r3, [r7, #15]
}
800589e: 4618 mov r0, r3
80058a0: 3710 adds r7, #16
80058a2: 46bd mov sp, r7
80058a4: bd80 pop {r7, pc}
80058a6: bf00 nop
80058a8: 00100070 .word 0x00100070
80058ac: 00100040 .word 0x00100040
80058b0: 00100030 .word 0x00100030
80058b4: 00100020 .word 0x00100020
080058b8 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
80058b8: b480 push {r7}
80058ba: b083 sub sp, #12
80058bc: af00 add r7, sp, #0
80058be: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
80058c0: bf00 nop
80058c2: 370c adds r7, #12
80058c4: 46bd mov sp, r7
80058c6: f85d 7b04 ldr.w r7, [sp], #4
80058ca: 4770 bx lr
080058cc <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
80058cc: b480 push {r7}
80058ce: b083 sub sp, #12
80058d0: af00 add r7, sp, #0
80058d2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
80058d4: bf00 nop
80058d6: 370c adds r7, #12
80058d8: 46bd mov sp, r7
80058da: f85d 7b04 ldr.w r7, [sp], #4
80058de: 4770 bx lr
080058e0 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
80058e0: b480 push {r7}
80058e2: b083 sub sp, #12
80058e4: af00 add r7, sp, #0
80058e6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
80058e8: bf00 nop
80058ea: 370c adds r7, #12
80058ec: 46bd mov sp, r7
80058ee: f85d 7b04 ldr.w r7, [sp], #4
80058f2: 4770 bx lr
080058f4 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
80058f4: b480 push {r7}
80058f6: b083 sub sp, #12
80058f8: af00 add r7, sp, #0
80058fa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
80058fc: bf00 nop
80058fe: 370c adds r7, #12
8005900: 46bd mov sp, r7
8005902: f85d 7b04 ldr.w r7, [sp], #4
8005906: 4770 bx lr
08005908 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8005908: b480 push {r7}
800590a: b083 sub sp, #12
800590c: af00 add r7, sp, #0
800590e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8005910: bf00 nop
8005912: 370c adds r7, #12
8005914: 46bd mov sp, r7
8005916: f85d 7b04 ldr.w r7, [sp], #4
800591a: 4770 bx lr
0800591c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
800591c: b480 push {r7}
800591e: b085 sub sp, #20
8005920: af00 add r7, sp, #0
8005922: 6078 str r0, [r7, #4]
8005924: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8005926: 687b ldr r3, [r7, #4]
8005928: 681b ldr r3, [r3, #0]
800592a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800592c: 687b ldr r3, [r7, #4]
800592e: 4a42 ldr r2, [pc, #264] @ (8005a38 <TIM_Base_SetConfig+0x11c>)
8005930: 4293 cmp r3, r2
8005932: d00f beq.n 8005954 <TIM_Base_SetConfig+0x38>
8005934: 687b ldr r3, [r7, #4]
8005936: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800593a: d00b beq.n 8005954 <TIM_Base_SetConfig+0x38>
800593c: 687b ldr r3, [r7, #4]
800593e: 4a3f ldr r2, [pc, #252] @ (8005a3c <TIM_Base_SetConfig+0x120>)
8005940: 4293 cmp r3, r2
8005942: d007 beq.n 8005954 <TIM_Base_SetConfig+0x38>
8005944: 687b ldr r3, [r7, #4]
8005946: 4a3e ldr r2, [pc, #248] @ (8005a40 <TIM_Base_SetConfig+0x124>)
8005948: 4293 cmp r3, r2
800594a: d003 beq.n 8005954 <TIM_Base_SetConfig+0x38>
800594c: 687b ldr r3, [r7, #4]
800594e: 4a3d ldr r2, [pc, #244] @ (8005a44 <TIM_Base_SetConfig+0x128>)
8005950: 4293 cmp r3, r2
8005952: d108 bne.n 8005966 <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8005954: 68fb ldr r3, [r7, #12]
8005956: f023 0370 bic.w r3, r3, #112 @ 0x70
800595a: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800595c: 683b ldr r3, [r7, #0]
800595e: 685b ldr r3, [r3, #4]
8005960: 68fa ldr r2, [r7, #12]
8005962: 4313 orrs r3, r2
8005964: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8005966: 687b ldr r3, [r7, #4]
8005968: 4a33 ldr r2, [pc, #204] @ (8005a38 <TIM_Base_SetConfig+0x11c>)
800596a: 4293 cmp r3, r2
800596c: d01b beq.n 80059a6 <TIM_Base_SetConfig+0x8a>
800596e: 687b ldr r3, [r7, #4]
8005970: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005974: d017 beq.n 80059a6 <TIM_Base_SetConfig+0x8a>
8005976: 687b ldr r3, [r7, #4]
8005978: 4a30 ldr r2, [pc, #192] @ (8005a3c <TIM_Base_SetConfig+0x120>)
800597a: 4293 cmp r3, r2
800597c: d013 beq.n 80059a6 <TIM_Base_SetConfig+0x8a>
800597e: 687b ldr r3, [r7, #4]
8005980: 4a2f ldr r2, [pc, #188] @ (8005a40 <TIM_Base_SetConfig+0x124>)
8005982: 4293 cmp r3, r2
8005984: d00f beq.n 80059a6 <TIM_Base_SetConfig+0x8a>
8005986: 687b ldr r3, [r7, #4]
8005988: 4a2e ldr r2, [pc, #184] @ (8005a44 <TIM_Base_SetConfig+0x128>)
800598a: 4293 cmp r3, r2
800598c: d00b beq.n 80059a6 <TIM_Base_SetConfig+0x8a>
800598e: 687b ldr r3, [r7, #4]
8005990: 4a2d ldr r2, [pc, #180] @ (8005a48 <TIM_Base_SetConfig+0x12c>)
8005992: 4293 cmp r3, r2
8005994: d007 beq.n 80059a6 <TIM_Base_SetConfig+0x8a>
8005996: 687b ldr r3, [r7, #4]
8005998: 4a2c ldr r2, [pc, #176] @ (8005a4c <TIM_Base_SetConfig+0x130>)
800599a: 4293 cmp r3, r2
800599c: d003 beq.n 80059a6 <TIM_Base_SetConfig+0x8a>
800599e: 687b ldr r3, [r7, #4]
80059a0: 4a2b ldr r2, [pc, #172] @ (8005a50 <TIM_Base_SetConfig+0x134>)
80059a2: 4293 cmp r3, r2
80059a4: d108 bne.n 80059b8 <TIM_Base_SetConfig+0x9c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80059a6: 68fb ldr r3, [r7, #12]
80059a8: f423 7340 bic.w r3, r3, #768 @ 0x300
80059ac: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80059ae: 683b ldr r3, [r7, #0]
80059b0: 68db ldr r3, [r3, #12]
80059b2: 68fa ldr r2, [r7, #12]
80059b4: 4313 orrs r3, r2
80059b6: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80059b8: 68fb ldr r3, [r7, #12]
80059ba: f023 0280 bic.w r2, r3, #128 @ 0x80
80059be: 683b ldr r3, [r7, #0]
80059c0: 695b ldr r3, [r3, #20]
80059c2: 4313 orrs r3, r2
80059c4: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80059c6: 687b ldr r3, [r7, #4]
80059c8: 68fa ldr r2, [r7, #12]
80059ca: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80059cc: 683b ldr r3, [r7, #0]
80059ce: 689a ldr r2, [r3, #8]
80059d0: 687b ldr r3, [r7, #4]
80059d2: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80059d4: 683b ldr r3, [r7, #0]
80059d6: 681a ldr r2, [r3, #0]
80059d8: 687b ldr r3, [r7, #4]
80059da: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80059dc: 687b ldr r3, [r7, #4]
80059de: 4a16 ldr r2, [pc, #88] @ (8005a38 <TIM_Base_SetConfig+0x11c>)
80059e0: 4293 cmp r3, r2
80059e2: d00f beq.n 8005a04 <TIM_Base_SetConfig+0xe8>
80059e4: 687b ldr r3, [r7, #4]
80059e6: 4a17 ldr r2, [pc, #92] @ (8005a44 <TIM_Base_SetConfig+0x128>)
80059e8: 4293 cmp r3, r2
80059ea: d00b beq.n 8005a04 <TIM_Base_SetConfig+0xe8>
80059ec: 687b ldr r3, [r7, #4]
80059ee: 4a16 ldr r2, [pc, #88] @ (8005a48 <TIM_Base_SetConfig+0x12c>)
80059f0: 4293 cmp r3, r2
80059f2: d007 beq.n 8005a04 <TIM_Base_SetConfig+0xe8>
80059f4: 687b ldr r3, [r7, #4]
80059f6: 4a15 ldr r2, [pc, #84] @ (8005a4c <TIM_Base_SetConfig+0x130>)
80059f8: 4293 cmp r3, r2
80059fa: d003 beq.n 8005a04 <TIM_Base_SetConfig+0xe8>
80059fc: 687b ldr r3, [r7, #4]
80059fe: 4a14 ldr r2, [pc, #80] @ (8005a50 <TIM_Base_SetConfig+0x134>)
8005a00: 4293 cmp r3, r2
8005a02: d103 bne.n 8005a0c <TIM_Base_SetConfig+0xf0>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8005a04: 683b ldr r3, [r7, #0]
8005a06: 691a ldr r2, [r3, #16]
8005a08: 687b ldr r3, [r7, #4]
8005a0a: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8005a0c: 687b ldr r3, [r7, #4]
8005a0e: 2201 movs r2, #1
8005a10: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8005a12: 687b ldr r3, [r7, #4]
8005a14: 691b ldr r3, [r3, #16]
8005a16: f003 0301 and.w r3, r3, #1
8005a1a: 2b01 cmp r3, #1
8005a1c: d105 bne.n 8005a2a <TIM_Base_SetConfig+0x10e>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8005a1e: 687b ldr r3, [r7, #4]
8005a20: 691b ldr r3, [r3, #16]
8005a22: f023 0201 bic.w r2, r3, #1
8005a26: 687b ldr r3, [r7, #4]
8005a28: 611a str r2, [r3, #16]
}
}
8005a2a: bf00 nop
8005a2c: 3714 adds r7, #20
8005a2e: 46bd mov sp, r7
8005a30: f85d 7b04 ldr.w r7, [sp], #4
8005a34: 4770 bx lr
8005a36: bf00 nop
8005a38: 40012c00 .word 0x40012c00
8005a3c: 40000400 .word 0x40000400
8005a40: 40000800 .word 0x40000800
8005a44: 40013400 .word 0x40013400
8005a48: 40014000 .word 0x40014000
8005a4c: 40014400 .word 0x40014400
8005a50: 40014800 .word 0x40014800
08005a54 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005a54: b480 push {r7}
8005a56: b087 sub sp, #28
8005a58: af00 add r7, sp, #0
8005a5a: 6078 str r0, [r7, #4]
8005a5c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005a5e: 687b ldr r3, [r7, #4]
8005a60: 6a1b ldr r3, [r3, #32]
8005a62: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8005a64: 687b ldr r3, [r7, #4]
8005a66: 6a1b ldr r3, [r3, #32]
8005a68: f023 0201 bic.w r2, r3, #1
8005a6c: 687b ldr r3, [r7, #4]
8005a6e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005a70: 687b ldr r3, [r7, #4]
8005a72: 685b ldr r3, [r3, #4]
8005a74: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8005a76: 687b ldr r3, [r7, #4]
8005a78: 699b ldr r3, [r3, #24]
8005a7a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8005a7c: 68fb ldr r3, [r7, #12]
8005a7e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005a82: f023 0370 bic.w r3, r3, #112 @ 0x70
8005a86: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8005a88: 68fb ldr r3, [r7, #12]
8005a8a: f023 0303 bic.w r3, r3, #3
8005a8e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8005a90: 683b ldr r3, [r7, #0]
8005a92: 681b ldr r3, [r3, #0]
8005a94: 68fa ldr r2, [r7, #12]
8005a96: 4313 orrs r3, r2
8005a98: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8005a9a: 697b ldr r3, [r7, #20]
8005a9c: f023 0302 bic.w r3, r3, #2
8005aa0: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8005aa2: 683b ldr r3, [r7, #0]
8005aa4: 689b ldr r3, [r3, #8]
8005aa6: 697a ldr r2, [r7, #20]
8005aa8: 4313 orrs r3, r2
8005aaa: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8005aac: 687b ldr r3, [r7, #4]
8005aae: 4a2c ldr r2, [pc, #176] @ (8005b60 <TIM_OC1_SetConfig+0x10c>)
8005ab0: 4293 cmp r3, r2
8005ab2: d00f beq.n 8005ad4 <TIM_OC1_SetConfig+0x80>
8005ab4: 687b ldr r3, [r7, #4]
8005ab6: 4a2b ldr r2, [pc, #172] @ (8005b64 <TIM_OC1_SetConfig+0x110>)
8005ab8: 4293 cmp r3, r2
8005aba: d00b beq.n 8005ad4 <TIM_OC1_SetConfig+0x80>
8005abc: 687b ldr r3, [r7, #4]
8005abe: 4a2a ldr r2, [pc, #168] @ (8005b68 <TIM_OC1_SetConfig+0x114>)
8005ac0: 4293 cmp r3, r2
8005ac2: d007 beq.n 8005ad4 <TIM_OC1_SetConfig+0x80>
8005ac4: 687b ldr r3, [r7, #4]
8005ac6: 4a29 ldr r2, [pc, #164] @ (8005b6c <TIM_OC1_SetConfig+0x118>)
8005ac8: 4293 cmp r3, r2
8005aca: d003 beq.n 8005ad4 <TIM_OC1_SetConfig+0x80>
8005acc: 687b ldr r3, [r7, #4]
8005ace: 4a28 ldr r2, [pc, #160] @ (8005b70 <TIM_OC1_SetConfig+0x11c>)
8005ad0: 4293 cmp r3, r2
8005ad2: d10c bne.n 8005aee <TIM_OC1_SetConfig+0x9a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8005ad4: 697b ldr r3, [r7, #20]
8005ad6: f023 0308 bic.w r3, r3, #8
8005ada: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8005adc: 683b ldr r3, [r7, #0]
8005ade: 68db ldr r3, [r3, #12]
8005ae0: 697a ldr r2, [r7, #20]
8005ae2: 4313 orrs r3, r2
8005ae4: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8005ae6: 697b ldr r3, [r7, #20]
8005ae8: f023 0304 bic.w r3, r3, #4
8005aec: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005aee: 687b ldr r3, [r7, #4]
8005af0: 4a1b ldr r2, [pc, #108] @ (8005b60 <TIM_OC1_SetConfig+0x10c>)
8005af2: 4293 cmp r3, r2
8005af4: d00f beq.n 8005b16 <TIM_OC1_SetConfig+0xc2>
8005af6: 687b ldr r3, [r7, #4]
8005af8: 4a1a ldr r2, [pc, #104] @ (8005b64 <TIM_OC1_SetConfig+0x110>)
8005afa: 4293 cmp r3, r2
8005afc: d00b beq.n 8005b16 <TIM_OC1_SetConfig+0xc2>
8005afe: 687b ldr r3, [r7, #4]
8005b00: 4a19 ldr r2, [pc, #100] @ (8005b68 <TIM_OC1_SetConfig+0x114>)
8005b02: 4293 cmp r3, r2
8005b04: d007 beq.n 8005b16 <TIM_OC1_SetConfig+0xc2>
8005b06: 687b ldr r3, [r7, #4]
8005b08: 4a18 ldr r2, [pc, #96] @ (8005b6c <TIM_OC1_SetConfig+0x118>)
8005b0a: 4293 cmp r3, r2
8005b0c: d003 beq.n 8005b16 <TIM_OC1_SetConfig+0xc2>
8005b0e: 687b ldr r3, [r7, #4]
8005b10: 4a17 ldr r2, [pc, #92] @ (8005b70 <TIM_OC1_SetConfig+0x11c>)
8005b12: 4293 cmp r3, r2
8005b14: d111 bne.n 8005b3a <TIM_OC1_SetConfig+0xe6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8005b16: 693b ldr r3, [r7, #16]
8005b18: f423 7380 bic.w r3, r3, #256 @ 0x100
8005b1c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8005b1e: 693b ldr r3, [r7, #16]
8005b20: f423 7300 bic.w r3, r3, #512 @ 0x200
8005b24: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8005b26: 683b ldr r3, [r7, #0]
8005b28: 695b ldr r3, [r3, #20]
8005b2a: 693a ldr r2, [r7, #16]
8005b2c: 4313 orrs r3, r2
8005b2e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8005b30: 683b ldr r3, [r7, #0]
8005b32: 699b ldr r3, [r3, #24]
8005b34: 693a ldr r2, [r7, #16]
8005b36: 4313 orrs r3, r2
8005b38: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005b3a: 687b ldr r3, [r7, #4]
8005b3c: 693a ldr r2, [r7, #16]
8005b3e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8005b40: 687b ldr r3, [r7, #4]
8005b42: 68fa ldr r2, [r7, #12]
8005b44: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8005b46: 683b ldr r3, [r7, #0]
8005b48: 685a ldr r2, [r3, #4]
8005b4a: 687b ldr r3, [r7, #4]
8005b4c: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005b4e: 687b ldr r3, [r7, #4]
8005b50: 697a ldr r2, [r7, #20]
8005b52: 621a str r2, [r3, #32]
}
8005b54: bf00 nop
8005b56: 371c adds r7, #28
8005b58: 46bd mov sp, r7
8005b5a: f85d 7b04 ldr.w r7, [sp], #4
8005b5e: 4770 bx lr
8005b60: 40012c00 .word 0x40012c00
8005b64: 40013400 .word 0x40013400
8005b68: 40014000 .word 0x40014000
8005b6c: 40014400 .word 0x40014400
8005b70: 40014800 .word 0x40014800
08005b74 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005b74: b480 push {r7}
8005b76: b087 sub sp, #28
8005b78: af00 add r7, sp, #0
8005b7a: 6078 str r0, [r7, #4]
8005b7c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005b7e: 687b ldr r3, [r7, #4]
8005b80: 6a1b ldr r3, [r3, #32]
8005b82: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8005b84: 687b ldr r3, [r7, #4]
8005b86: 6a1b ldr r3, [r3, #32]
8005b88: f023 0210 bic.w r2, r3, #16
8005b8c: 687b ldr r3, [r7, #4]
8005b8e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005b90: 687b ldr r3, [r7, #4]
8005b92: 685b ldr r3, [r3, #4]
8005b94: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8005b96: 687b ldr r3, [r7, #4]
8005b98: 699b ldr r3, [r3, #24]
8005b9a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8005b9c: 68fb ldr r3, [r7, #12]
8005b9e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005ba2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005ba6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8005ba8: 68fb ldr r3, [r7, #12]
8005baa: f423 7340 bic.w r3, r3, #768 @ 0x300
8005bae: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005bb0: 683b ldr r3, [r7, #0]
8005bb2: 681b ldr r3, [r3, #0]
8005bb4: 021b lsls r3, r3, #8
8005bb6: 68fa ldr r2, [r7, #12]
8005bb8: 4313 orrs r3, r2
8005bba: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8005bbc: 697b ldr r3, [r7, #20]
8005bbe: f023 0320 bic.w r3, r3, #32
8005bc2: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8005bc4: 683b ldr r3, [r7, #0]
8005bc6: 689b ldr r3, [r3, #8]
8005bc8: 011b lsls r3, r3, #4
8005bca: 697a ldr r2, [r7, #20]
8005bcc: 4313 orrs r3, r2
8005bce: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8005bd0: 687b ldr r3, [r7, #4]
8005bd2: 4a28 ldr r2, [pc, #160] @ (8005c74 <TIM_OC2_SetConfig+0x100>)
8005bd4: 4293 cmp r3, r2
8005bd6: d003 beq.n 8005be0 <TIM_OC2_SetConfig+0x6c>
8005bd8: 687b ldr r3, [r7, #4]
8005bda: 4a27 ldr r2, [pc, #156] @ (8005c78 <TIM_OC2_SetConfig+0x104>)
8005bdc: 4293 cmp r3, r2
8005bde: d10d bne.n 8005bfc <TIM_OC2_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8005be0: 697b ldr r3, [r7, #20]
8005be2: f023 0380 bic.w r3, r3, #128 @ 0x80
8005be6: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8005be8: 683b ldr r3, [r7, #0]
8005bea: 68db ldr r3, [r3, #12]
8005bec: 011b lsls r3, r3, #4
8005bee: 697a ldr r2, [r7, #20]
8005bf0: 4313 orrs r3, r2
8005bf2: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8005bf4: 697b ldr r3, [r7, #20]
8005bf6: f023 0340 bic.w r3, r3, #64 @ 0x40
8005bfa: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005bfc: 687b ldr r3, [r7, #4]
8005bfe: 4a1d ldr r2, [pc, #116] @ (8005c74 <TIM_OC2_SetConfig+0x100>)
8005c00: 4293 cmp r3, r2
8005c02: d00f beq.n 8005c24 <TIM_OC2_SetConfig+0xb0>
8005c04: 687b ldr r3, [r7, #4]
8005c06: 4a1c ldr r2, [pc, #112] @ (8005c78 <TIM_OC2_SetConfig+0x104>)
8005c08: 4293 cmp r3, r2
8005c0a: d00b beq.n 8005c24 <TIM_OC2_SetConfig+0xb0>
8005c0c: 687b ldr r3, [r7, #4]
8005c0e: 4a1b ldr r2, [pc, #108] @ (8005c7c <TIM_OC2_SetConfig+0x108>)
8005c10: 4293 cmp r3, r2
8005c12: d007 beq.n 8005c24 <TIM_OC2_SetConfig+0xb0>
8005c14: 687b ldr r3, [r7, #4]
8005c16: 4a1a ldr r2, [pc, #104] @ (8005c80 <TIM_OC2_SetConfig+0x10c>)
8005c18: 4293 cmp r3, r2
8005c1a: d003 beq.n 8005c24 <TIM_OC2_SetConfig+0xb0>
8005c1c: 687b ldr r3, [r7, #4]
8005c1e: 4a19 ldr r2, [pc, #100] @ (8005c84 <TIM_OC2_SetConfig+0x110>)
8005c20: 4293 cmp r3, r2
8005c22: d113 bne.n 8005c4c <TIM_OC2_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8005c24: 693b ldr r3, [r7, #16]
8005c26: f423 6380 bic.w r3, r3, #1024 @ 0x400
8005c2a: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8005c2c: 693b ldr r3, [r7, #16]
8005c2e: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005c32: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8005c34: 683b ldr r3, [r7, #0]
8005c36: 695b ldr r3, [r3, #20]
8005c38: 009b lsls r3, r3, #2
8005c3a: 693a ldr r2, [r7, #16]
8005c3c: 4313 orrs r3, r2
8005c3e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8005c40: 683b ldr r3, [r7, #0]
8005c42: 699b ldr r3, [r3, #24]
8005c44: 009b lsls r3, r3, #2
8005c46: 693a ldr r2, [r7, #16]
8005c48: 4313 orrs r3, r2
8005c4a: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005c4c: 687b ldr r3, [r7, #4]
8005c4e: 693a ldr r2, [r7, #16]
8005c50: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8005c52: 687b ldr r3, [r7, #4]
8005c54: 68fa ldr r2, [r7, #12]
8005c56: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8005c58: 683b ldr r3, [r7, #0]
8005c5a: 685a ldr r2, [r3, #4]
8005c5c: 687b ldr r3, [r7, #4]
8005c5e: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005c60: 687b ldr r3, [r7, #4]
8005c62: 697a ldr r2, [r7, #20]
8005c64: 621a str r2, [r3, #32]
}
8005c66: bf00 nop
8005c68: 371c adds r7, #28
8005c6a: 46bd mov sp, r7
8005c6c: f85d 7b04 ldr.w r7, [sp], #4
8005c70: 4770 bx lr
8005c72: bf00 nop
8005c74: 40012c00 .word 0x40012c00
8005c78: 40013400 .word 0x40013400
8005c7c: 40014000 .word 0x40014000
8005c80: 40014400 .word 0x40014400
8005c84: 40014800 .word 0x40014800
08005c88 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005c88: b480 push {r7}
8005c8a: b087 sub sp, #28
8005c8c: af00 add r7, sp, #0
8005c8e: 6078 str r0, [r7, #4]
8005c90: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005c92: 687b ldr r3, [r7, #4]
8005c94: 6a1b ldr r3, [r3, #32]
8005c96: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8005c98: 687b ldr r3, [r7, #4]
8005c9a: 6a1b ldr r3, [r3, #32]
8005c9c: f423 7280 bic.w r2, r3, #256 @ 0x100
8005ca0: 687b ldr r3, [r7, #4]
8005ca2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005ca4: 687b ldr r3, [r7, #4]
8005ca6: 685b ldr r3, [r3, #4]
8005ca8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8005caa: 687b ldr r3, [r7, #4]
8005cac: 69db ldr r3, [r3, #28]
8005cae: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8005cb0: 68fb ldr r3, [r7, #12]
8005cb2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005cb6: f023 0370 bic.w r3, r3, #112 @ 0x70
8005cba: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8005cbc: 68fb ldr r3, [r7, #12]
8005cbe: f023 0303 bic.w r3, r3, #3
8005cc2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8005cc4: 683b ldr r3, [r7, #0]
8005cc6: 681b ldr r3, [r3, #0]
8005cc8: 68fa ldr r2, [r7, #12]
8005cca: 4313 orrs r3, r2
8005ccc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8005cce: 697b ldr r3, [r7, #20]
8005cd0: f423 7300 bic.w r3, r3, #512 @ 0x200
8005cd4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8005cd6: 683b ldr r3, [r7, #0]
8005cd8: 689b ldr r3, [r3, #8]
8005cda: 021b lsls r3, r3, #8
8005cdc: 697a ldr r2, [r7, #20]
8005cde: 4313 orrs r3, r2
8005ce0: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8005ce2: 687b ldr r3, [r7, #4]
8005ce4: 4a27 ldr r2, [pc, #156] @ (8005d84 <TIM_OC3_SetConfig+0xfc>)
8005ce6: 4293 cmp r3, r2
8005ce8: d003 beq.n 8005cf2 <TIM_OC3_SetConfig+0x6a>
8005cea: 687b ldr r3, [r7, #4]
8005cec: 4a26 ldr r2, [pc, #152] @ (8005d88 <TIM_OC3_SetConfig+0x100>)
8005cee: 4293 cmp r3, r2
8005cf0: d10d bne.n 8005d0e <TIM_OC3_SetConfig+0x86>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8005cf2: 697b ldr r3, [r7, #20]
8005cf4: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005cf8: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8005cfa: 683b ldr r3, [r7, #0]
8005cfc: 68db ldr r3, [r3, #12]
8005cfe: 021b lsls r3, r3, #8
8005d00: 697a ldr r2, [r7, #20]
8005d02: 4313 orrs r3, r2
8005d04: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8005d06: 697b ldr r3, [r7, #20]
8005d08: f423 6380 bic.w r3, r3, #1024 @ 0x400
8005d0c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005d0e: 687b ldr r3, [r7, #4]
8005d10: 4a1c ldr r2, [pc, #112] @ (8005d84 <TIM_OC3_SetConfig+0xfc>)
8005d12: 4293 cmp r3, r2
8005d14: d00f beq.n 8005d36 <TIM_OC3_SetConfig+0xae>
8005d16: 687b ldr r3, [r7, #4]
8005d18: 4a1b ldr r2, [pc, #108] @ (8005d88 <TIM_OC3_SetConfig+0x100>)
8005d1a: 4293 cmp r3, r2
8005d1c: d00b beq.n 8005d36 <TIM_OC3_SetConfig+0xae>
8005d1e: 687b ldr r3, [r7, #4]
8005d20: 4a1a ldr r2, [pc, #104] @ (8005d8c <TIM_OC3_SetConfig+0x104>)
8005d22: 4293 cmp r3, r2
8005d24: d007 beq.n 8005d36 <TIM_OC3_SetConfig+0xae>
8005d26: 687b ldr r3, [r7, #4]
8005d28: 4a19 ldr r2, [pc, #100] @ (8005d90 <TIM_OC3_SetConfig+0x108>)
8005d2a: 4293 cmp r3, r2
8005d2c: d003 beq.n 8005d36 <TIM_OC3_SetConfig+0xae>
8005d2e: 687b ldr r3, [r7, #4]
8005d30: 4a18 ldr r2, [pc, #96] @ (8005d94 <TIM_OC3_SetConfig+0x10c>)
8005d32: 4293 cmp r3, r2
8005d34: d113 bne.n 8005d5e <TIM_OC3_SetConfig+0xd6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8005d36: 693b ldr r3, [r7, #16]
8005d38: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8005d3c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8005d3e: 693b ldr r3, [r7, #16]
8005d40: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8005d44: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8005d46: 683b ldr r3, [r7, #0]
8005d48: 695b ldr r3, [r3, #20]
8005d4a: 011b lsls r3, r3, #4
8005d4c: 693a ldr r2, [r7, #16]
8005d4e: 4313 orrs r3, r2
8005d50: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8005d52: 683b ldr r3, [r7, #0]
8005d54: 699b ldr r3, [r3, #24]
8005d56: 011b lsls r3, r3, #4
8005d58: 693a ldr r2, [r7, #16]
8005d5a: 4313 orrs r3, r2
8005d5c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005d5e: 687b ldr r3, [r7, #4]
8005d60: 693a ldr r2, [r7, #16]
8005d62: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8005d64: 687b ldr r3, [r7, #4]
8005d66: 68fa ldr r2, [r7, #12]
8005d68: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8005d6a: 683b ldr r3, [r7, #0]
8005d6c: 685a ldr r2, [r3, #4]
8005d6e: 687b ldr r3, [r7, #4]
8005d70: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005d72: 687b ldr r3, [r7, #4]
8005d74: 697a ldr r2, [r7, #20]
8005d76: 621a str r2, [r3, #32]
}
8005d78: bf00 nop
8005d7a: 371c adds r7, #28
8005d7c: 46bd mov sp, r7
8005d7e: f85d 7b04 ldr.w r7, [sp], #4
8005d82: 4770 bx lr
8005d84: 40012c00 .word 0x40012c00
8005d88: 40013400 .word 0x40013400
8005d8c: 40014000 .word 0x40014000
8005d90: 40014400 .word 0x40014400
8005d94: 40014800 .word 0x40014800
08005d98 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005d98: b480 push {r7}
8005d9a: b087 sub sp, #28
8005d9c: af00 add r7, sp, #0
8005d9e: 6078 str r0, [r7, #4]
8005da0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005da2: 687b ldr r3, [r7, #4]
8005da4: 6a1b ldr r3, [r3, #32]
8005da6: 617b str r3, [r7, #20]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8005da8: 687b ldr r3, [r7, #4]
8005daa: 6a1b ldr r3, [r3, #32]
8005dac: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8005db0: 687b ldr r3, [r7, #4]
8005db2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005db4: 687b ldr r3, [r7, #4]
8005db6: 685b ldr r3, [r3, #4]
8005db8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8005dba: 687b ldr r3, [r7, #4]
8005dbc: 69db ldr r3, [r3, #28]
8005dbe: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8005dc0: 68fb ldr r3, [r7, #12]
8005dc2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005dc6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005dca: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8005dcc: 68fb ldr r3, [r7, #12]
8005dce: f423 7340 bic.w r3, r3, #768 @ 0x300
8005dd2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005dd4: 683b ldr r3, [r7, #0]
8005dd6: 681b ldr r3, [r3, #0]
8005dd8: 021b lsls r3, r3, #8
8005dda: 68fa ldr r2, [r7, #12]
8005ddc: 4313 orrs r3, r2
8005dde: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8005de0: 697b ldr r3, [r7, #20]
8005de2: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8005de6: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8005de8: 683b ldr r3, [r7, #0]
8005dea: 689b ldr r3, [r3, #8]
8005dec: 031b lsls r3, r3, #12
8005dee: 697a ldr r2, [r7, #20]
8005df0: 4313 orrs r3, r2
8005df2: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
8005df4: 687b ldr r3, [r7, #4]
8005df6: 4a28 ldr r2, [pc, #160] @ (8005e98 <TIM_OC4_SetConfig+0x100>)
8005df8: 4293 cmp r3, r2
8005dfa: d003 beq.n 8005e04 <TIM_OC4_SetConfig+0x6c>
8005dfc: 687b ldr r3, [r7, #4]
8005dfe: 4a27 ldr r2, [pc, #156] @ (8005e9c <TIM_OC4_SetConfig+0x104>)
8005e00: 4293 cmp r3, r2
8005e02: d10d bne.n 8005e20 <TIM_OC4_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC4NP;
8005e04: 697b ldr r3, [r7, #20]
8005e06: f423 4300 bic.w r3, r3, #32768 @ 0x8000
8005e0a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 12U);
8005e0c: 683b ldr r3, [r7, #0]
8005e0e: 68db ldr r3, [r3, #12]
8005e10: 031b lsls r3, r3, #12
8005e12: 697a ldr r2, [r7, #20]
8005e14: 4313 orrs r3, r2
8005e16: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC4NE;
8005e18: 697b ldr r3, [r7, #20]
8005e1a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005e1e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005e20: 687b ldr r3, [r7, #4]
8005e22: 4a1d ldr r2, [pc, #116] @ (8005e98 <TIM_OC4_SetConfig+0x100>)
8005e24: 4293 cmp r3, r2
8005e26: d00f beq.n 8005e48 <TIM_OC4_SetConfig+0xb0>
8005e28: 687b ldr r3, [r7, #4]
8005e2a: 4a1c ldr r2, [pc, #112] @ (8005e9c <TIM_OC4_SetConfig+0x104>)
8005e2c: 4293 cmp r3, r2
8005e2e: d00b beq.n 8005e48 <TIM_OC4_SetConfig+0xb0>
8005e30: 687b ldr r3, [r7, #4]
8005e32: 4a1b ldr r2, [pc, #108] @ (8005ea0 <TIM_OC4_SetConfig+0x108>)
8005e34: 4293 cmp r3, r2
8005e36: d007 beq.n 8005e48 <TIM_OC4_SetConfig+0xb0>
8005e38: 687b ldr r3, [r7, #4]
8005e3a: 4a1a ldr r2, [pc, #104] @ (8005ea4 <TIM_OC4_SetConfig+0x10c>)
8005e3c: 4293 cmp r3, r2
8005e3e: d003 beq.n 8005e48 <TIM_OC4_SetConfig+0xb0>
8005e40: 687b ldr r3, [r7, #4]
8005e42: 4a19 ldr r2, [pc, #100] @ (8005ea8 <TIM_OC4_SetConfig+0x110>)
8005e44: 4293 cmp r3, r2
8005e46: d113 bne.n 8005e70 <TIM_OC4_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8005e48: 693b ldr r3, [r7, #16]
8005e4a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005e4e: 613b str r3, [r7, #16]
/* Reset the Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4N;
8005e50: 693b ldr r3, [r7, #16]
8005e52: f423 4300 bic.w r3, r3, #32768 @ 0x8000
8005e56: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8005e58: 683b ldr r3, [r7, #0]
8005e5a: 695b ldr r3, [r3, #20]
8005e5c: 019b lsls r3, r3, #6
8005e5e: 693a ldr r2, [r7, #16]
8005e60: 4313 orrs r3, r2
8005e62: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 6U);
8005e64: 683b ldr r3, [r7, #0]
8005e66: 699b ldr r3, [r3, #24]
8005e68: 019b lsls r3, r3, #6
8005e6a: 693a ldr r2, [r7, #16]
8005e6c: 4313 orrs r3, r2
8005e6e: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005e70: 687b ldr r3, [r7, #4]
8005e72: 693a ldr r2, [r7, #16]
8005e74: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8005e76: 687b ldr r3, [r7, #4]
8005e78: 68fa ldr r2, [r7, #12]
8005e7a: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8005e7c: 683b ldr r3, [r7, #0]
8005e7e: 685a ldr r2, [r3, #4]
8005e80: 687b ldr r3, [r7, #4]
8005e82: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005e84: 687b ldr r3, [r7, #4]
8005e86: 697a ldr r2, [r7, #20]
8005e88: 621a str r2, [r3, #32]
}
8005e8a: bf00 nop
8005e8c: 371c adds r7, #28
8005e8e: 46bd mov sp, r7
8005e90: f85d 7b04 ldr.w r7, [sp], #4
8005e94: 4770 bx lr
8005e96: bf00 nop
8005e98: 40012c00 .word 0x40012c00
8005e9c: 40013400 .word 0x40013400
8005ea0: 40014000 .word 0x40014000
8005ea4: 40014400 .word 0x40014400
8005ea8: 40014800 .word 0x40014800
08005eac <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8005eac: b480 push {r7}
8005eae: b087 sub sp, #28
8005eb0: af00 add r7, sp, #0
8005eb2: 6078 str r0, [r7, #4]
8005eb4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005eb6: 687b ldr r3, [r7, #4]
8005eb8: 6a1b ldr r3, [r3, #32]
8005eba: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8005ebc: 687b ldr r3, [r7, #4]
8005ebe: 6a1b ldr r3, [r3, #32]
8005ec0: f423 3280 bic.w r2, r3, #65536 @ 0x10000
8005ec4: 687b ldr r3, [r7, #4]
8005ec6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005ec8: 687b ldr r3, [r7, #4]
8005eca: 685b ldr r3, [r3, #4]
8005ecc: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8005ece: 687b ldr r3, [r7, #4]
8005ed0: 6d1b ldr r3, [r3, #80] @ 0x50
8005ed2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8005ed4: 68fb ldr r3, [r7, #12]
8005ed6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005eda: f023 0370 bic.w r3, r3, #112 @ 0x70
8005ede: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8005ee0: 683b ldr r3, [r7, #0]
8005ee2: 681b ldr r3, [r3, #0]
8005ee4: 68fa ldr r2, [r7, #12]
8005ee6: 4313 orrs r3, r2
8005ee8: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8005eea: 693b ldr r3, [r7, #16]
8005eec: f423 3300 bic.w r3, r3, #131072 @ 0x20000
8005ef0: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
8005ef2: 683b ldr r3, [r7, #0]
8005ef4: 689b ldr r3, [r3, #8]
8005ef6: 041b lsls r3, r3, #16
8005ef8: 693a ldr r2, [r7, #16]
8005efa: 4313 orrs r3, r2
8005efc: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005efe: 687b ldr r3, [r7, #4]
8005f00: 4a17 ldr r2, [pc, #92] @ (8005f60 <TIM_OC5_SetConfig+0xb4>)
8005f02: 4293 cmp r3, r2
8005f04: d00f beq.n 8005f26 <TIM_OC5_SetConfig+0x7a>
8005f06: 687b ldr r3, [r7, #4]
8005f08: 4a16 ldr r2, [pc, #88] @ (8005f64 <TIM_OC5_SetConfig+0xb8>)
8005f0a: 4293 cmp r3, r2
8005f0c: d00b beq.n 8005f26 <TIM_OC5_SetConfig+0x7a>
8005f0e: 687b ldr r3, [r7, #4]
8005f10: 4a15 ldr r2, [pc, #84] @ (8005f68 <TIM_OC5_SetConfig+0xbc>)
8005f12: 4293 cmp r3, r2
8005f14: d007 beq.n 8005f26 <TIM_OC5_SetConfig+0x7a>
8005f16: 687b ldr r3, [r7, #4]
8005f18: 4a14 ldr r2, [pc, #80] @ (8005f6c <TIM_OC5_SetConfig+0xc0>)
8005f1a: 4293 cmp r3, r2
8005f1c: d003 beq.n 8005f26 <TIM_OC5_SetConfig+0x7a>
8005f1e: 687b ldr r3, [r7, #4]
8005f20: 4a13 ldr r2, [pc, #76] @ (8005f70 <TIM_OC5_SetConfig+0xc4>)
8005f22: 4293 cmp r3, r2
8005f24: d109 bne.n 8005f3a <TIM_OC5_SetConfig+0x8e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
8005f26: 697b ldr r3, [r7, #20]
8005f28: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005f2c: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8005f2e: 683b ldr r3, [r7, #0]
8005f30: 695b ldr r3, [r3, #20]
8005f32: 021b lsls r3, r3, #8
8005f34: 697a ldr r2, [r7, #20]
8005f36: 4313 orrs r3, r2
8005f38: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005f3a: 687b ldr r3, [r7, #4]
8005f3c: 697a ldr r2, [r7, #20]
8005f3e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8005f40: 687b ldr r3, [r7, #4]
8005f42: 68fa ldr r2, [r7, #12]
8005f44: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8005f46: 683b ldr r3, [r7, #0]
8005f48: 685a ldr r2, [r3, #4]
8005f4a: 687b ldr r3, [r7, #4]
8005f4c: 649a str r2, [r3, #72] @ 0x48
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005f4e: 687b ldr r3, [r7, #4]
8005f50: 693a ldr r2, [r7, #16]
8005f52: 621a str r2, [r3, #32]
}
8005f54: bf00 nop
8005f56: 371c adds r7, #28
8005f58: 46bd mov sp, r7
8005f5a: f85d 7b04 ldr.w r7, [sp], #4
8005f5e: 4770 bx lr
8005f60: 40012c00 .word 0x40012c00
8005f64: 40013400 .word 0x40013400
8005f68: 40014000 .word 0x40014000
8005f6c: 40014400 .word 0x40014400
8005f70: 40014800 .word 0x40014800
08005f74 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8005f74: b480 push {r7}
8005f76: b087 sub sp, #28
8005f78: af00 add r7, sp, #0
8005f7a: 6078 str r0, [r7, #4]
8005f7c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005f7e: 687b ldr r3, [r7, #4]
8005f80: 6a1b ldr r3, [r3, #32]
8005f82: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8005f84: 687b ldr r3, [r7, #4]
8005f86: 6a1b ldr r3, [r3, #32]
8005f88: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8005f8c: 687b ldr r3, [r7, #4]
8005f8e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005f90: 687b ldr r3, [r7, #4]
8005f92: 685b ldr r3, [r3, #4]
8005f94: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8005f96: 687b ldr r3, [r7, #4]
8005f98: 6d1b ldr r3, [r3, #80] @ 0x50
8005f9a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8005f9c: 68fb ldr r3, [r7, #12]
8005f9e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005fa2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005fa6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005fa8: 683b ldr r3, [r7, #0]
8005faa: 681b ldr r3, [r3, #0]
8005fac: 021b lsls r3, r3, #8
8005fae: 68fa ldr r2, [r7, #12]
8005fb0: 4313 orrs r3, r2
8005fb2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8005fb4: 693b ldr r3, [r7, #16]
8005fb6: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8005fba: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8005fbc: 683b ldr r3, [r7, #0]
8005fbe: 689b ldr r3, [r3, #8]
8005fc0: 051b lsls r3, r3, #20
8005fc2: 693a ldr r2, [r7, #16]
8005fc4: 4313 orrs r3, r2
8005fc6: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005fc8: 687b ldr r3, [r7, #4]
8005fca: 4a18 ldr r2, [pc, #96] @ (800602c <TIM_OC6_SetConfig+0xb8>)
8005fcc: 4293 cmp r3, r2
8005fce: d00f beq.n 8005ff0 <TIM_OC6_SetConfig+0x7c>
8005fd0: 687b ldr r3, [r7, #4]
8005fd2: 4a17 ldr r2, [pc, #92] @ (8006030 <TIM_OC6_SetConfig+0xbc>)
8005fd4: 4293 cmp r3, r2
8005fd6: d00b beq.n 8005ff0 <TIM_OC6_SetConfig+0x7c>
8005fd8: 687b ldr r3, [r7, #4]
8005fda: 4a16 ldr r2, [pc, #88] @ (8006034 <TIM_OC6_SetConfig+0xc0>)
8005fdc: 4293 cmp r3, r2
8005fde: d007 beq.n 8005ff0 <TIM_OC6_SetConfig+0x7c>
8005fe0: 687b ldr r3, [r7, #4]
8005fe2: 4a15 ldr r2, [pc, #84] @ (8006038 <TIM_OC6_SetConfig+0xc4>)
8005fe4: 4293 cmp r3, r2
8005fe6: d003 beq.n 8005ff0 <TIM_OC6_SetConfig+0x7c>
8005fe8: 687b ldr r3, [r7, #4]
8005fea: 4a14 ldr r2, [pc, #80] @ (800603c <TIM_OC6_SetConfig+0xc8>)
8005fec: 4293 cmp r3, r2
8005fee: d109 bne.n 8006004 <TIM_OC6_SetConfig+0x90>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8005ff0: 697b ldr r3, [r7, #20]
8005ff2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005ff6: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8005ff8: 683b ldr r3, [r7, #0]
8005ffa: 695b ldr r3, [r3, #20]
8005ffc: 029b lsls r3, r3, #10
8005ffe: 697a ldr r2, [r7, #20]
8006000: 4313 orrs r3, r2
8006002: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8006004: 687b ldr r3, [r7, #4]
8006006: 697a ldr r2, [r7, #20]
8006008: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800600a: 687b ldr r3, [r7, #4]
800600c: 68fa ldr r2, [r7, #12]
800600e: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8006010: 683b ldr r3, [r7, #0]
8006012: 685a ldr r2, [r3, #4]
8006014: 687b ldr r3, [r7, #4]
8006016: 64da str r2, [r3, #76] @ 0x4c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8006018: 687b ldr r3, [r7, #4]
800601a: 693a ldr r2, [r7, #16]
800601c: 621a str r2, [r3, #32]
}
800601e: bf00 nop
8006020: 371c adds r7, #28
8006022: 46bd mov sp, r7
8006024: f85d 7b04 ldr.w r7, [sp], #4
8006028: 4770 bx lr
800602a: bf00 nop
800602c: 40012c00 .word 0x40012c00
8006030: 40013400 .word 0x40013400
8006034: 40014000 .word 0x40014000
8006038: 40014400 .word 0x40014400
800603c: 40014800 .word 0x40014800
08006040 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8006040: b480 push {r7}
8006042: b087 sub sp, #28
8006044: af00 add r7, sp, #0
8006046: 60f8 str r0, [r7, #12]
8006048: 60b9 str r1, [r7, #8]
800604a: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
800604c: 68fb ldr r3, [r7, #12]
800604e: 6a1b ldr r3, [r3, #32]
8006050: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8006052: 68fb ldr r3, [r7, #12]
8006054: 6a1b ldr r3, [r3, #32]
8006056: f023 0201 bic.w r2, r3, #1
800605a: 68fb ldr r3, [r7, #12]
800605c: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800605e: 68fb ldr r3, [r7, #12]
8006060: 699b ldr r3, [r3, #24]
8006062: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8006064: 693b ldr r3, [r7, #16]
8006066: f023 03f0 bic.w r3, r3, #240 @ 0xf0
800606a: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
800606c: 687b ldr r3, [r7, #4]
800606e: 011b lsls r3, r3, #4
8006070: 693a ldr r2, [r7, #16]
8006072: 4313 orrs r3, r2
8006074: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8006076: 697b ldr r3, [r7, #20]
8006078: f023 030a bic.w r3, r3, #10
800607c: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800607e: 697a ldr r2, [r7, #20]
8006080: 68bb ldr r3, [r7, #8]
8006082: 4313 orrs r3, r2
8006084: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8006086: 68fb ldr r3, [r7, #12]
8006088: 693a ldr r2, [r7, #16]
800608a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800608c: 68fb ldr r3, [r7, #12]
800608e: 697a ldr r2, [r7, #20]
8006090: 621a str r2, [r3, #32]
}
8006092: bf00 nop
8006094: 371c adds r7, #28
8006096: 46bd mov sp, r7
8006098: f85d 7b04 ldr.w r7, [sp], #4
800609c: 4770 bx lr
0800609e <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800609e: b480 push {r7}
80060a0: b087 sub sp, #28
80060a2: af00 add r7, sp, #0
80060a4: 60f8 str r0, [r7, #12]
80060a6: 60b9 str r1, [r7, #8]
80060a8: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
80060aa: 68fb ldr r3, [r7, #12]
80060ac: 6a1b ldr r3, [r3, #32]
80060ae: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
80060b0: 68fb ldr r3, [r7, #12]
80060b2: 6a1b ldr r3, [r3, #32]
80060b4: f023 0210 bic.w r2, r3, #16
80060b8: 68fb ldr r3, [r7, #12]
80060ba: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80060bc: 68fb ldr r3, [r7, #12]
80060be: 699b ldr r3, [r3, #24]
80060c0: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80060c2: 693b ldr r3, [r7, #16]
80060c4: f423 4370 bic.w r3, r3, #61440 @ 0xf000
80060c8: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
80060ca: 687b ldr r3, [r7, #4]
80060cc: 031b lsls r3, r3, #12
80060ce: 693a ldr r2, [r7, #16]
80060d0: 4313 orrs r3, r2
80060d2: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80060d4: 697b ldr r3, [r7, #20]
80060d6: f023 03a0 bic.w r3, r3, #160 @ 0xa0
80060da: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
80060dc: 68bb ldr r3, [r7, #8]
80060de: 011b lsls r3, r3, #4
80060e0: 697a ldr r2, [r7, #20]
80060e2: 4313 orrs r3, r2
80060e4: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80060e6: 68fb ldr r3, [r7, #12]
80060e8: 693a ldr r2, [r7, #16]
80060ea: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80060ec: 68fb ldr r3, [r7, #12]
80060ee: 697a ldr r2, [r7, #20]
80060f0: 621a str r2, [r3, #32]
}
80060f2: bf00 nop
80060f4: 371c adds r7, #28
80060f6: 46bd mov sp, r7
80060f8: f85d 7b04 ldr.w r7, [sp], #4
80060fc: 4770 bx lr
080060fe <TIM_ITRx_SetConfig>:
* (*) Value not defined in all devices.
*
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80060fe: b480 push {r7}
8006100: b085 sub sp, #20
8006102: af00 add r7, sp, #0
8006104: 6078 str r0, [r7, #4]
8006106: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8006108: 687b ldr r3, [r7, #4]
800610a: 689b ldr r3, [r3, #8]
800610c: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800610e: 68fb ldr r3, [r7, #12]
8006110: f423 1340 bic.w r3, r3, #3145728 @ 0x300000
8006114: f023 0370 bic.w r3, r3, #112 @ 0x70
8006118: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800611a: 683a ldr r2, [r7, #0]
800611c: 68fb ldr r3, [r7, #12]
800611e: 4313 orrs r3, r2
8006120: f043 0307 orr.w r3, r3, #7
8006124: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8006126: 687b ldr r3, [r7, #4]
8006128: 68fa ldr r2, [r7, #12]
800612a: 609a str r2, [r3, #8]
}
800612c: bf00 nop
800612e: 3714 adds r7, #20
8006130: 46bd mov sp, r7
8006132: f85d 7b04 ldr.w r7, [sp], #4
8006136: 4770 bx lr
08006138 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8006138: b480 push {r7}
800613a: b087 sub sp, #28
800613c: af00 add r7, sp, #0
800613e: 60f8 str r0, [r7, #12]
8006140: 60b9 str r1, [r7, #8]
8006142: 607a str r2, [r7, #4]
8006144: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8006146: 68fb ldr r3, [r7, #12]
8006148: 689b ldr r3, [r3, #8]
800614a: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800614c: 697b ldr r3, [r7, #20]
800614e: f423 437f bic.w r3, r3, #65280 @ 0xff00
8006152: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8006154: 683b ldr r3, [r7, #0]
8006156: 021a lsls r2, r3, #8
8006158: 687b ldr r3, [r7, #4]
800615a: 431a orrs r2, r3
800615c: 68bb ldr r3, [r7, #8]
800615e: 4313 orrs r3, r2
8006160: 697a ldr r2, [r7, #20]
8006162: 4313 orrs r3, r2
8006164: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8006166: 68fb ldr r3, [r7, #12]
8006168: 697a ldr r2, [r7, #20]
800616a: 609a str r2, [r3, #8]
}
800616c: bf00 nop
800616e: 371c adds r7, #28
8006170: 46bd mov sp, r7
8006172: f85d 7b04 ldr.w r7, [sp], #4
8006176: 4770 bx lr
08006178 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8006178: b480 push {r7}
800617a: b087 sub sp, #28
800617c: af00 add r7, sp, #0
800617e: 60f8 str r0, [r7, #12]
8006180: 60b9 str r1, [r7, #8]
8006182: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8006184: 68bb ldr r3, [r7, #8]
8006186: f003 031f and.w r3, r3, #31
800618a: 2201 movs r2, #1
800618c: fa02 f303 lsl.w r3, r2, r3
8006190: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8006192: 68fb ldr r3, [r7, #12]
8006194: 6a1a ldr r2, [r3, #32]
8006196: 697b ldr r3, [r7, #20]
8006198: 43db mvns r3, r3
800619a: 401a ands r2, r3
800619c: 68fb ldr r3, [r7, #12]
800619e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
80061a0: 68fb ldr r3, [r7, #12]
80061a2: 6a1a ldr r2, [r3, #32]
80061a4: 68bb ldr r3, [r7, #8]
80061a6: f003 031f and.w r3, r3, #31
80061aa: 6879 ldr r1, [r7, #4]
80061ac: fa01 f303 lsl.w r3, r1, r3
80061b0: 431a orrs r2, r3
80061b2: 68fb ldr r3, [r7, #12]
80061b4: 621a str r2, [r3, #32]
}
80061b6: bf00 nop
80061b8: 371c adds r7, #28
80061ba: 46bd mov sp, r7
80061bc: f85d 7b04 ldr.w r7, [sp], #4
80061c0: 4770 bx lr
...
080061c4 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
80061c4: b480 push {r7}
80061c6: b085 sub sp, #20
80061c8: af00 add r7, sp, #0
80061ca: 6078 str r0, [r7, #4]
80061cc: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80061ce: 687b ldr r3, [r7, #4]
80061d0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80061d4: 2b01 cmp r3, #1
80061d6: d101 bne.n 80061dc <HAL_TIMEx_MasterConfigSynchronization+0x18>
80061d8: 2302 movs r3, #2
80061da: e065 b.n 80062a8 <HAL_TIMEx_MasterConfigSynchronization+0xe4>
80061dc: 687b ldr r3, [r7, #4]
80061de: 2201 movs r2, #1
80061e0: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80061e4: 687b ldr r3, [r7, #4]
80061e6: 2202 movs r2, #2
80061e8: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80061ec: 687b ldr r3, [r7, #4]
80061ee: 681b ldr r3, [r3, #0]
80061f0: 685b ldr r3, [r3, #4]
80061f2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80061f4: 687b ldr r3, [r7, #4]
80061f6: 681b ldr r3, [r3, #0]
80061f8: 689b ldr r3, [r3, #8]
80061fa: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80061fc: 687b ldr r3, [r7, #4]
80061fe: 681b ldr r3, [r3, #0]
8006200: 4a2c ldr r2, [pc, #176] @ (80062b4 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8006202: 4293 cmp r3, r2
8006204: d004 beq.n 8006210 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
8006206: 687b ldr r3, [r7, #4]
8006208: 681b ldr r3, [r3, #0]
800620a: 4a2b ldr r2, [pc, #172] @ (80062b8 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
800620c: 4293 cmp r3, r2
800620e: d108 bne.n 8006222 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8006210: 68fb ldr r3, [r7, #12]
8006212: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
8006216: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8006218: 683b ldr r3, [r7, #0]
800621a: 685b ldr r3, [r3, #4]
800621c: 68fa ldr r2, [r7, #12]
800621e: 4313 orrs r3, r2
8006220: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8006222: 68fb ldr r3, [r7, #12]
8006224: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000
8006228: f023 0370 bic.w r3, r3, #112 @ 0x70
800622c: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800622e: 683b ldr r3, [r7, #0]
8006230: 681b ldr r3, [r3, #0]
8006232: 68fa ldr r2, [r7, #12]
8006234: 4313 orrs r3, r2
8006236: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8006238: 687b ldr r3, [r7, #4]
800623a: 681b ldr r3, [r3, #0]
800623c: 68fa ldr r2, [r7, #12]
800623e: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8006240: 687b ldr r3, [r7, #4]
8006242: 681b ldr r3, [r3, #0]
8006244: 4a1b ldr r2, [pc, #108] @ (80062b4 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8006246: 4293 cmp r3, r2
8006248: d018 beq.n 800627c <HAL_TIMEx_MasterConfigSynchronization+0xb8>
800624a: 687b ldr r3, [r7, #4]
800624c: 681b ldr r3, [r3, #0]
800624e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8006252: d013 beq.n 800627c <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8006254: 687b ldr r3, [r7, #4]
8006256: 681b ldr r3, [r3, #0]
8006258: 4a18 ldr r2, [pc, #96] @ (80062bc <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
800625a: 4293 cmp r3, r2
800625c: d00e beq.n 800627c <HAL_TIMEx_MasterConfigSynchronization+0xb8>
800625e: 687b ldr r3, [r7, #4]
8006260: 681b ldr r3, [r3, #0]
8006262: 4a17 ldr r2, [pc, #92] @ (80062c0 <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
8006264: 4293 cmp r3, r2
8006266: d009 beq.n 800627c <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8006268: 687b ldr r3, [r7, #4]
800626a: 681b ldr r3, [r3, #0]
800626c: 4a12 ldr r2, [pc, #72] @ (80062b8 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
800626e: 4293 cmp r3, r2
8006270: d004 beq.n 800627c <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8006272: 687b ldr r3, [r7, #4]
8006274: 681b ldr r3, [r3, #0]
8006276: 4a13 ldr r2, [pc, #76] @ (80062c4 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
8006278: 4293 cmp r3, r2
800627a: d10c bne.n 8006296 <HAL_TIMEx_MasterConfigSynchronization+0xd2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800627c: 68bb ldr r3, [r7, #8]
800627e: f023 0380 bic.w r3, r3, #128 @ 0x80
8006282: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8006284: 683b ldr r3, [r7, #0]
8006286: 689b ldr r3, [r3, #8]
8006288: 68ba ldr r2, [r7, #8]
800628a: 4313 orrs r3, r2
800628c: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800628e: 687b ldr r3, [r7, #4]
8006290: 681b ldr r3, [r3, #0]
8006292: 68ba ldr r2, [r7, #8]
8006294: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8006296: 687b ldr r3, [r7, #4]
8006298: 2201 movs r2, #1
800629a: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
800629e: 687b ldr r3, [r7, #4]
80062a0: 2200 movs r2, #0
80062a2: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80062a6: 2300 movs r3, #0
}
80062a8: 4618 mov r0, r3
80062aa: 3714 adds r7, #20
80062ac: 46bd mov sp, r7
80062ae: f85d 7b04 ldr.w r7, [sp], #4
80062b2: 4770 bx lr
80062b4: 40012c00 .word 0x40012c00
80062b8: 40013400 .word 0x40013400
80062bc: 40000400 .word 0x40000400
80062c0: 40000800 .word 0x40000800
80062c4: 40014000 .word 0x40014000
080062c8 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
80062c8: b480 push {r7}
80062ca: b085 sub sp, #20
80062cc: af00 add r7, sp, #0
80062ce: 6078 str r0, [r7, #4]
80062d0: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
80062d2: 2300 movs r3, #0
80062d4: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Check input state */
__HAL_LOCK(htim);
80062d6: 687b ldr r3, [r7, #4]
80062d8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80062dc: 2b01 cmp r3, #1
80062de: d101 bne.n 80062e4 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
80062e0: 2302 movs r3, #2
80062e2: e073 b.n 80063cc <HAL_TIMEx_ConfigBreakDeadTime+0x104>
80062e4: 687b ldr r3, [r7, #4]
80062e6: 2201 movs r2, #1
80062e8: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
80062ec: 68fb ldr r3, [r7, #12]
80062ee: f023 02ff bic.w r2, r3, #255 @ 0xff
80062f2: 683b ldr r3, [r7, #0]
80062f4: 68db ldr r3, [r3, #12]
80062f6: 4313 orrs r3, r2
80062f8: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
80062fa: 68fb ldr r3, [r7, #12]
80062fc: f423 7240 bic.w r2, r3, #768 @ 0x300
8006300: 683b ldr r3, [r7, #0]
8006302: 689b ldr r3, [r3, #8]
8006304: 4313 orrs r3, r2
8006306: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8006308: 68fb ldr r3, [r7, #12]
800630a: f423 6280 bic.w r2, r3, #1024 @ 0x400
800630e: 683b ldr r3, [r7, #0]
8006310: 685b ldr r3, [r3, #4]
8006312: 4313 orrs r3, r2
8006314: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8006316: 68fb ldr r3, [r7, #12]
8006318: f423 6200 bic.w r2, r3, #2048 @ 0x800
800631c: 683b ldr r3, [r7, #0]
800631e: 681b ldr r3, [r3, #0]
8006320: 4313 orrs r3, r2
8006322: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8006324: 68fb ldr r3, [r7, #12]
8006326: f423 5280 bic.w r2, r3, #4096 @ 0x1000
800632a: 683b ldr r3, [r7, #0]
800632c: 691b ldr r3, [r3, #16]
800632e: 4313 orrs r3, r2
8006330: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8006332: 68fb ldr r3, [r7, #12]
8006334: f423 5200 bic.w r2, r3, #8192 @ 0x2000
8006338: 683b ldr r3, [r7, #0]
800633a: 695b ldr r3, [r3, #20]
800633c: 4313 orrs r3, r2
800633e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8006340: 68fb ldr r3, [r7, #12]
8006342: f423 4280 bic.w r2, r3, #16384 @ 0x4000
8006346: 683b ldr r3, [r7, #0]
8006348: 6b1b ldr r3, [r3, #48] @ 0x30
800634a: 4313 orrs r3, r2
800634c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
800634e: 68fb ldr r3, [r7, #12]
8006350: f423 2270 bic.w r2, r3, #983040 @ 0xf0000
8006354: 683b ldr r3, [r7, #0]
8006356: 699b ldr r3, [r3, #24]
8006358: 041b lsls r3, r3, #16
800635a: 4313 orrs r3, r2
800635c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
800635e: 68fb ldr r3, [r7, #12]
8006360: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
8006364: 683b ldr r3, [r7, #0]
8006366: 69db ldr r3, [r3, #28]
8006368: 4313 orrs r3, r2
800636a: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
800636c: 687b ldr r3, [r7, #4]
800636e: 681b ldr r3, [r3, #0]
8006370: 4a19 ldr r2, [pc, #100] @ (80063d8 <HAL_TIMEx_ConfigBreakDeadTime+0x110>)
8006372: 4293 cmp r3, r2
8006374: d004 beq.n 8006380 <HAL_TIMEx_ConfigBreakDeadTime+0xb8>
8006376: 687b ldr r3, [r7, #4]
8006378: 681b ldr r3, [r3, #0]
800637a: 4a18 ldr r2, [pc, #96] @ (80063dc <HAL_TIMEx_ConfigBreakDeadTime+0x114>)
800637c: 4293 cmp r3, r2
800637e: d11c bne.n 80063ba <HAL_TIMEx_ConfigBreakDeadTime+0xf2>
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
8006380: 68fb ldr r3, [r7, #12]
8006382: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000
8006386: 683b ldr r3, [r7, #0]
8006388: 6a9b ldr r3, [r3, #40] @ 0x28
800638a: 051b lsls r3, r3, #20
800638c: 4313 orrs r3, r2
800638e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
8006390: 68fb ldr r3, [r7, #12]
8006392: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
8006396: 683b ldr r3, [r7, #0]
8006398: 6a1b ldr r3, [r3, #32]
800639a: 4313 orrs r3, r2
800639c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
800639e: 68fb ldr r3, [r7, #12]
80063a0: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
80063a4: 683b ldr r3, [r7, #0]
80063a6: 6a5b ldr r3, [r3, #36] @ 0x24
80063a8: 4313 orrs r3, r2
80063aa: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
80063ac: 68fb ldr r3, [r7, #12]
80063ae: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
80063b2: 683b ldr r3, [r7, #0]
80063b4: 6adb ldr r3, [r3, #44] @ 0x2c
80063b6: 4313 orrs r3, r2
80063b8: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
80063ba: 687b ldr r3, [r7, #4]
80063bc: 681b ldr r3, [r3, #0]
80063be: 68fa ldr r2, [r7, #12]
80063c0: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
80063c2: 687b ldr r3, [r7, #4]
80063c4: 2200 movs r2, #0
80063c6: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80063ca: 2300 movs r3, #0
}
80063cc: 4618 mov r0, r3
80063ce: 3714 adds r7, #20
80063d0: 46bd mov sp, r7
80063d2: f85d 7b04 ldr.w r7, [sp], #4
80063d6: 4770 bx lr
80063d8: 40012c00 .word 0x40012c00
80063dc: 40013400 .word 0x40013400
080063e0 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
80063e0: b480 push {r7}
80063e2: b083 sub sp, #12
80063e4: af00 add r7, sp, #0
80063e6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
80063e8: bf00 nop
80063ea: 370c adds r7, #12
80063ec: 46bd mov sp, r7
80063ee: f85d 7b04 ldr.w r7, [sp], #4
80063f2: 4770 bx lr
080063f4 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
80063f4: b480 push {r7}
80063f6: b083 sub sp, #12
80063f8: af00 add r7, sp, #0
80063fa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80063fc: bf00 nop
80063fe: 370c adds r7, #12
8006400: 46bd mov sp, r7
8006402: f85d 7b04 ldr.w r7, [sp], #4
8006406: 4770 bx lr
08006408 <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
8006408: b480 push {r7}
800640a: b083 sub sp, #12
800640c: af00 add r7, sp, #0
800640e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8006410: bf00 nop
8006412: 370c adds r7, #12
8006414: 46bd mov sp, r7
8006416: f85d 7b04 ldr.w r7, [sp], #4
800641a: 4770 bx lr
0800641c <HAL_TIMEx_EncoderIndexCallback>:
* @brief Encoder index callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
{
800641c: b480 push {r7}
800641e: b083 sub sp, #12
8006420: af00 add r7, sp, #0
8006422: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
*/
}
8006424: bf00 nop
8006426: 370c adds r7, #12
8006428: 46bd mov sp, r7
800642a: f85d 7b04 ldr.w r7, [sp], #4
800642e: 4770 bx lr
08006430 <HAL_TIMEx_DirectionChangeCallback>:
* @brief Direction change callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
{
8006430: b480 push {r7}
8006432: b083 sub sp, #12
8006434: af00 add r7, sp, #0
8006436: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
*/
}
8006438: bf00 nop
800643a: 370c adds r7, #12
800643c: 46bd mov sp, r7
800643e: f85d 7b04 ldr.w r7, [sp], #4
8006442: 4770 bx lr
08006444 <HAL_TIMEx_IndexErrorCallback>:
* @brief Index error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
{
8006444: b480 push {r7}
8006446: b083 sub sp, #12
8006448: af00 add r7, sp, #0
800644a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
*/
}
800644c: bf00 nop
800644e: 370c adds r7, #12
8006450: 46bd mov sp, r7
8006452: f85d 7b04 ldr.w r7, [sp], #4
8006456: 4770 bx lr
08006458 <HAL_TIMEx_TransitionErrorCallback>:
* @brief Transition error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
{
8006458: b480 push {r7}
800645a: b083 sub sp, #12
800645c: af00 add r7, sp, #0
800645e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
*/
}
8006460: bf00 nop
8006462: 370c adds r7, #12
8006464: 46bd mov sp, r7
8006466: f85d 7b04 ldr.w r7, [sp], #4
800646a: 4770 bx lr
0800646c <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
800646c: b580 push {r7, lr}
800646e: b082 sub sp, #8
8006470: af00 add r7, sp, #0
8006472: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8006474: 687b ldr r3, [r7, #4]
8006476: 2b00 cmp r3, #0
8006478: d101 bne.n 800647e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800647a: 2301 movs r3, #1
800647c: e042 b.n 8006504 <HAL_UART_Init+0x98>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
800647e: 687b ldr r3, [r7, #4]
8006480: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006484: 2b00 cmp r3, #0
8006486: d106 bne.n 8006496 <HAL_UART_Init+0x2a>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8006488: 687b ldr r3, [r7, #4]
800648a: 2200 movs r2, #0
800648c: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8006490: 6878 ldr r0, [r7, #4]
8006492: f7fb fbb1 bl 8001bf8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8006496: 687b ldr r3, [r7, #4]
8006498: 2224 movs r2, #36 @ 0x24
800649a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UART_DISABLE(huart);
800649e: 687b ldr r3, [r7, #4]
80064a0: 681b ldr r3, [r3, #0]
80064a2: 681a ldr r2, [r3, #0]
80064a4: 687b ldr r3, [r7, #4]
80064a6: 681b ldr r3, [r3, #0]
80064a8: f022 0201 bic.w r2, r2, #1
80064ac: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80064ae: 687b ldr r3, [r7, #4]
80064b0: 6a9b ldr r3, [r3, #40] @ 0x28
80064b2: 2b00 cmp r3, #0
80064b4: d002 beq.n 80064bc <HAL_UART_Init+0x50>
{
UART_AdvFeatureConfig(huart);
80064b6: 6878 ldr r0, [r7, #4]
80064b8: f000 ff26 bl 8007308 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
80064bc: 6878 ldr r0, [r7, #4]
80064be: f000 fc57 bl 8006d70 <UART_SetConfig>
80064c2: 4603 mov r3, r0
80064c4: 2b01 cmp r3, #1
80064c6: d101 bne.n 80064cc <HAL_UART_Init+0x60>
{
return HAL_ERROR;
80064c8: 2301 movs r3, #1
80064ca: e01b b.n 8006504 <HAL_UART_Init+0x98>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80064cc: 687b ldr r3, [r7, #4]
80064ce: 681b ldr r3, [r3, #0]
80064d0: 685a ldr r2, [r3, #4]
80064d2: 687b ldr r3, [r7, #4]
80064d4: 681b ldr r3, [r3, #0]
80064d6: f422 4290 bic.w r2, r2, #18432 @ 0x4800
80064da: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80064dc: 687b ldr r3, [r7, #4]
80064de: 681b ldr r3, [r3, #0]
80064e0: 689a ldr r2, [r3, #8]
80064e2: 687b ldr r3, [r7, #4]
80064e4: 681b ldr r3, [r3, #0]
80064e6: f022 022a bic.w r2, r2, #42 @ 0x2a
80064ea: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
80064ec: 687b ldr r3, [r7, #4]
80064ee: 681b ldr r3, [r3, #0]
80064f0: 681a ldr r2, [r3, #0]
80064f2: 687b ldr r3, [r7, #4]
80064f4: 681b ldr r3, [r3, #0]
80064f6: f042 0201 orr.w r2, r2, #1
80064fa: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
80064fc: 6878 ldr r0, [r7, #4]
80064fe: f000 ffa5 bl 800744c <UART_CheckIdleState>
8006502: 4603 mov r3, r0
}
8006504: 4618 mov r0, r3
8006506: 3708 adds r7, #8
8006508: 46bd mov sp, r7
800650a: bd80 pop {r7, pc}
0800650c <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800650c: b580 push {r7, lr}
800650e: b08a sub sp, #40 @ 0x28
8006510: af02 add r7, sp, #8
8006512: 60f8 str r0, [r7, #12]
8006514: 60b9 str r1, [r7, #8]
8006516: 603b str r3, [r7, #0]
8006518: 4613 mov r3, r2
800651a: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800651c: 68fb ldr r3, [r7, #12]
800651e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006522: 2b20 cmp r3, #32
8006524: d17b bne.n 800661e <HAL_UART_Transmit+0x112>
{
if ((pData == NULL) || (Size == 0U))
8006526: 68bb ldr r3, [r7, #8]
8006528: 2b00 cmp r3, #0
800652a: d002 beq.n 8006532 <HAL_UART_Transmit+0x26>
800652c: 88fb ldrh r3, [r7, #6]
800652e: 2b00 cmp r3, #0
8006530: d101 bne.n 8006536 <HAL_UART_Transmit+0x2a>
{
return HAL_ERROR;
8006532: 2301 movs r3, #1
8006534: e074 b.n 8006620 <HAL_UART_Transmit+0x114>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8006536: 68fb ldr r3, [r7, #12]
8006538: 2200 movs r2, #0
800653a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
huart->gState = HAL_UART_STATE_BUSY_TX;
800653e: 68fb ldr r3, [r7, #12]
8006540: 2221 movs r2, #33 @ 0x21
8006542: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8006546: f7fb fc9b bl 8001e80 <HAL_GetTick>
800654a: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
800654c: 68fb ldr r3, [r7, #12]
800654e: 88fa ldrh r2, [r7, #6]
8006550: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
huart->TxXferCount = Size;
8006554: 68fb ldr r3, [r7, #12]
8006556: 88fa ldrh r2, [r7, #6]
8006558: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
800655c: 68fb ldr r3, [r7, #12]
800655e: 689b ldr r3, [r3, #8]
8006560: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8006564: d108 bne.n 8006578 <HAL_UART_Transmit+0x6c>
8006566: 68fb ldr r3, [r7, #12]
8006568: 691b ldr r3, [r3, #16]
800656a: 2b00 cmp r3, #0
800656c: d104 bne.n 8006578 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
800656e: 2300 movs r3, #0
8006570: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8006572: 68bb ldr r3, [r7, #8]
8006574: 61bb str r3, [r7, #24]
8006576: e003 b.n 8006580 <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
8006578: 68bb ldr r3, [r7, #8]
800657a: 61fb str r3, [r7, #28]
pdata16bits = NULL;
800657c: 2300 movs r3, #0
800657e: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8006580: e030 b.n 80065e4 <HAL_UART_Transmit+0xd8>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8006582: 683b ldr r3, [r7, #0]
8006584: 9300 str r3, [sp, #0]
8006586: 697b ldr r3, [r7, #20]
8006588: 2200 movs r2, #0
800658a: 2180 movs r1, #128 @ 0x80
800658c: 68f8 ldr r0, [r7, #12]
800658e: f001 f807 bl 80075a0 <UART_WaitOnFlagUntilTimeout>
8006592: 4603 mov r3, r0
8006594: 2b00 cmp r3, #0
8006596: d005 beq.n 80065a4 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
8006598: 68fb ldr r3, [r7, #12]
800659a: 2220 movs r2, #32
800659c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
80065a0: 2303 movs r3, #3
80065a2: e03d b.n 8006620 <HAL_UART_Transmit+0x114>
}
if (pdata8bits == NULL)
80065a4: 69fb ldr r3, [r7, #28]
80065a6: 2b00 cmp r3, #0
80065a8: d10b bne.n 80065c2 <HAL_UART_Transmit+0xb6>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
80065aa: 69bb ldr r3, [r7, #24]
80065ac: 881b ldrh r3, [r3, #0]
80065ae: 461a mov r2, r3
80065b0: 68fb ldr r3, [r7, #12]
80065b2: 681b ldr r3, [r3, #0]
80065b4: f3c2 0208 ubfx r2, r2, #0, #9
80065b8: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
80065ba: 69bb ldr r3, [r7, #24]
80065bc: 3302 adds r3, #2
80065be: 61bb str r3, [r7, #24]
80065c0: e007 b.n 80065d2 <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
80065c2: 69fb ldr r3, [r7, #28]
80065c4: 781a ldrb r2, [r3, #0]
80065c6: 68fb ldr r3, [r7, #12]
80065c8: 681b ldr r3, [r3, #0]
80065ca: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
80065cc: 69fb ldr r3, [r7, #28]
80065ce: 3301 adds r3, #1
80065d0: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
80065d2: 68fb ldr r3, [r7, #12]
80065d4: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
80065d8: b29b uxth r3, r3
80065da: 3b01 subs r3, #1
80065dc: b29a uxth r2, r3
80065de: 68fb ldr r3, [r7, #12]
80065e0: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
while (huart->TxXferCount > 0U)
80065e4: 68fb ldr r3, [r7, #12]
80065e6: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
80065ea: b29b uxth r3, r3
80065ec: 2b00 cmp r3, #0
80065ee: d1c8 bne.n 8006582 <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
80065f0: 683b ldr r3, [r7, #0]
80065f2: 9300 str r3, [sp, #0]
80065f4: 697b ldr r3, [r7, #20]
80065f6: 2200 movs r2, #0
80065f8: 2140 movs r1, #64 @ 0x40
80065fa: 68f8 ldr r0, [r7, #12]
80065fc: f000 ffd0 bl 80075a0 <UART_WaitOnFlagUntilTimeout>
8006600: 4603 mov r3, r0
8006602: 2b00 cmp r3, #0
8006604: d005 beq.n 8006612 <HAL_UART_Transmit+0x106>
{
huart->gState = HAL_UART_STATE_READY;
8006606: 68fb ldr r3, [r7, #12]
8006608: 2220 movs r2, #32
800660a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
800660e: 2303 movs r3, #3
8006610: e006 b.n 8006620 <HAL_UART_Transmit+0x114>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8006612: 68fb ldr r3, [r7, #12]
8006614: 2220 movs r2, #32
8006616: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_OK;
800661a: 2300 movs r3, #0
800661c: e000 b.n 8006620 <HAL_UART_Transmit+0x114>
}
else
{
return HAL_BUSY;
800661e: 2302 movs r3, #2
}
}
8006620: 4618 mov r0, r3
8006622: 3720 adds r7, #32
8006624: 46bd mov sp, r7
8006626: bd80 pop {r7, pc}
08006628 <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8006628: b580 push {r7, lr}
800662a: b08a sub sp, #40 @ 0x28
800662c: af00 add r7, sp, #0
800662e: 60f8 str r0, [r7, #12]
8006630: 60b9 str r1, [r7, #8]
8006632: 4613 mov r3, r2
8006634: 80fb strh r3, [r7, #6]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8006636: 68fb ldr r3, [r7, #12]
8006638: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800663c: 2b20 cmp r3, #32
800663e: d137 bne.n 80066b0 <HAL_UART_Receive_IT+0x88>
{
if ((pData == NULL) || (Size == 0U))
8006640: 68bb ldr r3, [r7, #8]
8006642: 2b00 cmp r3, #0
8006644: d002 beq.n 800664c <HAL_UART_Receive_IT+0x24>
8006646: 88fb ldrh r3, [r7, #6]
8006648: 2b00 cmp r3, #0
800664a: d101 bne.n 8006650 <HAL_UART_Receive_IT+0x28>
{
return HAL_ERROR;
800664c: 2301 movs r3, #1
800664e: e030 b.n 80066b2 <HAL_UART_Receive_IT+0x8a>
}
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006650: 68fb ldr r3, [r7, #12]
8006652: 2200 movs r2, #0
8006654: 66da str r2, [r3, #108] @ 0x6c
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8006656: 68fb ldr r3, [r7, #12]
8006658: 681b ldr r3, [r3, #0]
800665a: 4a18 ldr r2, [pc, #96] @ (80066bc <HAL_UART_Receive_IT+0x94>)
800665c: 4293 cmp r3, r2
800665e: d01f beq.n 80066a0 <HAL_UART_Receive_IT+0x78>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8006660: 68fb ldr r3, [r7, #12]
8006662: 681b ldr r3, [r3, #0]
8006664: 685b ldr r3, [r3, #4]
8006666: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800666a: 2b00 cmp r3, #0
800666c: d018 beq.n 80066a0 <HAL_UART_Receive_IT+0x78>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
800666e: 68fb ldr r3, [r7, #12]
8006670: 681b ldr r3, [r3, #0]
8006672: 617b str r3, [r7, #20]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006674: 697b ldr r3, [r7, #20]
8006676: e853 3f00 ldrex r3, [r3]
800667a: 613b str r3, [r7, #16]
return(result);
800667c: 693b ldr r3, [r7, #16]
800667e: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8006682: 627b str r3, [r7, #36] @ 0x24
8006684: 68fb ldr r3, [r7, #12]
8006686: 681b ldr r3, [r3, #0]
8006688: 461a mov r2, r3
800668a: 6a7b ldr r3, [r7, #36] @ 0x24
800668c: 623b str r3, [r7, #32]
800668e: 61fa str r2, [r7, #28]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006690: 69f9 ldr r1, [r7, #28]
8006692: 6a3a ldr r2, [r7, #32]
8006694: e841 2300 strex r3, r2, [r1]
8006698: 61bb str r3, [r7, #24]
return(result);
800669a: 69bb ldr r3, [r7, #24]
800669c: 2b00 cmp r3, #0
800669e: d1e6 bne.n 800666e <HAL_UART_Receive_IT+0x46>
}
}
return (UART_Start_Receive_IT(huart, pData, Size));
80066a0: 88fb ldrh r3, [r7, #6]
80066a2: 461a mov r2, r3
80066a4: 68b9 ldr r1, [r7, #8]
80066a6: 68f8 ldr r0, [r7, #12]
80066a8: f000 ffe8 bl 800767c <UART_Start_Receive_IT>
80066ac: 4603 mov r3, r0
80066ae: e000 b.n 80066b2 <HAL_UART_Receive_IT+0x8a>
}
else
{
return HAL_BUSY;
80066b0: 2302 movs r3, #2
}
}
80066b2: 4618 mov r0, r3
80066b4: 3728 adds r7, #40 @ 0x28
80066b6: 46bd mov sp, r7
80066b8: bd80 pop {r7, pc}
80066ba: bf00 nop
80066bc: 40008000 .word 0x40008000
080066c0 <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
80066c0: b580 push {r7, lr}
80066c2: b0ba sub sp, #232 @ 0xe8
80066c4: af00 add r7, sp, #0
80066c6: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
80066c8: 687b ldr r3, [r7, #4]
80066ca: 681b ldr r3, [r3, #0]
80066cc: 69db ldr r3, [r3, #28]
80066ce: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80066d2: 687b ldr r3, [r7, #4]
80066d4: 681b ldr r3, [r3, #0]
80066d6: 681b ldr r3, [r3, #0]
80066d8: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
80066dc: 687b ldr r3, [r7, #4]
80066de: 681b ldr r3, [r3, #0]
80066e0: 689b ldr r3, [r3, #8]
80066e2: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
80066e6: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
80066ea: f640 030f movw r3, #2063 @ 0x80f
80066ee: 4013 ands r3, r2
80066f0: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (errorflags == 0U)
80066f4: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
80066f8: 2b00 cmp r3, #0
80066fa: d11b bne.n 8006734 <HAL_UART_IRQHandler+0x74>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
80066fc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006700: f003 0320 and.w r3, r3, #32
8006704: 2b00 cmp r3, #0
8006706: d015 beq.n 8006734 <HAL_UART_IRQHandler+0x74>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
8006708: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800670c: f003 0320 and.w r3, r3, #32
8006710: 2b00 cmp r3, #0
8006712: d105 bne.n 8006720 <HAL_UART_IRQHandler+0x60>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8006714: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006718: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800671c: 2b00 cmp r3, #0
800671e: d009 beq.n 8006734 <HAL_UART_IRQHandler+0x74>
{
if (huart->RxISR != NULL)
8006720: 687b ldr r3, [r7, #4]
8006722: 6f5b ldr r3, [r3, #116] @ 0x74
8006724: 2b00 cmp r3, #0
8006726: f000 8300 beq.w 8006d2a <HAL_UART_IRQHandler+0x66a>
{
huart->RxISR(huart);
800672a: 687b ldr r3, [r7, #4]
800672c: 6f5b ldr r3, [r3, #116] @ 0x74
800672e: 6878 ldr r0, [r7, #4]
8006730: 4798 blx r3
}
return;
8006732: e2fa b.n 8006d2a <HAL_UART_IRQHandler+0x66a>
}
}
/* If some errors occur */
if ((errorflags != 0U)
8006734: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8006738: 2b00 cmp r3, #0
800673a: f000 8123 beq.w 8006984 <HAL_UART_IRQHandler+0x2c4>
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
800673e: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
8006742: 4b8d ldr r3, [pc, #564] @ (8006978 <HAL_UART_IRQHandler+0x2b8>)
8006744: 4013 ands r3, r2
8006746: 2b00 cmp r3, #0
8006748: d106 bne.n 8006758 <HAL_UART_IRQHandler+0x98>
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
800674a: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
800674e: 4b8b ldr r3, [pc, #556] @ (800697c <HAL_UART_IRQHandler+0x2bc>)
8006750: 4013 ands r3, r2
8006752: 2b00 cmp r3, #0
8006754: f000 8116 beq.w 8006984 <HAL_UART_IRQHandler+0x2c4>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8006758: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800675c: f003 0301 and.w r3, r3, #1
8006760: 2b00 cmp r3, #0
8006762: d011 beq.n 8006788 <HAL_UART_IRQHandler+0xc8>
8006764: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006768: f403 7380 and.w r3, r3, #256 @ 0x100
800676c: 2b00 cmp r3, #0
800676e: d00b beq.n 8006788 <HAL_UART_IRQHandler+0xc8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8006770: 687b ldr r3, [r7, #4]
8006772: 681b ldr r3, [r3, #0]
8006774: 2201 movs r2, #1
8006776: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8006778: 687b ldr r3, [r7, #4]
800677a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800677e: f043 0201 orr.w r2, r3, #1
8006782: 687b ldr r3, [r7, #4]
8006784: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8006788: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800678c: f003 0302 and.w r3, r3, #2
8006790: 2b00 cmp r3, #0
8006792: d011 beq.n 80067b8 <HAL_UART_IRQHandler+0xf8>
8006794: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006798: f003 0301 and.w r3, r3, #1
800679c: 2b00 cmp r3, #0
800679e: d00b beq.n 80067b8 <HAL_UART_IRQHandler+0xf8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
80067a0: 687b ldr r3, [r7, #4]
80067a2: 681b ldr r3, [r3, #0]
80067a4: 2202 movs r2, #2
80067a6: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
80067a8: 687b ldr r3, [r7, #4]
80067aa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80067ae: f043 0204 orr.w r2, r3, #4
80067b2: 687b ldr r3, [r7, #4]
80067b4: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80067b8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80067bc: f003 0304 and.w r3, r3, #4
80067c0: 2b00 cmp r3, #0
80067c2: d011 beq.n 80067e8 <HAL_UART_IRQHandler+0x128>
80067c4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80067c8: f003 0301 and.w r3, r3, #1
80067cc: 2b00 cmp r3, #0
80067ce: d00b beq.n 80067e8 <HAL_UART_IRQHandler+0x128>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
80067d0: 687b ldr r3, [r7, #4]
80067d2: 681b ldr r3, [r3, #0]
80067d4: 2204 movs r2, #4
80067d6: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
80067d8: 687b ldr r3, [r7, #4]
80067da: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80067de: f043 0202 orr.w r2, r3, #2
80067e2: 687b ldr r3, [r7, #4]
80067e4: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U)
80067e8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80067ec: f003 0308 and.w r3, r3, #8
80067f0: 2b00 cmp r3, #0
80067f2: d017 beq.n 8006824 <HAL_UART_IRQHandler+0x164>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
80067f4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80067f8: f003 0320 and.w r3, r3, #32
80067fc: 2b00 cmp r3, #0
80067fe: d105 bne.n 800680c <HAL_UART_IRQHandler+0x14c>
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
8006800: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
8006804: 4b5c ldr r3, [pc, #368] @ (8006978 <HAL_UART_IRQHandler+0x2b8>)
8006806: 4013 ands r3, r2
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
8006808: 2b00 cmp r3, #0
800680a: d00b beq.n 8006824 <HAL_UART_IRQHandler+0x164>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
800680c: 687b ldr r3, [r7, #4]
800680e: 681b ldr r3, [r3, #0]
8006810: 2208 movs r2, #8
8006812: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8006814: 687b ldr r3, [r7, #4]
8006816: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800681a: f043 0208 orr.w r2, r3, #8
800681e: 687b ldr r3, [r7, #4]
8006820: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
8006824: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006828: f403 6300 and.w r3, r3, #2048 @ 0x800
800682c: 2b00 cmp r3, #0
800682e: d012 beq.n 8006856 <HAL_UART_IRQHandler+0x196>
8006830: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006834: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8006838: 2b00 cmp r3, #0
800683a: d00c beq.n 8006856 <HAL_UART_IRQHandler+0x196>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
800683c: 687b ldr r3, [r7, #4]
800683e: 681b ldr r3, [r3, #0]
8006840: f44f 6200 mov.w r2, #2048 @ 0x800
8006844: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
8006846: 687b ldr r3, [r7, #4]
8006848: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800684c: f043 0220 orr.w r2, r3, #32
8006850: 687b ldr r3, [r7, #4]
8006852: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8006856: 687b ldr r3, [r7, #4]
8006858: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800685c: 2b00 cmp r3, #0
800685e: f000 8266 beq.w 8006d2e <HAL_UART_IRQHandler+0x66e>
{
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
8006862: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006866: f003 0320 and.w r3, r3, #32
800686a: 2b00 cmp r3, #0
800686c: d013 beq.n 8006896 <HAL_UART_IRQHandler+0x1d6>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
800686e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006872: f003 0320 and.w r3, r3, #32
8006876: 2b00 cmp r3, #0
8006878: d105 bne.n 8006886 <HAL_UART_IRQHandler+0x1c6>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
800687a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
800687e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8006882: 2b00 cmp r3, #0
8006884: d007 beq.n 8006896 <HAL_UART_IRQHandler+0x1d6>
{
if (huart->RxISR != NULL)
8006886: 687b ldr r3, [r7, #4]
8006888: 6f5b ldr r3, [r3, #116] @ 0x74
800688a: 2b00 cmp r3, #0
800688c: d003 beq.n 8006896 <HAL_UART_IRQHandler+0x1d6>
{
huart->RxISR(huart);
800688e: 687b ldr r3, [r7, #4]
8006890: 6f5b ldr r3, [r3, #116] @ 0x74
8006892: 6878 ldr r0, [r7, #4]
8006894: 4798 blx r3
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
8006896: 687b ldr r3, [r7, #4]
8006898: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800689c: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
80068a0: 687b ldr r3, [r7, #4]
80068a2: 681b ldr r3, [r3, #0]
80068a4: 689b ldr r3, [r3, #8]
80068a6: f003 0340 and.w r3, r3, #64 @ 0x40
80068aa: 2b40 cmp r3, #64 @ 0x40
80068ac: d005 beq.n 80068ba <HAL_UART_IRQHandler+0x1fa>
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
80068ae: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
80068b2: f003 0328 and.w r3, r3, #40 @ 0x28
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
80068b6: 2b00 cmp r3, #0
80068b8: d054 beq.n 8006964 <HAL_UART_IRQHandler+0x2a4>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
80068ba: 6878 ldr r0, [r7, #4]
80068bc: f001 f800 bl 80078c0 <UART_EndRxTransfer>
/* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80068c0: 687b ldr r3, [r7, #4]
80068c2: 681b ldr r3, [r3, #0]
80068c4: 689b ldr r3, [r3, #8]
80068c6: f003 0340 and.w r3, r3, #64 @ 0x40
80068ca: 2b40 cmp r3, #64 @ 0x40
80068cc: d146 bne.n 800695c <HAL_UART_IRQHandler+0x29c>
{
/* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80068ce: 687b ldr r3, [r7, #4]
80068d0: 681b ldr r3, [r3, #0]
80068d2: 3308 adds r3, #8
80068d4: f8c7 309c str.w r3, [r7, #156] @ 0x9c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80068d8: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
80068dc: e853 3f00 ldrex r3, [r3]
80068e0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
return(result);
80068e4: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80068e8: f023 0340 bic.w r3, r3, #64 @ 0x40
80068ec: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
80068f0: 687b ldr r3, [r7, #4]
80068f2: 681b ldr r3, [r3, #0]
80068f4: 3308 adds r3, #8
80068f6: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
80068fa: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
80068fe: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006902: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
8006906: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
800690a: e841 2300 strex r3, r2, [r1]
800690e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return(result);
8006912: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8006916: 2b00 cmp r3, #0
8006918: d1d9 bne.n 80068ce <HAL_UART_IRQHandler+0x20e>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
800691a: 687b ldr r3, [r7, #4]
800691c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006920: 2b00 cmp r3, #0
8006922: d017 beq.n 8006954 <HAL_UART_IRQHandler+0x294>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8006924: 687b ldr r3, [r7, #4]
8006926: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800692a: 4a15 ldr r2, [pc, #84] @ (8006980 <HAL_UART_IRQHandler+0x2c0>)
800692c: 639a str r2, [r3, #56] @ 0x38
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
800692e: 687b ldr r3, [r7, #4]
8006930: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006934: 4618 mov r0, r3
8006936: f7fd f8d5 bl 8003ae4 <HAL_DMA_Abort_IT>
800693a: 4603 mov r3, r0
800693c: 2b00 cmp r3, #0
800693e: d019 beq.n 8006974 <HAL_UART_IRQHandler+0x2b4>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
8006940: 687b ldr r3, [r7, #4]
8006942: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006946: 6b9b ldr r3, [r3, #56] @ 0x38
8006948: 687a ldr r2, [r7, #4]
800694a: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80
800694e: 4610 mov r0, r2
8006950: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006952: e00f b.n 8006974 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006954: 6878 ldr r0, [r7, #4]
8006956: f000 f9f5 bl 8006d44 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800695a: e00b b.n 8006974 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800695c: 6878 ldr r0, [r7, #4]
800695e: f000 f9f1 bl 8006d44 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006962: e007 b.n 8006974 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006964: 6878 ldr r0, [r7, #4]
8006966: f000 f9ed bl 8006d44 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800696a: 687b ldr r3, [r7, #4]
800696c: 2200 movs r2, #0
800696e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
return;
8006972: e1dc b.n 8006d2e <HAL_UART_IRQHandler+0x66e>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006974: bf00 nop
return;
8006976: e1da b.n 8006d2e <HAL_UART_IRQHandler+0x66e>
8006978: 10000001 .word 0x10000001
800697c: 04000120 .word 0x04000120
8006980: 0800798d .word 0x0800798d
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006984: 687b ldr r3, [r7, #4]
8006986: 6edb ldr r3, [r3, #108] @ 0x6c
8006988: 2b01 cmp r3, #1
800698a: f040 8170 bne.w 8006c6e <HAL_UART_IRQHandler+0x5ae>
&& ((isrflags & USART_ISR_IDLE) != 0U)
800698e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006992: f003 0310 and.w r3, r3, #16
8006996: 2b00 cmp r3, #0
8006998: f000 8169 beq.w 8006c6e <HAL_UART_IRQHandler+0x5ae>
&& ((cr1its & USART_ISR_IDLE) != 0U))
800699c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80069a0: f003 0310 and.w r3, r3, #16
80069a4: 2b00 cmp r3, #0
80069a6: f000 8162 beq.w 8006c6e <HAL_UART_IRQHandler+0x5ae>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
80069aa: 687b ldr r3, [r7, #4]
80069ac: 681b ldr r3, [r3, #0]
80069ae: 2210 movs r2, #16
80069b0: 621a str r2, [r3, #32]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80069b2: 687b ldr r3, [r7, #4]
80069b4: 681b ldr r3, [r3, #0]
80069b6: 689b ldr r3, [r3, #8]
80069b8: f003 0340 and.w r3, r3, #64 @ 0x40
80069bc: 2b40 cmp r3, #64 @ 0x40
80069be: f040 80d8 bne.w 8006b72 <HAL_UART_IRQHandler+0x4b2>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
80069c2: 687b ldr r3, [r7, #4]
80069c4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80069c8: 681b ldr r3, [r3, #0]
80069ca: 685b ldr r3, [r3, #4]
80069cc: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
if ((nb_remaining_rx_data > 0U)
80069d0: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
80069d4: 2b00 cmp r3, #0
80069d6: f000 80af beq.w 8006b38 <HAL_UART_IRQHandler+0x478>
&& (nb_remaining_rx_data < huart->RxXferSize))
80069da: 687b ldr r3, [r7, #4]
80069dc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
80069e0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
80069e4: 429a cmp r2, r3
80069e6: f080 80a7 bcs.w 8006b38 <HAL_UART_IRQHandler+0x478>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
80069ea: 687b ldr r3, [r7, #4]
80069ec: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
80069f0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
80069f4: 687b ldr r3, [r7, #4]
80069f6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80069fa: 681b ldr r3, [r3, #0]
80069fc: 681b ldr r3, [r3, #0]
80069fe: f003 0320 and.w r3, r3, #32
8006a02: 2b00 cmp r3, #0
8006a04: f040 8087 bne.w 8006b16 <HAL_UART_IRQHandler+0x456>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8006a08: 687b ldr r3, [r7, #4]
8006a0a: 681b ldr r3, [r3, #0]
8006a0c: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006a10: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8006a14: e853 3f00 ldrex r3, [r3]
8006a18: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return(result);
8006a1c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8006a20: f423 7380 bic.w r3, r3, #256 @ 0x100
8006a24: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8006a28: 687b ldr r3, [r7, #4]
8006a2a: 681b ldr r3, [r3, #0]
8006a2c: 461a mov r2, r3
8006a2e: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006a32: f8c7 3094 str.w r3, [r7, #148] @ 0x94
8006a36: f8c7 2090 str.w r2, [r7, #144] @ 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006a3a: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
8006a3e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
8006a42: e841 2300 strex r3, r2, [r1]
8006a46: f8c7 308c str.w r3, [r7, #140] @ 0x8c
return(result);
8006a4a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006a4e: 2b00 cmp r3, #0
8006a50: d1da bne.n 8006a08 <HAL_UART_IRQHandler+0x348>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006a52: 687b ldr r3, [r7, #4]
8006a54: 681b ldr r3, [r3, #0]
8006a56: 3308 adds r3, #8
8006a58: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006a5a: 6f7b ldr r3, [r7, #116] @ 0x74
8006a5c: e853 3f00 ldrex r3, [r3]
8006a60: 673b str r3, [r7, #112] @ 0x70
return(result);
8006a62: 6f3b ldr r3, [r7, #112] @ 0x70
8006a64: f023 0301 bic.w r3, r3, #1
8006a68: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
8006a6c: 687b ldr r3, [r7, #4]
8006a6e: 681b ldr r3, [r3, #0]
8006a70: 3308 adds r3, #8
8006a72: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
8006a76: f8c7 2080 str.w r2, [r7, #128] @ 0x80
8006a7a: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006a7c: 6ff9 ldr r1, [r7, #124] @ 0x7c
8006a7e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
8006a82: e841 2300 strex r3, r2, [r1]
8006a86: 67bb str r3, [r7, #120] @ 0x78
return(result);
8006a88: 6fbb ldr r3, [r7, #120] @ 0x78
8006a8a: 2b00 cmp r3, #0
8006a8c: d1e1 bne.n 8006a52 <HAL_UART_IRQHandler+0x392>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8006a8e: 687b ldr r3, [r7, #4]
8006a90: 681b ldr r3, [r3, #0]
8006a92: 3308 adds r3, #8
8006a94: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006a96: 6e3b ldr r3, [r7, #96] @ 0x60
8006a98: e853 3f00 ldrex r3, [r3]
8006a9c: 65fb str r3, [r7, #92] @ 0x5c
return(result);
8006a9e: 6dfb ldr r3, [r7, #92] @ 0x5c
8006aa0: f023 0340 bic.w r3, r3, #64 @ 0x40
8006aa4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8006aa8: 687b ldr r3, [r7, #4]
8006aaa: 681b ldr r3, [r3, #0]
8006aac: 3308 adds r3, #8
8006aae: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
8006ab2: 66fa str r2, [r7, #108] @ 0x6c
8006ab4: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006ab6: 6eb9 ldr r1, [r7, #104] @ 0x68
8006ab8: 6efa ldr r2, [r7, #108] @ 0x6c
8006aba: e841 2300 strex r3, r2, [r1]
8006abe: 667b str r3, [r7, #100] @ 0x64
return(result);
8006ac0: 6e7b ldr r3, [r7, #100] @ 0x64
8006ac2: 2b00 cmp r3, #0
8006ac4: d1e3 bne.n 8006a8e <HAL_UART_IRQHandler+0x3ce>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006ac6: 687b ldr r3, [r7, #4]
8006ac8: 2220 movs r2, #32
8006aca: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006ace: 687b ldr r3, [r7, #4]
8006ad0: 2200 movs r2, #0
8006ad2: 66da str r2, [r3, #108] @ 0x6c
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006ad4: 687b ldr r3, [r7, #4]
8006ad6: 681b ldr r3, [r3, #0]
8006ad8: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006ada: 6cfb ldr r3, [r7, #76] @ 0x4c
8006adc: e853 3f00 ldrex r3, [r3]
8006ae0: 64bb str r3, [r7, #72] @ 0x48
return(result);
8006ae2: 6cbb ldr r3, [r7, #72] @ 0x48
8006ae4: f023 0310 bic.w r3, r3, #16
8006ae8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8006aec: 687b ldr r3, [r7, #4]
8006aee: 681b ldr r3, [r3, #0]
8006af0: 461a mov r2, r3
8006af2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8006af6: 65bb str r3, [r7, #88] @ 0x58
8006af8: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006afa: 6d79 ldr r1, [r7, #84] @ 0x54
8006afc: 6dba ldr r2, [r7, #88] @ 0x58
8006afe: e841 2300 strex r3, r2, [r1]
8006b02: 653b str r3, [r7, #80] @ 0x50
return(result);
8006b04: 6d3b ldr r3, [r7, #80] @ 0x50
8006b06: 2b00 cmp r3, #0
8006b08: d1e4 bne.n 8006ad4 <HAL_UART_IRQHandler+0x414>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8006b0a: 687b ldr r3, [r7, #4]
8006b0c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006b10: 4618 mov r0, r3
8006b12: f7fc ff8e bl 8003a32 <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006b16: 687b ldr r3, [r7, #4]
8006b18: 2202 movs r2, #2
8006b1a: 671a str r2, [r3, #112] @ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8006b1c: 687b ldr r3, [r7, #4]
8006b1e: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
8006b22: 687b ldr r3, [r7, #4]
8006b24: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8006b28: b29b uxth r3, r3
8006b2a: 1ad3 subs r3, r2, r3
8006b2c: b29b uxth r3, r3
8006b2e: 4619 mov r1, r3
8006b30: 6878 ldr r0, [r7, #4]
8006b32: f000 f911 bl 8006d58 <HAL_UARTEx_RxEventCallback>
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
}
}
return;
8006b36: e0fc b.n 8006d32 <HAL_UART_IRQHandler+0x672>
if (nb_remaining_rx_data == huart->RxXferSize)
8006b38: 687b ldr r3, [r7, #4]
8006b3a: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8006b3e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8006b42: 429a cmp r2, r3
8006b44: f040 80f5 bne.w 8006d32 <HAL_UART_IRQHandler+0x672>
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
8006b48: 687b ldr r3, [r7, #4]
8006b4a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006b4e: 681b ldr r3, [r3, #0]
8006b50: 681b ldr r3, [r3, #0]
8006b52: f003 0320 and.w r3, r3, #32
8006b56: 2b20 cmp r3, #32
8006b58: f040 80eb bne.w 8006d32 <HAL_UART_IRQHandler+0x672>
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006b5c: 687b ldr r3, [r7, #4]
8006b5e: 2202 movs r2, #2
8006b60: 671a str r2, [r3, #112] @ 0x70
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006b62: 687b ldr r3, [r7, #4]
8006b64: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8006b68: 4619 mov r1, r3
8006b6a: 6878 ldr r0, [r7, #4]
8006b6c: f000 f8f4 bl 8006d58 <HAL_UARTEx_RxEventCallback>
return;
8006b70: e0df b.n 8006d32 <HAL_UART_IRQHandler+0x672>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8006b72: 687b ldr r3, [r7, #4]
8006b74: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
8006b78: 687b ldr r3, [r7, #4]
8006b7a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8006b7e: b29b uxth r3, r3
8006b80: 1ad3 subs r3, r2, r3
8006b82: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
if ((huart->RxXferCount > 0U)
8006b86: 687b ldr r3, [r7, #4]
8006b88: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8006b8c: b29b uxth r3, r3
8006b8e: 2b00 cmp r3, #0
8006b90: f000 80d1 beq.w 8006d36 <HAL_UART_IRQHandler+0x676>
&& (nb_rx_data > 0U))
8006b94: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8006b98: 2b00 cmp r3, #0
8006b9a: f000 80cc beq.w 8006d36 <HAL_UART_IRQHandler+0x676>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006b9e: 687b ldr r3, [r7, #4]
8006ba0: 681b ldr r3, [r3, #0]
8006ba2: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006ba4: 6bbb ldr r3, [r7, #56] @ 0x38
8006ba6: e853 3f00 ldrex r3, [r3]
8006baa: 637b str r3, [r7, #52] @ 0x34
return(result);
8006bac: 6b7b ldr r3, [r7, #52] @ 0x34
8006bae: f423 7390 bic.w r3, r3, #288 @ 0x120
8006bb2: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8006bb6: 687b ldr r3, [r7, #4]
8006bb8: 681b ldr r3, [r3, #0]
8006bba: 461a mov r2, r3
8006bbc: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8006bc0: 647b str r3, [r7, #68] @ 0x44
8006bc2: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006bc4: 6c39 ldr r1, [r7, #64] @ 0x40
8006bc6: 6c7a ldr r2, [r7, #68] @ 0x44
8006bc8: e841 2300 strex r3, r2, [r1]
8006bcc: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8006bce: 6bfb ldr r3, [r7, #60] @ 0x3c
8006bd0: 2b00 cmp r3, #0
8006bd2: d1e4 bne.n 8006b9e <HAL_UART_IRQHandler+0x4de>
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8006bd4: 687b ldr r3, [r7, #4]
8006bd6: 681b ldr r3, [r3, #0]
8006bd8: 3308 adds r3, #8
8006bda: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006bdc: 6a7b ldr r3, [r7, #36] @ 0x24
8006bde: e853 3f00 ldrex r3, [r3]
8006be2: 623b str r3, [r7, #32]
return(result);
8006be4: 6a3b ldr r3, [r7, #32]
8006be6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8006bea: f023 0301 bic.w r3, r3, #1
8006bee: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8006bf2: 687b ldr r3, [r7, #4]
8006bf4: 681b ldr r3, [r3, #0]
8006bf6: 3308 adds r3, #8
8006bf8: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
8006bfc: 633a str r2, [r7, #48] @ 0x30
8006bfe: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006c00: 6af9 ldr r1, [r7, #44] @ 0x2c
8006c02: 6b3a ldr r2, [r7, #48] @ 0x30
8006c04: e841 2300 strex r3, r2, [r1]
8006c08: 62bb str r3, [r7, #40] @ 0x28
return(result);
8006c0a: 6abb ldr r3, [r7, #40] @ 0x28
8006c0c: 2b00 cmp r3, #0
8006c0e: d1e1 bne.n 8006bd4 <HAL_UART_IRQHandler+0x514>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006c10: 687b ldr r3, [r7, #4]
8006c12: 2220 movs r2, #32
8006c14: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006c18: 687b ldr r3, [r7, #4]
8006c1a: 2200 movs r2, #0
8006c1c: 66da str r2, [r3, #108] @ 0x6c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006c1e: 687b ldr r3, [r7, #4]
8006c20: 2200 movs r2, #0
8006c22: 675a str r2, [r3, #116] @ 0x74
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006c24: 687b ldr r3, [r7, #4]
8006c26: 681b ldr r3, [r3, #0]
8006c28: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006c2a: 693b ldr r3, [r7, #16]
8006c2c: e853 3f00 ldrex r3, [r3]
8006c30: 60fb str r3, [r7, #12]
return(result);
8006c32: 68fb ldr r3, [r7, #12]
8006c34: f023 0310 bic.w r3, r3, #16
8006c38: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8006c3c: 687b ldr r3, [r7, #4]
8006c3e: 681b ldr r3, [r3, #0]
8006c40: 461a mov r2, r3
8006c42: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8006c46: 61fb str r3, [r7, #28]
8006c48: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006c4a: 69b9 ldr r1, [r7, #24]
8006c4c: 69fa ldr r2, [r7, #28]
8006c4e: e841 2300 strex r3, r2, [r1]
8006c52: 617b str r3, [r7, #20]
return(result);
8006c54: 697b ldr r3, [r7, #20]
8006c56: 2b00 cmp r3, #0
8006c58: d1e4 bne.n 8006c24 <HAL_UART_IRQHandler+0x564>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006c5a: 687b ldr r3, [r7, #4]
8006c5c: 2202 movs r2, #2
8006c5e: 671a str r2, [r3, #112] @ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8006c60: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8006c64: 4619 mov r1, r3
8006c66: 6878 ldr r0, [r7, #4]
8006c68: f000 f876 bl 8006d58 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8006c6c: e063 b.n 8006d36 <HAL_UART_IRQHandler+0x676>
}
}
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
8006c6e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006c72: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8006c76: 2b00 cmp r3, #0
8006c78: d00e beq.n 8006c98 <HAL_UART_IRQHandler+0x5d8>
8006c7a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006c7e: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8006c82: 2b00 cmp r3, #0
8006c84: d008 beq.n 8006c98 <HAL_UART_IRQHandler+0x5d8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8006c86: 687b ldr r3, [r7, #4]
8006c88: 681b ldr r3, [r3, #0]
8006c8a: f44f 1280 mov.w r2, #1048576 @ 0x100000
8006c8e: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
8006c90: 6878 ldr r0, [r7, #4]
8006c92: f001 fbd9 bl 8008448 <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006c96: e051 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
8006c98: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006c9c: f003 0380 and.w r3, r3, #128 @ 0x80
8006ca0: 2b00 cmp r3, #0
8006ca2: d014 beq.n 8006cce <HAL_UART_IRQHandler+0x60e>
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
8006ca4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006ca8: f003 0380 and.w r3, r3, #128 @ 0x80
8006cac: 2b00 cmp r3, #0
8006cae: d105 bne.n 8006cbc <HAL_UART_IRQHandler+0x5fc>
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
8006cb0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006cb4: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8006cb8: 2b00 cmp r3, #0
8006cba: d008 beq.n 8006cce <HAL_UART_IRQHandler+0x60e>
{
if (huart->TxISR != NULL)
8006cbc: 687b ldr r3, [r7, #4]
8006cbe: 6f9b ldr r3, [r3, #120] @ 0x78
8006cc0: 2b00 cmp r3, #0
8006cc2: d03a beq.n 8006d3a <HAL_UART_IRQHandler+0x67a>
{
huart->TxISR(huart);
8006cc4: 687b ldr r3, [r7, #4]
8006cc6: 6f9b ldr r3, [r3, #120] @ 0x78
8006cc8: 6878 ldr r0, [r7, #4]
8006cca: 4798 blx r3
}
return;
8006ccc: e035 b.n 8006d3a <HAL_UART_IRQHandler+0x67a>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
8006cce: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006cd2: f003 0340 and.w r3, r3, #64 @ 0x40
8006cd6: 2b00 cmp r3, #0
8006cd8: d009 beq.n 8006cee <HAL_UART_IRQHandler+0x62e>
8006cda: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006cde: f003 0340 and.w r3, r3, #64 @ 0x40
8006ce2: 2b00 cmp r3, #0
8006ce4: d003 beq.n 8006cee <HAL_UART_IRQHandler+0x62e>
{
UART_EndTransmit_IT(huart);
8006ce6: 6878 ldr r0, [r7, #4]
8006ce8: f000 fe62 bl 80079b0 <UART_EndTransmit_IT>
return;
8006cec: e026 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
}
/* UART TX Fifo Empty occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
8006cee: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006cf2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8006cf6: 2b00 cmp r3, #0
8006cf8: d009 beq.n 8006d0e <HAL_UART_IRQHandler+0x64e>
8006cfa: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006cfe: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
8006d02: 2b00 cmp r3, #0
8006d04: d003 beq.n 8006d0e <HAL_UART_IRQHandler+0x64e>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Tx Fifo Empty Callback */
huart->TxFifoEmptyCallback(huart);
#else
/* Call legacy weak Tx Fifo Empty Callback */
HAL_UARTEx_TxFifoEmptyCallback(huart);
8006d06: 6878 ldr r0, [r7, #4]
8006d08: f001 fbb2 bl 8008470 <HAL_UARTEx_TxFifoEmptyCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006d0c: e016 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
}
/* UART RX Fifo Full occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
8006d0e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006d12: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8006d16: 2b00 cmp r3, #0
8006d18: d010 beq.n 8006d3c <HAL_UART_IRQHandler+0x67c>
8006d1a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006d1e: 2b00 cmp r3, #0
8006d20: da0c bge.n 8006d3c <HAL_UART_IRQHandler+0x67c>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Rx Fifo Full Callback */
huart->RxFifoFullCallback(huart);
#else
/* Call legacy weak Rx Fifo Full Callback */
HAL_UARTEx_RxFifoFullCallback(huart);
8006d22: 6878 ldr r0, [r7, #4]
8006d24: f001 fb9a bl 800845c <HAL_UARTEx_RxFifoFullCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006d28: e008 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
return;
8006d2a: bf00 nop
8006d2c: e006 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
return;
8006d2e: bf00 nop
8006d30: e004 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
return;
8006d32: bf00 nop
8006d34: e002 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
return;
8006d36: bf00 nop
8006d38: e000 b.n 8006d3c <HAL_UART_IRQHandler+0x67c>
return;
8006d3a: bf00 nop
}
}
8006d3c: 37e8 adds r7, #232 @ 0xe8
8006d3e: 46bd mov sp, r7
8006d40: bd80 pop {r7, pc}
8006d42: bf00 nop
08006d44 <HAL_UART_ErrorCallback>:
* @brief UART error callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
8006d44: b480 push {r7}
8006d46: b083 sub sp, #12
8006d48: af00 add r7, sp, #0
8006d4a: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file.
*/
}
8006d4c: bf00 nop
8006d4e: 370c adds r7, #12
8006d50: 46bd mov sp, r7
8006d52: f85d 7b04 ldr.w r7, [sp], #4
8006d56: 4770 bx lr
08006d58 <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8006d58: b480 push {r7}
8006d5a: b083 sub sp, #12
8006d5c: af00 add r7, sp, #0
8006d5e: 6078 str r0, [r7, #4]
8006d60: 460b mov r3, r1
8006d62: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8006d64: bf00 nop
8006d66: 370c adds r7, #12
8006d68: 46bd mov sp, r7
8006d6a: f85d 7b04 ldr.w r7, [sp], #4
8006d6e: 4770 bx lr
08006d70 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8006d70: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8006d74: b08c sub sp, #48 @ 0x30
8006d76: af00 add r7, sp, #0
8006d78: 6178 str r0, [r7, #20]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8006d7a: 2300 movs r3, #0
8006d7c: f887 302a strb.w r3, [r7, #42] @ 0x2a
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8006d80: 697b ldr r3, [r7, #20]
8006d82: 689a ldr r2, [r3, #8]
8006d84: 697b ldr r3, [r7, #20]
8006d86: 691b ldr r3, [r3, #16]
8006d88: 431a orrs r2, r3
8006d8a: 697b ldr r3, [r7, #20]
8006d8c: 695b ldr r3, [r3, #20]
8006d8e: 431a orrs r2, r3
8006d90: 697b ldr r3, [r7, #20]
8006d92: 69db ldr r3, [r3, #28]
8006d94: 4313 orrs r3, r2
8006d96: 62fb str r3, [r7, #44] @ 0x2c
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8006d98: 697b ldr r3, [r7, #20]
8006d9a: 681b ldr r3, [r3, #0]
8006d9c: 681a ldr r2, [r3, #0]
8006d9e: 4bab ldr r3, [pc, #684] @ (800704c <UART_SetConfig+0x2dc>)
8006da0: 4013 ands r3, r2
8006da2: 697a ldr r2, [r7, #20]
8006da4: 6812 ldr r2, [r2, #0]
8006da6: 6af9 ldr r1, [r7, #44] @ 0x2c
8006da8: 430b orrs r3, r1
8006daa: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8006dac: 697b ldr r3, [r7, #20]
8006dae: 681b ldr r3, [r3, #0]
8006db0: 685b ldr r3, [r3, #4]
8006db2: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8006db6: 697b ldr r3, [r7, #20]
8006db8: 68da ldr r2, [r3, #12]
8006dba: 697b ldr r3, [r7, #20]
8006dbc: 681b ldr r3, [r3, #0]
8006dbe: 430a orrs r2, r1
8006dc0: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8006dc2: 697b ldr r3, [r7, #20]
8006dc4: 699b ldr r3, [r3, #24]
8006dc6: 62fb str r3, [r7, #44] @ 0x2c
if (!(UART_INSTANCE_LOWPOWER(huart)))
8006dc8: 697b ldr r3, [r7, #20]
8006dca: 681b ldr r3, [r3, #0]
8006dcc: 4aa0 ldr r2, [pc, #640] @ (8007050 <UART_SetConfig+0x2e0>)
8006dce: 4293 cmp r3, r2
8006dd0: d004 beq.n 8006ddc <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
8006dd2: 697b ldr r3, [r7, #20]
8006dd4: 6a1b ldr r3, [r3, #32]
8006dd6: 6afa ldr r2, [r7, #44] @ 0x2c
8006dd8: 4313 orrs r3, r2
8006dda: 62fb str r3, [r7, #44] @ 0x2c
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8006ddc: 697b ldr r3, [r7, #20]
8006dde: 681b ldr r3, [r3, #0]
8006de0: 689b ldr r3, [r3, #8]
8006de2: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000
8006de6: f423 6330 bic.w r3, r3, #2816 @ 0xb00
8006dea: 697a ldr r2, [r7, #20]
8006dec: 6812 ldr r2, [r2, #0]
8006dee: 6af9 ldr r1, [r7, #44] @ 0x2c
8006df0: 430b orrs r3, r1
8006df2: 6093 str r3, [r2, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8006df4: 697b ldr r3, [r7, #20]
8006df6: 681b ldr r3, [r3, #0]
8006df8: 6adb ldr r3, [r3, #44] @ 0x2c
8006dfa: f023 010f bic.w r1, r3, #15
8006dfe: 697b ldr r3, [r7, #20]
8006e00: 6a5a ldr r2, [r3, #36] @ 0x24
8006e02: 697b ldr r3, [r7, #20]
8006e04: 681b ldr r3, [r3, #0]
8006e06: 430a orrs r2, r1
8006e08: 62da str r2, [r3, #44] @ 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8006e0a: 697b ldr r3, [r7, #20]
8006e0c: 681b ldr r3, [r3, #0]
8006e0e: 4a91 ldr r2, [pc, #580] @ (8007054 <UART_SetConfig+0x2e4>)
8006e10: 4293 cmp r3, r2
8006e12: d125 bne.n 8006e60 <UART_SetConfig+0xf0>
8006e14: 4b90 ldr r3, [pc, #576] @ (8007058 <UART_SetConfig+0x2e8>)
8006e16: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006e1a: f003 0303 and.w r3, r3, #3
8006e1e: 2b03 cmp r3, #3
8006e20: d81a bhi.n 8006e58 <UART_SetConfig+0xe8>
8006e22: a201 add r2, pc, #4 @ (adr r2, 8006e28 <UART_SetConfig+0xb8>)
8006e24: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006e28: 08006e39 .word 0x08006e39
8006e2c: 08006e49 .word 0x08006e49
8006e30: 08006e41 .word 0x08006e41
8006e34: 08006e51 .word 0x08006e51
8006e38: 2301 movs r3, #1
8006e3a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e3e: e0d6 b.n 8006fee <UART_SetConfig+0x27e>
8006e40: 2302 movs r3, #2
8006e42: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e46: e0d2 b.n 8006fee <UART_SetConfig+0x27e>
8006e48: 2304 movs r3, #4
8006e4a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e4e: e0ce b.n 8006fee <UART_SetConfig+0x27e>
8006e50: 2308 movs r3, #8
8006e52: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e56: e0ca b.n 8006fee <UART_SetConfig+0x27e>
8006e58: 2310 movs r3, #16
8006e5a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e5e: e0c6 b.n 8006fee <UART_SetConfig+0x27e>
8006e60: 697b ldr r3, [r7, #20]
8006e62: 681b ldr r3, [r3, #0]
8006e64: 4a7d ldr r2, [pc, #500] @ (800705c <UART_SetConfig+0x2ec>)
8006e66: 4293 cmp r3, r2
8006e68: d138 bne.n 8006edc <UART_SetConfig+0x16c>
8006e6a: 4b7b ldr r3, [pc, #492] @ (8007058 <UART_SetConfig+0x2e8>)
8006e6c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006e70: f003 030c and.w r3, r3, #12
8006e74: 2b0c cmp r3, #12
8006e76: d82d bhi.n 8006ed4 <UART_SetConfig+0x164>
8006e78: a201 add r2, pc, #4 @ (adr r2, 8006e80 <UART_SetConfig+0x110>)
8006e7a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006e7e: bf00 nop
8006e80: 08006eb5 .word 0x08006eb5
8006e84: 08006ed5 .word 0x08006ed5
8006e88: 08006ed5 .word 0x08006ed5
8006e8c: 08006ed5 .word 0x08006ed5
8006e90: 08006ec5 .word 0x08006ec5
8006e94: 08006ed5 .word 0x08006ed5
8006e98: 08006ed5 .word 0x08006ed5
8006e9c: 08006ed5 .word 0x08006ed5
8006ea0: 08006ebd .word 0x08006ebd
8006ea4: 08006ed5 .word 0x08006ed5
8006ea8: 08006ed5 .word 0x08006ed5
8006eac: 08006ed5 .word 0x08006ed5
8006eb0: 08006ecd .word 0x08006ecd
8006eb4: 2300 movs r3, #0
8006eb6: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006eba: e098 b.n 8006fee <UART_SetConfig+0x27e>
8006ebc: 2302 movs r3, #2
8006ebe: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006ec2: e094 b.n 8006fee <UART_SetConfig+0x27e>
8006ec4: 2304 movs r3, #4
8006ec6: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006eca: e090 b.n 8006fee <UART_SetConfig+0x27e>
8006ecc: 2308 movs r3, #8
8006ece: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006ed2: e08c b.n 8006fee <UART_SetConfig+0x27e>
8006ed4: 2310 movs r3, #16
8006ed6: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006eda: e088 b.n 8006fee <UART_SetConfig+0x27e>
8006edc: 697b ldr r3, [r7, #20]
8006ede: 681b ldr r3, [r3, #0]
8006ee0: 4a5f ldr r2, [pc, #380] @ (8007060 <UART_SetConfig+0x2f0>)
8006ee2: 4293 cmp r3, r2
8006ee4: d125 bne.n 8006f32 <UART_SetConfig+0x1c2>
8006ee6: 4b5c ldr r3, [pc, #368] @ (8007058 <UART_SetConfig+0x2e8>)
8006ee8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006eec: f003 0330 and.w r3, r3, #48 @ 0x30
8006ef0: 2b30 cmp r3, #48 @ 0x30
8006ef2: d016 beq.n 8006f22 <UART_SetConfig+0x1b2>
8006ef4: 2b30 cmp r3, #48 @ 0x30
8006ef6: d818 bhi.n 8006f2a <UART_SetConfig+0x1ba>
8006ef8: 2b20 cmp r3, #32
8006efa: d00a beq.n 8006f12 <UART_SetConfig+0x1a2>
8006efc: 2b20 cmp r3, #32
8006efe: d814 bhi.n 8006f2a <UART_SetConfig+0x1ba>
8006f00: 2b00 cmp r3, #0
8006f02: d002 beq.n 8006f0a <UART_SetConfig+0x19a>
8006f04: 2b10 cmp r3, #16
8006f06: d008 beq.n 8006f1a <UART_SetConfig+0x1aa>
8006f08: e00f b.n 8006f2a <UART_SetConfig+0x1ba>
8006f0a: 2300 movs r3, #0
8006f0c: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f10: e06d b.n 8006fee <UART_SetConfig+0x27e>
8006f12: 2302 movs r3, #2
8006f14: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f18: e069 b.n 8006fee <UART_SetConfig+0x27e>
8006f1a: 2304 movs r3, #4
8006f1c: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f20: e065 b.n 8006fee <UART_SetConfig+0x27e>
8006f22: 2308 movs r3, #8
8006f24: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f28: e061 b.n 8006fee <UART_SetConfig+0x27e>
8006f2a: 2310 movs r3, #16
8006f2c: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f30: e05d b.n 8006fee <UART_SetConfig+0x27e>
8006f32: 697b ldr r3, [r7, #20]
8006f34: 681b ldr r3, [r3, #0]
8006f36: 4a4b ldr r2, [pc, #300] @ (8007064 <UART_SetConfig+0x2f4>)
8006f38: 4293 cmp r3, r2
8006f3a: d125 bne.n 8006f88 <UART_SetConfig+0x218>
8006f3c: 4b46 ldr r3, [pc, #280] @ (8007058 <UART_SetConfig+0x2e8>)
8006f3e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006f42: f003 03c0 and.w r3, r3, #192 @ 0xc0
8006f46: 2bc0 cmp r3, #192 @ 0xc0
8006f48: d016 beq.n 8006f78 <UART_SetConfig+0x208>
8006f4a: 2bc0 cmp r3, #192 @ 0xc0
8006f4c: d818 bhi.n 8006f80 <UART_SetConfig+0x210>
8006f4e: 2b80 cmp r3, #128 @ 0x80
8006f50: d00a beq.n 8006f68 <UART_SetConfig+0x1f8>
8006f52: 2b80 cmp r3, #128 @ 0x80
8006f54: d814 bhi.n 8006f80 <UART_SetConfig+0x210>
8006f56: 2b00 cmp r3, #0
8006f58: d002 beq.n 8006f60 <UART_SetConfig+0x1f0>
8006f5a: 2b40 cmp r3, #64 @ 0x40
8006f5c: d008 beq.n 8006f70 <UART_SetConfig+0x200>
8006f5e: e00f b.n 8006f80 <UART_SetConfig+0x210>
8006f60: 2300 movs r3, #0
8006f62: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f66: e042 b.n 8006fee <UART_SetConfig+0x27e>
8006f68: 2302 movs r3, #2
8006f6a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f6e: e03e b.n 8006fee <UART_SetConfig+0x27e>
8006f70: 2304 movs r3, #4
8006f72: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f76: e03a b.n 8006fee <UART_SetConfig+0x27e>
8006f78: 2308 movs r3, #8
8006f7a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f7e: e036 b.n 8006fee <UART_SetConfig+0x27e>
8006f80: 2310 movs r3, #16
8006f82: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f86: e032 b.n 8006fee <UART_SetConfig+0x27e>
8006f88: 697b ldr r3, [r7, #20]
8006f8a: 681b ldr r3, [r3, #0]
8006f8c: 4a30 ldr r2, [pc, #192] @ (8007050 <UART_SetConfig+0x2e0>)
8006f8e: 4293 cmp r3, r2
8006f90: d12a bne.n 8006fe8 <UART_SetConfig+0x278>
8006f92: 4b31 ldr r3, [pc, #196] @ (8007058 <UART_SetConfig+0x2e8>)
8006f94: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006f98: f403 6340 and.w r3, r3, #3072 @ 0xc00
8006f9c: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8006fa0: d01a beq.n 8006fd8 <UART_SetConfig+0x268>
8006fa2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8006fa6: d81b bhi.n 8006fe0 <UART_SetConfig+0x270>
8006fa8: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8006fac: d00c beq.n 8006fc8 <UART_SetConfig+0x258>
8006fae: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8006fb2: d815 bhi.n 8006fe0 <UART_SetConfig+0x270>
8006fb4: 2b00 cmp r3, #0
8006fb6: d003 beq.n 8006fc0 <UART_SetConfig+0x250>
8006fb8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8006fbc: d008 beq.n 8006fd0 <UART_SetConfig+0x260>
8006fbe: e00f b.n 8006fe0 <UART_SetConfig+0x270>
8006fc0: 2300 movs r3, #0
8006fc2: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006fc6: e012 b.n 8006fee <UART_SetConfig+0x27e>
8006fc8: 2302 movs r3, #2
8006fca: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006fce: e00e b.n 8006fee <UART_SetConfig+0x27e>
8006fd0: 2304 movs r3, #4
8006fd2: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006fd6: e00a b.n 8006fee <UART_SetConfig+0x27e>
8006fd8: 2308 movs r3, #8
8006fda: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006fde: e006 b.n 8006fee <UART_SetConfig+0x27e>
8006fe0: 2310 movs r3, #16
8006fe2: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006fe6: e002 b.n 8006fee <UART_SetConfig+0x27e>
8006fe8: 2310 movs r3, #16
8006fea: f887 302b strb.w r3, [r7, #43] @ 0x2b
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8006fee: 697b ldr r3, [r7, #20]
8006ff0: 681b ldr r3, [r3, #0]
8006ff2: 4a17 ldr r2, [pc, #92] @ (8007050 <UART_SetConfig+0x2e0>)
8006ff4: 4293 cmp r3, r2
8006ff6: f040 80a8 bne.w 800714a <UART_SetConfig+0x3da>
{
/* Retrieve frequency clock */
switch (clocksource)
8006ffa: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8006ffe: 2b08 cmp r3, #8
8007000: d834 bhi.n 800706c <UART_SetConfig+0x2fc>
8007002: a201 add r2, pc, #4 @ (adr r2, 8007008 <UART_SetConfig+0x298>)
8007004: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007008: 0800702d .word 0x0800702d
800700c: 0800706d .word 0x0800706d
8007010: 08007035 .word 0x08007035
8007014: 0800706d .word 0x0800706d
8007018: 0800703b .word 0x0800703b
800701c: 0800706d .word 0x0800706d
8007020: 0800706d .word 0x0800706d
8007024: 0800706d .word 0x0800706d
8007028: 08007043 .word 0x08007043
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800702c: f7fd fccc bl 80049c8 <HAL_RCC_GetPCLK1Freq>
8007030: 6278 str r0, [r7, #36] @ 0x24
break;
8007032: e021 b.n 8007078 <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8007034: 4b0c ldr r3, [pc, #48] @ (8007068 <UART_SetConfig+0x2f8>)
8007036: 627b str r3, [r7, #36] @ 0x24
break;
8007038: e01e b.n 8007078 <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800703a: f7fd fc57 bl 80048ec <HAL_RCC_GetSysClockFreq>
800703e: 6278 str r0, [r7, #36] @ 0x24
break;
8007040: e01a b.n 8007078 <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8007042: f44f 4300 mov.w r3, #32768 @ 0x8000
8007046: 627b str r3, [r7, #36] @ 0x24
break;
8007048: e016 b.n 8007078 <UART_SetConfig+0x308>
800704a: bf00 nop
800704c: cfff69f3 .word 0xcfff69f3
8007050: 40008000 .word 0x40008000
8007054: 40013800 .word 0x40013800
8007058: 40021000 .word 0x40021000
800705c: 40004400 .word 0x40004400
8007060: 40004800 .word 0x40004800
8007064: 40004c00 .word 0x40004c00
8007068: 00f42400 .word 0x00f42400
default:
pclk = 0U;
800706c: 2300 movs r3, #0
800706e: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8007070: 2301 movs r3, #1
8007072: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
8007076: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
8007078: 6a7b ldr r3, [r7, #36] @ 0x24
800707a: 2b00 cmp r3, #0
800707c: f000 812a beq.w 80072d4 <UART_SetConfig+0x564>
{
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
8007080: 697b ldr r3, [r7, #20]
8007082: 6a5b ldr r3, [r3, #36] @ 0x24
8007084: 4a9e ldr r2, [pc, #632] @ (8007300 <UART_SetConfig+0x590>)
8007086: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
800708a: 461a mov r2, r3
800708c: 6a7b ldr r3, [r7, #36] @ 0x24
800708e: fbb3 f3f2 udiv r3, r3, r2
8007092: 61bb str r3, [r7, #24]
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8007094: 697b ldr r3, [r7, #20]
8007096: 685a ldr r2, [r3, #4]
8007098: 4613 mov r3, r2
800709a: 005b lsls r3, r3, #1
800709c: 4413 add r3, r2
800709e: 69ba ldr r2, [r7, #24]
80070a0: 429a cmp r2, r3
80070a2: d305 bcc.n 80070b0 <UART_SetConfig+0x340>
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
80070a4: 697b ldr r3, [r7, #20]
80070a6: 685b ldr r3, [r3, #4]
80070a8: 031b lsls r3, r3, #12
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
80070aa: 69ba ldr r2, [r7, #24]
80070ac: 429a cmp r2, r3
80070ae: d903 bls.n 80070b8 <UART_SetConfig+0x348>
{
ret = HAL_ERROR;
80070b0: 2301 movs r3, #1
80070b2: f887 302a strb.w r3, [r7, #42] @ 0x2a
80070b6: e10d b.n 80072d4 <UART_SetConfig+0x564>
}
else
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
80070b8: 6a7b ldr r3, [r7, #36] @ 0x24
80070ba: 2200 movs r2, #0
80070bc: 60bb str r3, [r7, #8]
80070be: 60fa str r2, [r7, #12]
80070c0: 697b ldr r3, [r7, #20]
80070c2: 6a5b ldr r3, [r3, #36] @ 0x24
80070c4: 4a8e ldr r2, [pc, #568] @ (8007300 <UART_SetConfig+0x590>)
80070c6: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80070ca: b29b uxth r3, r3
80070cc: 2200 movs r2, #0
80070ce: 603b str r3, [r7, #0]
80070d0: 607a str r2, [r7, #4]
80070d2: e9d7 2300 ldrd r2, r3, [r7]
80070d6: e9d7 0102 ldrd r0, r1, [r7, #8]
80070da: f7f9 fba3 bl 8000824 <__aeabi_uldivmod>
80070de: 4602 mov r2, r0
80070e0: 460b mov r3, r1
80070e2: 4610 mov r0, r2
80070e4: 4619 mov r1, r3
80070e6: f04f 0200 mov.w r2, #0
80070ea: f04f 0300 mov.w r3, #0
80070ee: 020b lsls r3, r1, #8
80070f0: ea43 6310 orr.w r3, r3, r0, lsr #24
80070f4: 0202 lsls r2, r0, #8
80070f6: 6979 ldr r1, [r7, #20]
80070f8: 6849 ldr r1, [r1, #4]
80070fa: 0849 lsrs r1, r1, #1
80070fc: 2000 movs r0, #0
80070fe: 460c mov r4, r1
8007100: 4605 mov r5, r0
8007102: eb12 0804 adds.w r8, r2, r4
8007106: eb43 0905 adc.w r9, r3, r5
800710a: 697b ldr r3, [r7, #20]
800710c: 685b ldr r3, [r3, #4]
800710e: 2200 movs r2, #0
8007110: 469a mov sl, r3
8007112: 4693 mov fp, r2
8007114: 4652 mov r2, sl
8007116: 465b mov r3, fp
8007118: 4640 mov r0, r8
800711a: 4649 mov r1, r9
800711c: f7f9 fb82 bl 8000824 <__aeabi_uldivmod>
8007120: 4602 mov r2, r0
8007122: 460b mov r3, r1
8007124: 4613 mov r3, r2
8007126: 623b str r3, [r7, #32]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
8007128: 6a3b ldr r3, [r7, #32]
800712a: f5b3 7f40 cmp.w r3, #768 @ 0x300
800712e: d308 bcc.n 8007142 <UART_SetConfig+0x3d2>
8007130: 6a3b ldr r3, [r7, #32]
8007132: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8007136: d204 bcs.n 8007142 <UART_SetConfig+0x3d2>
{
huart->Instance->BRR = usartdiv;
8007138: 697b ldr r3, [r7, #20]
800713a: 681b ldr r3, [r3, #0]
800713c: 6a3a ldr r2, [r7, #32]
800713e: 60da str r2, [r3, #12]
8007140: e0c8 b.n 80072d4 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
8007142: 2301 movs r3, #1
8007144: f887 302a strb.w r3, [r7, #42] @ 0x2a
8007148: e0c4 b.n 80072d4 <UART_SetConfig+0x564>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
800714a: 697b ldr r3, [r7, #20]
800714c: 69db ldr r3, [r3, #28]
800714e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8007152: d167 bne.n 8007224 <UART_SetConfig+0x4b4>
{
switch (clocksource)
8007154: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8007158: 2b08 cmp r3, #8
800715a: d828 bhi.n 80071ae <UART_SetConfig+0x43e>
800715c: a201 add r2, pc, #4 @ (adr r2, 8007164 <UART_SetConfig+0x3f4>)
800715e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007162: bf00 nop
8007164: 08007189 .word 0x08007189
8007168: 08007191 .word 0x08007191
800716c: 08007199 .word 0x08007199
8007170: 080071af .word 0x080071af
8007174: 0800719f .word 0x0800719f
8007178: 080071af .word 0x080071af
800717c: 080071af .word 0x080071af
8007180: 080071af .word 0x080071af
8007184: 080071a7 .word 0x080071a7
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8007188: f7fd fc1e bl 80049c8 <HAL_RCC_GetPCLK1Freq>
800718c: 6278 str r0, [r7, #36] @ 0x24
break;
800718e: e014 b.n 80071ba <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8007190: f7fd fc30 bl 80049f4 <HAL_RCC_GetPCLK2Freq>
8007194: 6278 str r0, [r7, #36] @ 0x24
break;
8007196: e010 b.n 80071ba <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8007198: 4b5a ldr r3, [pc, #360] @ (8007304 <UART_SetConfig+0x594>)
800719a: 627b str r3, [r7, #36] @ 0x24
break;
800719c: e00d b.n 80071ba <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800719e: f7fd fba5 bl 80048ec <HAL_RCC_GetSysClockFreq>
80071a2: 6278 str r0, [r7, #36] @ 0x24
break;
80071a4: e009 b.n 80071ba <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80071a6: f44f 4300 mov.w r3, #32768 @ 0x8000
80071aa: 627b str r3, [r7, #36] @ 0x24
break;
80071ac: e005 b.n 80071ba <UART_SetConfig+0x44a>
default:
pclk = 0U;
80071ae: 2300 movs r3, #0
80071b0: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
80071b2: 2301 movs r3, #1
80071b4: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
80071b8: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80071ba: 6a7b ldr r3, [r7, #36] @ 0x24
80071bc: 2b00 cmp r3, #0
80071be: f000 8089 beq.w 80072d4 <UART_SetConfig+0x564>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
80071c2: 697b ldr r3, [r7, #20]
80071c4: 6a5b ldr r3, [r3, #36] @ 0x24
80071c6: 4a4e ldr r2, [pc, #312] @ (8007300 <UART_SetConfig+0x590>)
80071c8: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80071cc: 461a mov r2, r3
80071ce: 6a7b ldr r3, [r7, #36] @ 0x24
80071d0: fbb3 f3f2 udiv r3, r3, r2
80071d4: 005a lsls r2, r3, #1
80071d6: 697b ldr r3, [r7, #20]
80071d8: 685b ldr r3, [r3, #4]
80071da: 085b lsrs r3, r3, #1
80071dc: 441a add r2, r3
80071de: 697b ldr r3, [r7, #20]
80071e0: 685b ldr r3, [r3, #4]
80071e2: fbb2 f3f3 udiv r3, r2, r3
80071e6: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80071e8: 6a3b ldr r3, [r7, #32]
80071ea: 2b0f cmp r3, #15
80071ec: d916 bls.n 800721c <UART_SetConfig+0x4ac>
80071ee: 6a3b ldr r3, [r7, #32]
80071f0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80071f4: d212 bcs.n 800721c <UART_SetConfig+0x4ac>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
80071f6: 6a3b ldr r3, [r7, #32]
80071f8: b29b uxth r3, r3
80071fa: f023 030f bic.w r3, r3, #15
80071fe: 83fb strh r3, [r7, #30]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8007200: 6a3b ldr r3, [r7, #32]
8007202: 085b lsrs r3, r3, #1
8007204: b29b uxth r3, r3
8007206: f003 0307 and.w r3, r3, #7
800720a: b29a uxth r2, r3
800720c: 8bfb ldrh r3, [r7, #30]
800720e: 4313 orrs r3, r2
8007210: 83fb strh r3, [r7, #30]
huart->Instance->BRR = brrtemp;
8007212: 697b ldr r3, [r7, #20]
8007214: 681b ldr r3, [r3, #0]
8007216: 8bfa ldrh r2, [r7, #30]
8007218: 60da str r2, [r3, #12]
800721a: e05b b.n 80072d4 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
800721c: 2301 movs r3, #1
800721e: f887 302a strb.w r3, [r7, #42] @ 0x2a
8007222: e057 b.n 80072d4 <UART_SetConfig+0x564>
}
}
}
else
{
switch (clocksource)
8007224: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8007228: 2b08 cmp r3, #8
800722a: d828 bhi.n 800727e <UART_SetConfig+0x50e>
800722c: a201 add r2, pc, #4 @ (adr r2, 8007234 <UART_SetConfig+0x4c4>)
800722e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007232: bf00 nop
8007234: 08007259 .word 0x08007259
8007238: 08007261 .word 0x08007261
800723c: 08007269 .word 0x08007269
8007240: 0800727f .word 0x0800727f
8007244: 0800726f .word 0x0800726f
8007248: 0800727f .word 0x0800727f
800724c: 0800727f .word 0x0800727f
8007250: 0800727f .word 0x0800727f
8007254: 08007277 .word 0x08007277
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8007258: f7fd fbb6 bl 80049c8 <HAL_RCC_GetPCLK1Freq>
800725c: 6278 str r0, [r7, #36] @ 0x24
break;
800725e: e014 b.n 800728a <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8007260: f7fd fbc8 bl 80049f4 <HAL_RCC_GetPCLK2Freq>
8007264: 6278 str r0, [r7, #36] @ 0x24
break;
8007266: e010 b.n 800728a <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8007268: 4b26 ldr r3, [pc, #152] @ (8007304 <UART_SetConfig+0x594>)
800726a: 627b str r3, [r7, #36] @ 0x24
break;
800726c: e00d b.n 800728a <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800726e: f7fd fb3d bl 80048ec <HAL_RCC_GetSysClockFreq>
8007272: 6278 str r0, [r7, #36] @ 0x24
break;
8007274: e009 b.n 800728a <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8007276: f44f 4300 mov.w r3, #32768 @ 0x8000
800727a: 627b str r3, [r7, #36] @ 0x24
break;
800727c: e005 b.n 800728a <UART_SetConfig+0x51a>
default:
pclk = 0U;
800727e: 2300 movs r3, #0
8007280: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8007282: 2301 movs r3, #1
8007284: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
8007288: bf00 nop
}
if (pclk != 0U)
800728a: 6a7b ldr r3, [r7, #36] @ 0x24
800728c: 2b00 cmp r3, #0
800728e: d021 beq.n 80072d4 <UART_SetConfig+0x564>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8007290: 697b ldr r3, [r7, #20]
8007292: 6a5b ldr r3, [r3, #36] @ 0x24
8007294: 4a1a ldr r2, [pc, #104] @ (8007300 <UART_SetConfig+0x590>)
8007296: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
800729a: 461a mov r2, r3
800729c: 6a7b ldr r3, [r7, #36] @ 0x24
800729e: fbb3 f2f2 udiv r2, r3, r2
80072a2: 697b ldr r3, [r7, #20]
80072a4: 685b ldr r3, [r3, #4]
80072a6: 085b lsrs r3, r3, #1
80072a8: 441a add r2, r3
80072aa: 697b ldr r3, [r7, #20]
80072ac: 685b ldr r3, [r3, #4]
80072ae: fbb2 f3f3 udiv r3, r2, r3
80072b2: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80072b4: 6a3b ldr r3, [r7, #32]
80072b6: 2b0f cmp r3, #15
80072b8: d909 bls.n 80072ce <UART_SetConfig+0x55e>
80072ba: 6a3b ldr r3, [r7, #32]
80072bc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80072c0: d205 bcs.n 80072ce <UART_SetConfig+0x55e>
{
huart->Instance->BRR = (uint16_t)usartdiv;
80072c2: 6a3b ldr r3, [r7, #32]
80072c4: b29a uxth r2, r3
80072c6: 697b ldr r3, [r7, #20]
80072c8: 681b ldr r3, [r3, #0]
80072ca: 60da str r2, [r3, #12]
80072cc: e002 b.n 80072d4 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
80072ce: 2301 movs r3, #1
80072d0: f887 302a strb.w r3, [r7, #42] @ 0x2a
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
80072d4: 697b ldr r3, [r7, #20]
80072d6: 2201 movs r2, #1
80072d8: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1;
80072dc: 697b ldr r3, [r7, #20]
80072de: 2201 movs r2, #1
80072e0: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
/* Clear ISR function pointers */
huart->RxISR = NULL;
80072e4: 697b ldr r3, [r7, #20]
80072e6: 2200 movs r2, #0
80072e8: 675a str r2, [r3, #116] @ 0x74
huart->TxISR = NULL;
80072ea: 697b ldr r3, [r7, #20]
80072ec: 2200 movs r2, #0
80072ee: 679a str r2, [r3, #120] @ 0x78
return ret;
80072f0: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
}
80072f4: 4618 mov r0, r3
80072f6: 3730 adds r7, #48 @ 0x30
80072f8: 46bd mov sp, r7
80072fa: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80072fe: bf00 nop
8007300: 08008714 .word 0x08008714
8007304: 00f42400 .word 0x00f42400
08007308 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8007308: b480 push {r7}
800730a: b083 sub sp, #12
800730c: af00 add r7, sp, #0
800730e: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8007310: 687b ldr r3, [r7, #4]
8007312: 6a9b ldr r3, [r3, #40] @ 0x28
8007314: f003 0308 and.w r3, r3, #8
8007318: 2b00 cmp r3, #0
800731a: d00a beq.n 8007332 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
800731c: 687b ldr r3, [r7, #4]
800731e: 681b ldr r3, [r3, #0]
8007320: 685b ldr r3, [r3, #4]
8007322: f423 4100 bic.w r1, r3, #32768 @ 0x8000
8007326: 687b ldr r3, [r7, #4]
8007328: 6b9a ldr r2, [r3, #56] @ 0x38
800732a: 687b ldr r3, [r7, #4]
800732c: 681b ldr r3, [r3, #0]
800732e: 430a orrs r2, r1
8007330: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8007332: 687b ldr r3, [r7, #4]
8007334: 6a9b ldr r3, [r3, #40] @ 0x28
8007336: f003 0301 and.w r3, r3, #1
800733a: 2b00 cmp r3, #0
800733c: d00a beq.n 8007354 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
800733e: 687b ldr r3, [r7, #4]
8007340: 681b ldr r3, [r3, #0]
8007342: 685b ldr r3, [r3, #4]
8007344: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8007348: 687b ldr r3, [r7, #4]
800734a: 6ada ldr r2, [r3, #44] @ 0x2c
800734c: 687b ldr r3, [r7, #4]
800734e: 681b ldr r3, [r3, #0]
8007350: 430a orrs r2, r1
8007352: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8007354: 687b ldr r3, [r7, #4]
8007356: 6a9b ldr r3, [r3, #40] @ 0x28
8007358: f003 0302 and.w r3, r3, #2
800735c: 2b00 cmp r3, #0
800735e: d00a beq.n 8007376 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8007360: 687b ldr r3, [r7, #4]
8007362: 681b ldr r3, [r3, #0]
8007364: 685b ldr r3, [r3, #4]
8007366: f423 3180 bic.w r1, r3, #65536 @ 0x10000
800736a: 687b ldr r3, [r7, #4]
800736c: 6b1a ldr r2, [r3, #48] @ 0x30
800736e: 687b ldr r3, [r7, #4]
8007370: 681b ldr r3, [r3, #0]
8007372: 430a orrs r2, r1
8007374: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8007376: 687b ldr r3, [r7, #4]
8007378: 6a9b ldr r3, [r3, #40] @ 0x28
800737a: f003 0304 and.w r3, r3, #4
800737e: 2b00 cmp r3, #0
8007380: d00a beq.n 8007398 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8007382: 687b ldr r3, [r7, #4]
8007384: 681b ldr r3, [r3, #0]
8007386: 685b ldr r3, [r3, #4]
8007388: f423 2180 bic.w r1, r3, #262144 @ 0x40000
800738c: 687b ldr r3, [r7, #4]
800738e: 6b5a ldr r2, [r3, #52] @ 0x34
8007390: 687b ldr r3, [r7, #4]
8007392: 681b ldr r3, [r3, #0]
8007394: 430a orrs r2, r1
8007396: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8007398: 687b ldr r3, [r7, #4]
800739a: 6a9b ldr r3, [r3, #40] @ 0x28
800739c: f003 0310 and.w r3, r3, #16
80073a0: 2b00 cmp r3, #0
80073a2: d00a beq.n 80073ba <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80073a4: 687b ldr r3, [r7, #4]
80073a6: 681b ldr r3, [r3, #0]
80073a8: 689b ldr r3, [r3, #8]
80073aa: f423 5180 bic.w r1, r3, #4096 @ 0x1000
80073ae: 687b ldr r3, [r7, #4]
80073b0: 6bda ldr r2, [r3, #60] @ 0x3c
80073b2: 687b ldr r3, [r7, #4]
80073b4: 681b ldr r3, [r3, #0]
80073b6: 430a orrs r2, r1
80073b8: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
80073ba: 687b ldr r3, [r7, #4]
80073bc: 6a9b ldr r3, [r3, #40] @ 0x28
80073be: f003 0320 and.w r3, r3, #32
80073c2: 2b00 cmp r3, #0
80073c4: d00a beq.n 80073dc <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
80073c6: 687b ldr r3, [r7, #4]
80073c8: 681b ldr r3, [r3, #0]
80073ca: 689b ldr r3, [r3, #8]
80073cc: f423 5100 bic.w r1, r3, #8192 @ 0x2000
80073d0: 687b ldr r3, [r7, #4]
80073d2: 6c1a ldr r2, [r3, #64] @ 0x40
80073d4: 687b ldr r3, [r7, #4]
80073d6: 681b ldr r3, [r3, #0]
80073d8: 430a orrs r2, r1
80073da: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
80073dc: 687b ldr r3, [r7, #4]
80073de: 6a9b ldr r3, [r3, #40] @ 0x28
80073e0: f003 0340 and.w r3, r3, #64 @ 0x40
80073e4: 2b00 cmp r3, #0
80073e6: d01a beq.n 800741e <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
80073e8: 687b ldr r3, [r7, #4]
80073ea: 681b ldr r3, [r3, #0]
80073ec: 685b ldr r3, [r3, #4]
80073ee: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
80073f2: 687b ldr r3, [r7, #4]
80073f4: 6c5a ldr r2, [r3, #68] @ 0x44
80073f6: 687b ldr r3, [r7, #4]
80073f8: 681b ldr r3, [r3, #0]
80073fa: 430a orrs r2, r1
80073fc: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
80073fe: 687b ldr r3, [r7, #4]
8007400: 6c5b ldr r3, [r3, #68] @ 0x44
8007402: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8007406: d10a bne.n 800741e <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8007408: 687b ldr r3, [r7, #4]
800740a: 681b ldr r3, [r3, #0]
800740c: 685b ldr r3, [r3, #4]
800740e: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8007412: 687b ldr r3, [r7, #4]
8007414: 6c9a ldr r2, [r3, #72] @ 0x48
8007416: 687b ldr r3, [r7, #4]
8007418: 681b ldr r3, [r3, #0]
800741a: 430a orrs r2, r1
800741c: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
800741e: 687b ldr r3, [r7, #4]
8007420: 6a9b ldr r3, [r3, #40] @ 0x28
8007422: f003 0380 and.w r3, r3, #128 @ 0x80
8007426: 2b00 cmp r3, #0
8007428: d00a beq.n 8007440 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800742a: 687b ldr r3, [r7, #4]
800742c: 681b ldr r3, [r3, #0]
800742e: 685b ldr r3, [r3, #4]
8007430: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8007434: 687b ldr r3, [r7, #4]
8007436: 6cda ldr r2, [r3, #76] @ 0x4c
8007438: 687b ldr r3, [r7, #4]
800743a: 681b ldr r3, [r3, #0]
800743c: 430a orrs r2, r1
800743e: 605a str r2, [r3, #4]
}
}
8007440: bf00 nop
8007442: 370c adds r7, #12
8007444: 46bd mov sp, r7
8007446: f85d 7b04 ldr.w r7, [sp], #4
800744a: 4770 bx lr
0800744c <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
800744c: b580 push {r7, lr}
800744e: b098 sub sp, #96 @ 0x60
8007450: af02 add r7, sp, #8
8007452: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007454: 687b ldr r3, [r7, #4]
8007456: 2200 movs r2, #0
8007458: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800745c: f7fa fd10 bl 8001e80 <HAL_GetTick>
8007460: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8007462: 687b ldr r3, [r7, #4]
8007464: 681b ldr r3, [r3, #0]
8007466: 681b ldr r3, [r3, #0]
8007468: f003 0308 and.w r3, r3, #8
800746c: 2b08 cmp r3, #8
800746e: d12f bne.n 80074d0 <UART_CheckIdleState+0x84>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8007470: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8007474: 9300 str r3, [sp, #0]
8007476: 6d7b ldr r3, [r7, #84] @ 0x54
8007478: 2200 movs r2, #0
800747a: f44f 1100 mov.w r1, #2097152 @ 0x200000
800747e: 6878 ldr r0, [r7, #4]
8007480: f000 f88e bl 80075a0 <UART_WaitOnFlagUntilTimeout>
8007484: 4603 mov r3, r0
8007486: 2b00 cmp r3, #0
8007488: d022 beq.n 80074d0 <UART_CheckIdleState+0x84>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
800748a: 687b ldr r3, [r7, #4]
800748c: 681b ldr r3, [r3, #0]
800748e: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007490: 6bbb ldr r3, [r7, #56] @ 0x38
8007492: e853 3f00 ldrex r3, [r3]
8007496: 637b str r3, [r7, #52] @ 0x34
return(result);
8007498: 6b7b ldr r3, [r7, #52] @ 0x34
800749a: f023 0380 bic.w r3, r3, #128 @ 0x80
800749e: 653b str r3, [r7, #80] @ 0x50
80074a0: 687b ldr r3, [r7, #4]
80074a2: 681b ldr r3, [r3, #0]
80074a4: 461a mov r2, r3
80074a6: 6d3b ldr r3, [r7, #80] @ 0x50
80074a8: 647b str r3, [r7, #68] @ 0x44
80074aa: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80074ac: 6c39 ldr r1, [r7, #64] @ 0x40
80074ae: 6c7a ldr r2, [r7, #68] @ 0x44
80074b0: e841 2300 strex r3, r2, [r1]
80074b4: 63fb str r3, [r7, #60] @ 0x3c
return(result);
80074b6: 6bfb ldr r3, [r7, #60] @ 0x3c
80074b8: 2b00 cmp r3, #0
80074ba: d1e6 bne.n 800748a <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
80074bc: 687b ldr r3, [r7, #4]
80074be: 2220 movs r2, #32
80074c0: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UNLOCK(huart);
80074c4: 687b ldr r3, [r7, #4]
80074c6: 2200 movs r2, #0
80074c8: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
80074cc: 2303 movs r3, #3
80074ce: e063 b.n 8007598 <UART_CheckIdleState+0x14c>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
80074d0: 687b ldr r3, [r7, #4]
80074d2: 681b ldr r3, [r3, #0]
80074d4: 681b ldr r3, [r3, #0]
80074d6: f003 0304 and.w r3, r3, #4
80074da: 2b04 cmp r3, #4
80074dc: d149 bne.n 8007572 <UART_CheckIdleState+0x126>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80074de: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80074e2: 9300 str r3, [sp, #0]
80074e4: 6d7b ldr r3, [r7, #84] @ 0x54
80074e6: 2200 movs r2, #0
80074e8: f44f 0180 mov.w r1, #4194304 @ 0x400000
80074ec: 6878 ldr r0, [r7, #4]
80074ee: f000 f857 bl 80075a0 <UART_WaitOnFlagUntilTimeout>
80074f2: 4603 mov r3, r0
80074f4: 2b00 cmp r3, #0
80074f6: d03c beq.n 8007572 <UART_CheckIdleState+0x126>
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80074f8: 687b ldr r3, [r7, #4]
80074fa: 681b ldr r3, [r3, #0]
80074fc: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80074fe: 6a7b ldr r3, [r7, #36] @ 0x24
8007500: e853 3f00 ldrex r3, [r3]
8007504: 623b str r3, [r7, #32]
return(result);
8007506: 6a3b ldr r3, [r7, #32]
8007508: f423 7390 bic.w r3, r3, #288 @ 0x120
800750c: 64fb str r3, [r7, #76] @ 0x4c
800750e: 687b ldr r3, [r7, #4]
8007510: 681b ldr r3, [r3, #0]
8007512: 461a mov r2, r3
8007514: 6cfb ldr r3, [r7, #76] @ 0x4c
8007516: 633b str r3, [r7, #48] @ 0x30
8007518: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800751a: 6af9 ldr r1, [r7, #44] @ 0x2c
800751c: 6b3a ldr r2, [r7, #48] @ 0x30
800751e: e841 2300 strex r3, r2, [r1]
8007522: 62bb str r3, [r7, #40] @ 0x28
return(result);
8007524: 6abb ldr r3, [r7, #40] @ 0x28
8007526: 2b00 cmp r3, #0
8007528: d1e6 bne.n 80074f8 <UART_CheckIdleState+0xac>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800752a: 687b ldr r3, [r7, #4]
800752c: 681b ldr r3, [r3, #0]
800752e: 3308 adds r3, #8
8007530: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007532: 693b ldr r3, [r7, #16]
8007534: e853 3f00 ldrex r3, [r3]
8007538: 60fb str r3, [r7, #12]
return(result);
800753a: 68fb ldr r3, [r7, #12]
800753c: f023 0301 bic.w r3, r3, #1
8007540: 64bb str r3, [r7, #72] @ 0x48
8007542: 687b ldr r3, [r7, #4]
8007544: 681b ldr r3, [r3, #0]
8007546: 3308 adds r3, #8
8007548: 6cba ldr r2, [r7, #72] @ 0x48
800754a: 61fa str r2, [r7, #28]
800754c: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800754e: 69b9 ldr r1, [r7, #24]
8007550: 69fa ldr r2, [r7, #28]
8007552: e841 2300 strex r3, r2, [r1]
8007556: 617b str r3, [r7, #20]
return(result);
8007558: 697b ldr r3, [r7, #20]
800755a: 2b00 cmp r3, #0
800755c: d1e5 bne.n 800752a <UART_CheckIdleState+0xde>
huart->RxState = HAL_UART_STATE_READY;
800755e: 687b ldr r3, [r7, #4]
8007560: 2220 movs r2, #32
8007562: f8c3 208c str.w r2, [r3, #140] @ 0x8c
__HAL_UNLOCK(huart);
8007566: 687b ldr r3, [r7, #4]
8007568: 2200 movs r2, #0
800756a: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
800756e: 2303 movs r3, #3
8007570: e012 b.n 8007598 <UART_CheckIdleState+0x14c>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8007572: 687b ldr r3, [r7, #4]
8007574: 2220 movs r2, #32
8007576: f8c3 2088 str.w r2, [r3, #136] @ 0x88
huart->RxState = HAL_UART_STATE_READY;
800757a: 687b ldr r3, [r7, #4]
800757c: 2220 movs r2, #32
800757e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007582: 687b ldr r3, [r7, #4]
8007584: 2200 movs r2, #0
8007586: 66da str r2, [r3, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007588: 687b ldr r3, [r7, #4]
800758a: 2200 movs r2, #0
800758c: 671a str r2, [r3, #112] @ 0x70
__HAL_UNLOCK(huart);
800758e: 687b ldr r3, [r7, #4]
8007590: 2200 movs r2, #0
8007592: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8007596: 2300 movs r3, #0
}
8007598: 4618 mov r0, r3
800759a: 3758 adds r7, #88 @ 0x58
800759c: 46bd mov sp, r7
800759e: bd80 pop {r7, pc}
080075a0 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80075a0: b580 push {r7, lr}
80075a2: b084 sub sp, #16
80075a4: af00 add r7, sp, #0
80075a6: 60f8 str r0, [r7, #12]
80075a8: 60b9 str r1, [r7, #8]
80075aa: 603b str r3, [r7, #0]
80075ac: 4613 mov r3, r2
80075ae: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80075b0: e04f b.n 8007652 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80075b2: 69bb ldr r3, [r7, #24]
80075b4: f1b3 3fff cmp.w r3, #4294967295
80075b8: d04b beq.n 8007652 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80075ba: f7fa fc61 bl 8001e80 <HAL_GetTick>
80075be: 4602 mov r2, r0
80075c0: 683b ldr r3, [r7, #0]
80075c2: 1ad3 subs r3, r2, r3
80075c4: 69ba ldr r2, [r7, #24]
80075c6: 429a cmp r2, r3
80075c8: d302 bcc.n 80075d0 <UART_WaitOnFlagUntilTimeout+0x30>
80075ca: 69bb ldr r3, [r7, #24]
80075cc: 2b00 cmp r3, #0
80075ce: d101 bne.n 80075d4 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
80075d0: 2303 movs r3, #3
80075d2: e04e b.n 8007672 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
80075d4: 68fb ldr r3, [r7, #12]
80075d6: 681b ldr r3, [r3, #0]
80075d8: 681b ldr r3, [r3, #0]
80075da: f003 0304 and.w r3, r3, #4
80075de: 2b00 cmp r3, #0
80075e0: d037 beq.n 8007652 <UART_WaitOnFlagUntilTimeout+0xb2>
80075e2: 68bb ldr r3, [r7, #8]
80075e4: 2b80 cmp r3, #128 @ 0x80
80075e6: d034 beq.n 8007652 <UART_WaitOnFlagUntilTimeout+0xb2>
80075e8: 68bb ldr r3, [r7, #8]
80075ea: 2b40 cmp r3, #64 @ 0x40
80075ec: d031 beq.n 8007652 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
80075ee: 68fb ldr r3, [r7, #12]
80075f0: 681b ldr r3, [r3, #0]
80075f2: 69db ldr r3, [r3, #28]
80075f4: f003 0308 and.w r3, r3, #8
80075f8: 2b08 cmp r3, #8
80075fa: d110 bne.n 800761e <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
80075fc: 68fb ldr r3, [r7, #12]
80075fe: 681b ldr r3, [r3, #0]
8007600: 2208 movs r2, #8
8007602: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8007604: 68f8 ldr r0, [r7, #12]
8007606: f000 f95b bl 80078c0 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
800760a: 68fb ldr r3, [r7, #12]
800760c: 2208 movs r2, #8
800760e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007612: 68fb ldr r3, [r7, #12]
8007614: 2200 movs r2, #0
8007616: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_ERROR;
800761a: 2301 movs r3, #1
800761c: e029 b.n 8007672 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
800761e: 68fb ldr r3, [r7, #12]
8007620: 681b ldr r3, [r3, #0]
8007622: 69db ldr r3, [r3, #28]
8007624: f403 6300 and.w r3, r3, #2048 @ 0x800
8007628: f5b3 6f00 cmp.w r3, #2048 @ 0x800
800762c: d111 bne.n 8007652 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
800762e: 68fb ldr r3, [r7, #12]
8007630: 681b ldr r3, [r3, #0]
8007632: f44f 6200 mov.w r2, #2048 @ 0x800
8007636: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8007638: 68f8 ldr r0, [r7, #12]
800763a: f000 f941 bl 80078c0 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
800763e: 68fb ldr r3, [r7, #12]
8007640: 2220 movs r2, #32
8007642: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007646: 68fb ldr r3, [r7, #12]
8007648: 2200 movs r2, #0
800764a: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_TIMEOUT;
800764e: 2303 movs r3, #3
8007650: e00f b.n 8007672 <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8007652: 68fb ldr r3, [r7, #12]
8007654: 681b ldr r3, [r3, #0]
8007656: 69da ldr r2, [r3, #28]
8007658: 68bb ldr r3, [r7, #8]
800765a: 4013 ands r3, r2
800765c: 68ba ldr r2, [r7, #8]
800765e: 429a cmp r2, r3
8007660: bf0c ite eq
8007662: 2301 moveq r3, #1
8007664: 2300 movne r3, #0
8007666: b2db uxtb r3, r3
8007668: 461a mov r2, r3
800766a: 79fb ldrb r3, [r7, #7]
800766c: 429a cmp r2, r3
800766e: d0a0 beq.n 80075b2 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8007670: 2300 movs r3, #0
}
8007672: 4618 mov r0, r3
8007674: 3710 adds r7, #16
8007676: 46bd mov sp, r7
8007678: bd80 pop {r7, pc}
...
0800767c <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
800767c: b480 push {r7}
800767e: b0a3 sub sp, #140 @ 0x8c
8007680: af00 add r7, sp, #0
8007682: 60f8 str r0, [r7, #12]
8007684: 60b9 str r1, [r7, #8]
8007686: 4613 mov r3, r2
8007688: 80fb strh r3, [r7, #6]
huart->pRxBuffPtr = pData;
800768a: 68fb ldr r3, [r7, #12]
800768c: 68ba ldr r2, [r7, #8]
800768e: 659a str r2, [r3, #88] @ 0x58
huart->RxXferSize = Size;
8007690: 68fb ldr r3, [r7, #12]
8007692: 88fa ldrh r2, [r7, #6]
8007694: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
huart->RxXferCount = Size;
8007698: 68fb ldr r3, [r7, #12]
800769a: 88fa ldrh r2, [r7, #6]
800769c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
huart->RxISR = NULL;
80076a0: 68fb ldr r3, [r7, #12]
80076a2: 2200 movs r2, #0
80076a4: 675a str r2, [r3, #116] @ 0x74
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
80076a6: 68fb ldr r3, [r7, #12]
80076a8: 689b ldr r3, [r3, #8]
80076aa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80076ae: d10e bne.n 80076ce <UART_Start_Receive_IT+0x52>
80076b0: 68fb ldr r3, [r7, #12]
80076b2: 691b ldr r3, [r3, #16]
80076b4: 2b00 cmp r3, #0
80076b6: d105 bne.n 80076c4 <UART_Start_Receive_IT+0x48>
80076b8: 68fb ldr r3, [r7, #12]
80076ba: f240 12ff movw r2, #511 @ 0x1ff
80076be: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
80076c2: e02d b.n 8007720 <UART_Start_Receive_IT+0xa4>
80076c4: 68fb ldr r3, [r7, #12]
80076c6: 22ff movs r2, #255 @ 0xff
80076c8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
80076cc: e028 b.n 8007720 <UART_Start_Receive_IT+0xa4>
80076ce: 68fb ldr r3, [r7, #12]
80076d0: 689b ldr r3, [r3, #8]
80076d2: 2b00 cmp r3, #0
80076d4: d10d bne.n 80076f2 <UART_Start_Receive_IT+0x76>
80076d6: 68fb ldr r3, [r7, #12]
80076d8: 691b ldr r3, [r3, #16]
80076da: 2b00 cmp r3, #0
80076dc: d104 bne.n 80076e8 <UART_Start_Receive_IT+0x6c>
80076de: 68fb ldr r3, [r7, #12]
80076e0: 22ff movs r2, #255 @ 0xff
80076e2: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
80076e6: e01b b.n 8007720 <UART_Start_Receive_IT+0xa4>
80076e8: 68fb ldr r3, [r7, #12]
80076ea: 227f movs r2, #127 @ 0x7f
80076ec: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
80076f0: e016 b.n 8007720 <UART_Start_Receive_IT+0xa4>
80076f2: 68fb ldr r3, [r7, #12]
80076f4: 689b ldr r3, [r3, #8]
80076f6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
80076fa: d10d bne.n 8007718 <UART_Start_Receive_IT+0x9c>
80076fc: 68fb ldr r3, [r7, #12]
80076fe: 691b ldr r3, [r3, #16]
8007700: 2b00 cmp r3, #0
8007702: d104 bne.n 800770e <UART_Start_Receive_IT+0x92>
8007704: 68fb ldr r3, [r7, #12]
8007706: 227f movs r2, #127 @ 0x7f
8007708: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
800770c: e008 b.n 8007720 <UART_Start_Receive_IT+0xa4>
800770e: 68fb ldr r3, [r7, #12]
8007710: 223f movs r2, #63 @ 0x3f
8007712: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007716: e003 b.n 8007720 <UART_Start_Receive_IT+0xa4>
8007718: 68fb ldr r3, [r7, #12]
800771a: 2200 movs r2, #0
800771c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007720: 68fb ldr r3, [r7, #12]
8007722: 2200 movs r2, #0
8007724: f8c3 2090 str.w r2, [r3, #144] @ 0x90
huart->RxState = HAL_UART_STATE_BUSY_RX;
8007728: 68fb ldr r3, [r7, #12]
800772a: 2222 movs r2, #34 @ 0x22
800772c: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
8007730: 68fb ldr r3, [r7, #12]
8007732: 681b ldr r3, [r3, #0]
8007734: 3308 adds r3, #8
8007736: 667b str r3, [r7, #100] @ 0x64
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007738: 6e7b ldr r3, [r7, #100] @ 0x64
800773a: e853 3f00 ldrex r3, [r3]
800773e: 663b str r3, [r7, #96] @ 0x60
return(result);
8007740: 6e3b ldr r3, [r7, #96] @ 0x60
8007742: f043 0301 orr.w r3, r3, #1
8007746: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800774a: 68fb ldr r3, [r7, #12]
800774c: 681b ldr r3, [r3, #0]
800774e: 3308 adds r3, #8
8007750: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
8007754: 673a str r2, [r7, #112] @ 0x70
8007756: 66fb str r3, [r7, #108] @ 0x6c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007758: 6ef9 ldr r1, [r7, #108] @ 0x6c
800775a: 6f3a ldr r2, [r7, #112] @ 0x70
800775c: e841 2300 strex r3, r2, [r1]
8007760: 66bb str r3, [r7, #104] @ 0x68
return(result);
8007762: 6ebb ldr r3, [r7, #104] @ 0x68
8007764: 2b00 cmp r3, #0
8007766: d1e3 bne.n 8007730 <UART_Start_Receive_IT+0xb4>
/* Configure Rx interrupt processing */
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
8007768: 68fb ldr r3, [r7, #12]
800776a: 6e5b ldr r3, [r3, #100] @ 0x64
800776c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8007770: d14f bne.n 8007812 <UART_Start_Receive_IT+0x196>
8007772: 68fb ldr r3, [r7, #12]
8007774: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8007778: 88fa ldrh r2, [r7, #6]
800777a: 429a cmp r2, r3
800777c: d349 bcc.n 8007812 <UART_Start_Receive_IT+0x196>
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
800777e: 68fb ldr r3, [r7, #12]
8007780: 689b ldr r3, [r3, #8]
8007782: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8007786: d107 bne.n 8007798 <UART_Start_Receive_IT+0x11c>
8007788: 68fb ldr r3, [r7, #12]
800778a: 691b ldr r3, [r3, #16]
800778c: 2b00 cmp r3, #0
800778e: d103 bne.n 8007798 <UART_Start_Receive_IT+0x11c>
{
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
8007790: 68fb ldr r3, [r7, #12]
8007792: 4a47 ldr r2, [pc, #284] @ (80078b0 <UART_Start_Receive_IT+0x234>)
8007794: 675a str r2, [r3, #116] @ 0x74
8007796: e002 b.n 800779e <UART_Start_Receive_IT+0x122>
}
else
{
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
8007798: 68fb ldr r3, [r7, #12]
800779a: 4a46 ldr r2, [pc, #280] @ (80078b4 <UART_Start_Receive_IT+0x238>)
800779c: 675a str r2, [r3, #116] @ 0x74
}
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
800779e: 68fb ldr r3, [r7, #12]
80077a0: 691b ldr r3, [r3, #16]
80077a2: 2b00 cmp r3, #0
80077a4: d01a beq.n 80077dc <UART_Start_Receive_IT+0x160>
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
80077a6: 68fb ldr r3, [r7, #12]
80077a8: 681b ldr r3, [r3, #0]
80077aa: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80077ac: 6d3b ldr r3, [r7, #80] @ 0x50
80077ae: e853 3f00 ldrex r3, [r3]
80077b2: 64fb str r3, [r7, #76] @ 0x4c
return(result);
80077b4: 6cfb ldr r3, [r7, #76] @ 0x4c
80077b6: f443 7380 orr.w r3, r3, #256 @ 0x100
80077ba: f8c7 3080 str.w r3, [r7, #128] @ 0x80
80077be: 68fb ldr r3, [r7, #12]
80077c0: 681b ldr r3, [r3, #0]
80077c2: 461a mov r2, r3
80077c4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
80077c8: 65fb str r3, [r7, #92] @ 0x5c
80077ca: 65ba str r2, [r7, #88] @ 0x58
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80077cc: 6db9 ldr r1, [r7, #88] @ 0x58
80077ce: 6dfa ldr r2, [r7, #92] @ 0x5c
80077d0: e841 2300 strex r3, r2, [r1]
80077d4: 657b str r3, [r7, #84] @ 0x54
return(result);
80077d6: 6d7b ldr r3, [r7, #84] @ 0x54
80077d8: 2b00 cmp r3, #0
80077da: d1e4 bne.n 80077a6 <UART_Start_Receive_IT+0x12a>
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
80077dc: 68fb ldr r3, [r7, #12]
80077de: 681b ldr r3, [r3, #0]
80077e0: 3308 adds r3, #8
80077e2: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80077e4: 6bfb ldr r3, [r7, #60] @ 0x3c
80077e6: e853 3f00 ldrex r3, [r3]
80077ea: 63bb str r3, [r7, #56] @ 0x38
return(result);
80077ec: 6bbb ldr r3, [r7, #56] @ 0x38
80077ee: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80077f2: 67fb str r3, [r7, #124] @ 0x7c
80077f4: 68fb ldr r3, [r7, #12]
80077f6: 681b ldr r3, [r3, #0]
80077f8: 3308 adds r3, #8
80077fa: 6ffa ldr r2, [r7, #124] @ 0x7c
80077fc: 64ba str r2, [r7, #72] @ 0x48
80077fe: 647b str r3, [r7, #68] @ 0x44
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007800: 6c79 ldr r1, [r7, #68] @ 0x44
8007802: 6cba ldr r2, [r7, #72] @ 0x48
8007804: e841 2300 strex r3, r2, [r1]
8007808: 643b str r3, [r7, #64] @ 0x40
return(result);
800780a: 6c3b ldr r3, [r7, #64] @ 0x40
800780c: 2b00 cmp r3, #0
800780e: d1e5 bne.n 80077dc <UART_Start_Receive_IT+0x160>
8007810: e046 b.n 80078a0 <UART_Start_Receive_IT+0x224>
}
else
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8007812: 68fb ldr r3, [r7, #12]
8007814: 689b ldr r3, [r3, #8]
8007816: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800781a: d107 bne.n 800782c <UART_Start_Receive_IT+0x1b0>
800781c: 68fb ldr r3, [r7, #12]
800781e: 691b ldr r3, [r3, #16]
8007820: 2b00 cmp r3, #0
8007822: d103 bne.n 800782c <UART_Start_Receive_IT+0x1b0>
{
huart->RxISR = UART_RxISR_16BIT;
8007824: 68fb ldr r3, [r7, #12]
8007826: 4a24 ldr r2, [pc, #144] @ (80078b8 <UART_Start_Receive_IT+0x23c>)
8007828: 675a str r2, [r3, #116] @ 0x74
800782a: e002 b.n 8007832 <UART_Start_Receive_IT+0x1b6>
}
else
{
huart->RxISR = UART_RxISR_8BIT;
800782c: 68fb ldr r3, [r7, #12]
800782e: 4a23 ldr r2, [pc, #140] @ (80078bc <UART_Start_Receive_IT+0x240>)
8007830: 675a str r2, [r3, #116] @ 0x74
}
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
8007832: 68fb ldr r3, [r7, #12]
8007834: 691b ldr r3, [r3, #16]
8007836: 2b00 cmp r3, #0
8007838: d019 beq.n 800786e <UART_Start_Receive_IT+0x1f2>
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
800783a: 68fb ldr r3, [r7, #12]
800783c: 681b ldr r3, [r3, #0]
800783e: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007840: 6abb ldr r3, [r7, #40] @ 0x28
8007842: e853 3f00 ldrex r3, [r3]
8007846: 627b str r3, [r7, #36] @ 0x24
return(result);
8007848: 6a7b ldr r3, [r7, #36] @ 0x24
800784a: f443 7390 orr.w r3, r3, #288 @ 0x120
800784e: 677b str r3, [r7, #116] @ 0x74
8007850: 68fb ldr r3, [r7, #12]
8007852: 681b ldr r3, [r3, #0]
8007854: 461a mov r2, r3
8007856: 6f7b ldr r3, [r7, #116] @ 0x74
8007858: 637b str r3, [r7, #52] @ 0x34
800785a: 633a str r2, [r7, #48] @ 0x30
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800785c: 6b39 ldr r1, [r7, #48] @ 0x30
800785e: 6b7a ldr r2, [r7, #52] @ 0x34
8007860: e841 2300 strex r3, r2, [r1]
8007864: 62fb str r3, [r7, #44] @ 0x2c
return(result);
8007866: 6afb ldr r3, [r7, #44] @ 0x2c
8007868: 2b00 cmp r3, #0
800786a: d1e6 bne.n 800783a <UART_Start_Receive_IT+0x1be>
800786c: e018 b.n 80078a0 <UART_Start_Receive_IT+0x224>
}
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
800786e: 68fb ldr r3, [r7, #12]
8007870: 681b ldr r3, [r3, #0]
8007872: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007874: 697b ldr r3, [r7, #20]
8007876: e853 3f00 ldrex r3, [r3]
800787a: 613b str r3, [r7, #16]
return(result);
800787c: 693b ldr r3, [r7, #16]
800787e: f043 0320 orr.w r3, r3, #32
8007882: 67bb str r3, [r7, #120] @ 0x78
8007884: 68fb ldr r3, [r7, #12]
8007886: 681b ldr r3, [r3, #0]
8007888: 461a mov r2, r3
800788a: 6fbb ldr r3, [r7, #120] @ 0x78
800788c: 623b str r3, [r7, #32]
800788e: 61fa str r2, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007890: 69f9 ldr r1, [r7, #28]
8007892: 6a3a ldr r2, [r7, #32]
8007894: e841 2300 strex r3, r2, [r1]
8007898: 61bb str r3, [r7, #24]
return(result);
800789a: 69bb ldr r3, [r7, #24]
800789c: 2b00 cmp r3, #0
800789e: d1e6 bne.n 800786e <UART_Start_Receive_IT+0x1f2>
}
}
return HAL_OK;
80078a0: 2300 movs r3, #0
}
80078a2: 4618 mov r0, r3
80078a4: 378c adds r7, #140 @ 0x8c
80078a6: 46bd mov sp, r7
80078a8: f85d 7b04 ldr.w r7, [sp], #4
80078ac: 4770 bx lr
80078ae: bf00 nop
80078b0: 080080dd .word 0x080080dd
80078b4: 08007d79 .word 0x08007d79
80078b8: 08007bc1 .word 0x08007bc1
80078bc: 08007a09 .word 0x08007a09
080078c0 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
80078c0: b480 push {r7}
80078c2: b095 sub sp, #84 @ 0x54
80078c4: af00 add r7, sp, #0
80078c6: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80078c8: 687b ldr r3, [r7, #4]
80078ca: 681b ldr r3, [r3, #0]
80078cc: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80078ce: 6b7b ldr r3, [r7, #52] @ 0x34
80078d0: e853 3f00 ldrex r3, [r3]
80078d4: 633b str r3, [r7, #48] @ 0x30
return(result);
80078d6: 6b3b ldr r3, [r7, #48] @ 0x30
80078d8: f423 7390 bic.w r3, r3, #288 @ 0x120
80078dc: 64fb str r3, [r7, #76] @ 0x4c
80078de: 687b ldr r3, [r7, #4]
80078e0: 681b ldr r3, [r3, #0]
80078e2: 461a mov r2, r3
80078e4: 6cfb ldr r3, [r7, #76] @ 0x4c
80078e6: 643b str r3, [r7, #64] @ 0x40
80078e8: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80078ea: 6bf9 ldr r1, [r7, #60] @ 0x3c
80078ec: 6c3a ldr r2, [r7, #64] @ 0x40
80078ee: e841 2300 strex r3, r2, [r1]
80078f2: 63bb str r3, [r7, #56] @ 0x38
return(result);
80078f4: 6bbb ldr r3, [r7, #56] @ 0x38
80078f6: 2b00 cmp r3, #0
80078f8: d1e6 bne.n 80078c8 <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80078fa: 687b ldr r3, [r7, #4]
80078fc: 681b ldr r3, [r3, #0]
80078fe: 3308 adds r3, #8
8007900: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007902: 6a3b ldr r3, [r7, #32]
8007904: e853 3f00 ldrex r3, [r3]
8007908: 61fb str r3, [r7, #28]
return(result);
800790a: 69fb ldr r3, [r7, #28]
800790c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007910: f023 0301 bic.w r3, r3, #1
8007914: 64bb str r3, [r7, #72] @ 0x48
8007916: 687b ldr r3, [r7, #4]
8007918: 681b ldr r3, [r3, #0]
800791a: 3308 adds r3, #8
800791c: 6cba ldr r2, [r7, #72] @ 0x48
800791e: 62fa str r2, [r7, #44] @ 0x2c
8007920: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007922: 6ab9 ldr r1, [r7, #40] @ 0x28
8007924: 6afa ldr r2, [r7, #44] @ 0x2c
8007926: e841 2300 strex r3, r2, [r1]
800792a: 627b str r3, [r7, #36] @ 0x24
return(result);
800792c: 6a7b ldr r3, [r7, #36] @ 0x24
800792e: 2b00 cmp r3, #0
8007930: d1e3 bne.n 80078fa <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007932: 687b ldr r3, [r7, #4]
8007934: 6edb ldr r3, [r3, #108] @ 0x6c
8007936: 2b01 cmp r3, #1
8007938: d118 bne.n 800796c <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800793a: 687b ldr r3, [r7, #4]
800793c: 681b ldr r3, [r3, #0]
800793e: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007940: 68fb ldr r3, [r7, #12]
8007942: e853 3f00 ldrex r3, [r3]
8007946: 60bb str r3, [r7, #8]
return(result);
8007948: 68bb ldr r3, [r7, #8]
800794a: f023 0310 bic.w r3, r3, #16
800794e: 647b str r3, [r7, #68] @ 0x44
8007950: 687b ldr r3, [r7, #4]
8007952: 681b ldr r3, [r3, #0]
8007954: 461a mov r2, r3
8007956: 6c7b ldr r3, [r7, #68] @ 0x44
8007958: 61bb str r3, [r7, #24]
800795a: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800795c: 6979 ldr r1, [r7, #20]
800795e: 69ba ldr r2, [r7, #24]
8007960: e841 2300 strex r3, r2, [r1]
8007964: 613b str r3, [r7, #16]
return(result);
8007966: 693b ldr r3, [r7, #16]
8007968: 2b00 cmp r3, #0
800796a: d1e6 bne.n 800793a <UART_EndRxTransfer+0x7a>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800796c: 687b ldr r3, [r7, #4]
800796e: 2220 movs r2, #32
8007970: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007974: 687b ldr r3, [r7, #4]
8007976: 2200 movs r2, #0
8007978: 66da str r2, [r3, #108] @ 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
800797a: 687b ldr r3, [r7, #4]
800797c: 2200 movs r2, #0
800797e: 675a str r2, [r3, #116] @ 0x74
}
8007980: bf00 nop
8007982: 3754 adds r7, #84 @ 0x54
8007984: 46bd mov sp, r7
8007986: f85d 7b04 ldr.w r7, [sp], #4
800798a: 4770 bx lr
0800798c <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
800798c: b580 push {r7, lr}
800798e: b084 sub sp, #16
8007990: af00 add r7, sp, #0
8007992: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8007994: 687b ldr r3, [r7, #4]
8007996: 6a9b ldr r3, [r3, #40] @ 0x28
8007998: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
800799a: 68fb ldr r3, [r7, #12]
800799c: 2200 movs r2, #0
800799e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80079a2: 68f8 ldr r0, [r7, #12]
80079a4: f7ff f9ce bl 8006d44 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80079a8: bf00 nop
80079aa: 3710 adds r7, #16
80079ac: 46bd mov sp, r7
80079ae: bd80 pop {r7, pc}
080079b0 <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
80079b0: b580 push {r7, lr}
80079b2: b088 sub sp, #32
80079b4: af00 add r7, sp, #0
80079b6: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
80079b8: 687b ldr r3, [r7, #4]
80079ba: 681b ldr r3, [r3, #0]
80079bc: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80079be: 68fb ldr r3, [r7, #12]
80079c0: e853 3f00 ldrex r3, [r3]
80079c4: 60bb str r3, [r7, #8]
return(result);
80079c6: 68bb ldr r3, [r7, #8]
80079c8: f023 0340 bic.w r3, r3, #64 @ 0x40
80079cc: 61fb str r3, [r7, #28]
80079ce: 687b ldr r3, [r7, #4]
80079d0: 681b ldr r3, [r3, #0]
80079d2: 461a mov r2, r3
80079d4: 69fb ldr r3, [r7, #28]
80079d6: 61bb str r3, [r7, #24]
80079d8: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80079da: 6979 ldr r1, [r7, #20]
80079dc: 69ba ldr r2, [r7, #24]
80079de: e841 2300 strex r3, r2, [r1]
80079e2: 613b str r3, [r7, #16]
return(result);
80079e4: 693b ldr r3, [r7, #16]
80079e6: 2b00 cmp r3, #0
80079e8: d1e6 bne.n 80079b8 <UART_EndTransmit_IT+0x8>
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80079ea: 687b ldr r3, [r7, #4]
80079ec: 2220 movs r2, #32
80079ee: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
80079f2: 687b ldr r3, [r7, #4]
80079f4: 2200 movs r2, #0
80079f6: 679a str r2, [r3, #120] @ 0x78
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
80079f8: 6878 ldr r0, [r7, #4]
80079fa: f7f9 fea7 bl 800174c <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80079fe: bf00 nop
8007a00: 3720 adds r7, #32
8007a02: 46bd mov sp, r7
8007a04: bd80 pop {r7, pc}
...
08007a08 <UART_RxISR_8BIT>:
* @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
8007a08: b580 push {r7, lr}
8007a0a: b09c sub sp, #112 @ 0x70
8007a0c: af00 add r7, sp, #0
8007a0e: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8007a10: 687b ldr r3, [r7, #4]
8007a12: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007a16: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007a1a: 687b ldr r3, [r7, #4]
8007a1c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007a20: 2b22 cmp r3, #34 @ 0x22
8007a22: f040 80be bne.w 8007ba2 <UART_RxISR_8BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8007a26: 687b ldr r3, [r7, #4]
8007a28: 681b ldr r3, [r3, #0]
8007a2a: 6a5b ldr r3, [r3, #36] @ 0x24
8007a2c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8007a30: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8007a34: b2d9 uxtb r1, r3
8007a36: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
8007a3a: b2da uxtb r2, r3
8007a3c: 687b ldr r3, [r7, #4]
8007a3e: 6d9b ldr r3, [r3, #88] @ 0x58
8007a40: 400a ands r2, r1
8007a42: b2d2 uxtb r2, r2
8007a44: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
8007a46: 687b ldr r3, [r7, #4]
8007a48: 6d9b ldr r3, [r3, #88] @ 0x58
8007a4a: 1c5a adds r2, r3, #1
8007a4c: 687b ldr r3, [r7, #4]
8007a4e: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007a50: 687b ldr r3, [r7, #4]
8007a52: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007a56: b29b uxth r3, r3
8007a58: 3b01 subs r3, #1
8007a5a: b29a uxth r2, r3
8007a5c: 687b ldr r3, [r7, #4]
8007a5e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
if (huart->RxXferCount == 0U)
8007a62: 687b ldr r3, [r7, #4]
8007a64: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007a68: b29b uxth r3, r3
8007a6a: 2b00 cmp r3, #0
8007a6c: f040 80a1 bne.w 8007bb2 <UART_RxISR_8BIT+0x1aa>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8007a70: 687b ldr r3, [r7, #4]
8007a72: 681b ldr r3, [r3, #0]
8007a74: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007a76: 6cfb ldr r3, [r7, #76] @ 0x4c
8007a78: e853 3f00 ldrex r3, [r3]
8007a7c: 64bb str r3, [r7, #72] @ 0x48
return(result);
8007a7e: 6cbb ldr r3, [r7, #72] @ 0x48
8007a80: f423 7390 bic.w r3, r3, #288 @ 0x120
8007a84: 66bb str r3, [r7, #104] @ 0x68
8007a86: 687b ldr r3, [r7, #4]
8007a88: 681b ldr r3, [r3, #0]
8007a8a: 461a mov r2, r3
8007a8c: 6ebb ldr r3, [r7, #104] @ 0x68
8007a8e: 65bb str r3, [r7, #88] @ 0x58
8007a90: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007a92: 6d79 ldr r1, [r7, #84] @ 0x54
8007a94: 6dba ldr r2, [r7, #88] @ 0x58
8007a96: e841 2300 strex r3, r2, [r1]
8007a9a: 653b str r3, [r7, #80] @ 0x50
return(result);
8007a9c: 6d3b ldr r3, [r7, #80] @ 0x50
8007a9e: 2b00 cmp r3, #0
8007aa0: d1e6 bne.n 8007a70 <UART_RxISR_8BIT+0x68>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8007aa2: 687b ldr r3, [r7, #4]
8007aa4: 681b ldr r3, [r3, #0]
8007aa6: 3308 adds r3, #8
8007aa8: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007aaa: 6bbb ldr r3, [r7, #56] @ 0x38
8007aac: e853 3f00 ldrex r3, [r3]
8007ab0: 637b str r3, [r7, #52] @ 0x34
return(result);
8007ab2: 6b7b ldr r3, [r7, #52] @ 0x34
8007ab4: f023 0301 bic.w r3, r3, #1
8007ab8: 667b str r3, [r7, #100] @ 0x64
8007aba: 687b ldr r3, [r7, #4]
8007abc: 681b ldr r3, [r3, #0]
8007abe: 3308 adds r3, #8
8007ac0: 6e7a ldr r2, [r7, #100] @ 0x64
8007ac2: 647a str r2, [r7, #68] @ 0x44
8007ac4: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007ac6: 6c39 ldr r1, [r7, #64] @ 0x40
8007ac8: 6c7a ldr r2, [r7, #68] @ 0x44
8007aca: e841 2300 strex r3, r2, [r1]
8007ace: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8007ad0: 6bfb ldr r3, [r7, #60] @ 0x3c
8007ad2: 2b00 cmp r3, #0
8007ad4: d1e5 bne.n 8007aa2 <UART_RxISR_8BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007ad6: 687b ldr r3, [r7, #4]
8007ad8: 2220 movs r2, #32
8007ada: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007ade: 687b ldr r3, [r7, #4]
8007ae0: 2200 movs r2, #0
8007ae2: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007ae4: 687b ldr r3, [r7, #4]
8007ae6: 2200 movs r2, #0
8007ae8: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007aea: 687b ldr r3, [r7, #4]
8007aec: 681b ldr r3, [r3, #0]
8007aee: 4a33 ldr r2, [pc, #204] @ (8007bbc <UART_RxISR_8BIT+0x1b4>)
8007af0: 4293 cmp r3, r2
8007af2: d01f beq.n 8007b34 <UART_RxISR_8BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007af4: 687b ldr r3, [r7, #4]
8007af6: 681b ldr r3, [r3, #0]
8007af8: 685b ldr r3, [r3, #4]
8007afa: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007afe: 2b00 cmp r3, #0
8007b00: d018 beq.n 8007b34 <UART_RxISR_8BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007b02: 687b ldr r3, [r7, #4]
8007b04: 681b ldr r3, [r3, #0]
8007b06: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007b08: 6a7b ldr r3, [r7, #36] @ 0x24
8007b0a: e853 3f00 ldrex r3, [r3]
8007b0e: 623b str r3, [r7, #32]
return(result);
8007b10: 6a3b ldr r3, [r7, #32]
8007b12: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007b16: 663b str r3, [r7, #96] @ 0x60
8007b18: 687b ldr r3, [r7, #4]
8007b1a: 681b ldr r3, [r3, #0]
8007b1c: 461a mov r2, r3
8007b1e: 6e3b ldr r3, [r7, #96] @ 0x60
8007b20: 633b str r3, [r7, #48] @ 0x30
8007b22: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007b24: 6af9 ldr r1, [r7, #44] @ 0x2c
8007b26: 6b3a ldr r2, [r7, #48] @ 0x30
8007b28: e841 2300 strex r3, r2, [r1]
8007b2c: 62bb str r3, [r7, #40] @ 0x28
return(result);
8007b2e: 6abb ldr r3, [r7, #40] @ 0x28
8007b30: 2b00 cmp r3, #0
8007b32: d1e6 bne.n 8007b02 <UART_RxISR_8BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007b34: 687b ldr r3, [r7, #4]
8007b36: 6edb ldr r3, [r3, #108] @ 0x6c
8007b38: 2b01 cmp r3, #1
8007b3a: d12e bne.n 8007b9a <UART_RxISR_8BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007b3c: 687b ldr r3, [r7, #4]
8007b3e: 2200 movs r2, #0
8007b40: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007b42: 687b ldr r3, [r7, #4]
8007b44: 681b ldr r3, [r3, #0]
8007b46: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007b48: 693b ldr r3, [r7, #16]
8007b4a: e853 3f00 ldrex r3, [r3]
8007b4e: 60fb str r3, [r7, #12]
return(result);
8007b50: 68fb ldr r3, [r7, #12]
8007b52: f023 0310 bic.w r3, r3, #16
8007b56: 65fb str r3, [r7, #92] @ 0x5c
8007b58: 687b ldr r3, [r7, #4]
8007b5a: 681b ldr r3, [r3, #0]
8007b5c: 461a mov r2, r3
8007b5e: 6dfb ldr r3, [r7, #92] @ 0x5c
8007b60: 61fb str r3, [r7, #28]
8007b62: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007b64: 69b9 ldr r1, [r7, #24]
8007b66: 69fa ldr r2, [r7, #28]
8007b68: e841 2300 strex r3, r2, [r1]
8007b6c: 617b str r3, [r7, #20]
return(result);
8007b6e: 697b ldr r3, [r7, #20]
8007b70: 2b00 cmp r3, #0
8007b72: d1e6 bne.n 8007b42 <UART_RxISR_8BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007b74: 687b ldr r3, [r7, #4]
8007b76: 681b ldr r3, [r3, #0]
8007b78: 69db ldr r3, [r3, #28]
8007b7a: f003 0310 and.w r3, r3, #16
8007b7e: 2b10 cmp r3, #16
8007b80: d103 bne.n 8007b8a <UART_RxISR_8BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007b82: 687b ldr r3, [r7, #4]
8007b84: 681b ldr r3, [r3, #0]
8007b86: 2210 movs r2, #16
8007b88: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007b8a: 687b ldr r3, [r7, #4]
8007b8c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007b90: 4619 mov r1, r3
8007b92: 6878 ldr r0, [r7, #4]
8007b94: f7ff f8e0 bl 8006d58 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007b98: e00b b.n 8007bb2 <UART_RxISR_8BIT+0x1aa>
HAL_UART_RxCpltCallback(huart);
8007b9a: 6878 ldr r0, [r7, #4]
8007b9c: f7f9 fde0 bl 8001760 <HAL_UART_RxCpltCallback>
}
8007ba0: e007 b.n 8007bb2 <UART_RxISR_8BIT+0x1aa>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007ba2: 687b ldr r3, [r7, #4]
8007ba4: 681b ldr r3, [r3, #0]
8007ba6: 699a ldr r2, [r3, #24]
8007ba8: 687b ldr r3, [r7, #4]
8007baa: 681b ldr r3, [r3, #0]
8007bac: f042 0208 orr.w r2, r2, #8
8007bb0: 619a str r2, [r3, #24]
}
8007bb2: bf00 nop
8007bb4: 3770 adds r7, #112 @ 0x70
8007bb6: 46bd mov sp, r7
8007bb8: bd80 pop {r7, pc}
8007bba: bf00 nop
8007bbc: 40008000 .word 0x40008000
08007bc0 <UART_RxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
8007bc0: b580 push {r7, lr}
8007bc2: b09c sub sp, #112 @ 0x70
8007bc4: af00 add r7, sp, #0
8007bc6: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8007bc8: 687b ldr r3, [r7, #4]
8007bca: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007bce: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007bd2: 687b ldr r3, [r7, #4]
8007bd4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007bd8: 2b22 cmp r3, #34 @ 0x22
8007bda: f040 80be bne.w 8007d5a <UART_RxISR_16BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8007bde: 687b ldr r3, [r7, #4]
8007be0: 681b ldr r3, [r3, #0]
8007be2: 6a5b ldr r3, [r3, #36] @ 0x24
8007be4: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
tmp = (uint16_t *) huart->pRxBuffPtr ;
8007be8: 687b ldr r3, [r7, #4]
8007bea: 6d9b ldr r3, [r3, #88] @ 0x58
8007bec: 66bb str r3, [r7, #104] @ 0x68
*tmp = (uint16_t)(uhdata & uhMask);
8007bee: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c
8007bf2: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
8007bf6: 4013 ands r3, r2
8007bf8: b29a uxth r2, r3
8007bfa: 6ebb ldr r3, [r7, #104] @ 0x68
8007bfc: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8007bfe: 687b ldr r3, [r7, #4]
8007c00: 6d9b ldr r3, [r3, #88] @ 0x58
8007c02: 1c9a adds r2, r3, #2
8007c04: 687b ldr r3, [r7, #4]
8007c06: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007c08: 687b ldr r3, [r7, #4]
8007c0a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007c0e: b29b uxth r3, r3
8007c10: 3b01 subs r3, #1
8007c12: b29a uxth r2, r3
8007c14: 687b ldr r3, [r7, #4]
8007c16: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
if (huart->RxXferCount == 0U)
8007c1a: 687b ldr r3, [r7, #4]
8007c1c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007c20: b29b uxth r3, r3
8007c22: 2b00 cmp r3, #0
8007c24: f040 80a1 bne.w 8007d6a <UART_RxISR_16BIT+0x1aa>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8007c28: 687b ldr r3, [r7, #4]
8007c2a: 681b ldr r3, [r3, #0]
8007c2c: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007c2e: 6cbb ldr r3, [r7, #72] @ 0x48
8007c30: e853 3f00 ldrex r3, [r3]
8007c34: 647b str r3, [r7, #68] @ 0x44
return(result);
8007c36: 6c7b ldr r3, [r7, #68] @ 0x44
8007c38: f423 7390 bic.w r3, r3, #288 @ 0x120
8007c3c: 667b str r3, [r7, #100] @ 0x64
8007c3e: 687b ldr r3, [r7, #4]
8007c40: 681b ldr r3, [r3, #0]
8007c42: 461a mov r2, r3
8007c44: 6e7b ldr r3, [r7, #100] @ 0x64
8007c46: 657b str r3, [r7, #84] @ 0x54
8007c48: 653a str r2, [r7, #80] @ 0x50
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007c4a: 6d39 ldr r1, [r7, #80] @ 0x50
8007c4c: 6d7a ldr r2, [r7, #84] @ 0x54
8007c4e: e841 2300 strex r3, r2, [r1]
8007c52: 64fb str r3, [r7, #76] @ 0x4c
return(result);
8007c54: 6cfb ldr r3, [r7, #76] @ 0x4c
8007c56: 2b00 cmp r3, #0
8007c58: d1e6 bne.n 8007c28 <UART_RxISR_16BIT+0x68>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8007c5a: 687b ldr r3, [r7, #4]
8007c5c: 681b ldr r3, [r3, #0]
8007c5e: 3308 adds r3, #8
8007c60: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007c62: 6b7b ldr r3, [r7, #52] @ 0x34
8007c64: e853 3f00 ldrex r3, [r3]
8007c68: 633b str r3, [r7, #48] @ 0x30
return(result);
8007c6a: 6b3b ldr r3, [r7, #48] @ 0x30
8007c6c: f023 0301 bic.w r3, r3, #1
8007c70: 663b str r3, [r7, #96] @ 0x60
8007c72: 687b ldr r3, [r7, #4]
8007c74: 681b ldr r3, [r3, #0]
8007c76: 3308 adds r3, #8
8007c78: 6e3a ldr r2, [r7, #96] @ 0x60
8007c7a: 643a str r2, [r7, #64] @ 0x40
8007c7c: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007c7e: 6bf9 ldr r1, [r7, #60] @ 0x3c
8007c80: 6c3a ldr r2, [r7, #64] @ 0x40
8007c82: e841 2300 strex r3, r2, [r1]
8007c86: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007c88: 6bbb ldr r3, [r7, #56] @ 0x38
8007c8a: 2b00 cmp r3, #0
8007c8c: d1e5 bne.n 8007c5a <UART_RxISR_16BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007c8e: 687b ldr r3, [r7, #4]
8007c90: 2220 movs r2, #32
8007c92: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007c96: 687b ldr r3, [r7, #4]
8007c98: 2200 movs r2, #0
8007c9a: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007c9c: 687b ldr r3, [r7, #4]
8007c9e: 2200 movs r2, #0
8007ca0: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007ca2: 687b ldr r3, [r7, #4]
8007ca4: 681b ldr r3, [r3, #0]
8007ca6: 4a33 ldr r2, [pc, #204] @ (8007d74 <UART_RxISR_16BIT+0x1b4>)
8007ca8: 4293 cmp r3, r2
8007caa: d01f beq.n 8007cec <UART_RxISR_16BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007cac: 687b ldr r3, [r7, #4]
8007cae: 681b ldr r3, [r3, #0]
8007cb0: 685b ldr r3, [r3, #4]
8007cb2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007cb6: 2b00 cmp r3, #0
8007cb8: d018 beq.n 8007cec <UART_RxISR_16BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007cba: 687b ldr r3, [r7, #4]
8007cbc: 681b ldr r3, [r3, #0]
8007cbe: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007cc0: 6a3b ldr r3, [r7, #32]
8007cc2: e853 3f00 ldrex r3, [r3]
8007cc6: 61fb str r3, [r7, #28]
return(result);
8007cc8: 69fb ldr r3, [r7, #28]
8007cca: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007cce: 65fb str r3, [r7, #92] @ 0x5c
8007cd0: 687b ldr r3, [r7, #4]
8007cd2: 681b ldr r3, [r3, #0]
8007cd4: 461a mov r2, r3
8007cd6: 6dfb ldr r3, [r7, #92] @ 0x5c
8007cd8: 62fb str r3, [r7, #44] @ 0x2c
8007cda: 62ba str r2, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007cdc: 6ab9 ldr r1, [r7, #40] @ 0x28
8007cde: 6afa ldr r2, [r7, #44] @ 0x2c
8007ce0: e841 2300 strex r3, r2, [r1]
8007ce4: 627b str r3, [r7, #36] @ 0x24
return(result);
8007ce6: 6a7b ldr r3, [r7, #36] @ 0x24
8007ce8: 2b00 cmp r3, #0
8007cea: d1e6 bne.n 8007cba <UART_RxISR_16BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007cec: 687b ldr r3, [r7, #4]
8007cee: 6edb ldr r3, [r3, #108] @ 0x6c
8007cf0: 2b01 cmp r3, #1
8007cf2: d12e bne.n 8007d52 <UART_RxISR_16BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007cf4: 687b ldr r3, [r7, #4]
8007cf6: 2200 movs r2, #0
8007cf8: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007cfa: 687b ldr r3, [r7, #4]
8007cfc: 681b ldr r3, [r3, #0]
8007cfe: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007d00: 68fb ldr r3, [r7, #12]
8007d02: e853 3f00 ldrex r3, [r3]
8007d06: 60bb str r3, [r7, #8]
return(result);
8007d08: 68bb ldr r3, [r7, #8]
8007d0a: f023 0310 bic.w r3, r3, #16
8007d0e: 65bb str r3, [r7, #88] @ 0x58
8007d10: 687b ldr r3, [r7, #4]
8007d12: 681b ldr r3, [r3, #0]
8007d14: 461a mov r2, r3
8007d16: 6dbb ldr r3, [r7, #88] @ 0x58
8007d18: 61bb str r3, [r7, #24]
8007d1a: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007d1c: 6979 ldr r1, [r7, #20]
8007d1e: 69ba ldr r2, [r7, #24]
8007d20: e841 2300 strex r3, r2, [r1]
8007d24: 613b str r3, [r7, #16]
return(result);
8007d26: 693b ldr r3, [r7, #16]
8007d28: 2b00 cmp r3, #0
8007d2a: d1e6 bne.n 8007cfa <UART_RxISR_16BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007d2c: 687b ldr r3, [r7, #4]
8007d2e: 681b ldr r3, [r3, #0]
8007d30: 69db ldr r3, [r3, #28]
8007d32: f003 0310 and.w r3, r3, #16
8007d36: 2b10 cmp r3, #16
8007d38: d103 bne.n 8007d42 <UART_RxISR_16BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007d3a: 687b ldr r3, [r7, #4]
8007d3c: 681b ldr r3, [r3, #0]
8007d3e: 2210 movs r2, #16
8007d40: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007d42: 687b ldr r3, [r7, #4]
8007d44: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007d48: 4619 mov r1, r3
8007d4a: 6878 ldr r0, [r7, #4]
8007d4c: f7ff f804 bl 8006d58 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007d50: e00b b.n 8007d6a <UART_RxISR_16BIT+0x1aa>
HAL_UART_RxCpltCallback(huart);
8007d52: 6878 ldr r0, [r7, #4]
8007d54: f7f9 fd04 bl 8001760 <HAL_UART_RxCpltCallback>
}
8007d58: e007 b.n 8007d6a <UART_RxISR_16BIT+0x1aa>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007d5a: 687b ldr r3, [r7, #4]
8007d5c: 681b ldr r3, [r3, #0]
8007d5e: 699a ldr r2, [r3, #24]
8007d60: 687b ldr r3, [r7, #4]
8007d62: 681b ldr r3, [r3, #0]
8007d64: f042 0208 orr.w r2, r2, #8
8007d68: 619a str r2, [r3, #24]
}
8007d6a: bf00 nop
8007d6c: 3770 adds r7, #112 @ 0x70
8007d6e: 46bd mov sp, r7
8007d70: bd80 pop {r7, pc}
8007d72: bf00 nop
8007d74: 40008000 .word 0x40008000
08007d78 <UART_RxISR_8BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
8007d78: b580 push {r7, lr}
8007d7a: b0ac sub sp, #176 @ 0xb0
8007d7c: af00 add r7, sp, #0
8007d7e: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8007d80: 687b ldr r3, [r7, #4]
8007d82: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007d86: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8007d8a: 687b ldr r3, [r7, #4]
8007d8c: 681b ldr r3, [r3, #0]
8007d8e: 69db ldr r3, [r3, #28]
8007d90: f8c7 30ac str.w r3, [r7, #172] @ 0xac
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8007d94: 687b ldr r3, [r7, #4]
8007d96: 681b ldr r3, [r3, #0]
8007d98: 681b ldr r3, [r3, #0]
8007d9a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8007d9e: 687b ldr r3, [r7, #4]
8007da0: 681b ldr r3, [r3, #0]
8007da2: 689b ldr r3, [r3, #8]
8007da4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007da8: 687b ldr r3, [r7, #4]
8007daa: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007dae: 2b22 cmp r3, #34 @ 0x22
8007db0: f040 8183 bne.w 80080ba <UART_RxISR_8BIT_FIFOEN+0x342>
{
nb_rx_data = huart->NbRxDataToProcess;
8007db4: 687b ldr r3, [r7, #4]
8007db6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8007dba: f8a7 309e strh.w r3, [r7, #158] @ 0x9e
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8007dbe: e126 b.n 800800e <UART_RxISR_8BIT_FIFOEN+0x296>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8007dc0: 687b ldr r3, [r7, #4]
8007dc2: 681b ldr r3, [r3, #0]
8007dc4: 6a5b ldr r3, [r3, #36] @ 0x24
8007dc6: f8a7 309c strh.w r3, [r7, #156] @ 0x9c
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8007dca: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c
8007dce: b2d9 uxtb r1, r3
8007dd0: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa
8007dd4: b2da uxtb r2, r3
8007dd6: 687b ldr r3, [r7, #4]
8007dd8: 6d9b ldr r3, [r3, #88] @ 0x58
8007dda: 400a ands r2, r1
8007ddc: b2d2 uxtb r2, r2
8007dde: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
8007de0: 687b ldr r3, [r7, #4]
8007de2: 6d9b ldr r3, [r3, #88] @ 0x58
8007de4: 1c5a adds r2, r3, #1
8007de6: 687b ldr r3, [r7, #4]
8007de8: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007dea: 687b ldr r3, [r7, #4]
8007dec: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007df0: b29b uxth r3, r3
8007df2: 3b01 subs r3, #1
8007df4: b29a uxth r2, r3
8007df6: 687b ldr r3, [r7, #4]
8007df8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
isrflags = READ_REG(huart->Instance->ISR);
8007dfc: 687b ldr r3, [r7, #4]
8007dfe: 681b ldr r3, [r3, #0]
8007e00: 69db ldr r3, [r3, #28]
8007e02: f8c7 30ac str.w r3, [r7, #172] @ 0xac
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
8007e06: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007e0a: f003 0307 and.w r3, r3, #7
8007e0e: 2b00 cmp r3, #0
8007e10: d053 beq.n 8007eba <UART_RxISR_8BIT_FIFOEN+0x142>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8007e12: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007e16: f003 0301 and.w r3, r3, #1
8007e1a: 2b00 cmp r3, #0
8007e1c: d011 beq.n 8007e42 <UART_RxISR_8BIT_FIFOEN+0xca>
8007e1e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8007e22: f403 7380 and.w r3, r3, #256 @ 0x100
8007e26: 2b00 cmp r3, #0
8007e28: d00b beq.n 8007e42 <UART_RxISR_8BIT_FIFOEN+0xca>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8007e2a: 687b ldr r3, [r7, #4]
8007e2c: 681b ldr r3, [r3, #0]
8007e2e: 2201 movs r2, #1
8007e30: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8007e32: 687b ldr r3, [r7, #4]
8007e34: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007e38: f043 0201 orr.w r2, r3, #1
8007e3c: 687b ldr r3, [r7, #4]
8007e3e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007e42: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007e46: f003 0302 and.w r3, r3, #2
8007e4a: 2b00 cmp r3, #0
8007e4c: d011 beq.n 8007e72 <UART_RxISR_8BIT_FIFOEN+0xfa>
8007e4e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8007e52: f003 0301 and.w r3, r3, #1
8007e56: 2b00 cmp r3, #0
8007e58: d00b beq.n 8007e72 <UART_RxISR_8BIT_FIFOEN+0xfa>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8007e5a: 687b ldr r3, [r7, #4]
8007e5c: 681b ldr r3, [r3, #0]
8007e5e: 2202 movs r2, #2
8007e60: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8007e62: 687b ldr r3, [r7, #4]
8007e64: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007e68: f043 0204 orr.w r2, r3, #4
8007e6c: 687b ldr r3, [r7, #4]
8007e6e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007e72: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007e76: f003 0304 and.w r3, r3, #4
8007e7a: 2b00 cmp r3, #0
8007e7c: d011 beq.n 8007ea2 <UART_RxISR_8BIT_FIFOEN+0x12a>
8007e7e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8007e82: f003 0301 and.w r3, r3, #1
8007e86: 2b00 cmp r3, #0
8007e88: d00b beq.n 8007ea2 <UART_RxISR_8BIT_FIFOEN+0x12a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8007e8a: 687b ldr r3, [r7, #4]
8007e8c: 681b ldr r3, [r3, #0]
8007e8e: 2204 movs r2, #4
8007e90: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8007e92: 687b ldr r3, [r7, #4]
8007e94: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007e98: f043 0202 orr.w r2, r3, #2
8007e9c: 687b ldr r3, [r7, #4]
8007e9e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8007ea2: 687b ldr r3, [r7, #4]
8007ea4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007ea8: 2b00 cmp r3, #0
8007eaa: d006 beq.n 8007eba <UART_RxISR_8BIT_FIFOEN+0x142>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8007eac: 6878 ldr r0, [r7, #4]
8007eae: f7fe ff49 bl 8006d44 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007eb2: 687b ldr r3, [r7, #4]
8007eb4: 2200 movs r2, #0
8007eb6: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
if (huart->RxXferCount == 0U)
8007eba: 687b ldr r3, [r7, #4]
8007ebc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007ec0: b29b uxth r3, r3
8007ec2: 2b00 cmp r3, #0
8007ec4: f040 80a3 bne.w 800800e <UART_RxISR_8BIT_FIFOEN+0x296>
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8007ec8: 687b ldr r3, [r7, #4]
8007eca: 681b ldr r3, [r3, #0]
8007ecc: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007ece: 6f3b ldr r3, [r7, #112] @ 0x70
8007ed0: e853 3f00 ldrex r3, [r3]
8007ed4: 66fb str r3, [r7, #108] @ 0x6c
return(result);
8007ed6: 6efb ldr r3, [r7, #108] @ 0x6c
8007ed8: f423 7380 bic.w r3, r3, #256 @ 0x100
8007edc: f8c7 3098 str.w r3, [r7, #152] @ 0x98
8007ee0: 687b ldr r3, [r7, #4]
8007ee2: 681b ldr r3, [r3, #0]
8007ee4: 461a mov r2, r3
8007ee6: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8007eea: 67fb str r3, [r7, #124] @ 0x7c
8007eec: 67ba str r2, [r7, #120] @ 0x78
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007eee: 6fb9 ldr r1, [r7, #120] @ 0x78
8007ef0: 6ffa ldr r2, [r7, #124] @ 0x7c
8007ef2: e841 2300 strex r3, r2, [r1]
8007ef6: 677b str r3, [r7, #116] @ 0x74
return(result);
8007ef8: 6f7b ldr r3, [r7, #116] @ 0x74
8007efa: 2b00 cmp r3, #0
8007efc: d1e4 bne.n 8007ec8 <UART_RxISR_8BIT_FIFOEN+0x150>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8007efe: 687b ldr r3, [r7, #4]
8007f00: 681b ldr r3, [r3, #0]
8007f02: 3308 adds r3, #8
8007f04: 65fb str r3, [r7, #92] @ 0x5c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007f06: 6dfb ldr r3, [r7, #92] @ 0x5c
8007f08: e853 3f00 ldrex r3, [r3]
8007f0c: 65bb str r3, [r7, #88] @ 0x58
return(result);
8007f0e: 6dbb ldr r3, [r7, #88] @ 0x58
8007f10: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007f14: f023 0301 bic.w r3, r3, #1
8007f18: f8c7 3094 str.w r3, [r7, #148] @ 0x94
8007f1c: 687b ldr r3, [r7, #4]
8007f1e: 681b ldr r3, [r3, #0]
8007f20: 3308 adds r3, #8
8007f22: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
8007f26: 66ba str r2, [r7, #104] @ 0x68
8007f28: 667b str r3, [r7, #100] @ 0x64
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007f2a: 6e79 ldr r1, [r7, #100] @ 0x64
8007f2c: 6eba ldr r2, [r7, #104] @ 0x68
8007f2e: e841 2300 strex r3, r2, [r1]
8007f32: 663b str r3, [r7, #96] @ 0x60
return(result);
8007f34: 6e3b ldr r3, [r7, #96] @ 0x60
8007f36: 2b00 cmp r3, #0
8007f38: d1e1 bne.n 8007efe <UART_RxISR_8BIT_FIFOEN+0x186>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007f3a: 687b ldr r3, [r7, #4]
8007f3c: 2220 movs r2, #32
8007f3e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007f42: 687b ldr r3, [r7, #4]
8007f44: 2200 movs r2, #0
8007f46: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007f48: 687b ldr r3, [r7, #4]
8007f4a: 2200 movs r2, #0
8007f4c: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007f4e: 687b ldr r3, [r7, #4]
8007f50: 681b ldr r3, [r3, #0]
8007f52: 4a60 ldr r2, [pc, #384] @ (80080d4 <UART_RxISR_8BIT_FIFOEN+0x35c>)
8007f54: 4293 cmp r3, r2
8007f56: d021 beq.n 8007f9c <UART_RxISR_8BIT_FIFOEN+0x224>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007f58: 687b ldr r3, [r7, #4]
8007f5a: 681b ldr r3, [r3, #0]
8007f5c: 685b ldr r3, [r3, #4]
8007f5e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007f62: 2b00 cmp r3, #0
8007f64: d01a beq.n 8007f9c <UART_RxISR_8BIT_FIFOEN+0x224>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007f66: 687b ldr r3, [r7, #4]
8007f68: 681b ldr r3, [r3, #0]
8007f6a: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007f6c: 6cbb ldr r3, [r7, #72] @ 0x48
8007f6e: e853 3f00 ldrex r3, [r3]
8007f72: 647b str r3, [r7, #68] @ 0x44
return(result);
8007f74: 6c7b ldr r3, [r7, #68] @ 0x44
8007f76: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007f7a: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8007f7e: 687b ldr r3, [r7, #4]
8007f80: 681b ldr r3, [r3, #0]
8007f82: 461a mov r2, r3
8007f84: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8007f88: 657b str r3, [r7, #84] @ 0x54
8007f8a: 653a str r2, [r7, #80] @ 0x50
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007f8c: 6d39 ldr r1, [r7, #80] @ 0x50
8007f8e: 6d7a ldr r2, [r7, #84] @ 0x54
8007f90: e841 2300 strex r3, r2, [r1]
8007f94: 64fb str r3, [r7, #76] @ 0x4c
return(result);
8007f96: 6cfb ldr r3, [r7, #76] @ 0x4c
8007f98: 2b00 cmp r3, #0
8007f9a: d1e4 bne.n 8007f66 <UART_RxISR_8BIT_FIFOEN+0x1ee>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007f9c: 687b ldr r3, [r7, #4]
8007f9e: 6edb ldr r3, [r3, #108] @ 0x6c
8007fa0: 2b01 cmp r3, #1
8007fa2: d130 bne.n 8008006 <UART_RxISR_8BIT_FIFOEN+0x28e>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007fa4: 687b ldr r3, [r7, #4]
8007fa6: 2200 movs r2, #0
8007fa8: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007faa: 687b ldr r3, [r7, #4]
8007fac: 681b ldr r3, [r3, #0]
8007fae: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007fb0: 6b7b ldr r3, [r7, #52] @ 0x34
8007fb2: e853 3f00 ldrex r3, [r3]
8007fb6: 633b str r3, [r7, #48] @ 0x30
return(result);
8007fb8: 6b3b ldr r3, [r7, #48] @ 0x30
8007fba: f023 0310 bic.w r3, r3, #16
8007fbe: f8c7 308c str.w r3, [r7, #140] @ 0x8c
8007fc2: 687b ldr r3, [r7, #4]
8007fc4: 681b ldr r3, [r3, #0]
8007fc6: 461a mov r2, r3
8007fc8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8007fcc: 643b str r3, [r7, #64] @ 0x40
8007fce: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007fd0: 6bf9 ldr r1, [r7, #60] @ 0x3c
8007fd2: 6c3a ldr r2, [r7, #64] @ 0x40
8007fd4: e841 2300 strex r3, r2, [r1]
8007fd8: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007fda: 6bbb ldr r3, [r7, #56] @ 0x38
8007fdc: 2b00 cmp r3, #0
8007fde: d1e4 bne.n 8007faa <UART_RxISR_8BIT_FIFOEN+0x232>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007fe0: 687b ldr r3, [r7, #4]
8007fe2: 681b ldr r3, [r3, #0]
8007fe4: 69db ldr r3, [r3, #28]
8007fe6: f003 0310 and.w r3, r3, #16
8007fea: 2b10 cmp r3, #16
8007fec: d103 bne.n 8007ff6 <UART_RxISR_8BIT_FIFOEN+0x27e>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007fee: 687b ldr r3, [r7, #4]
8007ff0: 681b ldr r3, [r3, #0]
8007ff2: 2210 movs r2, #16
8007ff4: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007ff6: 687b ldr r3, [r7, #4]
8007ff8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007ffc: 4619 mov r1, r3
8007ffe: 6878 ldr r0, [r7, #4]
8008000: f7fe feaa bl 8006d58 <HAL_UARTEx_RxEventCallback>
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
break;
8008004: e00e b.n 8008024 <UART_RxISR_8BIT_FIFOEN+0x2ac>
HAL_UART_RxCpltCallback(huart);
8008006: 6878 ldr r0, [r7, #4]
8008008: f7f9 fbaa bl 8001760 <HAL_UART_RxCpltCallback>
break;
800800c: e00a b.n 8008024 <UART_RxISR_8BIT_FIFOEN+0x2ac>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
800800e: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e
8008012: 2b00 cmp r3, #0
8008014: d006 beq.n 8008024 <UART_RxISR_8BIT_FIFOEN+0x2ac>
8008016: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800801a: f003 0320 and.w r3, r3, #32
800801e: 2b00 cmp r3, #0
8008020: f47f aece bne.w 8007dc0 <UART_RxISR_8BIT_FIFOEN+0x48>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8008024: 687b ldr r3, [r7, #4]
8008026: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800802a: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
800802e: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8008032: 2b00 cmp r3, #0
8008034: d049 beq.n 80080ca <UART_RxISR_8BIT_FIFOEN+0x352>
8008036: 687b ldr r3, [r7, #4]
8008038: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
800803c: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a
8008040: 429a cmp r2, r3
8008042: d242 bcs.n 80080ca <UART_RxISR_8BIT_FIFOEN+0x352>
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
8008044: 687b ldr r3, [r7, #4]
8008046: 681b ldr r3, [r3, #0]
8008048: 3308 adds r3, #8
800804a: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800804c: 6a3b ldr r3, [r7, #32]
800804e: e853 3f00 ldrex r3, [r3]
8008052: 61fb str r3, [r7, #28]
return(result);
8008054: 69fb ldr r3, [r7, #28]
8008056: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800805a: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800805e: 687b ldr r3, [r7, #4]
8008060: 681b ldr r3, [r3, #0]
8008062: 3308 adds r3, #8
8008064: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
8008068: 62fa str r2, [r7, #44] @ 0x2c
800806a: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800806c: 6ab9 ldr r1, [r7, #40] @ 0x28
800806e: 6afa ldr r2, [r7, #44] @ 0x2c
8008070: e841 2300 strex r3, r2, [r1]
8008074: 627b str r3, [r7, #36] @ 0x24
return(result);
8008076: 6a7b ldr r3, [r7, #36] @ 0x24
8008078: 2b00 cmp r3, #0
800807a: d1e3 bne.n 8008044 <UART_RxISR_8BIT_FIFOEN+0x2cc>
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_8BIT;
800807c: 687b ldr r3, [r7, #4]
800807e: 4a16 ldr r2, [pc, #88] @ (80080d8 <UART_RxISR_8BIT_FIFOEN+0x360>)
8008080: 675a str r2, [r3, #116] @ 0x74
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8008082: 687b ldr r3, [r7, #4]
8008084: 681b ldr r3, [r3, #0]
8008086: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8008088: 68fb ldr r3, [r7, #12]
800808a: e853 3f00 ldrex r3, [r3]
800808e: 60bb str r3, [r7, #8]
return(result);
8008090: 68bb ldr r3, [r7, #8]
8008092: f043 0320 orr.w r3, r3, #32
8008096: f8c7 3080 str.w r3, [r7, #128] @ 0x80
800809a: 687b ldr r3, [r7, #4]
800809c: 681b ldr r3, [r3, #0]
800809e: 461a mov r2, r3
80080a0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
80080a4: 61bb str r3, [r7, #24]
80080a6: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80080a8: 6979 ldr r1, [r7, #20]
80080aa: 69ba ldr r2, [r7, #24]
80080ac: e841 2300 strex r3, r2, [r1]
80080b0: 613b str r3, [r7, #16]
return(result);
80080b2: 693b ldr r3, [r7, #16]
80080b4: 2b00 cmp r3, #0
80080b6: d1e4 bne.n 8008082 <UART_RxISR_8BIT_FIFOEN+0x30a>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
80080b8: e007 b.n 80080ca <UART_RxISR_8BIT_FIFOEN+0x352>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
80080ba: 687b ldr r3, [r7, #4]
80080bc: 681b ldr r3, [r3, #0]
80080be: 699a ldr r2, [r3, #24]
80080c0: 687b ldr r3, [r7, #4]
80080c2: 681b ldr r3, [r3, #0]
80080c4: f042 0208 orr.w r2, r2, #8
80080c8: 619a str r2, [r3, #24]
}
80080ca: bf00 nop
80080cc: 37b0 adds r7, #176 @ 0xb0
80080ce: 46bd mov sp, r7
80080d0: bd80 pop {r7, pc}
80080d2: bf00 nop
80080d4: 40008000 .word 0x40008000
80080d8: 08007a09 .word 0x08007a09
080080dc <UART_RxISR_16BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
80080dc: b580 push {r7, lr}
80080de: b0ae sub sp, #184 @ 0xb8
80080e0: af00 add r7, sp, #0
80080e2: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
80080e4: 687b ldr r3, [r7, #4]
80080e6: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
80080ea: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
80080ee: 687b ldr r3, [r7, #4]
80080f0: 681b ldr r3, [r3, #0]
80080f2: 69db ldr r3, [r3, #28]
80080f4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80080f8: 687b ldr r3, [r7, #4]
80080fa: 681b ldr r3, [r3, #0]
80080fc: 681b ldr r3, [r3, #0]
80080fe: f8c7 30ac str.w r3, [r7, #172] @ 0xac
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8008102: 687b ldr r3, [r7, #4]
8008104: 681b ldr r3, [r3, #0]
8008106: 689b ldr r3, [r3, #8]
8008108: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
800810c: 687b ldr r3, [r7, #4]
800810e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8008112: 2b22 cmp r3, #34 @ 0x22
8008114: f040 8187 bne.w 8008426 <UART_RxISR_16BIT_FIFOEN+0x34a>
{
nb_rx_data = huart->NbRxDataToProcess;
8008118: 687b ldr r3, [r7, #4]
800811a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
800811e: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8008122: e12a b.n 800837a <UART_RxISR_16BIT_FIFOEN+0x29e>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8008124: 687b ldr r3, [r7, #4]
8008126: 681b ldr r3, [r3, #0]
8008128: 6a5b ldr r3, [r3, #36] @ 0x24
800812a: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4
tmp = (uint16_t *) huart->pRxBuffPtr ;
800812e: 687b ldr r3, [r7, #4]
8008130: 6d9b ldr r3, [r3, #88] @ 0x58
8008132: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
*tmp = (uint16_t)(uhdata & uhMask);
8008136: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4
800813a: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2
800813e: 4013 ands r3, r2
8008140: b29a uxth r2, r3
8008142: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8008146: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8008148: 687b ldr r3, [r7, #4]
800814a: 6d9b ldr r3, [r3, #88] @ 0x58
800814c: 1c9a adds r2, r3, #2
800814e: 687b ldr r3, [r7, #4]
8008150: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8008152: 687b ldr r3, [r7, #4]
8008154: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8008158: b29b uxth r3, r3
800815a: 3b01 subs r3, #1
800815c: b29a uxth r2, r3
800815e: 687b ldr r3, [r7, #4]
8008160: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
isrflags = READ_REG(huart->Instance->ISR);
8008164: 687b ldr r3, [r7, #4]
8008166: 681b ldr r3, [r3, #0]
8008168: 69db ldr r3, [r3, #28]
800816a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
800816e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8008172: f003 0307 and.w r3, r3, #7
8008176: 2b00 cmp r3, #0
8008178: d053 beq.n 8008222 <UART_RxISR_16BIT_FIFOEN+0x146>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
800817a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
800817e: f003 0301 and.w r3, r3, #1
8008182: 2b00 cmp r3, #0
8008184: d011 beq.n 80081aa <UART_RxISR_16BIT_FIFOEN+0xce>
8008186: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800818a: f403 7380 and.w r3, r3, #256 @ 0x100
800818e: 2b00 cmp r3, #0
8008190: d00b beq.n 80081aa <UART_RxISR_16BIT_FIFOEN+0xce>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8008192: 687b ldr r3, [r7, #4]
8008194: 681b ldr r3, [r3, #0]
8008196: 2201 movs r2, #1
8008198: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
800819a: 687b ldr r3, [r7, #4]
800819c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80081a0: f043 0201 orr.w r2, r3, #1
80081a4: 687b ldr r3, [r7, #4]
80081a6: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80081aa: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80081ae: f003 0302 and.w r3, r3, #2
80081b2: 2b00 cmp r3, #0
80081b4: d011 beq.n 80081da <UART_RxISR_16BIT_FIFOEN+0xfe>
80081b6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80081ba: f003 0301 and.w r3, r3, #1
80081be: 2b00 cmp r3, #0
80081c0: d00b beq.n 80081da <UART_RxISR_16BIT_FIFOEN+0xfe>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
80081c2: 687b ldr r3, [r7, #4]
80081c4: 681b ldr r3, [r3, #0]
80081c6: 2202 movs r2, #2
80081c8: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
80081ca: 687b ldr r3, [r7, #4]
80081cc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80081d0: f043 0204 orr.w r2, r3, #4
80081d4: 687b ldr r3, [r7, #4]
80081d6: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80081da: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80081de: f003 0304 and.w r3, r3, #4
80081e2: 2b00 cmp r3, #0
80081e4: d011 beq.n 800820a <UART_RxISR_16BIT_FIFOEN+0x12e>
80081e6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80081ea: f003 0301 and.w r3, r3, #1
80081ee: 2b00 cmp r3, #0
80081f0: d00b beq.n 800820a <UART_RxISR_16BIT_FIFOEN+0x12e>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
80081f2: 687b ldr r3, [r7, #4]
80081f4: 681b ldr r3, [r3, #0]
80081f6: 2204 movs r2, #4
80081f8: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
80081fa: 687b ldr r3, [r7, #4]
80081fc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8008200: f043 0202 orr.w r2, r3, #2
8008204: 687b ldr r3, [r7, #4]
8008206: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800820a: 687b ldr r3, [r7, #4]
800820c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8008210: 2b00 cmp r3, #0
8008212: d006 beq.n 8008222 <UART_RxISR_16BIT_FIFOEN+0x146>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8008214: 6878 ldr r0, [r7, #4]
8008216: f7fe fd95 bl 8006d44 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800821a: 687b ldr r3, [r7, #4]
800821c: 2200 movs r2, #0
800821e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
if (huart->RxXferCount == 0U)
8008222: 687b ldr r3, [r7, #4]
8008224: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8008228: b29b uxth r3, r3
800822a: 2b00 cmp r3, #0
800822c: f040 80a5 bne.w 800837a <UART_RxISR_16BIT_FIFOEN+0x29e>
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8008230: 687b ldr r3, [r7, #4]
8008232: 681b ldr r3, [r3, #0]
8008234: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8008236: 6f7b ldr r3, [r7, #116] @ 0x74
8008238: e853 3f00 ldrex r3, [r3]
800823c: 673b str r3, [r7, #112] @ 0x70
return(result);
800823e: 6f3b ldr r3, [r7, #112] @ 0x70
8008240: f423 7380 bic.w r3, r3, #256 @ 0x100
8008244: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8008248: 687b ldr r3, [r7, #4]
800824a: 681b ldr r3, [r3, #0]
800824c: 461a mov r2, r3
800824e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8008252: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8008256: 67fa str r2, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8008258: 6ff9 ldr r1, [r7, #124] @ 0x7c
800825a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
800825e: e841 2300 strex r3, r2, [r1]
8008262: 67bb str r3, [r7, #120] @ 0x78
return(result);
8008264: 6fbb ldr r3, [r7, #120] @ 0x78
8008266: 2b00 cmp r3, #0
8008268: d1e2 bne.n 8008230 <UART_RxISR_16BIT_FIFOEN+0x154>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
800826a: 687b ldr r3, [r7, #4]
800826c: 681b ldr r3, [r3, #0]
800826e: 3308 adds r3, #8
8008270: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8008272: 6e3b ldr r3, [r7, #96] @ 0x60
8008274: e853 3f00 ldrex r3, [r3]
8008278: 65fb str r3, [r7, #92] @ 0x5c
return(result);
800827a: 6dfb ldr r3, [r7, #92] @ 0x5c
800827c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8008280: f023 0301 bic.w r3, r3, #1
8008284: f8c7 3098 str.w r3, [r7, #152] @ 0x98
8008288: 687b ldr r3, [r7, #4]
800828a: 681b ldr r3, [r3, #0]
800828c: 3308 adds r3, #8
800828e: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98
8008292: 66fa str r2, [r7, #108] @ 0x6c
8008294: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8008296: 6eb9 ldr r1, [r7, #104] @ 0x68
8008298: 6efa ldr r2, [r7, #108] @ 0x6c
800829a: e841 2300 strex r3, r2, [r1]
800829e: 667b str r3, [r7, #100] @ 0x64
return(result);
80082a0: 6e7b ldr r3, [r7, #100] @ 0x64
80082a2: 2b00 cmp r3, #0
80082a4: d1e1 bne.n 800826a <UART_RxISR_16BIT_FIFOEN+0x18e>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80082a6: 687b ldr r3, [r7, #4]
80082a8: 2220 movs r2, #32
80082aa: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
80082ae: 687b ldr r3, [r7, #4]
80082b0: 2200 movs r2, #0
80082b2: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
80082b4: 687b ldr r3, [r7, #4]
80082b6: 2200 movs r2, #0
80082b8: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
80082ba: 687b ldr r3, [r7, #4]
80082bc: 681b ldr r3, [r3, #0]
80082be: 4a60 ldr r2, [pc, #384] @ (8008440 <UART_RxISR_16BIT_FIFOEN+0x364>)
80082c0: 4293 cmp r3, r2
80082c2: d021 beq.n 8008308 <UART_RxISR_16BIT_FIFOEN+0x22c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
80082c4: 687b ldr r3, [r7, #4]
80082c6: 681b ldr r3, [r3, #0]
80082c8: 685b ldr r3, [r3, #4]
80082ca: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80082ce: 2b00 cmp r3, #0
80082d0: d01a beq.n 8008308 <UART_RxISR_16BIT_FIFOEN+0x22c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
80082d2: 687b ldr r3, [r7, #4]
80082d4: 681b ldr r3, [r3, #0]
80082d6: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80082d8: 6cfb ldr r3, [r7, #76] @ 0x4c
80082da: e853 3f00 ldrex r3, [r3]
80082de: 64bb str r3, [r7, #72] @ 0x48
return(result);
80082e0: 6cbb ldr r3, [r7, #72] @ 0x48
80082e2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
80082e6: f8c7 3094 str.w r3, [r7, #148] @ 0x94
80082ea: 687b ldr r3, [r7, #4]
80082ec: 681b ldr r3, [r3, #0]
80082ee: 461a mov r2, r3
80082f0: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
80082f4: 65bb str r3, [r7, #88] @ 0x58
80082f6: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80082f8: 6d79 ldr r1, [r7, #84] @ 0x54
80082fa: 6dba ldr r2, [r7, #88] @ 0x58
80082fc: e841 2300 strex r3, r2, [r1]
8008300: 653b str r3, [r7, #80] @ 0x50
return(result);
8008302: 6d3b ldr r3, [r7, #80] @ 0x50
8008304: 2b00 cmp r3, #0
8008306: d1e4 bne.n 80082d2 <UART_RxISR_16BIT_FIFOEN+0x1f6>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8008308: 687b ldr r3, [r7, #4]
800830a: 6edb ldr r3, [r3, #108] @ 0x6c
800830c: 2b01 cmp r3, #1
800830e: d130 bne.n 8008372 <UART_RxISR_16BIT_FIFOEN+0x296>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8008310: 687b ldr r3, [r7, #4]
8008312: 2200 movs r2, #0
8008314: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8008316: 687b ldr r3, [r7, #4]
8008318: 681b ldr r3, [r3, #0]
800831a: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800831c: 6bbb ldr r3, [r7, #56] @ 0x38
800831e: e853 3f00 ldrex r3, [r3]
8008322: 637b str r3, [r7, #52] @ 0x34
return(result);
8008324: 6b7b ldr r3, [r7, #52] @ 0x34
8008326: f023 0310 bic.w r3, r3, #16
800832a: f8c7 3090 str.w r3, [r7, #144] @ 0x90
800832e: 687b ldr r3, [r7, #4]
8008330: 681b ldr r3, [r3, #0]
8008332: 461a mov r2, r3
8008334: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8008338: 647b str r3, [r7, #68] @ 0x44
800833a: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800833c: 6c39 ldr r1, [r7, #64] @ 0x40
800833e: 6c7a ldr r2, [r7, #68] @ 0x44
8008340: e841 2300 strex r3, r2, [r1]
8008344: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8008346: 6bfb ldr r3, [r7, #60] @ 0x3c
8008348: 2b00 cmp r3, #0
800834a: d1e4 bne.n 8008316 <UART_RxISR_16BIT_FIFOEN+0x23a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
800834c: 687b ldr r3, [r7, #4]
800834e: 681b ldr r3, [r3, #0]
8008350: 69db ldr r3, [r3, #28]
8008352: f003 0310 and.w r3, r3, #16
8008356: 2b10 cmp r3, #16
8008358: d103 bne.n 8008362 <UART_RxISR_16BIT_FIFOEN+0x286>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800835a: 687b ldr r3, [r7, #4]
800835c: 681b ldr r3, [r3, #0]
800835e: 2210 movs r2, #16
8008360: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8008362: 687b ldr r3, [r7, #4]
8008364: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8008368: 4619 mov r1, r3
800836a: 6878 ldr r0, [r7, #4]
800836c: f7fe fcf4 bl 8006d58 <HAL_UARTEx_RxEventCallback>
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
break;
8008370: e00e b.n 8008390 <UART_RxISR_16BIT_FIFOEN+0x2b4>
HAL_UART_RxCpltCallback(huart);
8008372: 6878 ldr r0, [r7, #4]
8008374: f7f9 f9f4 bl 8001760 <HAL_UART_RxCpltCallback>
break;
8008378: e00a b.n 8008390 <UART_RxISR_16BIT_FIFOEN+0x2b4>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
800837a: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6
800837e: 2b00 cmp r3, #0
8008380: d006 beq.n 8008390 <UART_RxISR_16BIT_FIFOEN+0x2b4>
8008382: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8008386: f003 0320 and.w r3, r3, #32
800838a: 2b00 cmp r3, #0
800838c: f47f aeca bne.w 8008124 <UART_RxISR_16BIT_FIFOEN+0x48>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8008390: 687b ldr r3, [r7, #4]
8008392: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8008396: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
800839a: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
800839e: 2b00 cmp r3, #0
80083a0: d049 beq.n 8008436 <UART_RxISR_16BIT_FIFOEN+0x35a>
80083a2: 687b ldr r3, [r7, #4]
80083a4: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
80083a8: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e
80083ac: 429a cmp r2, r3
80083ae: d242 bcs.n 8008436 <UART_RxISR_16BIT_FIFOEN+0x35a>
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
80083b0: 687b ldr r3, [r7, #4]
80083b2: 681b ldr r3, [r3, #0]
80083b4: 3308 adds r3, #8
80083b6: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80083b8: 6a7b ldr r3, [r7, #36] @ 0x24
80083ba: e853 3f00 ldrex r3, [r3]
80083be: 623b str r3, [r7, #32]
return(result);
80083c0: 6a3b ldr r3, [r7, #32]
80083c2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80083c6: f8c7 3088 str.w r3, [r7, #136] @ 0x88
80083ca: 687b ldr r3, [r7, #4]
80083cc: 681b ldr r3, [r3, #0]
80083ce: 3308 adds r3, #8
80083d0: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88
80083d4: 633a str r2, [r7, #48] @ 0x30
80083d6: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80083d8: 6af9 ldr r1, [r7, #44] @ 0x2c
80083da: 6b3a ldr r2, [r7, #48] @ 0x30
80083dc: e841 2300 strex r3, r2, [r1]
80083e0: 62bb str r3, [r7, #40] @ 0x28
return(result);
80083e2: 6abb ldr r3, [r7, #40] @ 0x28
80083e4: 2b00 cmp r3, #0
80083e6: d1e3 bne.n 80083b0 <UART_RxISR_16BIT_FIFOEN+0x2d4>
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_16BIT;
80083e8: 687b ldr r3, [r7, #4]
80083ea: 4a16 ldr r2, [pc, #88] @ (8008444 <UART_RxISR_16BIT_FIFOEN+0x368>)
80083ec: 675a str r2, [r3, #116] @ 0x74
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
80083ee: 687b ldr r3, [r7, #4]
80083f0: 681b ldr r3, [r3, #0]
80083f2: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80083f4: 693b ldr r3, [r7, #16]
80083f6: e853 3f00 ldrex r3, [r3]
80083fa: 60fb str r3, [r7, #12]
return(result);
80083fc: 68fb ldr r3, [r7, #12]
80083fe: f043 0320 orr.w r3, r3, #32
8008402: f8c7 3084 str.w r3, [r7, #132] @ 0x84
8008406: 687b ldr r3, [r7, #4]
8008408: 681b ldr r3, [r3, #0]
800840a: 461a mov r2, r3
800840c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8008410: 61fb str r3, [r7, #28]
8008412: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8008414: 69b9 ldr r1, [r7, #24]
8008416: 69fa ldr r2, [r7, #28]
8008418: e841 2300 strex r3, r2, [r1]
800841c: 617b str r3, [r7, #20]
return(result);
800841e: 697b ldr r3, [r7, #20]
8008420: 2b00 cmp r3, #0
8008422: d1e4 bne.n 80083ee <UART_RxISR_16BIT_FIFOEN+0x312>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8008424: e007 b.n 8008436 <UART_RxISR_16BIT_FIFOEN+0x35a>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8008426: 687b ldr r3, [r7, #4]
8008428: 681b ldr r3, [r3, #0]
800842a: 699a ldr r2, [r3, #24]
800842c: 687b ldr r3, [r7, #4]
800842e: 681b ldr r3, [r3, #0]
8008430: f042 0208 orr.w r2, r2, #8
8008434: 619a str r2, [r3, #24]
}
8008436: bf00 nop
8008438: 37b8 adds r7, #184 @ 0xb8
800843a: 46bd mov sp, r7
800843c: bd80 pop {r7, pc}
800843e: bf00 nop
8008440: 40008000 .word 0x40008000
8008444: 08007bc1 .word 0x08007bc1
08008448 <HAL_UARTEx_WakeupCallback>:
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
8008448: b480 push {r7}
800844a: b083 sub sp, #12
800844c: af00 add r7, sp, #0
800844e: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8008450: bf00 nop
8008452: 370c adds r7, #12
8008454: 46bd mov sp, r7
8008456: f85d 7b04 ldr.w r7, [sp], #4
800845a: 4770 bx lr
0800845c <HAL_UARTEx_RxFifoFullCallback>:
* @brief UART RX Fifo full callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
800845c: b480 push {r7}
800845e: b083 sub sp, #12
8008460: af00 add r7, sp, #0
8008462: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
*/
}
8008464: bf00 nop
8008466: 370c adds r7, #12
8008468: 46bd mov sp, r7
800846a: f85d 7b04 ldr.w r7, [sp], #4
800846e: 4770 bx lr
08008470 <HAL_UARTEx_TxFifoEmptyCallback>:
* @brief UART TX Fifo empty callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
8008470: b480 push {r7}
8008472: b083 sub sp, #12
8008474: af00 add r7, sp, #0
8008476: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
8008478: bf00 nop
800847a: 370c adds r7, #12
800847c: 46bd mov sp, r7
800847e: f85d 7b04 ldr.w r7, [sp], #4
8008482: 4770 bx lr
08008484 <HAL_UARTEx_DisableFifoMode>:
* @brief Disable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
8008484: b480 push {r7}
8008486: b085 sub sp, #20
8008488: af00 add r7, sp, #0
800848a: 6078 str r0, [r7, #4]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
800848c: 687b ldr r3, [r7, #4]
800848e: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
8008492: 2b01 cmp r3, #1
8008494: d101 bne.n 800849a <HAL_UARTEx_DisableFifoMode+0x16>
8008496: 2302 movs r3, #2
8008498: e027 b.n 80084ea <HAL_UARTEx_DisableFifoMode+0x66>
800849a: 687b ldr r3, [r7, #4]
800849c: 2201 movs r2, #1
800849e: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
80084a2: 687b ldr r3, [r7, #4]
80084a4: 2224 movs r2, #36 @ 0x24
80084a6: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
80084aa: 687b ldr r3, [r7, #4]
80084ac: 681b ldr r3, [r3, #0]
80084ae: 681b ldr r3, [r3, #0]
80084b0: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
80084b2: 687b ldr r3, [r7, #4]
80084b4: 681b ldr r3, [r3, #0]
80084b6: 681a ldr r2, [r3, #0]
80084b8: 687b ldr r3, [r7, #4]
80084ba: 681b ldr r3, [r3, #0]
80084bc: f022 0201 bic.w r2, r2, #1
80084c0: 601a str r2, [r3, #0]
/* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
80084c2: 68fb ldr r3, [r7, #12]
80084c4: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
80084c8: 60fb str r3, [r7, #12]
huart->FifoMode = UART_FIFOMODE_DISABLE;
80084ca: 687b ldr r3, [r7, #4]
80084cc: 2200 movs r2, #0
80084ce: 665a str r2, [r3, #100] @ 0x64
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
80084d0: 687b ldr r3, [r7, #4]
80084d2: 681b ldr r3, [r3, #0]
80084d4: 68fa ldr r2, [r7, #12]
80084d6: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
80084d8: 687b ldr r3, [r7, #4]
80084da: 2220 movs r2, #32
80084dc: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
80084e0: 687b ldr r3, [r7, #4]
80084e2: 2200 movs r2, #0
80084e4: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
80084e8: 2300 movs r3, #0
}
80084ea: 4618 mov r0, r3
80084ec: 3714 adds r7, #20
80084ee: 46bd mov sp, r7
80084f0: f85d 7b04 ldr.w r7, [sp], #4
80084f4: 4770 bx lr
080084f6 <HAL_UARTEx_SetTxFifoThreshold>:
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
80084f6: b580 push {r7, lr}
80084f8: b084 sub sp, #16
80084fa: af00 add r7, sp, #0
80084fc: 6078 str r0, [r7, #4]
80084fe: 6039 str r1, [r7, #0]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8008500: 687b ldr r3, [r7, #4]
8008502: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
8008506: 2b01 cmp r3, #1
8008508: d101 bne.n 800850e <HAL_UARTEx_SetTxFifoThreshold+0x18>
800850a: 2302 movs r3, #2
800850c: e02d b.n 800856a <HAL_UARTEx_SetTxFifoThreshold+0x74>
800850e: 687b ldr r3, [r7, #4]
8008510: 2201 movs r2, #1
8008512: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
8008516: 687b ldr r3, [r7, #4]
8008518: 2224 movs r2, #36 @ 0x24
800851a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
800851e: 687b ldr r3, [r7, #4]
8008520: 681b ldr r3, [r3, #0]
8008522: 681b ldr r3, [r3, #0]
8008524: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8008526: 687b ldr r3, [r7, #4]
8008528: 681b ldr r3, [r3, #0]
800852a: 681a ldr r2, [r3, #0]
800852c: 687b ldr r3, [r7, #4]
800852e: 681b ldr r3, [r3, #0]
8008530: f022 0201 bic.w r2, r2, #1
8008534: 601a str r2, [r3, #0]
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
8008536: 687b ldr r3, [r7, #4]
8008538: 681b ldr r3, [r3, #0]
800853a: 689b ldr r3, [r3, #8]
800853c: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000
8008540: 687b ldr r3, [r7, #4]
8008542: 681b ldr r3, [r3, #0]
8008544: 683a ldr r2, [r7, #0]
8008546: 430a orrs r2, r1
8008548: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
800854a: 6878 ldr r0, [r7, #4]
800854c: f000 f850 bl 80085f0 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8008550: 687b ldr r3, [r7, #4]
8008552: 681b ldr r3, [r3, #0]
8008554: 68fa ldr r2, [r7, #12]
8008556: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8008558: 687b ldr r3, [r7, #4]
800855a: 2220 movs r2, #32
800855c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
8008560: 687b ldr r3, [r7, #4]
8008562: 2200 movs r2, #0
8008564: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8008568: 2300 movs r3, #0
}
800856a: 4618 mov r0, r3
800856c: 3710 adds r7, #16
800856e: 46bd mov sp, r7
8008570: bd80 pop {r7, pc}
08008572 <HAL_UARTEx_SetRxFifoThreshold>:
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
8008572: b580 push {r7, lr}
8008574: b084 sub sp, #16
8008576: af00 add r7, sp, #0
8008578: 6078 str r0, [r7, #4]
800857a: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
800857c: 687b ldr r3, [r7, #4]
800857e: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
8008582: 2b01 cmp r3, #1
8008584: d101 bne.n 800858a <HAL_UARTEx_SetRxFifoThreshold+0x18>
8008586: 2302 movs r3, #2
8008588: e02d b.n 80085e6 <HAL_UARTEx_SetRxFifoThreshold+0x74>
800858a: 687b ldr r3, [r7, #4]
800858c: 2201 movs r2, #1
800858e: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
8008592: 687b ldr r3, [r7, #4]
8008594: 2224 movs r2, #36 @ 0x24
8008596: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
800859a: 687b ldr r3, [r7, #4]
800859c: 681b ldr r3, [r3, #0]
800859e: 681b ldr r3, [r3, #0]
80085a0: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
80085a2: 687b ldr r3, [r7, #4]
80085a4: 681b ldr r3, [r3, #0]
80085a6: 681a ldr r2, [r3, #0]
80085a8: 687b ldr r3, [r7, #4]
80085aa: 681b ldr r3, [r3, #0]
80085ac: f022 0201 bic.w r2, r2, #1
80085b0: 601a str r2, [r3, #0]
/* Update RX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
80085b2: 687b ldr r3, [r7, #4]
80085b4: 681b ldr r3, [r3, #0]
80085b6: 689b ldr r3, [r3, #8]
80085b8: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000
80085bc: 687b ldr r3, [r7, #4]
80085be: 681b ldr r3, [r3, #0]
80085c0: 683a ldr r2, [r7, #0]
80085c2: 430a orrs r2, r1
80085c4: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
80085c6: 6878 ldr r0, [r7, #4]
80085c8: f000 f812 bl 80085f0 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
80085cc: 687b ldr r3, [r7, #4]
80085ce: 681b ldr r3, [r3, #0]
80085d0: 68fa ldr r2, [r7, #12]
80085d2: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
80085d4: 687b ldr r3, [r7, #4]
80085d6: 2220 movs r2, #32
80085d8: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
80085dc: 687b ldr r3, [r7, #4]
80085de: 2200 movs r2, #0
80085e0: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
80085e4: 2300 movs r3, #0
}
80085e6: 4618 mov r0, r3
80085e8: 3710 adds r7, #16
80085ea: 46bd mov sp, r7
80085ec: bd80 pop {r7, pc}
...
080085f0 <UARTEx_SetNbDataToProcess>:
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
80085f0: b480 push {r7}
80085f2: b085 sub sp, #20
80085f4: af00 add r7, sp, #0
80085f6: 6078 str r0, [r7, #4]
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
80085f8: 687b ldr r3, [r7, #4]
80085fa: 6e5b ldr r3, [r3, #100] @ 0x64
80085fc: 2b00 cmp r3, #0
80085fe: d108 bne.n 8008612 <UARTEx_SetNbDataToProcess+0x22>
{
huart->NbTxDataToProcess = 1U;
8008600: 687b ldr r3, [r7, #4]
8008602: 2201 movs r2, #1
8008604: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1U;
8008608: 687b ldr r3, [r7, #4]
800860a: 2201 movs r2, #1
800860c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
8008610: e031 b.n 8008676 <UARTEx_SetNbDataToProcess+0x86>
rx_fifo_depth = RX_FIFO_DEPTH;
8008612: 2308 movs r3, #8
8008614: 73fb strb r3, [r7, #15]
tx_fifo_depth = TX_FIFO_DEPTH;
8008616: 2308 movs r3, #8
8008618: 73bb strb r3, [r7, #14]
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
800861a: 687b ldr r3, [r7, #4]
800861c: 681b ldr r3, [r3, #0]
800861e: 689b ldr r3, [r3, #8]
8008620: 0e5b lsrs r3, r3, #25
8008622: b2db uxtb r3, r3
8008624: f003 0307 and.w r3, r3, #7
8008628: 737b strb r3, [r7, #13]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
800862a: 687b ldr r3, [r7, #4]
800862c: 681b ldr r3, [r3, #0]
800862e: 689b ldr r3, [r3, #8]
8008630: 0f5b lsrs r3, r3, #29
8008632: b2db uxtb r3, r3
8008634: f003 0307 and.w r3, r3, #7
8008638: 733b strb r3, [r7, #12]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
800863a: 7bbb ldrb r3, [r7, #14]
800863c: 7b3a ldrb r2, [r7, #12]
800863e: 4911 ldr r1, [pc, #68] @ (8008684 <UARTEx_SetNbDataToProcess+0x94>)
8008640: 5c8a ldrb r2, [r1, r2]
8008642: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[tx_fifo_threshold];
8008646: 7b3a ldrb r2, [r7, #12]
8008648: 490f ldr r1, [pc, #60] @ (8008688 <UARTEx_SetNbDataToProcess+0x98>)
800864a: 5c8a ldrb r2, [r1, r2]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
800864c: fb93 f3f2 sdiv r3, r3, r2
8008650: b29a uxth r2, r3
8008652: 687b ldr r3, [r7, #4]
8008654: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8008658: 7bfb ldrb r3, [r7, #15]
800865a: 7b7a ldrb r2, [r7, #13]
800865c: 4909 ldr r1, [pc, #36] @ (8008684 <UARTEx_SetNbDataToProcess+0x94>)
800865e: 5c8a ldrb r2, [r1, r2]
8008660: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[rx_fifo_threshold];
8008664: 7b7a ldrb r2, [r7, #13]
8008666: 4908 ldr r1, [pc, #32] @ (8008688 <UARTEx_SetNbDataToProcess+0x98>)
8008668: 5c8a ldrb r2, [r1, r2]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
800866a: fb93 f3f2 sdiv r3, r3, r2
800866e: b29a uxth r2, r3
8008670: 687b ldr r3, [r7, #4]
8008672: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
}
8008676: bf00 nop
8008678: 3714 adds r7, #20
800867a: 46bd mov sp, r7
800867c: f85d 7b04 ldr.w r7, [sp], #4
8008680: 4770 bx lr
8008682: bf00 nop
8008684: 0800872c .word 0x0800872c
8008688: 08008734 .word 0x08008734
0800868c <memset>:
800868c: 4402 add r2, r0
800868e: 4603 mov r3, r0
8008690: 4293 cmp r3, r2
8008692: d100 bne.n 8008696 <memset+0xa>
8008694: 4770 bx lr
8008696: f803 1b01 strb.w r1, [r3], #1
800869a: e7f9 b.n 8008690 <memset+0x4>
0800869c <__libc_init_array>:
800869c: b570 push {r4, r5, r6, lr}
800869e: 4d0d ldr r5, [pc, #52] @ (80086d4 <__libc_init_array+0x38>)
80086a0: 4c0d ldr r4, [pc, #52] @ (80086d8 <__libc_init_array+0x3c>)
80086a2: 1b64 subs r4, r4, r5
80086a4: 10a4 asrs r4, r4, #2
80086a6: 2600 movs r6, #0
80086a8: 42a6 cmp r6, r4
80086aa: d109 bne.n 80086c0 <__libc_init_array+0x24>
80086ac: 4d0b ldr r5, [pc, #44] @ (80086dc <__libc_init_array+0x40>)
80086ae: 4c0c ldr r4, [pc, #48] @ (80086e0 <__libc_init_array+0x44>)
80086b0: f000 f818 bl 80086e4 <_init>
80086b4: 1b64 subs r4, r4, r5
80086b6: 10a4 asrs r4, r4, #2
80086b8: 2600 movs r6, #0
80086ba: 42a6 cmp r6, r4
80086bc: d105 bne.n 80086ca <__libc_init_array+0x2e>
80086be: bd70 pop {r4, r5, r6, pc}
80086c0: f855 3b04 ldr.w r3, [r5], #4
80086c4: 4798 blx r3
80086c6: 3601 adds r6, #1
80086c8: e7ee b.n 80086a8 <__libc_init_array+0xc>
80086ca: f855 3b04 ldr.w r3, [r5], #4
80086ce: 4798 blx r3
80086d0: 3601 adds r6, #1
80086d2: e7f2 b.n 80086ba <__libc_init_array+0x1e>
80086d4: 08008744 .word 0x08008744
80086d8: 08008744 .word 0x08008744
80086dc: 08008744 .word 0x08008744
80086e0: 08008748 .word 0x08008748
080086e4 <_init>:
80086e4: b5f8 push {r3, r4, r5, r6, r7, lr}
80086e6: bf00 nop
80086e8: bcf8 pop {r3, r4, r5, r6, r7}
80086ea: bc08 pop {r3}
80086ec: 469e mov lr, r3
80086ee: 4770 bx lr
080086f0 <_fini>:
80086f0: b5f8 push {r3, r4, r5, r6, r7, lr}
80086f2: bf00 nop
80086f4: bcf8 pop {r3, r4, r5, r6, r7}
80086f6: bc08 pop {r3}
80086f8: 469e mov lr, r3
80086fa: 4770 bx lr
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