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7990f118dd0865c0a4422dcb84fe4208187130c9
Automotive-Power-Simulator/Debug/POWER_SWITCH.list
David Rice 7990f118dd updates
2026-01-20 16:51:04 +00:00

21872 lines
843 KiB
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POWER_SWITCH.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001d8 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00008468 080001d8 080001d8 000011d8 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000040 08008640 08008640 00009640 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08008680 08008680 0000a024 2**0
CONTENTS, READONLY
4 .ARM 00000008 08008680 08008680 00009680 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08008688 08008688 0000a024 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08008688 08008688 00009688 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800868c 0800868c 0000968c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000024 20000000 08008690 0000a000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000003a4 20000024 080086b4 0000a024 2**2
ALLOC
10 ._user_heap_stack 00000600 200003c8 080086b4 0000a3c8 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000a024 2**0
CONTENTS, READONLY
12 .debug_info 0001746b 00000000 00000000 0000a054 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00002a9b 00000000 00000000 000214bf 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000014c8 00000000 00000000 00023f60 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00001041 00000000 00000000 00025428 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001f9b8 00000000 00000000 00026469 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001694c 00000000 00000000 00045e21 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000d7f54 00000000 00000000 0005c76d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 001346c1 2**0
CONTENTS, READONLY
20 .debug_frame 00005b4c 00000000 00000000 00134704 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000006d 00000000 00000000 0013a250 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001d8 <__do_global_dtors_aux>:
80001d8: b510 push {r4, lr}
80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>)
80001dc: 7823 ldrb r3, [r4, #0]
80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>)
80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>)
80001e6: f3af 8000 nop.w
80001ea: 2301 movs r3, #1
80001ec: 7023 strb r3, [r4, #0]
80001ee: bd10 pop {r4, pc}
80001f0: 20000024 .word 0x20000024
80001f4: 00000000 .word 0x00000000
80001f8: 08008628 .word 0x08008628
080001fc <frame_dummy>:
80001fc: b508 push {r3, lr}
80001fe: 4b03 ldr r3, [pc, #12] @ (800020c <frame_dummy+0x10>)
8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
8000202: 4903 ldr r1, [pc, #12] @ (8000210 <frame_dummy+0x14>)
8000204: 4803 ldr r0, [pc, #12] @ (8000214 <frame_dummy+0x18>)
8000206: f3af 8000 nop.w
800020a: bd08 pop {r3, pc}
800020c: 00000000 .word 0x00000000
8000210: 20000028 .word 0x20000028
8000214: 08008628 .word 0x08008628
08000218 <__aeabi_dmul>:
8000218: b570 push {r4, r5, r6, lr}
800021a: f04f 0cff mov.w ip, #255 @ 0xff
800021e: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000222: ea1c 5411 ands.w r4, ip, r1, lsr #20
8000226: bf1d ittte ne
8000228: ea1c 5513 andsne.w r5, ip, r3, lsr #20
800022c: ea94 0f0c teqne r4, ip
8000230: ea95 0f0c teqne r5, ip
8000234: f000 f8de bleq 80003f4 <__aeabi_dmul+0x1dc>
8000238: 442c add r4, r5
800023a: ea81 0603 eor.w r6, r1, r3
800023e: ea21 514c bic.w r1, r1, ip, lsl #21
8000242: ea23 534c bic.w r3, r3, ip, lsl #21
8000246: ea50 3501 orrs.w r5, r0, r1, lsl #12
800024a: bf18 it ne
800024c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000250: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000254: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8000258: d038 beq.n 80002cc <__aeabi_dmul+0xb4>
800025a: fba0 ce02 umull ip, lr, r0, r2
800025e: f04f 0500 mov.w r5, #0
8000262: fbe1 e502 umlal lr, r5, r1, r2
8000266: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
800026a: fbe0 e503 umlal lr, r5, r0, r3
800026e: f04f 0600 mov.w r6, #0
8000272: fbe1 5603 umlal r5, r6, r1, r3
8000276: f09c 0f00 teq ip, #0
800027a: bf18 it ne
800027c: f04e 0e01 orrne.w lr, lr, #1
8000280: f1a4 04ff sub.w r4, r4, #255 @ 0xff
8000284: f5b6 7f00 cmp.w r6, #512 @ 0x200
8000288: f564 7440 sbc.w r4, r4, #768 @ 0x300
800028c: d204 bcs.n 8000298 <__aeabi_dmul+0x80>
800028e: ea5f 0e4e movs.w lr, lr, lsl #1
8000292: 416d adcs r5, r5
8000294: eb46 0606 adc.w r6, r6, r6
8000298: ea42 21c6 orr.w r1, r2, r6, lsl #11
800029c: ea41 5155 orr.w r1, r1, r5, lsr #21
80002a0: ea4f 20c5 mov.w r0, r5, lsl #11
80002a4: ea40 505e orr.w r0, r0, lr, lsr #21
80002a8: ea4f 2ece mov.w lr, lr, lsl #11
80002ac: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
80002b0: bf88 it hi
80002b2: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
80002b6: d81e bhi.n 80002f6 <__aeabi_dmul+0xde>
80002b8: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
80002bc: bf08 it eq
80002be: ea5f 0e50 movseq.w lr, r0, lsr #1
80002c2: f150 0000 adcs.w r0, r0, #0
80002c6: eb41 5104 adc.w r1, r1, r4, lsl #20
80002ca: bd70 pop {r4, r5, r6, pc}
80002cc: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
80002d0: ea46 0101 orr.w r1, r6, r1
80002d4: ea40 0002 orr.w r0, r0, r2
80002d8: ea81 0103 eor.w r1, r1, r3
80002dc: ebb4 045c subs.w r4, r4, ip, lsr #1
80002e0: bfc2 ittt gt
80002e2: ebd4 050c rsbsgt r5, r4, ip
80002e6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80002ea: bd70 popgt {r4, r5, r6, pc}
80002ec: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80002f0: f04f 0e00 mov.w lr, #0
80002f4: 3c01 subs r4, #1
80002f6: f300 80ab bgt.w 8000450 <__aeabi_dmul+0x238>
80002fa: f114 0f36 cmn.w r4, #54 @ 0x36
80002fe: bfde ittt le
8000300: 2000 movle r0, #0
8000302: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
8000306: bd70 pople {r4, r5, r6, pc}
8000308: f1c4 0400 rsb r4, r4, #0
800030c: 3c20 subs r4, #32
800030e: da35 bge.n 800037c <__aeabi_dmul+0x164>
8000310: 340c adds r4, #12
8000312: dc1b bgt.n 800034c <__aeabi_dmul+0x134>
8000314: f104 0414 add.w r4, r4, #20
8000318: f1c4 0520 rsb r5, r4, #32
800031c: fa00 f305 lsl.w r3, r0, r5
8000320: fa20 f004 lsr.w r0, r0, r4
8000324: fa01 f205 lsl.w r2, r1, r5
8000328: ea40 0002 orr.w r0, r0, r2
800032c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000330: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000334: eb10 70d3 adds.w r0, r0, r3, lsr #31
8000338: fa21 f604 lsr.w r6, r1, r4
800033c: eb42 0106 adc.w r1, r2, r6
8000340: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000344: bf08 it eq
8000346: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800034a: bd70 pop {r4, r5, r6, pc}
800034c: f1c4 040c rsb r4, r4, #12
8000350: f1c4 0520 rsb r5, r4, #32
8000354: fa00 f304 lsl.w r3, r0, r4
8000358: fa20 f005 lsr.w r0, r0, r5
800035c: fa01 f204 lsl.w r2, r1, r4
8000360: ea40 0002 orr.w r0, r0, r2
8000364: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000368: eb10 70d3 adds.w r0, r0, r3, lsr #31
800036c: f141 0100 adc.w r1, r1, #0
8000370: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000374: bf08 it eq
8000376: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800037a: bd70 pop {r4, r5, r6, pc}
800037c: f1c4 0520 rsb r5, r4, #32
8000380: fa00 f205 lsl.w r2, r0, r5
8000384: ea4e 0e02 orr.w lr, lr, r2
8000388: fa20 f304 lsr.w r3, r0, r4
800038c: fa01 f205 lsl.w r2, r1, r5
8000390: ea43 0302 orr.w r3, r3, r2
8000394: fa21 f004 lsr.w r0, r1, r4
8000398: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800039c: fa21 f204 lsr.w r2, r1, r4
80003a0: ea20 0002 bic.w r0, r0, r2
80003a4: eb00 70d3 add.w r0, r0, r3, lsr #31
80003a8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80003ac: bf08 it eq
80003ae: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80003b2: bd70 pop {r4, r5, r6, pc}
80003b4: f094 0f00 teq r4, #0
80003b8: d10f bne.n 80003da <__aeabi_dmul+0x1c2>
80003ba: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
80003be: 0040 lsls r0, r0, #1
80003c0: eb41 0101 adc.w r1, r1, r1
80003c4: f411 1f80 tst.w r1, #1048576 @ 0x100000
80003c8: bf08 it eq
80003ca: 3c01 subeq r4, #1
80003cc: d0f7 beq.n 80003be <__aeabi_dmul+0x1a6>
80003ce: ea41 0106 orr.w r1, r1, r6
80003d2: f095 0f00 teq r5, #0
80003d6: bf18 it ne
80003d8: 4770 bxne lr
80003da: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
80003de: 0052 lsls r2, r2, #1
80003e0: eb43 0303 adc.w r3, r3, r3
80003e4: f413 1f80 tst.w r3, #1048576 @ 0x100000
80003e8: bf08 it eq
80003ea: 3d01 subeq r5, #1
80003ec: d0f7 beq.n 80003de <__aeabi_dmul+0x1c6>
80003ee: ea43 0306 orr.w r3, r3, r6
80003f2: 4770 bx lr
80003f4: ea94 0f0c teq r4, ip
80003f8: ea0c 5513 and.w r5, ip, r3, lsr #20
80003fc: bf18 it ne
80003fe: ea95 0f0c teqne r5, ip
8000402: d00c beq.n 800041e <__aeabi_dmul+0x206>
8000404: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000408: bf18 it ne
800040a: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800040e: d1d1 bne.n 80003b4 <__aeabi_dmul+0x19c>
8000410: ea81 0103 eor.w r1, r1, r3
8000414: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000418: f04f 0000 mov.w r0, #0
800041c: bd70 pop {r4, r5, r6, pc}
800041e: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000422: bf06 itte eq
8000424: 4610 moveq r0, r2
8000426: 4619 moveq r1, r3
8000428: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800042c: d019 beq.n 8000462 <__aeabi_dmul+0x24a>
800042e: ea94 0f0c teq r4, ip
8000432: d102 bne.n 800043a <__aeabi_dmul+0x222>
8000434: ea50 3601 orrs.w r6, r0, r1, lsl #12
8000438: d113 bne.n 8000462 <__aeabi_dmul+0x24a>
800043a: ea95 0f0c teq r5, ip
800043e: d105 bne.n 800044c <__aeabi_dmul+0x234>
8000440: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000444: bf1c itt ne
8000446: 4610 movne r0, r2
8000448: 4619 movne r1, r3
800044a: d10a bne.n 8000462 <__aeabi_dmul+0x24a>
800044c: ea81 0103 eor.w r1, r1, r3
8000450: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000454: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000458: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
800045c: f04f 0000 mov.w r0, #0
8000460: bd70 pop {r4, r5, r6, pc}
8000462: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000466: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
800046a: bd70 pop {r4, r5, r6, pc}
0800046c <__aeabi_drsub>:
800046c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
8000470: e002 b.n 8000478 <__adddf3>
8000472: bf00 nop
08000474 <__aeabi_dsub>:
8000474: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
08000478 <__adddf3>:
8000478: b530 push {r4, r5, lr}
800047a: ea4f 0441 mov.w r4, r1, lsl #1
800047e: ea4f 0543 mov.w r5, r3, lsl #1
8000482: ea94 0f05 teq r4, r5
8000486: bf08 it eq
8000488: ea90 0f02 teqeq r0, r2
800048c: bf1f itttt ne
800048e: ea54 0c00 orrsne.w ip, r4, r0
8000492: ea55 0c02 orrsne.w ip, r5, r2
8000496: ea7f 5c64 mvnsne.w ip, r4, asr #21
800049a: ea7f 5c65 mvnsne.w ip, r5, asr #21
800049e: f000 80e2 beq.w 8000666 <__adddf3+0x1ee>
80004a2: ea4f 5454 mov.w r4, r4, lsr #21
80004a6: ebd4 5555 rsbs r5, r4, r5, lsr #21
80004aa: bfb8 it lt
80004ac: 426d neglt r5, r5
80004ae: dd0c ble.n 80004ca <__adddf3+0x52>
80004b0: 442c add r4, r5
80004b2: ea80 0202 eor.w r2, r0, r2
80004b6: ea81 0303 eor.w r3, r1, r3
80004ba: ea82 0000 eor.w r0, r2, r0
80004be: ea83 0101 eor.w r1, r3, r1
80004c2: ea80 0202 eor.w r2, r0, r2
80004c6: ea81 0303 eor.w r3, r1, r3
80004ca: 2d36 cmp r5, #54 @ 0x36
80004cc: bf88 it hi
80004ce: bd30 pophi {r4, r5, pc}
80004d0: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80004d4: ea4f 3101 mov.w r1, r1, lsl #12
80004d8: f44f 1c80 mov.w ip, #1048576 @ 0x100000
80004dc: ea4c 3111 orr.w r1, ip, r1, lsr #12
80004e0: d002 beq.n 80004e8 <__adddf3+0x70>
80004e2: 4240 negs r0, r0
80004e4: eb61 0141 sbc.w r1, r1, r1, lsl #1
80004e8: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
80004ec: ea4f 3303 mov.w r3, r3, lsl #12
80004f0: ea4c 3313 orr.w r3, ip, r3, lsr #12
80004f4: d002 beq.n 80004fc <__adddf3+0x84>
80004f6: 4252 negs r2, r2
80004f8: eb63 0343 sbc.w r3, r3, r3, lsl #1
80004fc: ea94 0f05 teq r4, r5
8000500: f000 80a7 beq.w 8000652 <__adddf3+0x1da>
8000504: f1a4 0401 sub.w r4, r4, #1
8000508: f1d5 0e20 rsbs lr, r5, #32
800050c: db0d blt.n 800052a <__adddf3+0xb2>
800050e: fa02 fc0e lsl.w ip, r2, lr
8000512: fa22 f205 lsr.w r2, r2, r5
8000516: 1880 adds r0, r0, r2
8000518: f141 0100 adc.w r1, r1, #0
800051c: fa03 f20e lsl.w r2, r3, lr
8000520: 1880 adds r0, r0, r2
8000522: fa43 f305 asr.w r3, r3, r5
8000526: 4159 adcs r1, r3
8000528: e00e b.n 8000548 <__adddf3+0xd0>
800052a: f1a5 0520 sub.w r5, r5, #32
800052e: f10e 0e20 add.w lr, lr, #32
8000532: 2a01 cmp r2, #1
8000534: fa03 fc0e lsl.w ip, r3, lr
8000538: bf28 it cs
800053a: f04c 0c02 orrcs.w ip, ip, #2
800053e: fa43 f305 asr.w r3, r3, r5
8000542: 18c0 adds r0, r0, r3
8000544: eb51 71e3 adcs.w r1, r1, r3, asr #31
8000548: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
800054c: d507 bpl.n 800055e <__adddf3+0xe6>
800054e: f04f 0e00 mov.w lr, #0
8000552: f1dc 0c00 rsbs ip, ip, #0
8000556: eb7e 0000 sbcs.w r0, lr, r0
800055a: eb6e 0101 sbc.w r1, lr, r1
800055e: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
8000562: d31b bcc.n 800059c <__adddf3+0x124>
8000564: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
8000568: d30c bcc.n 8000584 <__adddf3+0x10c>
800056a: 0849 lsrs r1, r1, #1
800056c: ea5f 0030 movs.w r0, r0, rrx
8000570: ea4f 0c3c mov.w ip, ip, rrx
8000574: f104 0401 add.w r4, r4, #1
8000578: ea4f 5244 mov.w r2, r4, lsl #21
800057c: f512 0f80 cmn.w r2, #4194304 @ 0x400000
8000580: f080 809a bcs.w 80006b8 <__adddf3+0x240>
8000584: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
8000588: bf08 it eq
800058a: ea5f 0c50 movseq.w ip, r0, lsr #1
800058e: f150 0000 adcs.w r0, r0, #0
8000592: eb41 5104 adc.w r1, r1, r4, lsl #20
8000596: ea41 0105 orr.w r1, r1, r5
800059a: bd30 pop {r4, r5, pc}
800059c: ea5f 0c4c movs.w ip, ip, lsl #1
80005a0: 4140 adcs r0, r0
80005a2: eb41 0101 adc.w r1, r1, r1
80005a6: 3c01 subs r4, #1
80005a8: bf28 it cs
80005aa: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80005ae: d2e9 bcs.n 8000584 <__adddf3+0x10c>
80005b0: f091 0f00 teq r1, #0
80005b4: bf04 itt eq
80005b6: 4601 moveq r1, r0
80005b8: 2000 moveq r0, #0
80005ba: fab1 f381 clz r3, r1
80005be: bf08 it eq
80005c0: 3320 addeq r3, #32
80005c2: f1a3 030b sub.w r3, r3, #11
80005c6: f1b3 0220 subs.w r2, r3, #32
80005ca: da0c bge.n 80005e6 <__adddf3+0x16e>
80005cc: 320c adds r2, #12
80005ce: dd08 ble.n 80005e2 <__adddf3+0x16a>
80005d0: f102 0c14 add.w ip, r2, #20
80005d4: f1c2 020c rsb r2, r2, #12
80005d8: fa01 f00c lsl.w r0, r1, ip
80005dc: fa21 f102 lsr.w r1, r1, r2
80005e0: e00c b.n 80005fc <__adddf3+0x184>
80005e2: f102 0214 add.w r2, r2, #20
80005e6: bfd8 it le
80005e8: f1c2 0c20 rsble ip, r2, #32
80005ec: fa01 f102 lsl.w r1, r1, r2
80005f0: fa20 fc0c lsr.w ip, r0, ip
80005f4: bfdc itt le
80005f6: ea41 010c orrle.w r1, r1, ip
80005fa: 4090 lslle r0, r2
80005fc: 1ae4 subs r4, r4, r3
80005fe: bfa2 ittt ge
8000600: eb01 5104 addge.w r1, r1, r4, lsl #20
8000604: 4329 orrge r1, r5
8000606: bd30 popge {r4, r5, pc}
8000608: ea6f 0404 mvn.w r4, r4
800060c: 3c1f subs r4, #31
800060e: da1c bge.n 800064a <__adddf3+0x1d2>
8000610: 340c adds r4, #12
8000612: dc0e bgt.n 8000632 <__adddf3+0x1ba>
8000614: f104 0414 add.w r4, r4, #20
8000618: f1c4 0220 rsb r2, r4, #32
800061c: fa20 f004 lsr.w r0, r0, r4
8000620: fa01 f302 lsl.w r3, r1, r2
8000624: ea40 0003 orr.w r0, r0, r3
8000628: fa21 f304 lsr.w r3, r1, r4
800062c: ea45 0103 orr.w r1, r5, r3
8000630: bd30 pop {r4, r5, pc}
8000632: f1c4 040c rsb r4, r4, #12
8000636: f1c4 0220 rsb r2, r4, #32
800063a: fa20 f002 lsr.w r0, r0, r2
800063e: fa01 f304 lsl.w r3, r1, r4
8000642: ea40 0003 orr.w r0, r0, r3
8000646: 4629 mov r1, r5
8000648: bd30 pop {r4, r5, pc}
800064a: fa21 f004 lsr.w r0, r1, r4
800064e: 4629 mov r1, r5
8000650: bd30 pop {r4, r5, pc}
8000652: f094 0f00 teq r4, #0
8000656: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800065a: bf06 itte eq
800065c: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
8000660: 3401 addeq r4, #1
8000662: 3d01 subne r5, #1
8000664: e74e b.n 8000504 <__adddf3+0x8c>
8000666: ea7f 5c64 mvns.w ip, r4, asr #21
800066a: bf18 it ne
800066c: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000670: d029 beq.n 80006c6 <__adddf3+0x24e>
8000672: ea94 0f05 teq r4, r5
8000676: bf08 it eq
8000678: ea90 0f02 teqeq r0, r2
800067c: d005 beq.n 800068a <__adddf3+0x212>
800067e: ea54 0c00 orrs.w ip, r4, r0
8000682: bf04 itt eq
8000684: 4619 moveq r1, r3
8000686: 4610 moveq r0, r2
8000688: bd30 pop {r4, r5, pc}
800068a: ea91 0f03 teq r1, r3
800068e: bf1e ittt ne
8000690: 2100 movne r1, #0
8000692: 2000 movne r0, #0
8000694: bd30 popne {r4, r5, pc}
8000696: ea5f 5c54 movs.w ip, r4, lsr #21
800069a: d105 bne.n 80006a8 <__adddf3+0x230>
800069c: 0040 lsls r0, r0, #1
800069e: 4149 adcs r1, r1
80006a0: bf28 it cs
80006a2: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80006a6: bd30 pop {r4, r5, pc}
80006a8: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80006ac: bf3c itt cc
80006ae: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80006b2: bd30 popcc {r4, r5, pc}
80006b4: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80006b8: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
80006bc: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80006c0: f04f 0000 mov.w r0, #0
80006c4: bd30 pop {r4, r5, pc}
80006c6: ea7f 5c64 mvns.w ip, r4, asr #21
80006ca: bf1a itte ne
80006cc: 4619 movne r1, r3
80006ce: 4610 movne r0, r2
80006d0: ea7f 5c65 mvnseq.w ip, r5, asr #21
80006d4: bf1c itt ne
80006d6: 460b movne r3, r1
80006d8: 4602 movne r2, r0
80006da: ea50 3401 orrs.w r4, r0, r1, lsl #12
80006de: bf06 itte eq
80006e0: ea52 3503 orrseq.w r5, r2, r3, lsl #12
80006e4: ea91 0f03 teqeq r1, r3
80006e8: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
80006ec: bd30 pop {r4, r5, pc}
80006ee: bf00 nop
080006f0 <__aeabi_ui2d>:
80006f0: f090 0f00 teq r0, #0
80006f4: bf04 itt eq
80006f6: 2100 moveq r1, #0
80006f8: 4770 bxeq lr
80006fa: b530 push {r4, r5, lr}
80006fc: f44f 6480 mov.w r4, #1024 @ 0x400
8000700: f104 0432 add.w r4, r4, #50 @ 0x32
8000704: f04f 0500 mov.w r5, #0
8000708: f04f 0100 mov.w r1, #0
800070c: e750 b.n 80005b0 <__adddf3+0x138>
800070e: bf00 nop
08000710 <__aeabi_i2d>:
8000710: f090 0f00 teq r0, #0
8000714: bf04 itt eq
8000716: 2100 moveq r1, #0
8000718: 4770 bxeq lr
800071a: b530 push {r4, r5, lr}
800071c: f44f 6480 mov.w r4, #1024 @ 0x400
8000720: f104 0432 add.w r4, r4, #50 @ 0x32
8000724: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
8000728: bf48 it mi
800072a: 4240 negmi r0, r0
800072c: f04f 0100 mov.w r1, #0
8000730: e73e b.n 80005b0 <__adddf3+0x138>
8000732: bf00 nop
08000734 <__aeabi_f2d>:
8000734: 0042 lsls r2, r0, #1
8000736: ea4f 01e2 mov.w r1, r2, asr #3
800073a: ea4f 0131 mov.w r1, r1, rrx
800073e: ea4f 7002 mov.w r0, r2, lsl #28
8000742: bf1f itttt ne
8000744: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
8000748: f093 4f7f teqne r3, #4278190080 @ 0xff000000
800074c: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000750: 4770 bxne lr
8000752: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
8000756: bf08 it eq
8000758: 4770 bxeq lr
800075a: f093 4f7f teq r3, #4278190080 @ 0xff000000
800075e: bf04 itt eq
8000760: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
8000764: 4770 bxeq lr
8000766: b530 push {r4, r5, lr}
8000768: f44f 7460 mov.w r4, #896 @ 0x380
800076c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000770: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000774: e71c b.n 80005b0 <__adddf3+0x138>
8000776: bf00 nop
08000778 <__aeabi_ul2d>:
8000778: ea50 0201 orrs.w r2, r0, r1
800077c: bf08 it eq
800077e: 4770 bxeq lr
8000780: b530 push {r4, r5, lr}
8000782: f04f 0500 mov.w r5, #0
8000786: e00a b.n 800079e <__aeabi_l2d+0x16>
08000788 <__aeabi_l2d>:
8000788: ea50 0201 orrs.w r2, r0, r1
800078c: bf08 it eq
800078e: 4770 bxeq lr
8000790: b530 push {r4, r5, lr}
8000792: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
8000796: d502 bpl.n 800079e <__aeabi_l2d+0x16>
8000798: 4240 negs r0, r0
800079a: eb61 0141 sbc.w r1, r1, r1, lsl #1
800079e: f44f 6480 mov.w r4, #1024 @ 0x400
80007a2: f104 0432 add.w r4, r4, #50 @ 0x32
80007a6: ea5f 5c91 movs.w ip, r1, lsr #22
80007aa: f43f aed8 beq.w 800055e <__adddf3+0xe6>
80007ae: f04f 0203 mov.w r2, #3
80007b2: ea5f 0cdc movs.w ip, ip, lsr #3
80007b6: bf18 it ne
80007b8: 3203 addne r2, #3
80007ba: ea5f 0cdc movs.w ip, ip, lsr #3
80007be: bf18 it ne
80007c0: 3203 addne r2, #3
80007c2: eb02 02dc add.w r2, r2, ip, lsr #3
80007c6: f1c2 0320 rsb r3, r2, #32
80007ca: fa00 fc03 lsl.w ip, r0, r3
80007ce: fa20 f002 lsr.w r0, r0, r2
80007d2: fa01 fe03 lsl.w lr, r1, r3
80007d6: ea40 000e orr.w r0, r0, lr
80007da: fa21 f102 lsr.w r1, r1, r2
80007de: 4414 add r4, r2
80007e0: e6bd b.n 800055e <__adddf3+0xe6>
80007e2: bf00 nop
080007e4 <__aeabi_d2uiz>:
80007e4: 004a lsls r2, r1, #1
80007e6: d211 bcs.n 800080c <__aeabi_d2uiz+0x28>
80007e8: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
80007ec: d211 bcs.n 8000812 <__aeabi_d2uiz+0x2e>
80007ee: d50d bpl.n 800080c <__aeabi_d2uiz+0x28>
80007f0: f46f 7378 mvn.w r3, #992 @ 0x3e0
80007f4: ebb3 5262 subs.w r2, r3, r2, asr #21
80007f8: d40e bmi.n 8000818 <__aeabi_d2uiz+0x34>
80007fa: ea4f 23c1 mov.w r3, r1, lsl #11
80007fe: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000802: ea43 5350 orr.w r3, r3, r0, lsr #21
8000806: fa23 f002 lsr.w r0, r3, r2
800080a: 4770 bx lr
800080c: f04f 0000 mov.w r0, #0
8000810: 4770 bx lr
8000812: ea50 3001 orrs.w r0, r0, r1, lsl #12
8000816: d102 bne.n 800081e <__aeabi_d2uiz+0x3a>
8000818: f04f 30ff mov.w r0, #4294967295
800081c: 4770 bx lr
800081e: f04f 0000 mov.w r0, #0
8000822: 4770 bx lr
08000824 <__aeabi_uldivmod>:
8000824: b953 cbnz r3, 800083c <__aeabi_uldivmod+0x18>
8000826: b94a cbnz r2, 800083c <__aeabi_uldivmod+0x18>
8000828: 2900 cmp r1, #0
800082a: bf08 it eq
800082c: 2800 cmpeq r0, #0
800082e: bf1c itt ne
8000830: f04f 31ff movne.w r1, #4294967295
8000834: f04f 30ff movne.w r0, #4294967295
8000838: f000 b988 b.w 8000b4c <__aeabi_idiv0>
800083c: f1ad 0c08 sub.w ip, sp, #8
8000840: e96d ce04 strd ip, lr, [sp, #-16]!
8000844: f000 f806 bl 8000854 <__udivmoddi4>
8000848: f8dd e004 ldr.w lr, [sp, #4]
800084c: e9dd 2302 ldrd r2, r3, [sp, #8]
8000850: b004 add sp, #16
8000852: 4770 bx lr
08000854 <__udivmoddi4>:
8000854: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000858: 9d08 ldr r5, [sp, #32]
800085a: 468e mov lr, r1
800085c: 4604 mov r4, r0
800085e: 4688 mov r8, r1
8000860: 2b00 cmp r3, #0
8000862: d14a bne.n 80008fa <__udivmoddi4+0xa6>
8000864: 428a cmp r2, r1
8000866: 4617 mov r7, r2
8000868: d962 bls.n 8000930 <__udivmoddi4+0xdc>
800086a: fab2 f682 clz r6, r2
800086e: b14e cbz r6, 8000884 <__udivmoddi4+0x30>
8000870: f1c6 0320 rsb r3, r6, #32
8000874: fa01 f806 lsl.w r8, r1, r6
8000878: fa20 f303 lsr.w r3, r0, r3
800087c: 40b7 lsls r7, r6
800087e: ea43 0808 orr.w r8, r3, r8
8000882: 40b4 lsls r4, r6
8000884: ea4f 4e17 mov.w lr, r7, lsr #16
8000888: fa1f fc87 uxth.w ip, r7
800088c: fbb8 f1fe udiv r1, r8, lr
8000890: 0c23 lsrs r3, r4, #16
8000892: fb0e 8811 mls r8, lr, r1, r8
8000896: ea43 4308 orr.w r3, r3, r8, lsl #16
800089a: fb01 f20c mul.w r2, r1, ip
800089e: 429a cmp r2, r3
80008a0: d909 bls.n 80008b6 <__udivmoddi4+0x62>
80008a2: 18fb adds r3, r7, r3
80008a4: f101 30ff add.w r0, r1, #4294967295
80008a8: f080 80ea bcs.w 8000a80 <__udivmoddi4+0x22c>
80008ac: 429a cmp r2, r3
80008ae: f240 80e7 bls.w 8000a80 <__udivmoddi4+0x22c>
80008b2: 3902 subs r1, #2
80008b4: 443b add r3, r7
80008b6: 1a9a subs r2, r3, r2
80008b8: b2a3 uxth r3, r4
80008ba: fbb2 f0fe udiv r0, r2, lr
80008be: fb0e 2210 mls r2, lr, r0, r2
80008c2: ea43 4302 orr.w r3, r3, r2, lsl #16
80008c6: fb00 fc0c mul.w ip, r0, ip
80008ca: 459c cmp ip, r3
80008cc: d909 bls.n 80008e2 <__udivmoddi4+0x8e>
80008ce: 18fb adds r3, r7, r3
80008d0: f100 32ff add.w r2, r0, #4294967295
80008d4: f080 80d6 bcs.w 8000a84 <__udivmoddi4+0x230>
80008d8: 459c cmp ip, r3
80008da: f240 80d3 bls.w 8000a84 <__udivmoddi4+0x230>
80008de: 443b add r3, r7
80008e0: 3802 subs r0, #2
80008e2: ea40 4001 orr.w r0, r0, r1, lsl #16
80008e6: eba3 030c sub.w r3, r3, ip
80008ea: 2100 movs r1, #0
80008ec: b11d cbz r5, 80008f6 <__udivmoddi4+0xa2>
80008ee: 40f3 lsrs r3, r6
80008f0: 2200 movs r2, #0
80008f2: e9c5 3200 strd r3, r2, [r5]
80008f6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80008fa: 428b cmp r3, r1
80008fc: d905 bls.n 800090a <__udivmoddi4+0xb6>
80008fe: b10d cbz r5, 8000904 <__udivmoddi4+0xb0>
8000900: e9c5 0100 strd r0, r1, [r5]
8000904: 2100 movs r1, #0
8000906: 4608 mov r0, r1
8000908: e7f5 b.n 80008f6 <__udivmoddi4+0xa2>
800090a: fab3 f183 clz r1, r3
800090e: 2900 cmp r1, #0
8000910: d146 bne.n 80009a0 <__udivmoddi4+0x14c>
8000912: 4573 cmp r3, lr
8000914: d302 bcc.n 800091c <__udivmoddi4+0xc8>
8000916: 4282 cmp r2, r0
8000918: f200 8105 bhi.w 8000b26 <__udivmoddi4+0x2d2>
800091c: 1a84 subs r4, r0, r2
800091e: eb6e 0203 sbc.w r2, lr, r3
8000922: 2001 movs r0, #1
8000924: 4690 mov r8, r2
8000926: 2d00 cmp r5, #0
8000928: d0e5 beq.n 80008f6 <__udivmoddi4+0xa2>
800092a: e9c5 4800 strd r4, r8, [r5]
800092e: e7e2 b.n 80008f6 <__udivmoddi4+0xa2>
8000930: 2a00 cmp r2, #0
8000932: f000 8090 beq.w 8000a56 <__udivmoddi4+0x202>
8000936: fab2 f682 clz r6, r2
800093a: 2e00 cmp r6, #0
800093c: f040 80a4 bne.w 8000a88 <__udivmoddi4+0x234>
8000940: 1a8a subs r2, r1, r2
8000942: 0c03 lsrs r3, r0, #16
8000944: ea4f 4e17 mov.w lr, r7, lsr #16
8000948: b280 uxth r0, r0
800094a: b2bc uxth r4, r7
800094c: 2101 movs r1, #1
800094e: fbb2 fcfe udiv ip, r2, lr
8000952: fb0e 221c mls r2, lr, ip, r2
8000956: ea43 4302 orr.w r3, r3, r2, lsl #16
800095a: fb04 f20c mul.w r2, r4, ip
800095e: 429a cmp r2, r3
8000960: d907 bls.n 8000972 <__udivmoddi4+0x11e>
8000962: 18fb adds r3, r7, r3
8000964: f10c 38ff add.w r8, ip, #4294967295
8000968: d202 bcs.n 8000970 <__udivmoddi4+0x11c>
800096a: 429a cmp r2, r3
800096c: f200 80e0 bhi.w 8000b30 <__udivmoddi4+0x2dc>
8000970: 46c4 mov ip, r8
8000972: 1a9b subs r3, r3, r2
8000974: fbb3 f2fe udiv r2, r3, lr
8000978: fb0e 3312 mls r3, lr, r2, r3
800097c: ea40 4303 orr.w r3, r0, r3, lsl #16
8000980: fb02 f404 mul.w r4, r2, r4
8000984: 429c cmp r4, r3
8000986: d907 bls.n 8000998 <__udivmoddi4+0x144>
8000988: 18fb adds r3, r7, r3
800098a: f102 30ff add.w r0, r2, #4294967295
800098e: d202 bcs.n 8000996 <__udivmoddi4+0x142>
8000990: 429c cmp r4, r3
8000992: f200 80ca bhi.w 8000b2a <__udivmoddi4+0x2d6>
8000996: 4602 mov r2, r0
8000998: 1b1b subs r3, r3, r4
800099a: ea42 400c orr.w r0, r2, ip, lsl #16
800099e: e7a5 b.n 80008ec <__udivmoddi4+0x98>
80009a0: f1c1 0620 rsb r6, r1, #32
80009a4: 408b lsls r3, r1
80009a6: fa22 f706 lsr.w r7, r2, r6
80009aa: 431f orrs r7, r3
80009ac: fa0e f401 lsl.w r4, lr, r1
80009b0: fa20 f306 lsr.w r3, r0, r6
80009b4: fa2e fe06 lsr.w lr, lr, r6
80009b8: ea4f 4917 mov.w r9, r7, lsr #16
80009bc: 4323 orrs r3, r4
80009be: fa00 f801 lsl.w r8, r0, r1
80009c2: fa1f fc87 uxth.w ip, r7
80009c6: fbbe f0f9 udiv r0, lr, r9
80009ca: 0c1c lsrs r4, r3, #16
80009cc: fb09 ee10 mls lr, r9, r0, lr
80009d0: ea44 440e orr.w r4, r4, lr, lsl #16
80009d4: fb00 fe0c mul.w lr, r0, ip
80009d8: 45a6 cmp lr, r4
80009da: fa02 f201 lsl.w r2, r2, r1
80009de: d909 bls.n 80009f4 <__udivmoddi4+0x1a0>
80009e0: 193c adds r4, r7, r4
80009e2: f100 3aff add.w sl, r0, #4294967295
80009e6: f080 809c bcs.w 8000b22 <__udivmoddi4+0x2ce>
80009ea: 45a6 cmp lr, r4
80009ec: f240 8099 bls.w 8000b22 <__udivmoddi4+0x2ce>
80009f0: 3802 subs r0, #2
80009f2: 443c add r4, r7
80009f4: eba4 040e sub.w r4, r4, lr
80009f8: fa1f fe83 uxth.w lr, r3
80009fc: fbb4 f3f9 udiv r3, r4, r9
8000a00: fb09 4413 mls r4, r9, r3, r4
8000a04: ea4e 4404 orr.w r4, lr, r4, lsl #16
8000a08: fb03 fc0c mul.w ip, r3, ip
8000a0c: 45a4 cmp ip, r4
8000a0e: d908 bls.n 8000a22 <__udivmoddi4+0x1ce>
8000a10: 193c adds r4, r7, r4
8000a12: f103 3eff add.w lr, r3, #4294967295
8000a16: f080 8082 bcs.w 8000b1e <__udivmoddi4+0x2ca>
8000a1a: 45a4 cmp ip, r4
8000a1c: d97f bls.n 8000b1e <__udivmoddi4+0x2ca>
8000a1e: 3b02 subs r3, #2
8000a20: 443c add r4, r7
8000a22: ea43 4000 orr.w r0, r3, r0, lsl #16
8000a26: eba4 040c sub.w r4, r4, ip
8000a2a: fba0 ec02 umull lr, ip, r0, r2
8000a2e: 4564 cmp r4, ip
8000a30: 4673 mov r3, lr
8000a32: 46e1 mov r9, ip
8000a34: d362 bcc.n 8000afc <__udivmoddi4+0x2a8>
8000a36: d05f beq.n 8000af8 <__udivmoddi4+0x2a4>
8000a38: b15d cbz r5, 8000a52 <__udivmoddi4+0x1fe>
8000a3a: ebb8 0203 subs.w r2, r8, r3
8000a3e: eb64 0409 sbc.w r4, r4, r9
8000a42: fa04 f606 lsl.w r6, r4, r6
8000a46: fa22 f301 lsr.w r3, r2, r1
8000a4a: 431e orrs r6, r3
8000a4c: 40cc lsrs r4, r1
8000a4e: e9c5 6400 strd r6, r4, [r5]
8000a52: 2100 movs r1, #0
8000a54: e74f b.n 80008f6 <__udivmoddi4+0xa2>
8000a56: fbb1 fcf2 udiv ip, r1, r2
8000a5a: 0c01 lsrs r1, r0, #16
8000a5c: ea41 410e orr.w r1, r1, lr, lsl #16
8000a60: b280 uxth r0, r0
8000a62: ea40 4201 orr.w r2, r0, r1, lsl #16
8000a66: 463b mov r3, r7
8000a68: 4638 mov r0, r7
8000a6a: 463c mov r4, r7
8000a6c: 46b8 mov r8, r7
8000a6e: 46be mov lr, r7
8000a70: 2620 movs r6, #32
8000a72: fbb1 f1f7 udiv r1, r1, r7
8000a76: eba2 0208 sub.w r2, r2, r8
8000a7a: ea41 410c orr.w r1, r1, ip, lsl #16
8000a7e: e766 b.n 800094e <__udivmoddi4+0xfa>
8000a80: 4601 mov r1, r0
8000a82: e718 b.n 80008b6 <__udivmoddi4+0x62>
8000a84: 4610 mov r0, r2
8000a86: e72c b.n 80008e2 <__udivmoddi4+0x8e>
8000a88: f1c6 0220 rsb r2, r6, #32
8000a8c: fa2e f302 lsr.w r3, lr, r2
8000a90: 40b7 lsls r7, r6
8000a92: 40b1 lsls r1, r6
8000a94: fa20 f202 lsr.w r2, r0, r2
8000a98: ea4f 4e17 mov.w lr, r7, lsr #16
8000a9c: 430a orrs r2, r1
8000a9e: fbb3 f8fe udiv r8, r3, lr
8000aa2: b2bc uxth r4, r7
8000aa4: fb0e 3318 mls r3, lr, r8, r3
8000aa8: 0c11 lsrs r1, r2, #16
8000aaa: ea41 4103 orr.w r1, r1, r3, lsl #16
8000aae: fb08 f904 mul.w r9, r8, r4
8000ab2: 40b0 lsls r0, r6
8000ab4: 4589 cmp r9, r1
8000ab6: ea4f 4310 mov.w r3, r0, lsr #16
8000aba: b280 uxth r0, r0
8000abc: d93e bls.n 8000b3c <__udivmoddi4+0x2e8>
8000abe: 1879 adds r1, r7, r1
8000ac0: f108 3cff add.w ip, r8, #4294967295
8000ac4: d201 bcs.n 8000aca <__udivmoddi4+0x276>
8000ac6: 4589 cmp r9, r1
8000ac8: d81f bhi.n 8000b0a <__udivmoddi4+0x2b6>
8000aca: eba1 0109 sub.w r1, r1, r9
8000ace: fbb1 f9fe udiv r9, r1, lr
8000ad2: fb09 f804 mul.w r8, r9, r4
8000ad6: fb0e 1119 mls r1, lr, r9, r1
8000ada: b292 uxth r2, r2
8000adc: ea42 4201 orr.w r2, r2, r1, lsl #16
8000ae0: 4542 cmp r2, r8
8000ae2: d229 bcs.n 8000b38 <__udivmoddi4+0x2e4>
8000ae4: 18ba adds r2, r7, r2
8000ae6: f109 31ff add.w r1, r9, #4294967295
8000aea: d2c4 bcs.n 8000a76 <__udivmoddi4+0x222>
8000aec: 4542 cmp r2, r8
8000aee: d2c2 bcs.n 8000a76 <__udivmoddi4+0x222>
8000af0: f1a9 0102 sub.w r1, r9, #2
8000af4: 443a add r2, r7
8000af6: e7be b.n 8000a76 <__udivmoddi4+0x222>
8000af8: 45f0 cmp r8, lr
8000afa: d29d bcs.n 8000a38 <__udivmoddi4+0x1e4>
8000afc: ebbe 0302 subs.w r3, lr, r2
8000b00: eb6c 0c07 sbc.w ip, ip, r7
8000b04: 3801 subs r0, #1
8000b06: 46e1 mov r9, ip
8000b08: e796 b.n 8000a38 <__udivmoddi4+0x1e4>
8000b0a: eba7 0909 sub.w r9, r7, r9
8000b0e: 4449 add r1, r9
8000b10: f1a8 0c02 sub.w ip, r8, #2
8000b14: fbb1 f9fe udiv r9, r1, lr
8000b18: fb09 f804 mul.w r8, r9, r4
8000b1c: e7db b.n 8000ad6 <__udivmoddi4+0x282>
8000b1e: 4673 mov r3, lr
8000b20: e77f b.n 8000a22 <__udivmoddi4+0x1ce>
8000b22: 4650 mov r0, sl
8000b24: e766 b.n 80009f4 <__udivmoddi4+0x1a0>
8000b26: 4608 mov r0, r1
8000b28: e6fd b.n 8000926 <__udivmoddi4+0xd2>
8000b2a: 443b add r3, r7
8000b2c: 3a02 subs r2, #2
8000b2e: e733 b.n 8000998 <__udivmoddi4+0x144>
8000b30: f1ac 0c02 sub.w ip, ip, #2
8000b34: 443b add r3, r7
8000b36: e71c b.n 8000972 <__udivmoddi4+0x11e>
8000b38: 4649 mov r1, r9
8000b3a: e79c b.n 8000a76 <__udivmoddi4+0x222>
8000b3c: eba1 0109 sub.w r1, r1, r9
8000b40: 46c4 mov ip, r8
8000b42: fbb1 f9fe udiv r9, r1, lr
8000b46: fb09 f804 mul.w r8, r9, r4
8000b4a: e7c4 b.n 8000ad6 <__udivmoddi4+0x282>
08000b4c <__aeabi_idiv0>:
8000b4c: 4770 bx lr
8000b4e: bf00 nop
08000b50 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b50: b580 push {r7, lr}
8000b52: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b54: f001 f8d1 bl 8001cfa <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b58: f000 f894 bl 8000c84 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b5c: f000 fae0 bl 8001120 <MX_GPIO_Init>
MX_USART2_UART_Init();
8000b60: f000 fa92 bl 8001088 <MX_USART2_UART_Init>
MX_ADC2_Init();
8000b64: f000 f952 bl 8000e0c <MX_ADC2_Init>
MX_TIM2_Init();
8000b68: f000 f9c6 bl 8000ef8 <MX_TIM2_Init>
MX_ADC1_Init();
8000b6c: f000 f8d6 bl 8000d1c <MX_ADC1_Init>
MX_TIM16_Init();
8000b70: f000 fa10 bl 8000f94 <MX_TIM16_Init>
/* USER CODE BEGIN 2 */
/*Configure GPIO pin output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000b74: 2200 movs r2, #0
8000b76: f44f 7180 mov.w r1, #256 @ 0x100
8000b7a: 4832 ldr r0, [pc, #200] @ (8000c44 <main+0xf4>)
8000b7c: f003 f93e bl 8003dfc <HAL_GPIO_WritePin>
/* Run ADC calibration */
HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);
8000b80: 217f movs r1, #127 @ 0x7f
8000b82: 4831 ldr r0, [pc, #196] @ (8000c48 <main+0xf8>)
8000b84: f002 fce2 bl 800354c <HAL_ADCEx_Calibration_Start>
HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED);
8000b88: 217f movs r1, #127 @ 0x7f
8000b8a: 4830 ldr r0, [pc, #192] @ (8000c4c <main+0xfc>)
8000b8c: f002 fcde bl 800354c <HAL_ADCEx_Calibration_Start>
/* Setup UART interrupts */
/* Make sure UART Rx counters and flags are reset */
rx_counter = 0x00;
8000b90: 4b2f ldr r3, [pc, #188] @ (8000c50 <main+0x100>)
8000b92: 2200 movs r2, #0
8000b94: 701a strb r2, [r3, #0]
rx_len = 0x00;
8000b96: 4b2f ldr r3, [pc, #188] @ (8000c54 <main+0x104>)
8000b98: 2200 movs r2, #0
8000b9a: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
8000b9c: 4b2e ldr r3, [pc, #184] @ (8000c58 <main+0x108>)
8000b9e: 2200 movs r2, #0
8000ba0: 701a strb r2, [r3, #0]
adc_task_flag = 0x00;
8000ba2: 4b2e ldr r3, [pc, #184] @ (8000c5c <main+0x10c>)
8000ba4: 2200 movs r2, #0
8000ba6: 701a strb r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
8000ba8: 2201 movs r2, #1
8000baa: 492d ldr r1, [pc, #180] @ (8000c60 <main+0x110>)
8000bac: 482d ldr r0, [pc, #180] @ (8000c64 <main+0x114>)
8000bae: f005 fcdd bl 800656c <HAL_UART_Receive_IT>
/* Get real VDDA value */
vdd_ref = get_actual_vdda(&hadc1);
8000bb2: 4825 ldr r0, [pc, #148] @ (8000c48 <main+0xf8>)
8000bb4: f000 fb54 bl 8001260 <get_actual_vdda>
8000bb8: 4603 mov r3, r0
8000bba: 4a2b ldr r2, [pc, #172] @ (8000c68 <main+0x118>)
8000bbc: 6013 str r3, [r2, #0]
/* Start output PWM at zero */
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
8000bbe: 4b2b ldr r3, [pc, #172] @ (8000c6c <main+0x11c>)
8000bc0: 681b ldr r3, [r3, #0]
8000bc2: 2200 movs r2, #0
8000bc4: 635a str r2, [r3, #52] @ 0x34
HAL_TIM_PWM_Start(&htim16, TIM_CHANNEL_1);
8000bc6: 2100 movs r1, #0
8000bc8: 4828 ldr r0, [pc, #160] @ (8000c6c <main+0x11c>)
8000bca: f004 f9b9 bl 8004f40 <HAL_TIM_PWM_Start>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
if (adc_task_flag == 0xff)
8000bce: 4b23 ldr r3, [pc, #140] @ (8000c5c <main+0x10c>)
8000bd0: 781b ldrb r3, [r3, #0]
8000bd2: 2bff cmp r3, #255 @ 0xff
8000bd4: d114 bne.n 8000c00 <main+0xb0>
{
adc_task_flag = 0x00;
8000bd6: 4b21 ldr r3, [pc, #132] @ (8000c5c <main+0x10c>)
8000bd8: 2200 movs r2, #0
8000bda: 701a strb r2, [r3, #0]
if (vset_task_flag != 0xff)
8000bdc: 4b24 ldr r3, [pc, #144] @ (8000c70 <main+0x120>)
8000bde: 781b ldrb r3, [r3, #0]
8000be0: 2bff cmp r3, #255 @ 0xff
8000be2: d00b beq.n 8000bfc <main+0xac>
{
adc_task();
8000be4: f000 fcfe bl 80015e4 <adc_task>
vout_adc_val_av = MA_Update (&movavFilter, vout_adc_val);
8000be8: 4b22 ldr r3, [pc, #136] @ (8000c74 <main+0x124>)
8000bea: 881b ldrh r3, [r3, #0]
8000bec: 4619 mov r1, r3
8000bee: 4822 ldr r0, [pc, #136] @ (8000c78 <main+0x128>)
8000bf0: f000 faf6 bl 80011e0 <MA_Update>
8000bf4: 4603 mov r3, r0
8000bf6: 461a mov r2, r3
8000bf8: 4b20 ldr r3, [pc, #128] @ (8000c7c <main+0x12c>)
8000bfa: 801a strh r2, [r3, #0]
}
voltage_conversion_task();
8000bfc: f000 fba0 bl 8001340 <voltage_conversion_task>
}
if (serial_number_flag == 0xff)
8000c00: 4b1f ldr r3, [pc, #124] @ (8000c80 <main+0x130>)
8000c02: 781b ldrb r3, [r3, #0]
8000c04: 2bff cmp r3, #255 @ 0xff
8000c06: d104 bne.n 8000c12 <main+0xc2>
{
serial_number_flag = 0x00;
8000c08: 4b1d ldr r3, [pc, #116] @ (8000c80 <main+0x130>)
8000c0a: 2200 movs r2, #0
8000c0c: 701a strb r2, [r3, #0]
serial_number_task ();
8000c0e: f000 fc51 bl 80014b4 <serial_number_task>
}
if (vset_task_flag == 0xff)
8000c12: 4b17 ldr r3, [pc, #92] @ (8000c70 <main+0x120>)
8000c14: 781b ldrb r3, [r3, #0]
8000c16: 2bff cmp r3, #255 @ 0xff
8000c18: d1d9 bne.n 8000bce <main+0x7e>
{
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 300);
8000c1a: 4b14 ldr r3, [pc, #80] @ (8000c6c <main+0x11c>)
8000c1c: 681b ldr r3, [r3, #0]
8000c1e: f44f 7296 mov.w r2, #300 @ 0x12c
8000c22: 635a str r2, [r3, #52] @ 0x34
adc_task();
8000c24: f000 fcde bl 80015e4 <adc_task>
vout_adc_val_av = MA_Update (&movavFilter, vout_adc_val);
8000c28: 4b12 ldr r3, [pc, #72] @ (8000c74 <main+0x124>)
8000c2a: 881b ldrh r3, [r3, #0]
8000c2c: 4619 mov r1, r3
8000c2e: 4812 ldr r0, [pc, #72] @ (8000c78 <main+0x128>)
8000c30: f000 fad6 bl 80011e0 <MA_Update>
8000c34: 4603 mov r3, r0
8000c36: 461a mov r2, r3
8000c38: 4b10 ldr r3, [pc, #64] @ (8000c7c <main+0x12c>)
8000c3a: 801a strh r2, [r3, #0]
voltage_conversion_task_no_tx();
8000c3c: f000 fc24 bl 8001488 <voltage_conversion_task_no_tx>
if (adc_task_flag == 0xff)
8000c40: e7c5 b.n 8000bce <main+0x7e>
8000c42: bf00 nop
8000c44: 48000400 .word 0x48000400
8000c48: 20000040 .word 0x20000040
8000c4c: 200000ac .word 0x200000ac
8000c50: 2000028e .word 0x2000028e
8000c54: 2000028f .word 0x2000028f
8000c58: 20000290 .word 0x20000290
8000c5c: 2000029c .word 0x2000029c
8000c60: 20000248 .word 0x20000248
8000c64: 200001b0 .word 0x200001b0
8000c68: 200002a4 .word 0x200002a4
8000c6c: 20000164 .word 0x20000164
8000c70: 200002b4 .word 0x200002b4
8000c74: 200002a0 .word 0x200002a0
8000c78: 200002b8 .word 0x200002b8
8000c7c: 200002a2 .word 0x200002a2
8000c80: 200002b5 .word 0x200002b5
08000c84 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000c84: b580 push {r7, lr}
8000c86: b094 sub sp, #80 @ 0x50
8000c88: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000c8a: f107 0318 add.w r3, r7, #24
8000c8e: 2238 movs r2, #56 @ 0x38
8000c90: 2100 movs r1, #0
8000c92: 4618 mov r0, r3
8000c94: f007 fc9c bl 80085d0 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000c98: 1d3b adds r3, r7, #4
8000c9a: 2200 movs r2, #0
8000c9c: 601a str r2, [r3, #0]
8000c9e: 605a str r2, [r3, #4]
8000ca0: 609a str r2, [r3, #8]
8000ca2: 60da str r2, [r3, #12]
8000ca4: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
8000ca6: f44f 7000 mov.w r0, #512 @ 0x200
8000caa: f003 f8bf bl 8003e2c <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000cae: 2302 movs r3, #2
8000cb0: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000cb2: f44f 7380 mov.w r3, #256 @ 0x100
8000cb6: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000cb8: 2340 movs r3, #64 @ 0x40
8000cba: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000cbc: 2302 movs r3, #2
8000cbe: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000cc0: 2302 movs r3, #2
8000cc2: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
8000cc4: 2301 movs r3, #1
8000cc6: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLN = 16;
8000cc8: 2310 movs r3, #16
8000cca: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000ccc: 2302 movs r3, #2
8000cce: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
8000cd0: 2302 movs r3, #2
8000cd2: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8000cd4: 2302 movs r3, #2
8000cd6: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000cd8: f107 0318 add.w r3, r7, #24
8000cdc: 4618 mov r0, r3
8000cde: f003 f959 bl 8003f94 <HAL_RCC_OscConfig>
8000ce2: 4603 mov r3, r0
8000ce4: 2b00 cmp r3, #0
8000ce6: d001 beq.n 8000cec <SystemClock_Config+0x68>
{
Error_Handler();
8000ce8: f000 fe02 bl 80018f0 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000cec: 230f movs r3, #15
8000cee: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000cf0: 2303 movs r3, #3
8000cf2: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000cf4: 2300 movs r3, #0
8000cf6: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000cf8: 2300 movs r3, #0
8000cfa: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000cfc: 2300 movs r3, #0
8000cfe: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
8000d00: 1d3b adds r3, r7, #4
8000d02: 2104 movs r1, #4
8000d04: 4618 mov r0, r3
8000d06: f003 fc57 bl 80045b8 <HAL_RCC_ClockConfig>
8000d0a: 4603 mov r3, r0
8000d0c: 2b00 cmp r3, #0
8000d0e: d001 beq.n 8000d14 <SystemClock_Config+0x90>
{
Error_Handler();
8000d10: f000 fdee bl 80018f0 <Error_Handler>
}
}
8000d14: bf00 nop
8000d16: 3750 adds r7, #80 @ 0x50
8000d18: 46bd mov sp, r7
8000d1a: bd80 pop {r7, pc}
08000d1c <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000d1c: b580 push {r7, lr}
8000d1e: b08c sub sp, #48 @ 0x30
8000d20: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
8000d22: f107 0324 add.w r3, r7, #36 @ 0x24
8000d26: 2200 movs r2, #0
8000d28: 601a str r2, [r3, #0]
8000d2a: 605a str r2, [r3, #4]
8000d2c: 609a str r2, [r3, #8]
ADC_ChannelConfTypeDef sConfig = {0};
8000d2e: 1d3b adds r3, r7, #4
8000d30: 2220 movs r2, #32
8000d32: 2100 movs r1, #0
8000d34: 4618 mov r0, r3
8000d36: f007 fc4b bl 80085d0 <memset>
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8000d3a: 4b32 ldr r3, [pc, #200] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d3c: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
8000d40: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
8000d42: 4b30 ldr r3, [pc, #192] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d44: f44f 1200 mov.w r2, #2097152 @ 0x200000
8000d48: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000d4a: 4b2e ldr r3, [pc, #184] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d4c: 2200 movs r2, #0
8000d4e: 609a str r2, [r3, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000d50: 4b2c ldr r3, [pc, #176] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d52: 2200 movs r2, #0
8000d54: 60da str r2, [r3, #12]
hadc1.Init.GainCompensation = 0;
8000d56: 4b2b ldr r3, [pc, #172] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d58: 2200 movs r2, #0
8000d5a: 611a str r2, [r3, #16]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000d5c: 4b29 ldr r3, [pc, #164] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d5e: 2200 movs r2, #0
8000d60: 615a str r2, [r3, #20]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000d62: 4b28 ldr r3, [pc, #160] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d64: 2204 movs r2, #4
8000d66: 619a str r2, [r3, #24]
hadc1.Init.LowPowerAutoWait = DISABLE;
8000d68: 4b26 ldr r3, [pc, #152] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d6a: 2200 movs r2, #0
8000d6c: 771a strb r2, [r3, #28]
hadc1.Init.ContinuousConvMode = DISABLE;
8000d6e: 4b25 ldr r3, [pc, #148] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d70: 2200 movs r2, #0
8000d72: 775a strb r2, [r3, #29]
hadc1.Init.NbrOfConversion = 1;
8000d74: 4b23 ldr r3, [pc, #140] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d76: 2201 movs r2, #1
8000d78: 621a str r2, [r3, #32]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000d7a: 4b22 ldr r3, [pc, #136] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d7c: 2200 movs r2, #0
8000d7e: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000d82: 4b20 ldr r3, [pc, #128] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d84: 2200 movs r2, #0
8000d86: 62da str r2, [r3, #44] @ 0x2c
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000d88: 4b1e ldr r3, [pc, #120] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d8a: 2200 movs r2, #0
8000d8c: 631a str r2, [r3, #48] @ 0x30
hadc1.Init.DMAContinuousRequests = DISABLE;
8000d8e: 4b1d ldr r3, [pc, #116] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d90: 2200 movs r2, #0
8000d92: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8000d96: 4b1b ldr r3, [pc, #108] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d98: 2200 movs r2, #0
8000d9a: 63da str r2, [r3, #60] @ 0x3c
hadc1.Init.OversamplingMode = DISABLE;
8000d9c: 4b19 ldr r3, [pc, #100] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000d9e: 2200 movs r2, #0
8000da0: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000da4: 4817 ldr r0, [pc, #92] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000da6: f001 fa93 bl 80022d0 <HAL_ADC_Init>
8000daa: 4603 mov r3, r0
8000dac: 2b00 cmp r3, #0
8000dae: d001 beq.n 8000db4 <MX_ADC1_Init+0x98>
{
Error_Handler();
8000db0: f000 fd9e bl 80018f0 <Error_Handler>
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
8000db4: 2300 movs r3, #0
8000db6: 627b str r3, [r7, #36] @ 0x24
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
8000db8: f107 0324 add.w r3, r7, #36 @ 0x24
8000dbc: 4619 mov r1, r3
8000dbe: 4811 ldr r0, [pc, #68] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000dc0: f002 fc26 bl 8003610 <HAL_ADCEx_MultiModeConfigChannel>
8000dc4: 4603 mov r3, r0
8000dc6: 2b00 cmp r3, #0
8000dc8: d001 beq.n 8000dce <MX_ADC1_Init+0xb2>
{
Error_Handler();
8000dca: f000 fd91 bl 80018f0 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_VREFINT;
8000dce: 4b0e ldr r3, [pc, #56] @ (8000e08 <MX_ADC1_Init+0xec>)
8000dd0: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000dd2: 2306 movs r3, #6
8000dd4: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
8000dd6: 2307 movs r3, #7
8000dd8: 60fb str r3, [r7, #12]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000dda: 237f movs r3, #127 @ 0x7f
8000ddc: 613b str r3, [r7, #16]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000dde: 2304 movs r3, #4
8000de0: 617b str r3, [r7, #20]
sConfig.Offset = 0;
8000de2: 2300 movs r3, #0
8000de4: 61bb str r3, [r7, #24]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000de6: 1d3b adds r3, r7, #4
8000de8: 4619 mov r1, r3
8000dea: 4806 ldr r0, [pc, #24] @ (8000e04 <MX_ADC1_Init+0xe8>)
8000dec: f001 fdca bl 8002984 <HAL_ADC_ConfigChannel>
8000df0: 4603 mov r3, r0
8000df2: 2b00 cmp r3, #0
8000df4: d001 beq.n 8000dfa <MX_ADC1_Init+0xde>
{
Error_Handler();
8000df6: f000 fd7b bl 80018f0 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000dfa: bf00 nop
8000dfc: 3730 adds r7, #48 @ 0x30
8000dfe: 46bd mov sp, r7
8000e00: bd80 pop {r7, pc}
8000e02: bf00 nop
8000e04: 20000040 .word 0x20000040
8000e08: cb840000 .word 0xcb840000
08000e0c <MX_ADC2_Init>:
* @brief ADC2 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC2_Init(void)
{
8000e0c: b580 push {r7, lr}
8000e0e: b088 sub sp, #32
8000e10: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000e12: 463b mov r3, r7
8000e14: 2220 movs r2, #32
8000e16: 2100 movs r1, #0
8000e18: 4618 mov r0, r3
8000e1a: f007 fbd9 bl 80085d0 <memset>
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
8000e1e: 4b32 ldr r3, [pc, #200] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e20: 4a32 ldr r2, [pc, #200] @ (8000eec <MX_ADC2_Init+0xe0>)
8000e22: 601a str r2, [r3, #0]
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
8000e24: 4b30 ldr r3, [pc, #192] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e26: f44f 1200 mov.w r2, #2097152 @ 0x200000
8000e2a: 605a str r2, [r3, #4]
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
8000e2c: 4b2e ldr r3, [pc, #184] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e2e: 2200 movs r2, #0
8000e30: 609a str r2, [r3, #8]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000e32: 4b2d ldr r3, [pc, #180] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e34: 2200 movs r2, #0
8000e36: 60da str r2, [r3, #12]
hadc2.Init.GainCompensation = 0;
8000e38: 4b2b ldr r3, [pc, #172] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e3a: 2200 movs r2, #0
8000e3c: 611a str r2, [r3, #16]
hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
8000e3e: 4b2a ldr r3, [pc, #168] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e40: 2201 movs r2, #1
8000e42: 615a str r2, [r3, #20]
hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000e44: 4b28 ldr r3, [pc, #160] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e46: 2204 movs r2, #4
8000e48: 619a str r2, [r3, #24]
hadc2.Init.LowPowerAutoWait = DISABLE;
8000e4a: 4b27 ldr r3, [pc, #156] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e4c: 2200 movs r2, #0
8000e4e: 771a strb r2, [r3, #28]
hadc2.Init.ContinuousConvMode = DISABLE;
8000e50: 4b25 ldr r3, [pc, #148] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e52: 2200 movs r2, #0
8000e54: 775a strb r2, [r3, #29]
hadc2.Init.NbrOfConversion = 2;
8000e56: 4b24 ldr r3, [pc, #144] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e58: 2202 movs r2, #2
8000e5a: 621a str r2, [r3, #32]
hadc2.Init.DiscontinuousConvMode = DISABLE;
8000e5c: 4b22 ldr r3, [pc, #136] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e5e: 2200 movs r2, #0
8000e60: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000e64: 4b20 ldr r3, [pc, #128] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e66: 2200 movs r2, #0
8000e68: 62da str r2, [r3, #44] @ 0x2c
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000e6a: 4b1f ldr r3, [pc, #124] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e6c: 2200 movs r2, #0
8000e6e: 631a str r2, [r3, #48] @ 0x30
hadc2.Init.DMAContinuousRequests = DISABLE;
8000e70: 4b1d ldr r3, [pc, #116] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e72: 2200 movs r2, #0
8000e74: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8000e78: 4b1b ldr r3, [pc, #108] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e7a: 2200 movs r2, #0
8000e7c: 63da str r2, [r3, #60] @ 0x3c
hadc2.Init.OversamplingMode = DISABLE;
8000e7e: 4b1a ldr r3, [pc, #104] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e80: 2200 movs r2, #0
8000e82: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8000e86: 4818 ldr r0, [pc, #96] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000e88: f001 fa22 bl 80022d0 <HAL_ADC_Init>
8000e8c: 4603 mov r3, r0
8000e8e: 2b00 cmp r3, #0
8000e90: d001 beq.n 8000e96 <MX_ADC2_Init+0x8a>
{
Error_Handler();
8000e92: f000 fd2d bl 80018f0 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
8000e96: 4b16 ldr r3, [pc, #88] @ (8000ef0 <MX_ADC2_Init+0xe4>)
8000e98: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000e9a: 2306 movs r3, #6
8000e9c: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
8000e9e: 2307 movs r3, #7
8000ea0: 60bb str r3, [r7, #8]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000ea2: 237f movs r3, #127 @ 0x7f
8000ea4: 60fb str r3, [r7, #12]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000ea6: 2304 movs r3, #4
8000ea8: 613b str r3, [r7, #16]
sConfig.Offset = 0;
8000eaa: 2300 movs r3, #0
8000eac: 617b str r3, [r7, #20]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000eae: 463b mov r3, r7
8000eb0: 4619 mov r1, r3
8000eb2: 480d ldr r0, [pc, #52] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000eb4: f001 fd66 bl 8002984 <HAL_ADC_ConfigChannel>
8000eb8: 4603 mov r3, r0
8000eba: 2b00 cmp r3, #0
8000ebc: d001 beq.n 8000ec2 <MX_ADC2_Init+0xb6>
{
Error_Handler();
8000ebe: f000 fd17 bl 80018f0 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
8000ec2: 4b0c ldr r3, [pc, #48] @ (8000ef4 <MX_ADC2_Init+0xe8>)
8000ec4: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_2;
8000ec6: 230c movs r3, #12
8000ec8: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000eca: 463b mov r3, r7
8000ecc: 4619 mov r1, r3
8000ece: 4806 ldr r0, [pc, #24] @ (8000ee8 <MX_ADC2_Init+0xdc>)
8000ed0: f001 fd58 bl 8002984 <HAL_ADC_ConfigChannel>
8000ed4: 4603 mov r3, r0
8000ed6: 2b00 cmp r3, #0
8000ed8: d001 beq.n 8000ede <MX_ADC2_Init+0xd2>
{
Error_Handler();
8000eda: f000 fd09 bl 80018f0 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
8000ede: bf00 nop
8000ee0: 3720 adds r7, #32
8000ee2: 46bd mov sp, r7
8000ee4: bd80 pop {r7, pc}
8000ee6: bf00 nop
8000ee8: 200000ac .word 0x200000ac
8000eec: 50000100 .word 0x50000100
8000ef0: 0c900008 .word 0x0c900008
8000ef4: 10c00010 .word 0x10c00010
08000ef8 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8000ef8: b580 push {r7, lr}
8000efa: b088 sub sp, #32
8000efc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000efe: f107 0310 add.w r3, r7, #16
8000f02: 2200 movs r2, #0
8000f04: 601a str r2, [r3, #0]
8000f06: 605a str r2, [r3, #4]
8000f08: 609a str r2, [r3, #8]
8000f0a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000f0c: 1d3b adds r3, r7, #4
8000f0e: 2200 movs r2, #0
8000f10: 601a str r2, [r3, #0]
8000f12: 605a str r2, [r3, #4]
8000f14: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000f16: 4b1d ldr r3, [pc, #116] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f18: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8000f1c: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
8000f1e: 4b1b ldr r3, [pc, #108] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f20: 2200 movs r2, #0
8000f22: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000f24: 4b19 ldr r3, [pc, #100] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f26: 2200 movs r2, #0
8000f28: 609a str r2, [r3, #8]
htim2.Init.Period = 128999;
8000f2a: 4b18 ldr r3, [pc, #96] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f2c: 4a18 ldr r2, [pc, #96] @ (8000f90 <MX_TIM2_Init+0x98>)
8000f2e: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000f30: 4b16 ldr r3, [pc, #88] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f32: 2200 movs r2, #0
8000f34: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000f36: 4b15 ldr r3, [pc, #84] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f38: 2200 movs r2, #0
8000f3a: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8000f3c: 4813 ldr r0, [pc, #76] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f3e: f003 ff47 bl 8004dd0 <HAL_TIM_Base_Init>
8000f42: 4603 mov r3, r0
8000f44: 2b00 cmp r3, #0
8000f46: d001 beq.n 8000f4c <MX_TIM2_Init+0x54>
{
Error_Handler();
8000f48: f000 fcd2 bl 80018f0 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000f4c: f44f 5380 mov.w r3, #4096 @ 0x1000
8000f50: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8000f52: f107 0310 add.w r3, r7, #16
8000f56: 4619 mov r1, r3
8000f58: 480c ldr r0, [pc, #48] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f5a: f004 fb55 bl 8005608 <HAL_TIM_ConfigClockSource>
8000f5e: 4603 mov r3, r0
8000f60: 2b00 cmp r3, #0
8000f62: d001 beq.n 8000f68 <MX_TIM2_Init+0x70>
{
Error_Handler();
8000f64: f000 fcc4 bl 80018f0 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000f68: 2300 movs r3, #0
8000f6a: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000f6c: 2300 movs r3, #0
8000f6e: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000f70: 1d3b adds r3, r7, #4
8000f72: 4619 mov r1, r3
8000f74: 4805 ldr r0, [pc, #20] @ (8000f8c <MX_TIM2_Init+0x94>)
8000f76: f005 f8c7 bl 8006108 <HAL_TIMEx_MasterConfigSynchronization>
8000f7a: 4603 mov r3, r0
8000f7c: 2b00 cmp r3, #0
8000f7e: d001 beq.n 8000f84 <MX_TIM2_Init+0x8c>
{
Error_Handler();
8000f80: f000 fcb6 bl 80018f0 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
8000f84: bf00 nop
8000f86: 3720 adds r7, #32
8000f88: 46bd mov sp, r7
8000f8a: bd80 pop {r7, pc}
8000f8c: 20000118 .word 0x20000118
8000f90: 0001f7e7 .word 0x0001f7e7
08000f94 <MX_TIM16_Init>:
* @brief TIM16 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM16_Init(void)
{
8000f94: b580 push {r7, lr}
8000f96: b094 sub sp, #80 @ 0x50
8000f98: af00 add r7, sp, #0
/* USER CODE BEGIN TIM16_Init 0 */
/* USER CODE END TIM16_Init 0 */
TIM_OC_InitTypeDef sConfigOC = {0};
8000f9a: f107 0334 add.w r3, r7, #52 @ 0x34
8000f9e: 2200 movs r2, #0
8000fa0: 601a str r2, [r3, #0]
8000fa2: 605a str r2, [r3, #4]
8000fa4: 609a str r2, [r3, #8]
8000fa6: 60da str r2, [r3, #12]
8000fa8: 611a str r2, [r3, #16]
8000faa: 615a str r2, [r3, #20]
8000fac: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8000fae: 463b mov r3, r7
8000fb0: 2234 movs r2, #52 @ 0x34
8000fb2: 2100 movs r1, #0
8000fb4: 4618 mov r0, r3
8000fb6: f007 fb0b bl 80085d0 <memset>
/* USER CODE BEGIN TIM16_Init 1 */
/* USER CODE END TIM16_Init 1 */
htim16.Instance = TIM16;
8000fba: 4b31 ldr r3, [pc, #196] @ (8001080 <MX_TIM16_Init+0xec>)
8000fbc: 4a31 ldr r2, [pc, #196] @ (8001084 <MX_TIM16_Init+0xf0>)
8000fbe: 601a str r2, [r3, #0]
htim16.Init.Prescaler = 1;
8000fc0: 4b2f ldr r3, [pc, #188] @ (8001080 <MX_TIM16_Init+0xec>)
8000fc2: 2201 movs r2, #1
8000fc4: 605a str r2, [r3, #4]
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
8000fc6: 4b2e ldr r3, [pc, #184] @ (8001080 <MX_TIM16_Init+0xec>)
8000fc8: 2200 movs r2, #0
8000fca: 609a str r2, [r3, #8]
htim16.Init.Period = 63999;
8000fcc: 4b2c ldr r3, [pc, #176] @ (8001080 <MX_TIM16_Init+0xec>)
8000fce: f64f 12ff movw r2, #63999 @ 0xf9ff
8000fd2: 60da str r2, [r3, #12]
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000fd4: 4b2a ldr r3, [pc, #168] @ (8001080 <MX_TIM16_Init+0xec>)
8000fd6: 2200 movs r2, #0
8000fd8: 611a str r2, [r3, #16]
htim16.Init.RepetitionCounter = 0;
8000fda: 4b29 ldr r3, [pc, #164] @ (8001080 <MX_TIM16_Init+0xec>)
8000fdc: 2200 movs r2, #0
8000fde: 615a str r2, [r3, #20]
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000fe0: 4b27 ldr r3, [pc, #156] @ (8001080 <MX_TIM16_Init+0xec>)
8000fe2: 2200 movs r2, #0
8000fe4: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
8000fe6: 4826 ldr r0, [pc, #152] @ (8001080 <MX_TIM16_Init+0xec>)
8000fe8: f003 fef2 bl 8004dd0 <HAL_TIM_Base_Init>
8000fec: 4603 mov r3, r0
8000fee: 2b00 cmp r3, #0
8000ff0: d001 beq.n 8000ff6 <MX_TIM16_Init+0x62>
{
Error_Handler();
8000ff2: f000 fc7d bl 80018f0 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim16) != HAL_OK)
8000ff6: 4822 ldr r0, [pc, #136] @ (8001080 <MX_TIM16_Init+0xec>)
8000ff8: f003 ff41 bl 8004e7e <HAL_TIM_PWM_Init>
8000ffc: 4603 mov r3, r0
8000ffe: 2b00 cmp r3, #0
8001000: d001 beq.n 8001006 <MX_TIM16_Init+0x72>
{
Error_Handler();
8001002: f000 fc75 bl 80018f0 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001006: 2360 movs r3, #96 @ 0x60
8001008: 637b str r3, [r7, #52] @ 0x34
sConfigOC.Pulse = 0;
800100a: 2300 movs r3, #0
800100c: 63bb str r3, [r7, #56] @ 0x38
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800100e: 2300 movs r3, #0
8001010: 63fb str r3, [r7, #60] @ 0x3c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
8001012: 2300 movs r3, #0
8001014: 643b str r3, [r7, #64] @ 0x40
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001016: 2300 movs r3, #0
8001018: 647b str r3, [r7, #68] @ 0x44
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
800101a: 2300 movs r3, #0
800101c: 64bb str r3, [r7, #72] @ 0x48
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
800101e: 2300 movs r3, #0
8001020: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_TIM_PWM_ConfigChannel(&htim16, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001022: f107 0334 add.w r3, r7, #52 @ 0x34
8001026: 2200 movs r2, #0
8001028: 4619 mov r1, r3
800102a: 4815 ldr r0, [pc, #84] @ (8001080 <MX_TIM16_Init+0xec>)
800102c: f004 f9d8 bl 80053e0 <HAL_TIM_PWM_ConfigChannel>
8001030: 4603 mov r3, r0
8001032: 2b00 cmp r3, #0
8001034: d001 beq.n 800103a <MX_TIM16_Init+0xa6>
{
Error_Handler();
8001036: f000 fc5b bl 80018f0 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800103a: 2300 movs r3, #0
800103c: 603b str r3, [r7, #0]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
800103e: 2300 movs r3, #0
8001040: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8001042: 2300 movs r3, #0
8001044: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.DeadTime = 0;
8001046: 2300 movs r3, #0
8001048: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
800104a: 2300 movs r3, #0
800104c: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
800104e: f44f 5300 mov.w r3, #8192 @ 0x2000
8001052: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakFilter = 0;
8001054: 2300 movs r3, #0
8001056: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8001058: 2300 movs r3, #0
800105a: 633b str r3, [r7, #48] @ 0x30
if (HAL_TIMEx_ConfigBreakDeadTime(&htim16, &sBreakDeadTimeConfig) != HAL_OK)
800105c: 463b mov r3, r7
800105e: 4619 mov r1, r3
8001060: 4807 ldr r0, [pc, #28] @ (8001080 <MX_TIM16_Init+0xec>)
8001062: f005 f8d3 bl 800620c <HAL_TIMEx_ConfigBreakDeadTime>
8001066: 4603 mov r3, r0
8001068: 2b00 cmp r3, #0
800106a: d001 beq.n 8001070 <MX_TIM16_Init+0xdc>
{
Error_Handler();
800106c: f000 fc40 bl 80018f0 <Error_Handler>
}
/* USER CODE BEGIN TIM16_Init 2 */
/* USER CODE END TIM16_Init 2 */
HAL_TIM_MspPostInit(&htim16);
8001070: 4803 ldr r0, [pc, #12] @ (8001080 <MX_TIM16_Init+0xec>)
8001072: f000 fd2b bl 8001acc <HAL_TIM_MspPostInit>
}
8001076: bf00 nop
8001078: 3750 adds r7, #80 @ 0x50
800107a: 46bd mov sp, r7
800107c: bd80 pop {r7, pc}
800107e: bf00 nop
8001080: 20000164 .word 0x20000164
8001084: 40014400 .word 0x40014400
08001088 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
8001088: b580 push {r7, lr}
800108a: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
800108c: 4b22 ldr r3, [pc, #136] @ (8001118 <MX_USART2_UART_Init+0x90>)
800108e: 4a23 ldr r2, [pc, #140] @ (800111c <MX_USART2_UART_Init+0x94>)
8001090: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8001092: 4b21 ldr r3, [pc, #132] @ (8001118 <MX_USART2_UART_Init+0x90>)
8001094: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8001098: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800109a: 4b1f ldr r3, [pc, #124] @ (8001118 <MX_USART2_UART_Init+0x90>)
800109c: 2200 movs r2, #0
800109e: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
80010a0: 4b1d ldr r3, [pc, #116] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010a2: 2200 movs r2, #0
80010a4: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
80010a6: 4b1c ldr r3, [pc, #112] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010a8: 2200 movs r2, #0
80010aa: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
80010ac: 4b1a ldr r3, [pc, #104] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010ae: 220c movs r2, #12
80010b0: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80010b2: 4b19 ldr r3, [pc, #100] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010b4: 2200 movs r2, #0
80010b6: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
80010b8: 4b17 ldr r3, [pc, #92] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010ba: 2200 movs r2, #0
80010bc: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80010be: 4b16 ldr r3, [pc, #88] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010c0: 2200 movs r2, #0
80010c2: 621a str r2, [r3, #32]
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
80010c4: 4b14 ldr r3, [pc, #80] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010c6: 2200 movs r2, #0
80010c8: 625a str r2, [r3, #36] @ 0x24
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80010ca: 4b13 ldr r3, [pc, #76] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010cc: 2200 movs r2, #0
80010ce: 629a str r2, [r3, #40] @ 0x28
if (HAL_UART_Init(&huart2) != HAL_OK)
80010d0: 4811 ldr r0, [pc, #68] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010d2: f005 f96d bl 80063b0 <HAL_UART_Init>
80010d6: 4603 mov r3, r0
80010d8: 2b00 cmp r3, #0
80010da: d001 beq.n 80010e0 <MX_USART2_UART_Init+0x58>
{
Error_Handler();
80010dc: f000 fc08 bl 80018f0 <Error_Handler>
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
80010e0: 2100 movs r1, #0
80010e2: 480d ldr r0, [pc, #52] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010e4: f007 f9a9 bl 800843a <HAL_UARTEx_SetTxFifoThreshold>
80010e8: 4603 mov r3, r0
80010ea: 2b00 cmp r3, #0
80010ec: d001 beq.n 80010f2 <MX_USART2_UART_Init+0x6a>
{
Error_Handler();
80010ee: f000 fbff bl 80018f0 <Error_Handler>
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
80010f2: 2100 movs r1, #0
80010f4: 4808 ldr r0, [pc, #32] @ (8001118 <MX_USART2_UART_Init+0x90>)
80010f6: f007 f9de bl 80084b6 <HAL_UARTEx_SetRxFifoThreshold>
80010fa: 4603 mov r3, r0
80010fc: 2b00 cmp r3, #0
80010fe: d001 beq.n 8001104 <MX_USART2_UART_Init+0x7c>
{
Error_Handler();
8001100: f000 fbf6 bl 80018f0 <Error_Handler>
}
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
8001104: 4804 ldr r0, [pc, #16] @ (8001118 <MX_USART2_UART_Init+0x90>)
8001106: f007 f95f bl 80083c8 <HAL_UARTEx_DisableFifoMode>
800110a: 4603 mov r3, r0
800110c: 2b00 cmp r3, #0
800110e: d001 beq.n 8001114 <MX_USART2_UART_Init+0x8c>
{
Error_Handler();
8001110: f000 fbee bl 80018f0 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8001114: bf00 nop
8001116: bd80 pop {r7, pc}
8001118: 200001b0 .word 0x200001b0
800111c: 40004400 .word 0x40004400
08001120 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001120: b580 push {r7, lr}
8001122: b088 sub sp, #32
8001124: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001126: f107 030c add.w r3, r7, #12
800112a: 2200 movs r2, #0
800112c: 601a str r2, [r3, #0]
800112e: 605a str r2, [r3, #4]
8001130: 609a str r2, [r3, #8]
8001132: 60da str r2, [r3, #12]
8001134: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001136: 4b18 ldr r3, [pc, #96] @ (8001198 <MX_GPIO_Init+0x78>)
8001138: 6cdb ldr r3, [r3, #76] @ 0x4c
800113a: 4a17 ldr r2, [pc, #92] @ (8001198 <MX_GPIO_Init+0x78>)
800113c: f043 0301 orr.w r3, r3, #1
8001140: 64d3 str r3, [r2, #76] @ 0x4c
8001142: 4b15 ldr r3, [pc, #84] @ (8001198 <MX_GPIO_Init+0x78>)
8001144: 6cdb ldr r3, [r3, #76] @ 0x4c
8001146: f003 0301 and.w r3, r3, #1
800114a: 60bb str r3, [r7, #8]
800114c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
800114e: 4b12 ldr r3, [pc, #72] @ (8001198 <MX_GPIO_Init+0x78>)
8001150: 6cdb ldr r3, [r3, #76] @ 0x4c
8001152: 4a11 ldr r2, [pc, #68] @ (8001198 <MX_GPIO_Init+0x78>)
8001154: f043 0302 orr.w r3, r3, #2
8001158: 64d3 str r3, [r2, #76] @ 0x4c
800115a: 4b0f ldr r3, [pc, #60] @ (8001198 <MX_GPIO_Init+0x78>)
800115c: 6cdb ldr r3, [r3, #76] @ 0x4c
800115e: f003 0302 and.w r3, r3, #2
8001162: 607b str r3, [r7, #4]
8001164: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8001166: 2200 movs r2, #0
8001168: f44f 7180 mov.w r1, #256 @ 0x100
800116c: 480b ldr r0, [pc, #44] @ (800119c <MX_GPIO_Init+0x7c>)
800116e: f002 fe45 bl 8003dfc <HAL_GPIO_WritePin>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
8001172: f44f 7380 mov.w r3, #256 @ 0x100
8001176: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001178: 2301 movs r3, #1
800117a: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800117c: 2300 movs r3, #0
800117e: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001180: 2300 movs r3, #0
8001182: 61bb str r3, [r7, #24]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
8001184: f107 030c add.w r3, r7, #12
8001188: 4619 mov r1, r3
800118a: 4804 ldr r0, [pc, #16] @ (800119c <MX_GPIO_Init+0x7c>)
800118c: f002 fcb4 bl 8003af8 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8001190: bf00 nop
8001192: 3720 adds r7, #32
8001194: 46bd mov sp, r7
8001196: bd80 pop {r7, pc}
8001198: 40021000 .word 0x40021000
800119c: 48000400 .word 0x48000400
080011a0 <MA_Init>:
/* USER CODE BEGIN 4 */
void MA_Init(MovingAverageFilter *filter)
{
80011a0: b480 push {r7}
80011a2: b085 sub sp, #20
80011a4: af00 add r7, sp, #0
80011a6: 6078 str r0, [r7, #4]
for (int i = 0; i < FILTER_SIZE; i++)
80011a8: 2300 movs r3, #0
80011aa: 60fb str r3, [r7, #12]
80011ac: e007 b.n 80011be <MA_Init+0x1e>
{
filter->buffer[i] = 0;
80011ae: 687b ldr r3, [r7, #4]
80011b0: 68fa ldr r2, [r7, #12]
80011b2: 2100 movs r1, #0
80011b4: f823 1012 strh.w r1, [r3, r2, lsl #1]
for (int i = 0; i < FILTER_SIZE; i++)
80011b8: 68fb ldr r3, [r7, #12]
80011ba: 3301 adds r3, #1
80011bc: 60fb str r3, [r7, #12]
80011be: 68fb ldr r3, [r7, #12]
80011c0: 2b7f cmp r3, #127 @ 0x7f
80011c2: ddf4 ble.n 80011ae <MA_Init+0xe>
}
filter->sum = 0;
80011c4: 687b ldr r3, [r7, #4]
80011c6: 2200 movs r2, #0
80011c8: f8c3 2100 str.w r2, [r3, #256] @ 0x100
filter->index = 0;
80011cc: 687b ldr r3, [r7, #4]
80011ce: 2200 movs r2, #0
80011d0: f883 2104 strb.w r2, [r3, #260] @ 0x104
}
80011d4: bf00 nop
80011d6: 3714 adds r7, #20
80011d8: 46bd mov sp, r7
80011da: f85d 7b04 ldr.w r7, [sp], #4
80011de: 4770 bx lr
080011e0 <MA_Update>:
uint16_t MA_Update(MovingAverageFilter *filter, uint16_t new_sample)
{
80011e0: b480 push {r7}
80011e2: b083 sub sp, #12
80011e4: af00 add r7, sp, #0
80011e6: 6078 str r0, [r7, #4]
80011e8: 460b mov r3, r1
80011ea: 807b strh r3, [r7, #2]
/* Subtract the oldest value from the running sum */
filter->sum -= filter->buffer[filter->index];
80011ec: 687b ldr r3, [r7, #4]
80011ee: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100
80011f2: 687a ldr r2, [r7, #4]
80011f4: f892 2104 ldrb.w r2, [r2, #260] @ 0x104
80011f8: 4611 mov r1, r2
80011fa: 687a ldr r2, [r7, #4]
80011fc: f832 2011 ldrh.w r2, [r2, r1, lsl #1]
8001200: 1a9a subs r2, r3, r2
8001202: 687b ldr r3, [r7, #4]
8001204: f8c3 2100 str.w r2, [r3, #256] @ 0x100
/* Add the new value to the running sum */
filter->sum += new_sample;
8001208: 687b ldr r3, [r7, #4]
800120a: f8d3 2100 ldr.w r2, [r3, #256] @ 0x100
800120e: 887b ldrh r3, [r7, #2]
8001210: 441a add r2, r3
8001212: 687b ldr r3, [r7, #4]
8001214: f8c3 2100 str.w r2, [r3, #256] @ 0x100
/* Store the new value in the buffer, overwriting the oldest one */
filter->buffer[filter->index] = new_sample;
8001218: 687b ldr r3, [r7, #4]
800121a: f893 3104 ldrb.w r3, [r3, #260] @ 0x104
800121e: 4619 mov r1, r3
8001220: 687b ldr r3, [r7, #4]
8001222: 887a ldrh r2, [r7, #2]
8001224: f823 2011 strh.w r2, [r3, r1, lsl #1]
/* Move the index to the next position (circular buffer wrap-around) */
filter->index++;
8001228: 687b ldr r3, [r7, #4]
800122a: f893 3104 ldrb.w r3, [r3, #260] @ 0x104
800122e: 3301 adds r3, #1
8001230: b2da uxtb r2, r3
8001232: 687b ldr r3, [r7, #4]
8001234: f883 2104 strb.w r2, [r3, #260] @ 0x104
filter->index &= (FILTER_SIZE - 1); /* Equivalent to: if (filter->index >= FILTER_SIZE) filter->index = 0; */
8001238: 687b ldr r3, [r7, #4]
800123a: f893 3104 ldrb.w r3, [r3, #260] @ 0x104
800123e: f003 037f and.w r3, r3, #127 @ 0x7f
8001242: b2da uxtb r2, r3
8001244: 687b ldr r3, [r7, #4]
8001246: f883 2104 strb.w r2, [r3, #260] @ 0x104
/* Calculate the average using bit-shifting (faster than division by power of 2) */
/* For FILTER_SIZE = 16, this is a right shift by 4 bits (sum / 16) */
/* If used 32, it would be sum >> 5 */
return (uint16_t)(filter->sum >> 7);
800124a: 687b ldr r3, [r7, #4]
800124c: f8d3 3100 ldr.w r3, [r3, #256] @ 0x100
8001250: 09db lsrs r3, r3, #7
8001252: b29b uxth r3, r3
}
8001254: 4618 mov r0, r3
8001256: 370c adds r7, #12
8001258: 46bd mov sp, r7
800125a: f85d 7b04 ldr.w r7, [sp], #4
800125e: 4770 bx lr
08001260 <get_actual_vdda>:
uint32_t get_actual_vdda(ADC_HandleTypeDef *hadc)
{
8001260: b580 push {r7, lr}
8001262: b084 sub sp, #16
8001264: af00 add r7, sp, #0
8001266: 6078 str r0, [r7, #4]
uint32_t vrefint_raw = 0;
8001268: 2300 movs r3, #0
800126a: 60fb str r3, [r7, #12]
/* Perform ADC reading of the VREFINT channel */
HAL_ADC_Start(hadc);
800126c: 6878 ldr r0, [r7, #4]
800126e: f001 f9b3 bl 80025d8 <HAL_ADC_Start>
if (HAL_ADC_PollForConversion(hadc, 10) == HAL_OK) {
8001272: 210a movs r1, #10
8001274: 6878 ldr r0, [r7, #4]
8001276: f001 fa9f bl 80027b8 <HAL_ADC_PollForConversion>
800127a: 4603 mov r3, r0
800127c: 2b00 cmp r3, #0
800127e: d103 bne.n 8001288 <get_actual_vdda+0x28>
vrefint_raw = HAL_ADC_GetValue(hadc);
8001280: 6878 ldr r0, [r7, #4]
8001282: f001 fb71 bl 8002968 <HAL_ADC_GetValue>
8001286: 60f8 str r0, [r7, #12]
}
HAL_ADC_Stop(hadc);
8001288: 6878 ldr r0, [r7, #4]
800128a: f001 fa61 bl 8002750 <HAL_ADC_Stop>
if (vrefint_raw == 0) return 0; /* Avoid division by zero */
800128e: 68fb ldr r3, [r7, #12]
8001290: 2b00 cmp r3, #0
8001292: d101 bne.n 8001298 <get_actual_vdda+0x38>
8001294: 2300 movs r3, #0
8001296: e00b b.n 80012b0 <get_actual_vdda+0x50>
/* Use the standard ST formula to calculate VDDA */
/* VDDA = VREFINT_CAL_VREF * VREFINT_CAL / VREFINT_DATA */
uint32_t vdda_mv = (VREFINT_CAL_VREF * (uint32_t)(*VREFINT_CAL_ADDR)) / vrefint_raw;
8001298: 4b07 ldr r3, [pc, #28] @ (80012b8 <get_actual_vdda+0x58>)
800129a: 881b ldrh r3, [r3, #0]
800129c: 461a mov r2, r3
800129e: f640 33b8 movw r3, #3000 @ 0xbb8
80012a2: fb03 f202 mul.w r2, r3, r2
80012a6: 68fb ldr r3, [r7, #12]
80012a8: fbb2 f3f3 udiv r3, r2, r3
80012ac: 60bb str r3, [r7, #8]
return vdda_mv;
80012ae: 68bb ldr r3, [r7, #8]
}
80012b0: 4618 mov r0, r3
80012b2: 3710 adds r7, #16
80012b4: 46bd mov sp, r7
80012b6: bd80 pop {r7, pc}
80012b8: 1fff75aa .word 0x1fff75aa
80012bc: 00000000 .word 0x00000000
080012c0 <get_divider_input_mv>:
/* Calculate original input voltage from a 22k/2.2k divider in mV */
uint32_t get_divider_input_mv(uint32_t raw_adc_value, uint32_t vdda_mv)
{
80012c0: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr}
80012c4: b086 sub sp, #24
80012c6: af00 add r7, sp, #0
80012c8: 6078 str r0, [r7, #4]
80012ca: 6039 str r1, [r7, #0]
/* Calculate the voltage at the ADC pin (Vout of the divider) */
/* Using 64-bit for intermediate to avoid overflow: (Raw * VDDA) / 4095 */
uint64_t vout_mv = ((uint64_t)raw_adc_value * vdda_mv) / 4095;
80012cc: 6879 ldr r1, [r7, #4]
80012ce: 2000 movs r0, #0
80012d0: 4688 mov r8, r1
80012d2: 4681 mov r9, r0
80012d4: 6839 ldr r1, [r7, #0]
80012d6: 2000 movs r0, #0
80012d8: 460a mov r2, r1
80012da: 4603 mov r3, r0
80012dc: fb02 f009 mul.w r0, r2, r9
80012e0: fb08 f103 mul.w r1, r8, r3
80012e4: 4401 add r1, r0
80012e6: fba8 4502 umull r4, r5, r8, r2
80012ea: 194b adds r3, r1, r5
80012ec: 461d mov r5, r3
80012ee: f640 72ff movw r2, #4095 @ 0xfff
80012f2: f04f 0300 mov.w r3, #0
80012f6: 4620 mov r0, r4
80012f8: 4629 mov r1, r5
80012fa: f7ff fa93 bl 8000824 <__aeabi_uldivmod>
80012fe: 4602 mov r2, r0
8001300: 460b mov r3, r1
8001302: e9c7 2304 strd r2, r3, [r7, #16]
/* Scale by the divider ratio: (22k + 2.2k) / 2.2k = 11 */
uint32_t vin_mv = (uint32_t)(vout_mv * 10.9);
8001306: e9d7 0104 ldrd r0, r1, [r7, #16]
800130a: f7ff fa35 bl 8000778 <__aeabi_ul2d>
800130e: a30a add r3, pc, #40 @ (adr r3, 8001338 <get_divider_input_mv+0x78>)
8001310: e9d3 2300 ldrd r2, r3, [r3]
8001314: f7fe ff80 bl 8000218 <__aeabi_dmul>
8001318: 4602 mov r2, r0
800131a: 460b mov r3, r1
800131c: 4610 mov r0, r2
800131e: 4619 mov r1, r3
8001320: f7ff fa60 bl 80007e4 <__aeabi_d2uiz>
8001324: 4603 mov r3, r0
8001326: 60fb str r3, [r7, #12]
return vin_mv;
8001328: 68fb ldr r3, [r7, #12]
}
800132a: 4618 mov r0, r3
800132c: 3718 adds r7, #24
800132e: 46bd mov sp, r7
8001330: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc}
8001334: f3af 8000 nop.w
8001338: cccccccd .word 0xcccccccd
800133c: 4025cccc .word 0x4025cccc
08001340 <voltage_conversion_task>:
/* Voltage Conversion Task */
void voltage_conversion_task(void)
{
8001340: b580 push {r7, lr}
8001342: af00 add r7, sp, #0
/* Get Vin voltage */
vin_val = get_divider_input_mv(vin_adc_val, vdd_ref);
8001344: 4b46 ldr r3, [pc, #280] @ (8001460 <voltage_conversion_task+0x120>)
8001346: 881b ldrh r3, [r3, #0]
8001348: 461a mov r2, r3
800134a: 4b46 ldr r3, [pc, #280] @ (8001464 <voltage_conversion_task+0x124>)
800134c: 681b ldr r3, [r3, #0]
800134e: 4619 mov r1, r3
8001350: 4610 mov r0, r2
8001352: f7ff ffb5 bl 80012c0 <get_divider_input_mv>
8001356: 4603 mov r3, r0
8001358: 4a43 ldr r2, [pc, #268] @ (8001468 <voltage_conversion_task+0x128>)
800135a: 6013 str r3, [r2, #0]
/* Get Vout voltage */
vout_val = get_divider_input_mv(vout_adc_val_av, vdd_ref);
800135c: 4b43 ldr r3, [pc, #268] @ (800146c <voltage_conversion_task+0x12c>)
800135e: 881b ldrh r3, [r3, #0]
8001360: 461a mov r2, r3
8001362: 4b40 ldr r3, [pc, #256] @ (8001464 <voltage_conversion_task+0x124>)
8001364: 681b ldr r3, [r3, #0]
8001366: 4619 mov r1, r3
8001368: 4610 mov r0, r2
800136a: f7ff ffa9 bl 80012c0 <get_divider_input_mv>
800136e: 4603 mov r3, r0
8001370: 4a3f ldr r2, [pc, #252] @ (8001470 <voltage_conversion_task+0x130>)
8001372: 6013 str r3, [r2, #0]
tx_len = 0x08;
8001374: 4b3f ldr r3, [pc, #252] @ (8001474 <voltage_conversion_task+0x134>)
8001376: 2208 movs r2, #8
8001378: 701a strb r2, [r3, #0]
tx_buffer[0] = IN_SYNC_BYTE_1;
800137a: 4b3f ldr r3, [pc, #252] @ (8001478 <voltage_conversion_task+0x138>)
800137c: 2241 movs r2, #65 @ 0x41
800137e: 701a strb r2, [r3, #0]
tx_buffer[1] = IN_SYNC_BYTE_2;
8001380: 4b3d ldr r3, [pc, #244] @ (8001478 <voltage_conversion_task+0x138>)
8001382: 2252 movs r2, #82 @ 0x52
8001384: 705a strb r2, [r3, #1]
tx_buffer[2] = tx_len;
8001386: 4b3b ldr r3, [pc, #236] @ (8001474 <voltage_conversion_task+0x134>)
8001388: 781a ldrb r2, [r3, #0]
800138a: 4b3b ldr r3, [pc, #236] @ (8001478 <voltage_conversion_task+0x138>)
800138c: 709a strb r2, [r3, #2]
tx_buffer[3] = (uint8_t)((vin_val >> 24) & 0xFF);
800138e: 4b36 ldr r3, [pc, #216] @ (8001468 <voltage_conversion_task+0x128>)
8001390: 681b ldr r3, [r3, #0]
8001392: 0e1b lsrs r3, r3, #24
8001394: b2da uxtb r2, r3
8001396: 4b38 ldr r3, [pc, #224] @ (8001478 <voltage_conversion_task+0x138>)
8001398: 70da strb r2, [r3, #3]
tx_buffer[4] = (uint8_t)((vin_val >> 16) & 0xFF);
800139a: 4b33 ldr r3, [pc, #204] @ (8001468 <voltage_conversion_task+0x128>)
800139c: 681b ldr r3, [r3, #0]
800139e: 0c1b lsrs r3, r3, #16
80013a0: b2da uxtb r2, r3
80013a2: 4b35 ldr r3, [pc, #212] @ (8001478 <voltage_conversion_task+0x138>)
80013a4: 711a strb r2, [r3, #4]
tx_buffer[5] = (uint8_t)((vin_val >> 8) & 0xFF);
80013a6: 4b30 ldr r3, [pc, #192] @ (8001468 <voltage_conversion_task+0x128>)
80013a8: 681b ldr r3, [r3, #0]
80013aa: 0a1b lsrs r3, r3, #8
80013ac: b2da uxtb r2, r3
80013ae: 4b32 ldr r3, [pc, #200] @ (8001478 <voltage_conversion_task+0x138>)
80013b0: 715a strb r2, [r3, #5]
tx_buffer[6] = (uint8_t)(vin_val & 0xFF);
80013b2: 4b2d ldr r3, [pc, #180] @ (8001468 <voltage_conversion_task+0x128>)
80013b4: 681b ldr r3, [r3, #0]
80013b6: b2da uxtb r2, r3
80013b8: 4b2f ldr r3, [pc, #188] @ (8001478 <voltage_conversion_task+0x138>)
80013ba: 719a strb r2, [r3, #6]
tx_buffer[7] = (uint8_t)((vout_val >> 24) & 0xFF);
80013bc: 4b2c ldr r3, [pc, #176] @ (8001470 <voltage_conversion_task+0x130>)
80013be: 681b ldr r3, [r3, #0]
80013c0: 0e1b lsrs r3, r3, #24
80013c2: b2da uxtb r2, r3
80013c4: 4b2c ldr r3, [pc, #176] @ (8001478 <voltage_conversion_task+0x138>)
80013c6: 71da strb r2, [r3, #7]
tx_buffer[8] = (uint8_t)((vout_val >> 16) & 0xFF);
80013c8: 4b29 ldr r3, [pc, #164] @ (8001470 <voltage_conversion_task+0x130>)
80013ca: 681b ldr r3, [r3, #0]
80013cc: 0c1b lsrs r3, r3, #16
80013ce: b2da uxtb r2, r3
80013d0: 4b29 ldr r3, [pc, #164] @ (8001478 <voltage_conversion_task+0x138>)
80013d2: 721a strb r2, [r3, #8]
tx_buffer[9] = (uint8_t)((vout_val >> 8) & 0xFF);
80013d4: 4b26 ldr r3, [pc, #152] @ (8001470 <voltage_conversion_task+0x130>)
80013d6: 681b ldr r3, [r3, #0]
80013d8: 0a1b lsrs r3, r3, #8
80013da: b2da uxtb r2, r3
80013dc: 4b26 ldr r3, [pc, #152] @ (8001478 <voltage_conversion_task+0x138>)
80013de: 725a strb r2, [r3, #9]
tx_buffer[10] = (uint8_t)(vout_val & 0xFF);
80013e0: 4b23 ldr r3, [pc, #140] @ (8001470 <voltage_conversion_task+0x130>)
80013e2: 681b ldr r3, [r3, #0]
80013e4: b2da uxtb r2, r3
80013e6: 4b24 ldr r3, [pc, #144] @ (8001478 <voltage_conversion_task+0x138>)
80013e8: 729a strb r2, [r3, #10]
/* Need to apply checksum to all data bits */
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
80013ea: 4b24 ldr r3, [pc, #144] @ (800147c <voltage_conversion_task+0x13c>)
80013ec: 2200 movs r2, #0
80013ee: 701a strb r2, [r3, #0]
80013f0: e011 b.n 8001416 <voltage_conversion_task+0xd6>
{
tx_checksum += tx_buffer[tx_len_counter + 3];
80013f2: 4b22 ldr r3, [pc, #136] @ (800147c <voltage_conversion_task+0x13c>)
80013f4: 781b ldrb r3, [r3, #0]
80013f6: 3303 adds r3, #3
80013f8: 4a1f ldr r2, [pc, #124] @ (8001478 <voltage_conversion_task+0x138>)
80013fa: 5cd3 ldrb r3, [r2, r3]
80013fc: 461a mov r2, r3
80013fe: 4b20 ldr r3, [pc, #128] @ (8001480 <voltage_conversion_task+0x140>)
8001400: 881b ldrh r3, [r3, #0]
8001402: 4413 add r3, r2
8001404: b29a uxth r2, r3
8001406: 4b1e ldr r3, [pc, #120] @ (8001480 <voltage_conversion_task+0x140>)
8001408: 801a strh r2, [r3, #0]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
800140a: 4b1c ldr r3, [pc, #112] @ (800147c <voltage_conversion_task+0x13c>)
800140c: 781b ldrb r3, [r3, #0]
800140e: 3301 adds r3, #1
8001410: b2da uxtb r2, r3
8001412: 4b1a ldr r3, [pc, #104] @ (800147c <voltage_conversion_task+0x13c>)
8001414: 701a strb r2, [r3, #0]
8001416: 4b19 ldr r3, [pc, #100] @ (800147c <voltage_conversion_task+0x13c>)
8001418: 781a ldrb r2, [r3, #0]
800141a: 4b16 ldr r3, [pc, #88] @ (8001474 <voltage_conversion_task+0x134>)
800141c: 781b ldrb r3, [r3, #0]
800141e: 429a cmp r2, r3
8001420: d3e7 bcc.n 80013f2 <voltage_conversion_task+0xb2>
}
tx_checksum = ~tx_checksum;
8001422: 4b17 ldr r3, [pc, #92] @ (8001480 <voltage_conversion_task+0x140>)
8001424: 881b ldrh r3, [r3, #0]
8001426: 43db mvns r3, r3
8001428: b29a uxth r2, r3
800142a: 4b15 ldr r3, [pc, #84] @ (8001480 <voltage_conversion_task+0x140>)
800142c: 801a strh r2, [r3, #0]
tx_buffer[11] = (uint8_t)((tx_checksum >> 8) & 0xFF);
800142e: 4b14 ldr r3, [pc, #80] @ (8001480 <voltage_conversion_task+0x140>)
8001430: 881b ldrh r3, [r3, #0]
8001432: 0a1b lsrs r3, r3, #8
8001434: b29b uxth r3, r3
8001436: b2da uxtb r2, r3
8001438: 4b0f ldr r3, [pc, #60] @ (8001478 <voltage_conversion_task+0x138>)
800143a: 72da strb r2, [r3, #11]
tx_buffer[12] = (uint8_t)(tx_checksum & 0xFF);
800143c: 4b10 ldr r3, [pc, #64] @ (8001480 <voltage_conversion_task+0x140>)
800143e: 881b ldrh r3, [r3, #0]
8001440: b2da uxtb r2, r3
8001442: 4b0d ldr r3, [pc, #52] @ (8001478 <voltage_conversion_task+0x138>)
8001444: 731a strb r2, [r3, #12]
tx_len = 0x0D;
8001446: 4b0b ldr r3, [pc, #44] @ (8001474 <voltage_conversion_task+0x134>)
8001448: 220d movs r2, #13
800144a: 701a strb r2, [r3, #0]
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
800144c: 4b09 ldr r3, [pc, #36] @ (8001474 <voltage_conversion_task+0x134>)
800144e: 781b ldrb r3, [r3, #0]
8001450: 461a mov r2, r3
8001452: 2364 movs r3, #100 @ 0x64
8001454: 4908 ldr r1, [pc, #32] @ (8001478 <voltage_conversion_task+0x138>)
8001456: 480b ldr r0, [pc, #44] @ (8001484 <voltage_conversion_task+0x144>)
8001458: f004 fffa bl 8006450 <HAL_UART_Transmit>
}
800145c: bf00 nop
800145e: bd80 pop {r7, pc}
8001460: 2000029e .word 0x2000029e
8001464: 200002a4 .word 0x200002a4
8001468: 200002a8 .word 0x200002a8
800146c: 200002a2 .word 0x200002a2
8001470: 200002ac .word 0x200002ac
8001474: 2000028c .word 0x2000028c
8001478: 2000026c .word 0x2000026c
800147c: 2000028d .word 0x2000028d
8001480: 20000294 .word 0x20000294
8001484: 200001b0 .word 0x200001b0
08001488 <voltage_conversion_task_no_tx>:
/* Voltage Conversion Task with No UART Tx */
void voltage_conversion_task_no_tx(void)
{
8001488: b580 push {r7, lr}
800148a: af00 add r7, sp, #0
/* Get Vout voltage */
vout_val = get_divider_input_mv(vout_adc_val_av, vdd_ref);
800148c: 4b06 ldr r3, [pc, #24] @ (80014a8 <voltage_conversion_task_no_tx+0x20>)
800148e: 881b ldrh r3, [r3, #0]
8001490: 461a mov r2, r3
8001492: 4b06 ldr r3, [pc, #24] @ (80014ac <voltage_conversion_task_no_tx+0x24>)
8001494: 681b ldr r3, [r3, #0]
8001496: 4619 mov r1, r3
8001498: 4610 mov r0, r2
800149a: f7ff ff11 bl 80012c0 <get_divider_input_mv>
800149e: 4603 mov r3, r0
80014a0: 4a03 ldr r2, [pc, #12] @ (80014b0 <voltage_conversion_task_no_tx+0x28>)
80014a2: 6013 str r3, [r2, #0]
}
80014a4: bf00 nop
80014a6: bd80 pop {r7, pc}
80014a8: 200002a2 .word 0x200002a2
80014ac: 200002a4 .word 0x200002a4
80014b0: 200002ac .word 0x200002ac
080014b4 <serial_number_task>:
void serial_number_task (void)
{
80014b4: b580 push {r7, lr}
80014b6: af00 add r7, sp, #0
tx_len = 0x13;
80014b8: 4b42 ldr r3, [pc, #264] @ (80015c4 <serial_number_task+0x110>)
80014ba: 2213 movs r2, #19
80014bc: 701a strb r2, [r3, #0]
tx_buffer[0] = IN_SYNC_BYTE_1;
80014be: 4b42 ldr r3, [pc, #264] @ (80015c8 <serial_number_task+0x114>)
80014c0: 2241 movs r2, #65 @ 0x41
80014c2: 701a strb r2, [r3, #0]
tx_buffer[1] = IN_SYNC_BYTE_2;
80014c4: 4b40 ldr r3, [pc, #256] @ (80015c8 <serial_number_task+0x114>)
80014c6: 2252 movs r2, #82 @ 0x52
80014c8: 705a strb r2, [r3, #1]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
80014ca: 4b40 ldr r3, [pc, #256] @ (80015cc <serial_number_task+0x118>)
80014cc: 2200 movs r2, #0
80014ce: 701a strb r2, [r3, #0]
80014d0: e00f b.n 80014f2 <serial_number_task+0x3e>
{
tx_buffer[tx_len_counter + 3] = serial_number[tx_len_counter];
80014d2: 4b3e ldr r3, [pc, #248] @ (80015cc <serial_number_task+0x118>)
80014d4: 781b ldrb r3, [r3, #0]
80014d6: 4619 mov r1, r3
80014d8: 4b3c ldr r3, [pc, #240] @ (80015cc <serial_number_task+0x118>)
80014da: 781b ldrb r3, [r3, #0]
80014dc: 3303 adds r3, #3
80014de: 4a3c ldr r2, [pc, #240] @ (80015d0 <serial_number_task+0x11c>)
80014e0: 5c51 ldrb r1, [r2, r1]
80014e2: 4a39 ldr r2, [pc, #228] @ (80015c8 <serial_number_task+0x114>)
80014e4: 54d1 strb r1, [r2, r3]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
80014e6: 4b39 ldr r3, [pc, #228] @ (80015cc <serial_number_task+0x118>)
80014e8: 781b ldrb r3, [r3, #0]
80014ea: 3301 adds r3, #1
80014ec: b2da uxtb r2, r3
80014ee: 4b37 ldr r3, [pc, #220] @ (80015cc <serial_number_task+0x118>)
80014f0: 701a strb r2, [r3, #0]
80014f2: 4b36 ldr r3, [pc, #216] @ (80015cc <serial_number_task+0x118>)
80014f4: 781a ldrb r2, [r3, #0]
80014f6: 4b33 ldr r3, [pc, #204] @ (80015c4 <serial_number_task+0x110>)
80014f8: 781b ldrb r3, [r3, #0]
80014fa: 429a cmp r2, r3
80014fc: d3e9 bcc.n 80014d2 <serial_number_task+0x1e>
}
tx_buffer[tx_len + 3] = 0x3A;
80014fe: 4b31 ldr r3, [pc, #196] @ (80015c4 <serial_number_task+0x110>)
8001500: 781b ldrb r3, [r3, #0]
8001502: 3303 adds r3, #3
8001504: 4a30 ldr r2, [pc, #192] @ (80015c8 <serial_number_task+0x114>)
8001506: 213a movs r1, #58 @ 0x3a
8001508: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 4] = fw_rev_h + 0x30;
800150a: 4b32 ldr r3, [pc, #200] @ (80015d4 <serial_number_task+0x120>)
800150c: 781a ldrb r2, [r3, #0]
800150e: 4b2d ldr r3, [pc, #180] @ (80015c4 <serial_number_task+0x110>)
8001510: 781b ldrb r3, [r3, #0]
8001512: 3304 adds r3, #4
8001514: 3230 adds r2, #48 @ 0x30
8001516: b2d1 uxtb r1, r2
8001518: 4a2b ldr r2, [pc, #172] @ (80015c8 <serial_number_task+0x114>)
800151a: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 5] = fw_rev_l + 0x30;
800151c: 4b2e ldr r3, [pc, #184] @ (80015d8 <serial_number_task+0x124>)
800151e: 781a ldrb r2, [r3, #0]
8001520: 4b28 ldr r3, [pc, #160] @ (80015c4 <serial_number_task+0x110>)
8001522: 781b ldrb r3, [r3, #0]
8001524: 3305 adds r3, #5
8001526: 3230 adds r2, #48 @ 0x30
8001528: b2d1 uxtb r1, r2
800152a: 4a27 ldr r2, [pc, #156] @ (80015c8 <serial_number_task+0x114>)
800152c: 54d1 strb r1, [r2, r3]
tx_len = 0x16;
800152e: 4b25 ldr r3, [pc, #148] @ (80015c4 <serial_number_task+0x110>)
8001530: 2216 movs r2, #22
8001532: 701a strb r2, [r3, #0]
tx_buffer[2] = tx_len;
8001534: 4b23 ldr r3, [pc, #140] @ (80015c4 <serial_number_task+0x110>)
8001536: 781a ldrb r2, [r3, #0]
8001538: 4b23 ldr r3, [pc, #140] @ (80015c8 <serial_number_task+0x114>)
800153a: 709a strb r2, [r3, #2]
tx_checksum = 0x00;
800153c: 4b27 ldr r3, [pc, #156] @ (80015dc <serial_number_task+0x128>)
800153e: 2200 movs r2, #0
8001540: 801a strh r2, [r3, #0]
/* Need to apply checksum to all data bits */
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8001542: 4b22 ldr r3, [pc, #136] @ (80015cc <serial_number_task+0x118>)
8001544: 2200 movs r2, #0
8001546: 701a strb r2, [r3, #0]
8001548: e011 b.n 800156e <serial_number_task+0xba>
{
tx_checksum += tx_buffer[tx_len_counter + 3];
800154a: 4b20 ldr r3, [pc, #128] @ (80015cc <serial_number_task+0x118>)
800154c: 781b ldrb r3, [r3, #0]
800154e: 3303 adds r3, #3
8001550: 4a1d ldr r2, [pc, #116] @ (80015c8 <serial_number_task+0x114>)
8001552: 5cd3 ldrb r3, [r2, r3]
8001554: 461a mov r2, r3
8001556: 4b21 ldr r3, [pc, #132] @ (80015dc <serial_number_task+0x128>)
8001558: 881b ldrh r3, [r3, #0]
800155a: 4413 add r3, r2
800155c: b29a uxth r2, r3
800155e: 4b1f ldr r3, [pc, #124] @ (80015dc <serial_number_task+0x128>)
8001560: 801a strh r2, [r3, #0]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8001562: 4b1a ldr r3, [pc, #104] @ (80015cc <serial_number_task+0x118>)
8001564: 781b ldrb r3, [r3, #0]
8001566: 3301 adds r3, #1
8001568: b2da uxtb r2, r3
800156a: 4b18 ldr r3, [pc, #96] @ (80015cc <serial_number_task+0x118>)
800156c: 701a strb r2, [r3, #0]
800156e: 4b17 ldr r3, [pc, #92] @ (80015cc <serial_number_task+0x118>)
8001570: 781a ldrb r2, [r3, #0]
8001572: 4b14 ldr r3, [pc, #80] @ (80015c4 <serial_number_task+0x110>)
8001574: 781b ldrb r3, [r3, #0]
8001576: 429a cmp r2, r3
8001578: d3e7 bcc.n 800154a <serial_number_task+0x96>
}
tx_checksum = ~tx_checksum;
800157a: 4b18 ldr r3, [pc, #96] @ (80015dc <serial_number_task+0x128>)
800157c: 881b ldrh r3, [r3, #0]
800157e: 43db mvns r3, r3
8001580: b29a uxth r2, r3
8001582: 4b16 ldr r3, [pc, #88] @ (80015dc <serial_number_task+0x128>)
8001584: 801a strh r2, [r3, #0]
tx_buffer[tx_len + 3] = (uint8_t)((tx_checksum >> 8) & 0xFF);
8001586: 4b15 ldr r3, [pc, #84] @ (80015dc <serial_number_task+0x128>)
8001588: 881b ldrh r3, [r3, #0]
800158a: 0a1b lsrs r3, r3, #8
800158c: b29a uxth r2, r3
800158e: 4b0d ldr r3, [pc, #52] @ (80015c4 <serial_number_task+0x110>)
8001590: 781b ldrb r3, [r3, #0]
8001592: 3303 adds r3, #3
8001594: b2d1 uxtb r1, r2
8001596: 4a0c ldr r2, [pc, #48] @ (80015c8 <serial_number_task+0x114>)
8001598: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 4] = (uint8_t)(tx_checksum & 0xFF);
800159a: 4b10 ldr r3, [pc, #64] @ (80015dc <serial_number_task+0x128>)
800159c: 881a ldrh r2, [r3, #0]
800159e: 4b09 ldr r3, [pc, #36] @ (80015c4 <serial_number_task+0x110>)
80015a0: 781b ldrb r3, [r3, #0]
80015a2: 3304 adds r3, #4
80015a4: b2d1 uxtb r1, r2
80015a6: 4a08 ldr r2, [pc, #32] @ (80015c8 <serial_number_task+0x114>)
80015a8: 54d1 strb r1, [r2, r3]
tx_len = 0x1B;
80015aa: 4b06 ldr r3, [pc, #24] @ (80015c4 <serial_number_task+0x110>)
80015ac: 221b movs r2, #27
80015ae: 701a strb r2, [r3, #0]
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
80015b0: 4b04 ldr r3, [pc, #16] @ (80015c4 <serial_number_task+0x110>)
80015b2: 781b ldrb r3, [r3, #0]
80015b4: 461a mov r2, r3
80015b6: 2364 movs r3, #100 @ 0x64
80015b8: 4903 ldr r1, [pc, #12] @ (80015c8 <serial_number_task+0x114>)
80015ba: 4809 ldr r0, [pc, #36] @ (80015e0 <serial_number_task+0x12c>)
80015bc: f004 ff48 bl 8006450 <HAL_UART_Transmit>
}
80015c0: bf00 nop
80015c2: bd80 pop {r7, pc}
80015c4: 2000028c .word 0x2000028c
80015c8: 2000026c .word 0x2000026c
80015cc: 2000028d .word 0x2000028d
80015d0: 20000004 .word 0x20000004
80015d4: 20000244 .word 0x20000244
80015d8: 20000000 .word 0x20000000
80015dc: 20000294 .word 0x20000294
80015e0: 200001b0 .word 0x200001b0
080015e4 <adc_task>:
/* ADC task */
void adc_task (void)
{
80015e4: b580 push {r7, lr}
80015e6: af00 add r7, sp, #0
HAL_ADC_Start(&hadc2);
80015e8: 4811 ldr r0, [pc, #68] @ (8001630 <adc_task+0x4c>)
80015ea: f000 fff5 bl 80025d8 <HAL_ADC_Start>
HAL_ADC_PollForConversion(&hadc2, 500);
80015ee: f44f 71fa mov.w r1, #500 @ 0x1f4
80015f2: 480f ldr r0, [pc, #60] @ (8001630 <adc_task+0x4c>)
80015f4: f001 f8e0 bl 80027b8 <HAL_ADC_PollForConversion>
vout_adc_val = HAL_ADC_GetValue(&hadc2);
80015f8: 480d ldr r0, [pc, #52] @ (8001630 <adc_task+0x4c>)
80015fa: f001 f9b5 bl 8002968 <HAL_ADC_GetValue>
80015fe: 4603 mov r3, r0
8001600: b29a uxth r2, r3
8001602: 4b0c ldr r3, [pc, #48] @ (8001634 <adc_task+0x50>)
8001604: 801a strh r2, [r3, #0]
HAL_ADC_Start(&hadc2);
8001606: 480a ldr r0, [pc, #40] @ (8001630 <adc_task+0x4c>)
8001608: f000 ffe6 bl 80025d8 <HAL_ADC_Start>
HAL_ADC_PollForConversion(&hadc2, 500);
800160c: f44f 71fa mov.w r1, #500 @ 0x1f4
8001610: 4807 ldr r0, [pc, #28] @ (8001630 <adc_task+0x4c>)
8001612: f001 f8d1 bl 80027b8 <HAL_ADC_PollForConversion>
vin_adc_val = HAL_ADC_GetValue(&hadc2);
8001616: 4806 ldr r0, [pc, #24] @ (8001630 <adc_task+0x4c>)
8001618: f001 f9a6 bl 8002968 <HAL_ADC_GetValue>
800161c: 4603 mov r3, r0
800161e: b29a uxth r2, r3
8001620: 4b05 ldr r3, [pc, #20] @ (8001638 <adc_task+0x54>)
8001622: 801a strh r2, [r3, #0]
HAL_ADC_Stop(&hadc2);
8001624: 4802 ldr r0, [pc, #8] @ (8001630 <adc_task+0x4c>)
8001626: f001 f893 bl 8002750 <HAL_ADC_Stop>
}
800162a: bf00 nop
800162c: bd80 pop {r7, pc}
800162e: bf00 nop
8001630: 200000ac .word 0x200000ac
8001634: 200002a0 .word 0x200002a0
8001638: 2000029e .word 0x2000029e
0800163c <power_switch>:
/* Power switch function */
void power_switch (uint8_t state)
{
800163c: b580 push {r7, lr}
800163e: b082 sub sp, #8
8001640: af00 add r7, sp, #0
8001642: 4603 mov r3, r0
8001644: 71fb strb r3, [r7, #7]
if (state == 1)
8001646: 79fb ldrb r3, [r7, #7]
8001648: 2b01 cmp r3, #1
800164a: d109 bne.n 8001660 <power_switch+0x24>
{
vset_task_flag = 0xFF;
800164c: 4b0d ldr r3, [pc, #52] @ (8001684 <power_switch+0x48>)
800164e: 22ff movs r2, #255 @ 0xff
8001650: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);
8001652: 2201 movs r2, #1
8001654: f44f 7180 mov.w r1, #256 @ 0x100
8001658: 480b ldr r0, [pc, #44] @ (8001688 <power_switch+0x4c>)
800165a: f002 fbcf bl 8003dfc <HAL_GPIO_WritePin>
{
vset_task_flag = 0x00;
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
}
}
800165e: e00c b.n 800167a <power_switch+0x3e>
vset_task_flag = 0x00;
8001660: 4b08 ldr r3, [pc, #32] @ (8001684 <power_switch+0x48>)
8001662: 2200 movs r2, #0
8001664: 701a strb r2, [r3, #0]
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
8001666: 4b09 ldr r3, [pc, #36] @ (800168c <power_switch+0x50>)
8001668: 681b ldr r3, [r3, #0]
800166a: 2200 movs r2, #0
800166c: 635a str r2, [r3, #52] @ 0x34
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
800166e: 2200 movs r2, #0
8001670: f44f 7180 mov.w r1, #256 @ 0x100
8001674: 4804 ldr r0, [pc, #16] @ (8001688 <power_switch+0x4c>)
8001676: f002 fbc1 bl 8003dfc <HAL_GPIO_WritePin>
}
800167a: bf00 nop
800167c: 3708 adds r7, #8
800167e: 46bd mov sp, r7
8001680: bd80 pop {r7, pc}
8001682: bf00 nop
8001684: 200002b4 .word 0x200002b4
8001688: 48000400 .word 0x48000400
800168c: 20000164 .word 0x20000164
08001690 <HAL_UART_TxCpltCallback>:
/* UART Tx callback */
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8001690: b480 push {r7}
8001692: b083 sub sp, #12
8001694: af00 add r7, sp, #0
8001696: 6078 str r0, [r7, #4]
/* Do nothing here for now */
}
8001698: bf00 nop
800169a: 370c adds r7, #12
800169c: 46bd mov sp, r7
800169e: f85d 7b04 ldr.w r7, [sp], #4
80016a2: 4770 bx lr
080016a4 <HAL_UART_RxCpltCallback>:
/* UART Rx callback */
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
80016a4: b580 push {r7, lr}
80016a6: b082 sub sp, #8
80016a8: af00 add r7, sp, #0
80016aa: 6078 str r0, [r7, #4]
/* If data received on UART */
if(huart->Instance==USART2)
80016ac: 687b ldr r3, [r7, #4]
80016ae: 681b ldr r3, [r3, #0]
80016b0: 4a7e ldr r2, [pc, #504] @ (80018ac <HAL_UART_RxCpltCallback+0x208>)
80016b2: 4293 cmp r3, r2
80016b4: f040 80f6 bne.w 80018a4 <HAL_UART_RxCpltCallback+0x200>
{
/* Act on received data */
switch (rx_counter)
80016b8: 4b7d ldr r3, [pc, #500] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
80016ba: 781b ldrb r3, [r3, #0]
80016bc: 2b05 cmp r3, #5
80016be: f200 80e7 bhi.w 8001890 <HAL_UART_RxCpltCallback+0x1ec>
80016c2: a201 add r2, pc, #4 @ (adr r2, 80016c8 <HAL_UART_RxCpltCallback+0x24>)
80016c4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80016c8: 080016e1 .word 0x080016e1
80016cc: 080016f9 .word 0x080016f9
80016d0: 08001727 .word 0x08001727
80016d4: 08001743 .word 0x08001743
80016d8: 0800177f .word 0x0800177f
80016dc: 08001795 .word 0x08001795
{
case 0x00:
/* Check to see if first sync byte has been received */
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
80016e0: 4b74 ldr r3, [pc, #464] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
80016e2: 781b ldrb r3, [r3, #0]
80016e4: 2b41 cmp r3, #65 @ 0x41
80016e6: f040 80d5 bne.w 8001894 <HAL_UART_RxCpltCallback+0x1f0>
{
/* Got it, so now wait for the second sync byte */
rx_counter++;
80016ea: 4b71 ldr r3, [pc, #452] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
80016ec: 781b ldrb r3, [r3, #0]
80016ee: 3301 adds r3, #1
80016f0: b2da uxtb r2, r3
80016f2: 4b6f ldr r3, [pc, #444] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
80016f4: 701a strb r2, [r3, #0]
}
break;
80016f6: e0cd b.n 8001894 <HAL_UART_RxCpltCallback+0x1f0>
case 0x01:
/* Check to see if second sync byte has been received */
if (rx_hold_buffer[0] == IN_SYNC_BYTE_2)
80016f8: 4b6e ldr r3, [pc, #440] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
80016fa: 781b ldrb r3, [r3, #0]
80016fc: 2b52 cmp r3, #82 @ 0x52
80016fe: d106 bne.n 800170e <HAL_UART_RxCpltCallback+0x6a>
{
/* Got it, so now wait for the data byte */
rx_counter++;
8001700: 4b6b ldr r3, [pc, #428] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001702: 781b ldrb r3, [r3, #0]
8001704: 3301 adds r3, #1
8001706: b2da uxtb r2, r3
8001708: 4b69 ldr r3, [pc, #420] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
800170a: 701a strb r2, [r3, #0]
{
rx_counter = 0x00;
}
}
break;
800170c: e0c5 b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
800170e: 4b69 ldr r3, [pc, #420] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
8001710: 781b ldrb r3, [r3, #0]
8001712: 2b41 cmp r3, #65 @ 0x41
8001714: d103 bne.n 800171e <HAL_UART_RxCpltCallback+0x7a>
rx_counter = 0x01;
8001716: 4b66 ldr r3, [pc, #408] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001718: 2201 movs r2, #1
800171a: 701a strb r2, [r3, #0]
break;
800171c: e0bd b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
rx_counter = 0x00;
800171e: 4b64 ldr r3, [pc, #400] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001720: 2200 movs r2, #0
8001722: 701a strb r2, [r3, #0]
break;
8001724: e0b9 b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
case 0x02:
/* Get rx length and reset counter */
rx_len = rx_hold_buffer[0];
8001726: 4b63 ldr r3, [pc, #396] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
8001728: 781a ldrb r2, [r3, #0]
800172a: 4b63 ldr r3, [pc, #396] @ (80018b8 <HAL_UART_RxCpltCallback+0x214>)
800172c: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
800172e: 4b63 ldr r3, [pc, #396] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
8001730: 2200 movs r2, #0
8001732: 701a strb r2, [r3, #0]
rx_counter++;
8001734: 4b5e ldr r3, [pc, #376] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001736: 781b ldrb r3, [r3, #0]
8001738: 3301 adds r3, #1
800173a: b2da uxtb r2, r3
800173c: 4b5c ldr r3, [pc, #368] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
800173e: 701a strb r2, [r3, #0]
break;
8001740: e0ab b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
case 0x03:
/* Store entire length of Data bytes */
/* Increase count */
rx_len_counter++;
8001742: 4b5e ldr r3, [pc, #376] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
8001744: 781b ldrb r3, [r3, #0]
8001746: 3301 adds r3, #1
8001748: b2da uxtb r2, r3
800174a: 4b5c ldr r3, [pc, #368] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
800174c: 701a strb r2, [r3, #0]
/* Store data */
rx_buffer[rx_len_counter - 1] = rx_hold_buffer[0];
800174e: 4b5b ldr r3, [pc, #364] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
8001750: 781b ldrb r3, [r3, #0]
8001752: 3b01 subs r3, #1
8001754: 4a57 ldr r2, [pc, #348] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
8001756: 7811 ldrb r1, [r2, #0]
8001758: 4a59 ldr r2, [pc, #356] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
800175a: 54d1 strb r1, [r2, r3]
/* Check to see if we have all the expected data bytes */
/* If so, then move on the CRC */
if (rx_len_counter == rx_len)
800175c: 4b57 ldr r3, [pc, #348] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
800175e: 781a ldrb r2, [r3, #0]
8001760: 4b55 ldr r3, [pc, #340] @ (80018b8 <HAL_UART_RxCpltCallback+0x214>)
8001762: 781b ldrb r3, [r3, #0]
8001764: 429a cmp r2, r3
8001766: f040 8097 bne.w 8001898 <HAL_UART_RxCpltCallback+0x1f4>
{
rx_counter++;
800176a: 4b51 ldr r3, [pc, #324] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
800176c: 781b ldrb r3, [r3, #0]
800176e: 3301 adds r3, #1
8001770: b2da uxtb r2, r3
8001772: 4b4f ldr r3, [pc, #316] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001774: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
8001776: 4b51 ldr r3, [pc, #324] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
8001778: 2200 movs r2, #0
800177a: 701a strb r2, [r3, #0]
}
break;
800177c: e08c b.n 8001898 <HAL_UART_RxCpltCallback+0x1f4>
case 0x04:
/* Store Rx checksum byte #1 */
rx_checksum_hold_1 = rx_hold_buffer[0];
800177e: 4b4d ldr r3, [pc, #308] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
8001780: 781a ldrb r2, [r3, #0]
8001782: 4b50 ldr r3, [pc, #320] @ (80018c4 <HAL_UART_RxCpltCallback+0x220>)
8001784: 701a strb r2, [r3, #0]
rx_counter++;
8001786: 4b4a ldr r3, [pc, #296] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001788: 781b ldrb r3, [r3, #0]
800178a: 3301 adds r3, #1
800178c: b2da uxtb r2, r3
800178e: 4b48 ldr r3, [pc, #288] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001790: 701a strb r2, [r3, #0]
break;
8001792: e082 b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
case 0x05:
/* Store Rx checksum byte #2, reset and calculate checksum */
rx_checksum_hold_2 = rx_hold_buffer[0];
8001794: 4b47 ldr r3, [pc, #284] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
8001796: 781a ldrb r2, [r3, #0]
8001798: 4b4b ldr r3, [pc, #300] @ (80018c8 <HAL_UART_RxCpltCallback+0x224>)
800179a: 701a strb r2, [r3, #0]
rx_checksum_hold = (rx_checksum_hold_1 << 8) | rx_checksum_hold_2;
800179c: 4b49 ldr r3, [pc, #292] @ (80018c4 <HAL_UART_RxCpltCallback+0x220>)
800179e: 781b ldrb r3, [r3, #0]
80017a0: b21b sxth r3, r3
80017a2: 021b lsls r3, r3, #8
80017a4: b21a sxth r2, r3
80017a6: 4b48 ldr r3, [pc, #288] @ (80018c8 <HAL_UART_RxCpltCallback+0x224>)
80017a8: 781b ldrb r3, [r3, #0]
80017aa: b21b sxth r3, r3
80017ac: 4313 orrs r3, r2
80017ae: b21b sxth r3, r3
80017b0: b29a uxth r2, r3
80017b2: 4b46 ldr r3, [pc, #280] @ (80018cc <HAL_UART_RxCpltCallback+0x228>)
80017b4: 801a strh r2, [r3, #0]
rx_checksum = 0;
80017b6: 4b46 ldr r3, [pc, #280] @ (80018d0 <HAL_UART_RxCpltCallback+0x22c>)
80017b8: 2200 movs r2, #0
80017ba: 801a strh r2, [r3, #0]
/* Need to apply to all data bits */
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
80017bc: 4b3f ldr r3, [pc, #252] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
80017be: 2200 movs r2, #0
80017c0: 701a strb r2, [r3, #0]
80017c2: e011 b.n 80017e8 <HAL_UART_RxCpltCallback+0x144>
{
rx_checksum += rx_buffer[rx_len_counter];
80017c4: 4b3d ldr r3, [pc, #244] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
80017c6: 781b ldrb r3, [r3, #0]
80017c8: 461a mov r2, r3
80017ca: 4b3d ldr r3, [pc, #244] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
80017cc: 5c9b ldrb r3, [r3, r2]
80017ce: 461a mov r2, r3
80017d0: 4b3f ldr r3, [pc, #252] @ (80018d0 <HAL_UART_RxCpltCallback+0x22c>)
80017d2: 881b ldrh r3, [r3, #0]
80017d4: 4413 add r3, r2
80017d6: b29a uxth r2, r3
80017d8: 4b3d ldr r3, [pc, #244] @ (80018d0 <HAL_UART_RxCpltCallback+0x22c>)
80017da: 801a strh r2, [r3, #0]
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
80017dc: 4b37 ldr r3, [pc, #220] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
80017de: 781b ldrb r3, [r3, #0]
80017e0: 3301 adds r3, #1
80017e2: b2da uxtb r2, r3
80017e4: 4b35 ldr r3, [pc, #212] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
80017e6: 701a strb r2, [r3, #0]
80017e8: 4b34 ldr r3, [pc, #208] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
80017ea: 781a ldrb r2, [r3, #0]
80017ec: 4b32 ldr r3, [pc, #200] @ (80018b8 <HAL_UART_RxCpltCallback+0x214>)
80017ee: 781b ldrb r3, [r3, #0]
80017f0: 429a cmp r2, r3
80017f2: d3e7 bcc.n 80017c4 <HAL_UART_RxCpltCallback+0x120>
}
rx_len = 0x00;
80017f4: 4b30 ldr r3, [pc, #192] @ (80018b8 <HAL_UART_RxCpltCallback+0x214>)
80017f6: 2200 movs r2, #0
80017f8: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
80017fa: 4b30 ldr r3, [pc, #192] @ (80018bc <HAL_UART_RxCpltCallback+0x218>)
80017fc: 2200 movs r2, #0
80017fe: 701a strb r2, [r3, #0]
rx_checksum = ~rx_checksum;
8001800: 4b33 ldr r3, [pc, #204] @ (80018d0 <HAL_UART_RxCpltCallback+0x22c>)
8001802: 881b ldrh r3, [r3, #0]
8001804: 43db mvns r3, r3
8001806: b29a uxth r2, r3
8001808: 4b31 ldr r3, [pc, #196] @ (80018d0 <HAL_UART_RxCpltCallback+0x22c>)
800180a: 801a strh r2, [r3, #0]
/* If checksum calculated equals the received checksum of packet then we got a good packet */
if (rx_checksum == rx_checksum_hold)
800180c: 4b30 ldr r3, [pc, #192] @ (80018d0 <HAL_UART_RxCpltCallback+0x22c>)
800180e: 881a ldrh r2, [r3, #0]
8001810: 4b2e ldr r3, [pc, #184] @ (80018cc <HAL_UART_RxCpltCallback+0x228>)
8001812: 881b ldrh r3, [r3, #0]
8001814: 429a cmp r2, r3
8001816: d135 bne.n 8001884 <HAL_UART_RxCpltCallback+0x1e0>
{
/* Rx is finished, so reset count to wait for another first sync byte (also act on command/data)*/
rx_counter = 0x00;
8001818: 4b25 ldr r3, [pc, #148] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
800181a: 2200 movs r2, #0
800181c: 701a strb r2, [r3, #0]
command = rx_buffer[0];
800181e: 4b28 ldr r3, [pc, #160] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
8001820: 781a ldrb r2, [r3, #0]
8001822: 4b2c ldr r3, [pc, #176] @ (80018d4 <HAL_UART_RxCpltCallback+0x230>)
8001824: 701a strb r2, [r3, #0]
switch (command)
8001826: 4b2b ldr r3, [pc, #172] @ (80018d4 <HAL_UART_RxCpltCallback+0x230>)
8001828: 781b ldrb r3, [r3, #0]
800182a: 2b56 cmp r3, #86 @ 0x56
800182c: d022 beq.n 8001874 <HAL_UART_RxCpltCallback+0x1d0>
800182e: 2b56 cmp r3, #86 @ 0x56
8001830: dc2c bgt.n 800188c <HAL_UART_RxCpltCallback+0x1e8>
8001832: 2b49 cmp r3, #73 @ 0x49
8001834: d022 beq.n 800187c <HAL_UART_RxCpltCallback+0x1d8>
8001836: 2b53 cmp r3, #83 @ 0x53
8001838: d128 bne.n 800188c <HAL_UART_RxCpltCallback+0x1e8>
{
/* 'S' - Set power output state */
case 0x53:
power_state_value = rx_buffer[1];
800183a: 4b21 ldr r3, [pc, #132] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
800183c: 785a ldrb r2, [r3, #1]
800183e: 4b26 ldr r3, [pc, #152] @ (80018d8 <HAL_UART_RxCpltCallback+0x234>)
8001840: 701a strb r2, [r3, #0]
v_target = ((uint32_t)rx_buffer[2] << 24) | ((uint32_t)rx_buffer[3] << 16) | ((uint32_t)rx_buffer[4] << 8) | ((uint32_t)rx_buffer[5]);
8001842: 4b1f ldr r3, [pc, #124] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
8001844: 789b ldrb r3, [r3, #2]
8001846: 061a lsls r2, r3, #24
8001848: 4b1d ldr r3, [pc, #116] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
800184a: 78db ldrb r3, [r3, #3]
800184c: 041b lsls r3, r3, #16
800184e: 431a orrs r2, r3
8001850: 4b1b ldr r3, [pc, #108] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
8001852: 791b ldrb r3, [r3, #4]
8001854: 021b lsls r3, r3, #8
8001856: 4313 orrs r3, r2
8001858: 4a19 ldr r2, [pc, #100] @ (80018c0 <HAL_UART_RxCpltCallback+0x21c>)
800185a: 7952 ldrb r2, [r2, #5]
800185c: 4313 orrs r3, r2
800185e: 4a1f ldr r2, [pc, #124] @ (80018dc <HAL_UART_RxCpltCallback+0x238>)
8001860: 6013 str r3, [r2, #0]
MA_Init(&movavFilter);
8001862: 481f ldr r0, [pc, #124] @ (80018e0 <HAL_UART_RxCpltCallback+0x23c>)
8001864: f7ff fc9c bl 80011a0 <MA_Init>
power_switch(power_state_value);
8001868: 4b1b ldr r3, [pc, #108] @ (80018d8 <HAL_UART_RxCpltCallback+0x234>)
800186a: 781b ldrb r3, [r3, #0]
800186c: 4618 mov r0, r3
800186e: f7ff fee5 bl 800163c <power_switch>
break;
8001872: e00c b.n 800188e <HAL_UART_RxCpltCallback+0x1ea>
/* 'V' - Get voltages (both input and output) */
case 0x56:
adc_task_flag = 0xff;
8001874: 4b1b ldr r3, [pc, #108] @ (80018e4 <HAL_UART_RxCpltCallback+0x240>)
8001876: 22ff movs r2, #255 @ 0xff
8001878: 701a strb r2, [r3, #0]
break;
800187a: e008 b.n 800188e <HAL_UART_RxCpltCallback+0x1ea>
/* 'I' - Get serial number information */
case 0x49:
serial_number_flag = 0xff;
800187c: 4b1a ldr r3, [pc, #104] @ (80018e8 <HAL_UART_RxCpltCallback+0x244>)
800187e: 22ff movs r2, #255 @ 0xff
8001880: 701a strb r2, [r3, #0]
break;
8001882: e004 b.n 800188e <HAL_UART_RxCpltCallback+0x1ea>
/* Bad packet received */
else
{
/* Rx is finished, so reset count to wait for another first sync byte (bad packet so no flag)*/
rx_counter = 0x00;
8001884: 4b0a ldr r3, [pc, #40] @ (80018b0 <HAL_UART_RxCpltCallback+0x20c>)
8001886: 2200 movs r2, #0
8001888: 701a strb r2, [r3, #0]
}
break;
800188a: e006 b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
break;
800188c: bf00 nop
break;
800188e: e004 b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
/* Default case - NOT USED!*/
default:
break;
8001890: bf00 nop
8001892: e002 b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
break;
8001894: bf00 nop
8001896: e000 b.n 800189a <HAL_UART_RxCpltCallback+0x1f6>
break;
8001898: bf00 nop
}
/* Reset interrupts */
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
800189a: 2201 movs r2, #1
800189c: 4905 ldr r1, [pc, #20] @ (80018b4 <HAL_UART_RxCpltCallback+0x210>)
800189e: 4813 ldr r0, [pc, #76] @ (80018ec <HAL_UART_RxCpltCallback+0x248>)
80018a0: f004 fe64 bl 800656c <HAL_UART_Receive_IT>
}
}
80018a4: bf00 nop
80018a6: 3708 adds r7, #8
80018a8: 46bd mov sp, r7
80018aa: bd80 pop {r7, pc}
80018ac: 40004400 .word 0x40004400
80018b0: 2000028e .word 0x2000028e
80018b4: 20000248 .word 0x20000248
80018b8: 2000028f .word 0x2000028f
80018bc: 20000290 .word 0x20000290
80018c0: 2000024c .word 0x2000024c
80018c4: 20000296 .word 0x20000296
80018c8: 20000297 .word 0x20000297
80018cc: 20000298 .word 0x20000298
80018d0: 20000292 .word 0x20000292
80018d4: 2000029b .word 0x2000029b
80018d8: 2000029a .word 0x2000029a
80018dc: 200002b0 .word 0x200002b0
80018e0: 200002b8 .word 0x200002b8
80018e4: 2000029c .word 0x2000029c
80018e8: 200002b5 .word 0x200002b5
80018ec: 200001b0 .word 0x200001b0
080018f0 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80018f0: b480 push {r7}
80018f2: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80018f4: b672 cpsid i
}
80018f6: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80018f8: bf00 nop
80018fa: e7fd b.n 80018f8 <Error_Handler+0x8>
080018fc <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80018fc: b580 push {r7, lr}
80018fe: b082 sub sp, #8
8001900: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001902: 4b0f ldr r3, [pc, #60] @ (8001940 <HAL_MspInit+0x44>)
8001904: 6e1b ldr r3, [r3, #96] @ 0x60
8001906: 4a0e ldr r2, [pc, #56] @ (8001940 <HAL_MspInit+0x44>)
8001908: f043 0301 orr.w r3, r3, #1
800190c: 6613 str r3, [r2, #96] @ 0x60
800190e: 4b0c ldr r3, [pc, #48] @ (8001940 <HAL_MspInit+0x44>)
8001910: 6e1b ldr r3, [r3, #96] @ 0x60
8001912: f003 0301 and.w r3, r3, #1
8001916: 607b str r3, [r7, #4]
8001918: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800191a: 4b09 ldr r3, [pc, #36] @ (8001940 <HAL_MspInit+0x44>)
800191c: 6d9b ldr r3, [r3, #88] @ 0x58
800191e: 4a08 ldr r2, [pc, #32] @ (8001940 <HAL_MspInit+0x44>)
8001920: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001924: 6593 str r3, [r2, #88] @ 0x58
8001926: 4b06 ldr r3, [pc, #24] @ (8001940 <HAL_MspInit+0x44>)
8001928: 6d9b ldr r3, [r3, #88] @ 0x58
800192a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800192e: 603b str r3, [r7, #0]
8001930: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
*/
HAL_PWREx_DisableUCPDDeadBattery();
8001932: f002 fb1f bl 8003f74 <HAL_PWREx_DisableUCPDDeadBattery>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001936: bf00 nop
8001938: 3708 adds r7, #8
800193a: 46bd mov sp, r7
800193c: bd80 pop {r7, pc}
800193e: bf00 nop
8001940: 40021000 .word 0x40021000
08001944 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8001944: b580 push {r7, lr}
8001946: b09c sub sp, #112 @ 0x70
8001948: af00 add r7, sp, #0
800194a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800194c: f107 035c add.w r3, r7, #92 @ 0x5c
8001950: 2200 movs r2, #0
8001952: 601a str r2, [r3, #0]
8001954: 605a str r2, [r3, #4]
8001956: 609a str r2, [r3, #8]
8001958: 60da str r2, [r3, #12]
800195a: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800195c: f107 0318 add.w r3, r7, #24
8001960: 2244 movs r2, #68 @ 0x44
8001962: 2100 movs r1, #0
8001964: 4618 mov r0, r3
8001966: f006 fe33 bl 80085d0 <memset>
if(hadc->Instance==ADC1)
800196a: 687b ldr r3, [r7, #4]
800196c: 681b ldr r3, [r3, #0]
800196e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8001972: d125 bne.n 80019c0 <HAL_ADC_MspInit+0x7c>
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
8001974: f44f 4300 mov.w r3, #32768 @ 0x8000
8001978: 61bb str r3, [r7, #24]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
800197a: f04f 5300 mov.w r3, #536870912 @ 0x20000000
800197e: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001980: f107 0318 add.w r3, r7, #24
8001984: 4618 mov r0, r3
8001986: f003 f833 bl 80049f0 <HAL_RCCEx_PeriphCLKConfig>
800198a: 4603 mov r3, r0
800198c: 2b00 cmp r3, #0
800198e: d001 beq.n 8001994 <HAL_ADC_MspInit+0x50>
{
Error_Handler();
8001990: f7ff ffae bl 80018f0 <Error_Handler>
}
/* Peripheral clock enable */
HAL_RCC_ADC12_CLK_ENABLED++;
8001994: 4b2e ldr r3, [pc, #184] @ (8001a50 <HAL_ADC_MspInit+0x10c>)
8001996: 681b ldr r3, [r3, #0]
8001998: 3301 adds r3, #1
800199a: 4a2d ldr r2, [pc, #180] @ (8001a50 <HAL_ADC_MspInit+0x10c>)
800199c: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
800199e: 4b2c ldr r3, [pc, #176] @ (8001a50 <HAL_ADC_MspInit+0x10c>)
80019a0: 681b ldr r3, [r3, #0]
80019a2: 2b01 cmp r3, #1
80019a4: d14f bne.n 8001a46 <HAL_ADC_MspInit+0x102>
__HAL_RCC_ADC12_CLK_ENABLE();
80019a6: 4b2b ldr r3, [pc, #172] @ (8001a54 <HAL_ADC_MspInit+0x110>)
80019a8: 6cdb ldr r3, [r3, #76] @ 0x4c
80019aa: 4a2a ldr r2, [pc, #168] @ (8001a54 <HAL_ADC_MspInit+0x110>)
80019ac: f443 5300 orr.w r3, r3, #8192 @ 0x2000
80019b0: 64d3 str r3, [r2, #76] @ 0x4c
80019b2: 4b28 ldr r3, [pc, #160] @ (8001a54 <HAL_ADC_MspInit+0x110>)
80019b4: 6cdb ldr r3, [r3, #76] @ 0x4c
80019b6: f403 5300 and.w r3, r3, #8192 @ 0x2000
80019ba: 617b str r3, [r7, #20]
80019bc: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
80019be: e042 b.n 8001a46 <HAL_ADC_MspInit+0x102>
else if(hadc->Instance==ADC2)
80019c0: 687b ldr r3, [r7, #4]
80019c2: 681b ldr r3, [r3, #0]
80019c4: 4a24 ldr r2, [pc, #144] @ (8001a58 <HAL_ADC_MspInit+0x114>)
80019c6: 4293 cmp r3, r2
80019c8: d13d bne.n 8001a46 <HAL_ADC_MspInit+0x102>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
80019ca: f44f 4300 mov.w r3, #32768 @ 0x8000
80019ce: 61bb str r3, [r7, #24]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
80019d0: f04f 5300 mov.w r3, #536870912 @ 0x20000000
80019d4: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80019d6: f107 0318 add.w r3, r7, #24
80019da: 4618 mov r0, r3
80019dc: f003 f808 bl 80049f0 <HAL_RCCEx_PeriphCLKConfig>
80019e0: 4603 mov r3, r0
80019e2: 2b00 cmp r3, #0
80019e4: d001 beq.n 80019ea <HAL_ADC_MspInit+0xa6>
Error_Handler();
80019e6: f7ff ff83 bl 80018f0 <Error_Handler>
HAL_RCC_ADC12_CLK_ENABLED++;
80019ea: 4b19 ldr r3, [pc, #100] @ (8001a50 <HAL_ADC_MspInit+0x10c>)
80019ec: 681b ldr r3, [r3, #0]
80019ee: 3301 adds r3, #1
80019f0: 4a17 ldr r2, [pc, #92] @ (8001a50 <HAL_ADC_MspInit+0x10c>)
80019f2: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
80019f4: 4b16 ldr r3, [pc, #88] @ (8001a50 <HAL_ADC_MspInit+0x10c>)
80019f6: 681b ldr r3, [r3, #0]
80019f8: 2b01 cmp r3, #1
80019fa: d10b bne.n 8001a14 <HAL_ADC_MspInit+0xd0>
__HAL_RCC_ADC12_CLK_ENABLE();
80019fc: 4b15 ldr r3, [pc, #84] @ (8001a54 <HAL_ADC_MspInit+0x110>)
80019fe: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a00: 4a14 ldr r2, [pc, #80] @ (8001a54 <HAL_ADC_MspInit+0x110>)
8001a02: f443 5300 orr.w r3, r3, #8192 @ 0x2000
8001a06: 64d3 str r3, [r2, #76] @ 0x4c
8001a08: 4b12 ldr r3, [pc, #72] @ (8001a54 <HAL_ADC_MspInit+0x110>)
8001a0a: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a0c: f403 5300 and.w r3, r3, #8192 @ 0x2000
8001a10: 613b str r3, [r7, #16]
8001a12: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001a14: 4b0f ldr r3, [pc, #60] @ (8001a54 <HAL_ADC_MspInit+0x110>)
8001a16: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a18: 4a0e ldr r2, [pc, #56] @ (8001a54 <HAL_ADC_MspInit+0x110>)
8001a1a: f043 0301 orr.w r3, r3, #1
8001a1e: 64d3 str r3, [r2, #76] @ 0x4c
8001a20: 4b0c ldr r3, [pc, #48] @ (8001a54 <HAL_ADC_MspInit+0x110>)
8001a22: 6cdb ldr r3, [r3, #76] @ 0x4c
8001a24: f003 0301 and.w r3, r3, #1
8001a28: 60fb str r3, [r7, #12]
8001a2a: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = VIN_Pin|VOUT_Pin;
8001a2c: 23c0 movs r3, #192 @ 0xc0
8001a2e: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001a30: 2303 movs r3, #3
8001a32: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a34: 2300 movs r3, #0
8001a36: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001a38: f107 035c add.w r3, r7, #92 @ 0x5c
8001a3c: 4619 mov r1, r3
8001a3e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001a42: f002 f859 bl 8003af8 <HAL_GPIO_Init>
}
8001a46: bf00 nop
8001a48: 3770 adds r7, #112 @ 0x70
8001a4a: 46bd mov sp, r7
8001a4c: bd80 pop {r7, pc}
8001a4e: bf00 nop
8001a50: 200003c0 .word 0x200003c0
8001a54: 40021000 .word 0x40021000
8001a58: 50000100 .word 0x50000100
08001a5c <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001a5c: b580 push {r7, lr}
8001a5e: b084 sub sp, #16
8001a60: af00 add r7, sp, #0
8001a62: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
8001a64: 687b ldr r3, [r7, #4]
8001a66: 681b ldr r3, [r3, #0]
8001a68: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001a6c: d114 bne.n 8001a98 <HAL_TIM_Base_MspInit+0x3c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001a6e: 4b15 ldr r3, [pc, #84] @ (8001ac4 <HAL_TIM_Base_MspInit+0x68>)
8001a70: 6d9b ldr r3, [r3, #88] @ 0x58
8001a72: 4a14 ldr r2, [pc, #80] @ (8001ac4 <HAL_TIM_Base_MspInit+0x68>)
8001a74: f043 0301 orr.w r3, r3, #1
8001a78: 6593 str r3, [r2, #88] @ 0x58
8001a7a: 4b12 ldr r3, [pc, #72] @ (8001ac4 <HAL_TIM_Base_MspInit+0x68>)
8001a7c: 6d9b ldr r3, [r3, #88] @ 0x58
8001a7e: f003 0301 and.w r3, r3, #1
8001a82: 60fb str r3, [r7, #12]
8001a84: 68fb ldr r3, [r7, #12]
/* TIM2 interrupt Init */
HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
8001a86: 2200 movs r2, #0
8001a88: 2100 movs r1, #0
8001a8a: 201c movs r0, #28
8001a8c: f001 ff3f bl 800390e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM2_IRQn);
8001a90: 201c movs r0, #28
8001a92: f001 ff56 bl 8003942 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM16_MspInit 1 */
/* USER CODE END TIM16_MspInit 1 */
}
}
8001a96: e010 b.n 8001aba <HAL_TIM_Base_MspInit+0x5e>
else if(htim_base->Instance==TIM16)
8001a98: 687b ldr r3, [r7, #4]
8001a9a: 681b ldr r3, [r3, #0]
8001a9c: 4a0a ldr r2, [pc, #40] @ (8001ac8 <HAL_TIM_Base_MspInit+0x6c>)
8001a9e: 4293 cmp r3, r2
8001aa0: d10b bne.n 8001aba <HAL_TIM_Base_MspInit+0x5e>
__HAL_RCC_TIM16_CLK_ENABLE();
8001aa2: 4b08 ldr r3, [pc, #32] @ (8001ac4 <HAL_TIM_Base_MspInit+0x68>)
8001aa4: 6e1b ldr r3, [r3, #96] @ 0x60
8001aa6: 4a07 ldr r2, [pc, #28] @ (8001ac4 <HAL_TIM_Base_MspInit+0x68>)
8001aa8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001aac: 6613 str r3, [r2, #96] @ 0x60
8001aae: 4b05 ldr r3, [pc, #20] @ (8001ac4 <HAL_TIM_Base_MspInit+0x68>)
8001ab0: 6e1b ldr r3, [r3, #96] @ 0x60
8001ab2: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001ab6: 60bb str r3, [r7, #8]
8001ab8: 68bb ldr r3, [r7, #8]
}
8001aba: bf00 nop
8001abc: 3710 adds r7, #16
8001abe: 46bd mov sp, r7
8001ac0: bd80 pop {r7, pc}
8001ac2: bf00 nop
8001ac4: 40021000 .word 0x40021000
8001ac8: 40014400 .word 0x40014400
08001acc <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001acc: b580 push {r7, lr}
8001ace: b088 sub sp, #32
8001ad0: af00 add r7, sp, #0
8001ad2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001ad4: f107 030c add.w r3, r7, #12
8001ad8: 2200 movs r2, #0
8001ada: 601a str r2, [r3, #0]
8001adc: 605a str r2, [r3, #4]
8001ade: 609a str r2, [r3, #8]
8001ae0: 60da str r2, [r3, #12]
8001ae2: 611a str r2, [r3, #16]
if(htim->Instance==TIM16)
8001ae4: 687b ldr r3, [r7, #4]
8001ae6: 681b ldr r3, [r3, #0]
8001ae8: 4a12 ldr r2, [pc, #72] @ (8001b34 <HAL_TIM_MspPostInit+0x68>)
8001aea: 4293 cmp r3, r2
8001aec: d11d bne.n 8001b2a <HAL_TIM_MspPostInit+0x5e>
{
/* USER CODE BEGIN TIM16_MspPostInit 0 */
/* USER CODE END TIM16_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001aee: 4b12 ldr r3, [pc, #72] @ (8001b38 <HAL_TIM_MspPostInit+0x6c>)
8001af0: 6cdb ldr r3, [r3, #76] @ 0x4c
8001af2: 4a11 ldr r2, [pc, #68] @ (8001b38 <HAL_TIM_MspPostInit+0x6c>)
8001af4: f043 0301 orr.w r3, r3, #1
8001af8: 64d3 str r3, [r2, #76] @ 0x4c
8001afa: 4b0f ldr r3, [pc, #60] @ (8001b38 <HAL_TIM_MspPostInit+0x6c>)
8001afc: 6cdb ldr r3, [r3, #76] @ 0x4c
8001afe: f003 0301 and.w r3, r3, #1
8001b02: 60bb str r3, [r7, #8]
8001b04: 68bb ldr r3, [r7, #8]
/**TIM16 GPIO Configuration
PA12 ------> TIM16_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_12;
8001b06: f44f 5380 mov.w r3, #4096 @ 0x1000
8001b0a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b0c: 2302 movs r3, #2
8001b0e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b10: 2300 movs r3, #0
8001b12: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b14: 2300 movs r3, #0
8001b16: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM16;
8001b18: 2301 movs r3, #1
8001b1a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001b1c: f107 030c add.w r3, r7, #12
8001b20: 4619 mov r1, r3
8001b22: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001b26: f001 ffe7 bl 8003af8 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM16_MspPostInit 1 */
/* USER CODE END TIM16_MspPostInit 1 */
}
}
8001b2a: bf00 nop
8001b2c: 3720 adds r7, #32
8001b2e: 46bd mov sp, r7
8001b30: bd80 pop {r7, pc}
8001b32: bf00 nop
8001b34: 40014400 .word 0x40014400
8001b38: 40021000 .word 0x40021000
08001b3c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001b3c: b580 push {r7, lr}
8001b3e: b09a sub sp, #104 @ 0x68
8001b40: af00 add r7, sp, #0
8001b42: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001b44: f107 0354 add.w r3, r7, #84 @ 0x54
8001b48: 2200 movs r2, #0
8001b4a: 601a str r2, [r3, #0]
8001b4c: 605a str r2, [r3, #4]
8001b4e: 609a str r2, [r3, #8]
8001b50: 60da str r2, [r3, #12]
8001b52: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001b54: f107 0310 add.w r3, r7, #16
8001b58: 2244 movs r2, #68 @ 0x44
8001b5a: 2100 movs r1, #0
8001b5c: 4618 mov r0, r3
8001b5e: f006 fd37 bl 80085d0 <memset>
if(huart->Instance==USART2)
8001b62: 687b ldr r3, [r7, #4]
8001b64: 681b ldr r3, [r3, #0]
8001b66: 4a23 ldr r2, [pc, #140] @ (8001bf4 <HAL_UART_MspInit+0xb8>)
8001b68: 4293 cmp r3, r2
8001b6a: d13e bne.n 8001bea <HAL_UART_MspInit+0xae>
/* USER CODE END USART2_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
8001b6c: 2302 movs r3, #2
8001b6e: 613b str r3, [r7, #16]
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
8001b70: 2300 movs r3, #0
8001b72: 61bb str r3, [r7, #24]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001b74: f107 0310 add.w r3, r7, #16
8001b78: 4618 mov r0, r3
8001b7a: f002 ff39 bl 80049f0 <HAL_RCCEx_PeriphCLKConfig>
8001b7e: 4603 mov r3, r0
8001b80: 2b00 cmp r3, #0
8001b82: d001 beq.n 8001b88 <HAL_UART_MspInit+0x4c>
{
Error_Handler();
8001b84: f7ff feb4 bl 80018f0 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
8001b88: 4b1b ldr r3, [pc, #108] @ (8001bf8 <HAL_UART_MspInit+0xbc>)
8001b8a: 6d9b ldr r3, [r3, #88] @ 0x58
8001b8c: 4a1a ldr r2, [pc, #104] @ (8001bf8 <HAL_UART_MspInit+0xbc>)
8001b8e: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001b92: 6593 str r3, [r2, #88] @ 0x58
8001b94: 4b18 ldr r3, [pc, #96] @ (8001bf8 <HAL_UART_MspInit+0xbc>)
8001b96: 6d9b ldr r3, [r3, #88] @ 0x58
8001b98: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001b9c: 60fb str r3, [r7, #12]
8001b9e: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001ba0: 4b15 ldr r3, [pc, #84] @ (8001bf8 <HAL_UART_MspInit+0xbc>)
8001ba2: 6cdb ldr r3, [r3, #76] @ 0x4c
8001ba4: 4a14 ldr r2, [pc, #80] @ (8001bf8 <HAL_UART_MspInit+0xbc>)
8001ba6: f043 0301 orr.w r3, r3, #1
8001baa: 64d3 str r3, [r2, #76] @ 0x4c
8001bac: 4b12 ldr r3, [pc, #72] @ (8001bf8 <HAL_UART_MspInit+0xbc>)
8001bae: 6cdb ldr r3, [r3, #76] @ 0x4c
8001bb0: f003 0301 and.w r3, r3, #1
8001bb4: 60bb str r3, [r7, #8]
8001bb6: 68bb ldr r3, [r7, #8]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin;
8001bb8: 230c movs r3, #12
8001bba: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bbc: 2302 movs r3, #2
8001bbe: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bc0: 2300 movs r3, #0
8001bc2: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001bc4: 2300 movs r3, #0
8001bc6: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8001bc8: 2307 movs r3, #7
8001bca: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001bcc: f107 0354 add.w r3, r7, #84 @ 0x54
8001bd0: 4619 mov r1, r3
8001bd2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001bd6: f001 ff8f bl 8003af8 <HAL_GPIO_Init>
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
8001bda: 2200 movs r2, #0
8001bdc: 2100 movs r1, #0
8001bde: 2026 movs r0, #38 @ 0x26
8001be0: f001 fe95 bl 800390e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
8001be4: 2026 movs r0, #38 @ 0x26
8001be6: f001 feac bl 8003942 <HAL_NVIC_EnableIRQ>
/* USER CODE END USART2_MspInit 1 */
}
}
8001bea: bf00 nop
8001bec: 3768 adds r7, #104 @ 0x68
8001bee: 46bd mov sp, r7
8001bf0: bd80 pop {r7, pc}
8001bf2: bf00 nop
8001bf4: 40004400 .word 0x40004400
8001bf8: 40021000 .word 0x40021000
08001bfc <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001bfc: b480 push {r7}
8001bfe: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001c00: bf00 nop
8001c02: e7fd b.n 8001c00 <NMI_Handler+0x4>
08001c04 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001c04: b480 push {r7}
8001c06: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001c08: bf00 nop
8001c0a: e7fd b.n 8001c08 <HardFault_Handler+0x4>
08001c0c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001c0c: b480 push {r7}
8001c0e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001c10: bf00 nop
8001c12: e7fd b.n 8001c10 <MemManage_Handler+0x4>
08001c14 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001c14: b480 push {r7}
8001c16: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001c18: bf00 nop
8001c1a: e7fd b.n 8001c18 <BusFault_Handler+0x4>
08001c1c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001c1c: b480 push {r7}
8001c1e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001c20: bf00 nop
8001c22: e7fd b.n 8001c20 <UsageFault_Handler+0x4>
08001c24 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001c24: b480 push {r7}
8001c26: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001c28: bf00 nop
8001c2a: 46bd mov sp, r7
8001c2c: f85d 7b04 ldr.w r7, [sp], #4
8001c30: 4770 bx lr
08001c32 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001c32: b480 push {r7}
8001c34: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001c36: bf00 nop
8001c38: 46bd mov sp, r7
8001c3a: f85d 7b04 ldr.w r7, [sp], #4
8001c3e: 4770 bx lr
08001c40 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001c40: b480 push {r7}
8001c42: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001c44: bf00 nop
8001c46: 46bd mov sp, r7
8001c48: f85d 7b04 ldr.w r7, [sp], #4
8001c4c: 4770 bx lr
08001c4e <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001c4e: b580 push {r7, lr}
8001c50: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001c52: f000 f8a5 bl 8001da0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001c56: bf00 nop
8001c58: bd80 pop {r7, pc}
...
08001c5c <TIM2_IRQHandler>:
/**
* @brief This function handles TIM2 global interrupt.
*/
void TIM2_IRQHandler(void)
{
8001c5c: b580 push {r7, lr}
8001c5e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_IRQn 0 */
/* USER CODE END TIM2_IRQn 0 */
HAL_TIM_IRQHandler(&htim2);
8001c60: 4802 ldr r0, [pc, #8] @ (8001c6c <TIM2_IRQHandler+0x10>)
8001c62: f003 fa6d bl 8005140 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM2_IRQn 1 */
/* USER CODE END TIM2_IRQn 1 */
}
8001c66: bf00 nop
8001c68: bd80 pop {r7, pc}
8001c6a: bf00 nop
8001c6c: 20000118 .word 0x20000118
08001c70 <USART2_IRQHandler>:
/**
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
*/
void USART2_IRQHandler(void)
{
8001c70: b580 push {r7, lr}
8001c72: af00 add r7, sp, #0
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
8001c74: 4802 ldr r0, [pc, #8] @ (8001c80 <USART2_IRQHandler+0x10>)
8001c76: f004 fcc5 bl 8006604 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
8001c7a: bf00 nop
8001c7c: bd80 pop {r7, pc}
8001c7e: bf00 nop
8001c80: 200001b0 .word 0x200001b0
08001c84 <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
8001c84: b480 push {r7}
8001c86: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
8001c88: 4b06 ldr r3, [pc, #24] @ (8001ca4 <SystemInit+0x20>)
8001c8a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8001c8e: 4a05 ldr r2, [pc, #20] @ (8001ca4 <SystemInit+0x20>)
8001c90: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8001c94: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001c98: bf00 nop
8001c9a: 46bd mov sp, r7
8001c9c: f85d 7b04 ldr.w r7, [sp], #4
8001ca0: 4770 bx lr
8001ca2: bf00 nop
8001ca4: e000ed00 .word 0xe000ed00
08001ca8 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8001ca8: 480d ldr r0, [pc, #52] @ (8001ce0 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8001caa: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8001cac: f7ff ffea bl 8001c84 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001cb0: 480c ldr r0, [pc, #48] @ (8001ce4 <LoopForever+0x6>)
ldr r1, =_edata
8001cb2: 490d ldr r1, [pc, #52] @ (8001ce8 <LoopForever+0xa>)
ldr r2, =_sidata
8001cb4: 4a0d ldr r2, [pc, #52] @ (8001cec <LoopForever+0xe>)
movs r3, #0
8001cb6: 2300 movs r3, #0
b LoopCopyDataInit
8001cb8: e002 b.n 8001cc0 <LoopCopyDataInit>
08001cba <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001cba: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001cbc: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001cbe: 3304 adds r3, #4
08001cc0 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001cc0: 18c4 adds r4, r0, r3
cmp r4, r1
8001cc2: 428c cmp r4, r1
bcc CopyDataInit
8001cc4: d3f9 bcc.n 8001cba <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001cc6: 4a0a ldr r2, [pc, #40] @ (8001cf0 <LoopForever+0x12>)
ldr r4, =_ebss
8001cc8: 4c0a ldr r4, [pc, #40] @ (8001cf4 <LoopForever+0x16>)
movs r3, #0
8001cca: 2300 movs r3, #0
b LoopFillZerobss
8001ccc: e001 b.n 8001cd2 <LoopFillZerobss>
08001cce <FillZerobss>:
FillZerobss:
str r3, [r2]
8001cce: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001cd0: 3204 adds r2, #4
08001cd2 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001cd2: 42a2 cmp r2, r4
bcc FillZerobss
8001cd4: d3fb bcc.n 8001cce <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001cd6: f006 fc83 bl 80085e0 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001cda: f7fe ff39 bl 8000b50 <main>
08001cde <LoopForever>:
LoopForever:
b LoopForever
8001cde: e7fe b.n 8001cde <LoopForever>
ldr r0, =_estack
8001ce0: 20008000 .word 0x20008000
ldr r0, =_sdata
8001ce4: 20000000 .word 0x20000000
ldr r1, =_edata
8001ce8: 20000024 .word 0x20000024
ldr r2, =_sidata
8001cec: 08008690 .word 0x08008690
ldr r2, =_sbss
8001cf0: 20000024 .word 0x20000024
ldr r4, =_ebss
8001cf4: 200003c8 .word 0x200003c8
08001cf8 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001cf8: e7fe b.n 8001cf8 <ADC1_2_IRQHandler>
08001cfa <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001cfa: b580 push {r7, lr}
8001cfc: b082 sub sp, #8
8001cfe: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001d00: 2300 movs r3, #0
8001d02: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001d04: 2003 movs r0, #3
8001d06: f001 fdf7 bl 80038f8 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001d0a: 2000 movs r0, #0
8001d0c: f000 f80e bl 8001d2c <HAL_InitTick>
8001d10: 4603 mov r3, r0
8001d12: 2b00 cmp r3, #0
8001d14: d002 beq.n 8001d1c <HAL_Init+0x22>
{
status = HAL_ERROR;
8001d16: 2301 movs r3, #1
8001d18: 71fb strb r3, [r7, #7]
8001d1a: e001 b.n 8001d20 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001d1c: f7ff fdee bl 80018fc <HAL_MspInit>
}
/* Return function status */
return status;
8001d20: 79fb ldrb r3, [r7, #7]
}
8001d22: 4618 mov r0, r3
8001d24: 3708 adds r7, #8
8001d26: 46bd mov sp, r7
8001d28: bd80 pop {r7, pc}
...
08001d2c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001d2c: b580 push {r7, lr}
8001d2e: b084 sub sp, #16
8001d30: af00 add r7, sp, #0
8001d32: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001d34: 2300 movs r3, #0
8001d36: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8001d38: 4b16 ldr r3, [pc, #88] @ (8001d94 <HAL_InitTick+0x68>)
8001d3a: 681b ldr r3, [r3, #0]
8001d3c: 2b00 cmp r3, #0
8001d3e: d022 beq.n 8001d86 <HAL_InitTick+0x5a>
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8001d40: 4b15 ldr r3, [pc, #84] @ (8001d98 <HAL_InitTick+0x6c>)
8001d42: 681a ldr r2, [r3, #0]
8001d44: 4b13 ldr r3, [pc, #76] @ (8001d94 <HAL_InitTick+0x68>)
8001d46: 681b ldr r3, [r3, #0]
8001d48: f44f 717a mov.w r1, #1000 @ 0x3e8
8001d4c: fbb1 f3f3 udiv r3, r1, r3
8001d50: fbb2 f3f3 udiv r3, r2, r3
8001d54: 4618 mov r0, r3
8001d56: f001 fe02 bl 800395e <HAL_SYSTICK_Config>
8001d5a: 4603 mov r3, r0
8001d5c: 2b00 cmp r3, #0
8001d5e: d10f bne.n 8001d80 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001d60: 687b ldr r3, [r7, #4]
8001d62: 2b0f cmp r3, #15
8001d64: d809 bhi.n 8001d7a <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001d66: 2200 movs r2, #0
8001d68: 6879 ldr r1, [r7, #4]
8001d6a: f04f 30ff mov.w r0, #4294967295
8001d6e: f001 fdce bl 800390e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001d72: 4a0a ldr r2, [pc, #40] @ (8001d9c <HAL_InitTick+0x70>)
8001d74: 687b ldr r3, [r7, #4]
8001d76: 6013 str r3, [r2, #0]
8001d78: e007 b.n 8001d8a <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8001d7a: 2301 movs r3, #1
8001d7c: 73fb strb r3, [r7, #15]
8001d7e: e004 b.n 8001d8a <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001d80: 2301 movs r3, #1
8001d82: 73fb strb r3, [r7, #15]
8001d84: e001 b.n 8001d8a <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001d86: 2301 movs r3, #1
8001d88: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001d8a: 7bfb ldrb r3, [r7, #15]
}
8001d8c: 4618 mov r0, r3
8001d8e: 3710 adds r7, #16
8001d90: 46bd mov sp, r7
8001d92: bd80 pop {r7, pc}
8001d94: 20000020 .word 0x20000020
8001d98: 20000018 .word 0x20000018
8001d9c: 2000001c .word 0x2000001c
08001da0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001da0: b480 push {r7}
8001da2: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001da4: 4b05 ldr r3, [pc, #20] @ (8001dbc <HAL_IncTick+0x1c>)
8001da6: 681a ldr r2, [r3, #0]
8001da8: 4b05 ldr r3, [pc, #20] @ (8001dc0 <HAL_IncTick+0x20>)
8001daa: 681b ldr r3, [r3, #0]
8001dac: 4413 add r3, r2
8001dae: 4a03 ldr r2, [pc, #12] @ (8001dbc <HAL_IncTick+0x1c>)
8001db0: 6013 str r3, [r2, #0]
}
8001db2: bf00 nop
8001db4: 46bd mov sp, r7
8001db6: f85d 7b04 ldr.w r7, [sp], #4
8001dba: 4770 bx lr
8001dbc: 200003c4 .word 0x200003c4
8001dc0: 20000020 .word 0x20000020
08001dc4 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001dc4: b480 push {r7}
8001dc6: af00 add r7, sp, #0
return uwTick;
8001dc8: 4b03 ldr r3, [pc, #12] @ (8001dd8 <HAL_GetTick+0x14>)
8001dca: 681b ldr r3, [r3, #0]
}
8001dcc: 4618 mov r0, r3
8001dce: 46bd mov sp, r7
8001dd0: f85d 7b04 ldr.w r7, [sp], #4
8001dd4: 4770 bx lr
8001dd6: bf00 nop
8001dd8: 200003c4 .word 0x200003c4
08001ddc <LL_ADC_SetCommonClock>:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
8001ddc: b480 push {r7}
8001dde: b083 sub sp, #12
8001de0: af00 add r7, sp, #0
8001de2: 6078 str r0, [r7, #4]
8001de4: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
8001de6: 687b ldr r3, [r7, #4]
8001de8: 689b ldr r3, [r3, #8]
8001dea: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000
8001dee: 683b ldr r3, [r7, #0]
8001df0: 431a orrs r2, r3
8001df2: 687b ldr r3, [r7, #4]
8001df4: 609a str r2, [r3, #8]
}
8001df6: bf00 nop
8001df8: 370c adds r7, #12
8001dfa: 46bd mov sp, r7
8001dfc: f85d 7b04 ldr.w r7, [sp], #4
8001e00: 4770 bx lr
08001e02 <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
8001e02: b480 push {r7}
8001e04: b083 sub sp, #12
8001e06: af00 add r7, sp, #0
8001e08: 6078 str r0, [r7, #4]
8001e0a: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
8001e0c: 687b ldr r3, [r7, #4]
8001e0e: 689b ldr r3, [r3, #8]
8001e10: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000
8001e14: 683b ldr r3, [r7, #0]
8001e16: 431a orrs r2, r3
8001e18: 687b ldr r3, [r7, #4]
8001e1a: 609a str r2, [r3, #8]
}
8001e1c: bf00 nop
8001e1e: 370c adds r7, #12
8001e20: 46bd mov sp, r7
8001e22: f85d 7b04 ldr.w r7, [sp], #4
8001e26: 4770 bx lr
08001e28 <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8001e28: b480 push {r7}
8001e2a: b083 sub sp, #12
8001e2c: af00 add r7, sp, #0
8001e2e: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
8001e30: 687b ldr r3, [r7, #4]
8001e32: 689b ldr r3, [r3, #8]
8001e34: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000
}
8001e38: 4618 mov r0, r3
8001e3a: 370c adds r7, #12
8001e3c: 46bd mov sp, r7
8001e3e: f85d 7b04 ldr.w r7, [sp], #4
8001e42: 4770 bx lr
08001e44 <LL_ADC_SetOffset>:
* (fADC) to convert in 12-bit resolution.\n
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
8001e44: b480 push {r7}
8001e46: b087 sub sp, #28
8001e48: af00 add r7, sp, #0
8001e4a: 60f8 str r0, [r7, #12]
8001e4c: 60b9 str r1, [r7, #8]
8001e4e: 607a str r2, [r7, #4]
8001e50: 603b str r3, [r7, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001e52: 68fb ldr r3, [r7, #12]
8001e54: 3360 adds r3, #96 @ 0x60
8001e56: 461a mov r2, r3
8001e58: 68bb ldr r3, [r7, #8]
8001e5a: 009b lsls r3, r3, #2
8001e5c: 4413 add r3, r2
8001e5e: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001e60: 697b ldr r3, [r7, #20]
8001e62: 681a ldr r2, [r3, #0]
8001e64: 4b08 ldr r3, [pc, #32] @ (8001e88 <LL_ADC_SetOffset+0x44>)
8001e66: 4013 ands r3, r2
8001e68: 687a ldr r2, [r7, #4]
8001e6a: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000
8001e6e: 683a ldr r2, [r7, #0]
8001e70: 430a orrs r2, r1
8001e72: 4313 orrs r3, r2
8001e74: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
8001e78: 697b ldr r3, [r7, #20]
8001e7a: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
}
8001e7c: bf00 nop
8001e7e: 371c adds r7, #28
8001e80: 46bd mov sp, r7
8001e82: f85d 7b04 ldr.w r7, [sp], #4
8001e86: 4770 bx lr
8001e88: 03fff000 .word 0x03fff000
08001e8c <LL_ADC_GetOffsetChannel>:
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
8001e8c: b480 push {r7}
8001e8e: b085 sub sp, #20
8001e90: af00 add r7, sp, #0
8001e92: 6078 str r0, [r7, #4]
8001e94: 6039 str r1, [r7, #0]
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001e96: 687b ldr r3, [r7, #4]
8001e98: 3360 adds r3, #96 @ 0x60
8001e9a: 461a mov r2, r3
8001e9c: 683b ldr r3, [r7, #0]
8001e9e: 009b lsls r3, r3, #2
8001ea0: 4413 add r3, r2
8001ea2: 60fb str r3, [r7, #12]
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
8001ea4: 68fb ldr r3, [r7, #12]
8001ea6: 681b ldr r3, [r3, #0]
8001ea8: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
}
8001eac: 4618 mov r0, r3
8001eae: 3714 adds r7, #20
8001eb0: 46bd mov sp, r7
8001eb2: f85d 7b04 ldr.w r7, [sp], #4
8001eb6: 4770 bx lr
08001eb8 <LL_ADC_SetOffsetState>:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
8001eb8: b480 push {r7}
8001eba: b087 sub sp, #28
8001ebc: af00 add r7, sp, #0
8001ebe: 60f8 str r0, [r7, #12]
8001ec0: 60b9 str r1, [r7, #8]
8001ec2: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001ec4: 68fb ldr r3, [r7, #12]
8001ec6: 3360 adds r3, #96 @ 0x60
8001ec8: 461a mov r2, r3
8001eca: 68bb ldr r3, [r7, #8]
8001ecc: 009b lsls r3, r3, #2
8001ece: 4413 add r3, r2
8001ed0: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001ed2: 697b ldr r3, [r7, #20]
8001ed4: 681b ldr r3, [r3, #0]
8001ed6: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8001eda: 687b ldr r3, [r7, #4]
8001edc: 431a orrs r2, r3
8001ede: 697b ldr r3, [r7, #20]
8001ee0: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN,
OffsetState);
}
8001ee2: bf00 nop
8001ee4: 371c adds r7, #28
8001ee6: 46bd mov sp, r7
8001ee8: f85d 7b04 ldr.w r7, [sp], #4
8001eec: 4770 bx lr
08001eee <LL_ADC_SetOffsetSign>:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
8001eee: b480 push {r7}
8001ef0: b087 sub sp, #28
8001ef2: af00 add r7, sp, #0
8001ef4: 60f8 str r0, [r7, #12]
8001ef6: 60b9 str r1, [r7, #8]
8001ef8: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001efa: 68fb ldr r3, [r7, #12]
8001efc: 3360 adds r3, #96 @ 0x60
8001efe: 461a mov r2, r3
8001f00: 68bb ldr r3, [r7, #8]
8001f02: 009b lsls r3, r3, #2
8001f04: 4413 add r3, r2
8001f06: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001f08: 697b ldr r3, [r7, #20]
8001f0a: 681b ldr r3, [r3, #0]
8001f0c: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
8001f10: 687b ldr r3, [r7, #4]
8001f12: 431a orrs r2, r3
8001f14: 697b ldr r3, [r7, #20]
8001f16: 601a str r2, [r3, #0]
ADC_OFR1_OFFSETPOS,
OffsetSign);
}
8001f18: bf00 nop
8001f1a: 371c adds r7, #28
8001f1c: 46bd mov sp, r7
8001f1e: f85d 7b04 ldr.w r7, [sp], #4
8001f22: 4770 bx lr
08001f24 <LL_ADC_SetOffsetSaturation>:
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
{
8001f24: b480 push {r7}
8001f26: b087 sub sp, #28
8001f28: af00 add r7, sp, #0
8001f2a: 60f8 str r0, [r7, #12]
8001f2c: 60b9 str r1, [r7, #8]
8001f2e: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001f30: 68fb ldr r3, [r7, #12]
8001f32: 3360 adds r3, #96 @ 0x60
8001f34: 461a mov r2, r3
8001f36: 68bb ldr r3, [r7, #8]
8001f38: 009b lsls r3, r3, #2
8001f3a: 4413 add r3, r2
8001f3c: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001f3e: 697b ldr r3, [r7, #20]
8001f40: 681b ldr r3, [r3, #0]
8001f42: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
8001f46: 687b ldr r3, [r7, #4]
8001f48: 431a orrs r2, r3
8001f4a: 697b ldr r3, [r7, #20]
8001f4c: 601a str r2, [r3, #0]
ADC_OFR1_SATEN,
OffsetSaturation);
}
8001f4e: bf00 nop
8001f50: 371c adds r7, #28
8001f52: 46bd mov sp, r7
8001f54: f85d 7b04 ldr.w r7, [sp], #4
8001f58: 4770 bx lr
08001f5a <LL_ADC_SetSamplingTimeCommonConfig>:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
{
8001f5a: b480 push {r7}
8001f5c: b083 sub sp, #12
8001f5e: af00 add r7, sp, #0
8001f60: 6078 str r0, [r7, #4]
8001f62: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
8001f64: 687b ldr r3, [r7, #4]
8001f66: 695b ldr r3, [r3, #20]
8001f68: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8001f6c: 683b ldr r3, [r7, #0]
8001f6e: 431a orrs r2, r3
8001f70: 687b ldr r3, [r7, #4]
8001f72: 615a str r2, [r3, #20]
}
8001f74: bf00 nop
8001f76: 370c adds r7, #12
8001f78: 46bd mov sp, r7
8001f7a: f85d 7b04 ldr.w r7, [sp], #4
8001f7e: 4770 bx lr
08001f80 <LL_ADC_REG_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
{
8001f80: b480 push {r7}
8001f82: b083 sub sp, #12
8001f84: af00 add r7, sp, #0
8001f86: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
8001f88: 687b ldr r3, [r7, #4]
8001f8a: 68db ldr r3, [r3, #12]
8001f8c: f403 6340 and.w r3, r3, #3072 @ 0xc00
8001f90: 2b00 cmp r3, #0
8001f92: d101 bne.n 8001f98 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
8001f94: 2301 movs r3, #1
8001f96: e000 b.n 8001f9a <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
8001f98: 2300 movs r3, #0
}
8001f9a: 4618 mov r0, r3
8001f9c: 370c adds r7, #12
8001f9e: 46bd mov sp, r7
8001fa0: f85d 7b04 ldr.w r7, [sp], #4
8001fa4: 4770 bx lr
08001fa6 <LL_ADC_REG_SetSequencerRanks>:
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
* (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
8001fa6: b480 push {r7}
8001fa8: b087 sub sp, #28
8001faa: af00 add r7, sp, #0
8001fac: 60f8 str r0, [r7, #12]
8001fae: 60b9 str r1, [r7, #8]
8001fb0: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
8001fb2: 68fb ldr r3, [r7, #12]
8001fb4: 3330 adds r3, #48 @ 0x30
8001fb6: 461a mov r2, r3
8001fb8: 68bb ldr r3, [r7, #8]
8001fba: 0a1b lsrs r3, r3, #8
8001fbc: 009b lsls r3, r3, #2
8001fbe: f003 030c and.w r3, r3, #12
8001fc2: 4413 add r3, r2
8001fc4: 617b str r3, [r7, #20]
((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
8001fc6: 697b ldr r3, [r7, #20]
8001fc8: 681a ldr r2, [r3, #0]
8001fca: 68bb ldr r3, [r7, #8]
8001fcc: f003 031f and.w r3, r3, #31
8001fd0: 211f movs r1, #31
8001fd2: fa01 f303 lsl.w r3, r1, r3
8001fd6: 43db mvns r3, r3
8001fd8: 401a ands r2, r3
8001fda: 687b ldr r3, [r7, #4]
8001fdc: 0e9b lsrs r3, r3, #26
8001fde: f003 011f and.w r1, r3, #31
8001fe2: 68bb ldr r3, [r7, #8]
8001fe4: f003 031f and.w r3, r3, #31
8001fe8: fa01 f303 lsl.w r3, r1, r3
8001fec: 431a orrs r2, r3
8001fee: 697b ldr r3, [r7, #20]
8001ff0: 601a str r2, [r3, #0]
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<< (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
8001ff2: bf00 nop
8001ff4: 371c adds r7, #28
8001ff6: 46bd mov sp, r7
8001ff8: f85d 7b04 ldr.w r7, [sp], #4
8001ffc: 4770 bx lr
08001ffe <LL_ADC_SetChannelSamplingTime>:
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
8001ffe: b480 push {r7}
8002000: b087 sub sp, #28
8002002: af00 add r7, sp, #0
8002004: 60f8 str r0, [r7, #12]
8002006: 60b9 str r1, [r7, #8]
8002008: 607a str r2, [r7, #4]
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
800200a: 68fb ldr r3, [r7, #12]
800200c: 3314 adds r3, #20
800200e: 461a mov r2, r3
8002010: 68bb ldr r3, [r7, #8]
8002012: 0e5b lsrs r3, r3, #25
8002014: 009b lsls r3, r3, #2
8002016: f003 0304 and.w r3, r3, #4
800201a: 4413 add r3, r2
800201c: 617b str r3, [r7, #20]
((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
800201e: 697b ldr r3, [r7, #20]
8002020: 681a ldr r2, [r3, #0]
8002022: 68bb ldr r3, [r7, #8]
8002024: 0d1b lsrs r3, r3, #20
8002026: f003 031f and.w r3, r3, #31
800202a: 2107 movs r1, #7
800202c: fa01 f303 lsl.w r3, r1, r3
8002030: 43db mvns r3, r3
8002032: 401a ands r2, r3
8002034: 68bb ldr r3, [r7, #8]
8002036: 0d1b lsrs r3, r3, #20
8002038: f003 031f and.w r3, r3, #31
800203c: 6879 ldr r1, [r7, #4]
800203e: fa01 f303 lsl.w r3, r1, r3
8002042: 431a orrs r2, r3
8002044: 697b ldr r3, [r7, #20]
8002046: 601a str r2, [r3, #0]
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
8002048: bf00 nop
800204a: 371c adds r7, #28
800204c: 46bd mov sp, r7
800204e: f85d 7b04 ldr.w r7, [sp], #4
8002052: 4770 bx lr
08002054 <LL_ADC_SetChannelSingleDiff>:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
8002054: b480 push {r7}
8002056: b085 sub sp, #20
8002058: af00 add r7, sp, #0
800205a: 60f8 str r0, [r7, #12]
800205c: 60b9 str r1, [r7, #8]
800205e: 607a str r2, [r7, #4]
/* Bits of channels in single or differential mode are set only for */
/* differential mode (for single mode, mask of bits allowed to be set is */
/* shifted out of range of bits of channels in single or differential mode. */
MODIFY_REG(ADCx->DIFSEL,
8002060: 68fb ldr r3, [r7, #12]
8002062: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0
8002066: 68bb ldr r3, [r7, #8]
8002068: f3c3 0312 ubfx r3, r3, #0, #19
800206c: 43db mvns r3, r3
800206e: 401a ands r2, r3
8002070: 687b ldr r3, [r7, #4]
8002072: f003 0318 and.w r3, r3, #24
8002076: 4908 ldr r1, [pc, #32] @ (8002098 <LL_ADC_SetChannelSingleDiff+0x44>)
8002078: 40d9 lsrs r1, r3
800207a: 68bb ldr r3, [r7, #8]
800207c: 400b ands r3, r1
800207e: f3c3 0312 ubfx r3, r3, #0, #19
8002082: 431a orrs r2, r3
8002084: 68fb ldr r3, [r7, #12]
8002086: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
& (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
}
800208a: bf00 nop
800208c: 3714 adds r7, #20
800208e: 46bd mov sp, r7
8002090: f85d 7b04 ldr.w r7, [sp], #4
8002094: 4770 bx lr
8002096: bf00 nop
8002098: 0007ffff .word 0x0007ffff
0800209c <LL_ADC_GetMultimode>:
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
{
800209c: b480 push {r7}
800209e: b083 sub sp, #12
80020a0: af00 add r7, sp, #0
80020a2: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
80020a4: 687b ldr r3, [r7, #4]
80020a6: 689b ldr r3, [r3, #8]
80020a8: f003 031f and.w r3, r3, #31
}
80020ac: 4618 mov r0, r3
80020ae: 370c adds r7, #12
80020b0: 46bd mov sp, r7
80020b2: f85d 7b04 ldr.w r7, [sp], #4
80020b6: 4770 bx lr
080020b8 <LL_ADC_GetMultiDMATransfer>:
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
{
80020b8: b480 push {r7}
80020ba: b083 sub sp, #12
80020bc: af00 add r7, sp, #0
80020be: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
80020c0: 687b ldr r3, [r7, #4]
80020c2: 689b ldr r3, [r3, #8]
80020c4: f403 4360 and.w r3, r3, #57344 @ 0xe000
}
80020c8: 4618 mov r0, r3
80020ca: 370c adds r7, #12
80020cc: 46bd mov sp, r7
80020ce: f85d 7b04 ldr.w r7, [sp], #4
80020d2: 4770 bx lr
080020d4 <LL_ADC_DisableDeepPowerDown>:
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
80020d4: b480 push {r7}
80020d6: b083 sub sp, #12
80020d8: af00 add r7, sp, #0
80020da: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
80020dc: 687b ldr r3, [r7, #4]
80020de: 689b ldr r3, [r3, #8]
80020e0: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000
80020e4: f023 033f bic.w r3, r3, #63 @ 0x3f
80020e8: 687a ldr r2, [r7, #4]
80020ea: 6093 str r3, [r2, #8]
}
80020ec: bf00 nop
80020ee: 370c adds r7, #12
80020f0: 46bd mov sp, r7
80020f2: f85d 7b04 ldr.w r7, [sp], #4
80020f6: 4770 bx lr
080020f8 <LL_ADC_IsDeepPowerDownEnabled>:
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
{
80020f8: b480 push {r7}
80020fa: b083 sub sp, #12
80020fc: af00 add r7, sp, #0
80020fe: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
8002100: 687b ldr r3, [r7, #4]
8002102: 689b ldr r3, [r3, #8]
8002104: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8002108: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
800210c: d101 bne.n 8002112 <LL_ADC_IsDeepPowerDownEnabled+0x1a>
800210e: 2301 movs r3, #1
8002110: e000 b.n 8002114 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
8002112: 2300 movs r3, #0
}
8002114: 4618 mov r0, r3
8002116: 370c adds r7, #12
8002118: 46bd mov sp, r7
800211a: f85d 7b04 ldr.w r7, [sp], #4
800211e: 4770 bx lr
08002120 <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
8002120: b480 push {r7}
8002122: b083 sub sp, #12
8002124: af00 add r7, sp, #0
8002126: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8002128: 687b ldr r3, [r7, #4]
800212a: 689b ldr r3, [r3, #8]
800212c: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000
8002130: f023 033f bic.w r3, r3, #63 @ 0x3f
8002134: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000
8002138: 687b ldr r3, [r7, #4]
800213a: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
800213c: bf00 nop
800213e: 370c adds r7, #12
8002140: 46bd mov sp, r7
8002142: f85d 7b04 ldr.w r7, [sp], #4
8002146: 4770 bx lr
08002148 <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
{
8002148: b480 push {r7}
800214a: b083 sub sp, #12
800214c: af00 add r7, sp, #0
800214e: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8002150: 687b ldr r3, [r7, #4]
8002152: 689b ldr r3, [r3, #8]
8002154: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002158: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800215c: d101 bne.n 8002162 <LL_ADC_IsInternalRegulatorEnabled+0x1a>
800215e: 2301 movs r3, #1
8002160: e000 b.n 8002164 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
8002162: 2300 movs r3, #0
}
8002164: 4618 mov r0, r3
8002166: 370c adds r7, #12
8002168: 46bd mov sp, r7
800216a: f85d 7b04 ldr.w r7, [sp], #4
800216e: 4770 bx lr
08002170 <LL_ADC_Enable>:
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
8002170: b480 push {r7}
8002172: b083 sub sp, #12
8002174: af00 add r7, sp, #0
8002176: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8002178: 687b ldr r3, [r7, #4]
800217a: 689b ldr r3, [r3, #8]
800217c: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8002180: f023 033f bic.w r3, r3, #63 @ 0x3f
8002184: f043 0201 orr.w r2, r3, #1
8002188: 687b ldr r3, [r7, #4]
800218a: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
800218c: bf00 nop
800218e: 370c adds r7, #12
8002190: 46bd mov sp, r7
8002192: f85d 7b04 ldr.w r7, [sp], #4
8002196: 4770 bx lr
08002198 <LL_ADC_Disable>:
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
8002198: b480 push {r7}
800219a: b083 sub sp, #12
800219c: af00 add r7, sp, #0
800219e: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
80021a0: 687b ldr r3, [r7, #4]
80021a2: 689b ldr r3, [r3, #8]
80021a4: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
80021a8: f023 033f bic.w r3, r3, #63 @ 0x3f
80021ac: f043 0202 orr.w r2, r3, #2
80021b0: 687b ldr r3, [r7, #4]
80021b2: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADDIS);
}
80021b4: bf00 nop
80021b6: 370c adds r7, #12
80021b8: 46bd mov sp, r7
80021ba: f85d 7b04 ldr.w r7, [sp], #4
80021be: 4770 bx lr
080021c0 <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
{
80021c0: b480 push {r7}
80021c2: b083 sub sp, #12
80021c4: af00 add r7, sp, #0
80021c6: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80021c8: 687b ldr r3, [r7, #4]
80021ca: 689b ldr r3, [r3, #8]
80021cc: f003 0301 and.w r3, r3, #1
80021d0: 2b01 cmp r3, #1
80021d2: d101 bne.n 80021d8 <LL_ADC_IsEnabled+0x18>
80021d4: 2301 movs r3, #1
80021d6: e000 b.n 80021da <LL_ADC_IsEnabled+0x1a>
80021d8: 2300 movs r3, #0
}
80021da: 4618 mov r0, r3
80021dc: 370c adds r7, #12
80021de: 46bd mov sp, r7
80021e0: f85d 7b04 ldr.w r7, [sp], #4
80021e4: 4770 bx lr
080021e6 <LL_ADC_IsDisableOngoing>:
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
{
80021e6: b480 push {r7}
80021e8: b083 sub sp, #12
80021ea: af00 add r7, sp, #0
80021ec: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
80021ee: 687b ldr r3, [r7, #4]
80021f0: 689b ldr r3, [r3, #8]
80021f2: f003 0302 and.w r3, r3, #2
80021f6: 2b02 cmp r3, #2
80021f8: d101 bne.n 80021fe <LL_ADC_IsDisableOngoing+0x18>
80021fa: 2301 movs r3, #1
80021fc: e000 b.n 8002200 <LL_ADC_IsDisableOngoing+0x1a>
80021fe: 2300 movs r3, #0
}
8002200: 4618 mov r0, r3
8002202: 370c adds r7, #12
8002204: 46bd mov sp, r7
8002206: f85d 7b04 ldr.w r7, [sp], #4
800220a: 4770 bx lr
0800220c <LL_ADC_REG_StartConversion>:
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
800220c: b480 push {r7}
800220e: b083 sub sp, #12
8002210: af00 add r7, sp, #0
8002212: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8002214: 687b ldr r3, [r7, #4]
8002216: 689b ldr r3, [r3, #8]
8002218: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
800221c: f023 033f bic.w r3, r3, #63 @ 0x3f
8002220: f043 0204 orr.w r2, r3, #4
8002224: 687b ldr r3, [r7, #4]
8002226: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
8002228: bf00 nop
800222a: 370c adds r7, #12
800222c: 46bd mov sp, r7
800222e: f85d 7b04 ldr.w r7, [sp], #4
8002232: 4770 bx lr
08002234 <LL_ADC_REG_StopConversion>:
* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
{
8002234: b480 push {r7}
8002236: b083 sub sp, #12
8002238: af00 add r7, sp, #0
800223a: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
800223c: 687b ldr r3, [r7, #4]
800223e: 689b ldr r3, [r3, #8]
8002240: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8002244: f023 033f bic.w r3, r3, #63 @ 0x3f
8002248: f043 0210 orr.w r2, r3, #16
800224c: 687b ldr r3, [r7, #4]
800224e: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTP);
}
8002250: bf00 nop
8002252: 370c adds r7, #12
8002254: 46bd mov sp, r7
8002256: f85d 7b04 ldr.w r7, [sp], #4
800225a: 4770 bx lr
0800225c <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
800225c: b480 push {r7}
800225e: b083 sub sp, #12
8002260: af00 add r7, sp, #0
8002262: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8002264: 687b ldr r3, [r7, #4]
8002266: 689b ldr r3, [r3, #8]
8002268: f003 0304 and.w r3, r3, #4
800226c: 2b04 cmp r3, #4
800226e: d101 bne.n 8002274 <LL_ADC_REG_IsConversionOngoing+0x18>
8002270: 2301 movs r3, #1
8002272: e000 b.n 8002276 <LL_ADC_REG_IsConversionOngoing+0x1a>
8002274: 2300 movs r3, #0
}
8002276: 4618 mov r0, r3
8002278: 370c adds r7, #12
800227a: 46bd mov sp, r7
800227c: f85d 7b04 ldr.w r7, [sp], #4
8002280: 4770 bx lr
08002282 <LL_ADC_INJ_StopConversion>:
* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
{
8002282: b480 push {r7}
8002284: b083 sub sp, #12
8002286: af00 add r7, sp, #0
8002288: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
800228a: 687b ldr r3, [r7, #4]
800228c: 689b ldr r3, [r3, #8]
800228e: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8002292: f023 033f bic.w r3, r3, #63 @ 0x3f
8002296: f043 0220 orr.w r2, r3, #32
800229a: 687b ldr r3, [r7, #4]
800229c: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_JADSTP);
}
800229e: bf00 nop
80022a0: 370c adds r7, #12
80022a2: 46bd mov sp, r7
80022a4: f85d 7b04 ldr.w r7, [sp], #4
80022a8: 4770 bx lr
080022aa <LL_ADC_INJ_IsConversionOngoing>:
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
80022aa: b480 push {r7}
80022ac: b083 sub sp, #12
80022ae: af00 add r7, sp, #0
80022b0: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
80022b2: 687b ldr r3, [r7, #4]
80022b4: 689b ldr r3, [r3, #8]
80022b6: f003 0308 and.w r3, r3, #8
80022ba: 2b08 cmp r3, #8
80022bc: d101 bne.n 80022c2 <LL_ADC_INJ_IsConversionOngoing+0x18>
80022be: 2301 movs r3, #1
80022c0: e000 b.n 80022c4 <LL_ADC_INJ_IsConversionOngoing+0x1a>
80022c2: 2300 movs r3, #0
}
80022c4: 4618 mov r0, r3
80022c6: 370c adds r7, #12
80022c8: 46bd mov sp, r7
80022ca: f85d 7b04 ldr.w r7, [sp], #4
80022ce: 4770 bx lr
080022d0 <HAL_ADC_Init>:
* without disabling the other ADCs.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
80022d0: b590 push {r4, r7, lr}
80022d2: b089 sub sp, #36 @ 0x24
80022d4: af00 add r7, sp, #0
80022d6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80022d8: 2300 movs r3, #0
80022da: 77fb strb r3, [r7, #31]
uint32_t tmp_cfgr;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0UL;
80022dc: 2300 movs r3, #0
80022de: 60fb str r3, [r7, #12]
/* Check ADC handle */
if (hadc == NULL)
80022e0: 687b ldr r3, [r7, #4]
80022e2: 2b00 cmp r3, #0
80022e4: d101 bne.n 80022ea <HAL_ADC_Init+0x1a>
{
return HAL_ERROR;
80022e6: 2301 movs r3, #1
80022e8: e167 b.n 80025ba <HAL_ADC_Init+0x2ea>
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
80022ea: 687b ldr r3, [r7, #4]
80022ec: 695b ldr r3, [r3, #20]
80022ee: 2b00 cmp r3, #0
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
80022f0: 687b ldr r3, [r7, #4]
80022f2: 6ddb ldr r3, [r3, #92] @ 0x5c
80022f4: 2b00 cmp r3, #0
80022f6: d109 bne.n 800230c <HAL_ADC_Init+0x3c>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
80022f8: 6878 ldr r0, [r7, #4]
80022fa: f7ff fb23 bl 8001944 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
80022fe: 687b ldr r3, [r7, #4]
8002300: 2200 movs r2, #0
8002302: 661a str r2, [r3, #96] @ 0x60
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
8002304: 687b ldr r3, [r7, #4]
8002306: 2200 movs r2, #0
8002308: f883 2058 strb.w r2, [r3, #88] @ 0x58
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
800230c: 687b ldr r3, [r7, #4]
800230e: 681b ldr r3, [r3, #0]
8002310: 4618 mov r0, r3
8002312: f7ff fef1 bl 80020f8 <LL_ADC_IsDeepPowerDownEnabled>
8002316: 4603 mov r3, r0
8002318: 2b00 cmp r3, #0
800231a: d004 beq.n 8002326 <HAL_ADC_Init+0x56>
{
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
800231c: 687b ldr r3, [r7, #4]
800231e: 681b ldr r3, [r3, #0]
8002320: 4618 mov r0, r3
8002322: f7ff fed7 bl 80020d4 <LL_ADC_DisableDeepPowerDown>
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8002326: 687b ldr r3, [r7, #4]
8002328: 681b ldr r3, [r3, #0]
800232a: 4618 mov r0, r3
800232c: f7ff ff0c bl 8002148 <LL_ADC_IsInternalRegulatorEnabled>
8002330: 4603 mov r3, r0
8002332: 2b00 cmp r3, #0
8002334: d115 bne.n 8002362 <HAL_ADC_Init+0x92>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
8002336: 687b ldr r3, [r7, #4]
8002338: 681b ldr r3, [r3, #0]
800233a: 4618 mov r0, r3
800233c: f7ff fef0 bl 8002120 <LL_ADC_EnableInternalRegulator>
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002340: 4ba0 ldr r3, [pc, #640] @ (80025c4 <HAL_ADC_Init+0x2f4>)
8002342: 681b ldr r3, [r3, #0]
8002344: 099b lsrs r3, r3, #6
8002346: 4aa0 ldr r2, [pc, #640] @ (80025c8 <HAL_ADC_Init+0x2f8>)
8002348: fba2 2303 umull r2, r3, r2, r3
800234c: 099b lsrs r3, r3, #6
800234e: 3301 adds r3, #1
8002350: 005b lsls r3, r3, #1
8002352: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002354: e002 b.n 800235c <HAL_ADC_Init+0x8c>
{
wait_loop_index--;
8002356: 68fb ldr r3, [r7, #12]
8002358: 3b01 subs r3, #1
800235a: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
800235c: 68fb ldr r3, [r7, #12]
800235e: 2b00 cmp r3, #0
8002360: d1f9 bne.n 8002356 <HAL_ADC_Init+0x86>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8002362: 687b ldr r3, [r7, #4]
8002364: 681b ldr r3, [r3, #0]
8002366: 4618 mov r0, r3
8002368: f7ff feee bl 8002148 <LL_ADC_IsInternalRegulatorEnabled>
800236c: 4603 mov r3, r0
800236e: 2b00 cmp r3, #0
8002370: d10d bne.n 800238e <HAL_ADC_Init+0xbe>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002372: 687b ldr r3, [r7, #4]
8002374: 6ddb ldr r3, [r3, #92] @ 0x5c
8002376: f043 0210 orr.w r2, r3, #16
800237a: 687b ldr r3, [r7, #4]
800237c: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800237e: 687b ldr r3, [r7, #4]
8002380: 6e1b ldr r3, [r3, #96] @ 0x60
8002382: f043 0201 orr.w r2, r3, #1
8002386: 687b ldr r3, [r7, #4]
8002388: 661a str r2, [r3, #96] @ 0x60
tmp_hal_status = HAL_ERROR;
800238a: 2301 movs r3, #1
800238c: 77fb strb r3, [r7, #31]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
800238e: 687b ldr r3, [r7, #4]
8002390: 681b ldr r3, [r3, #0]
8002392: 4618 mov r0, r3
8002394: f7ff ff62 bl 800225c <LL_ADC_REG_IsConversionOngoing>
8002398: 6178 str r0, [r7, #20]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
800239a: 687b ldr r3, [r7, #4]
800239c: 6ddb ldr r3, [r3, #92] @ 0x5c
800239e: f003 0310 and.w r3, r3, #16
80023a2: 2b00 cmp r3, #0
80023a4: f040 8100 bne.w 80025a8 <HAL_ADC_Init+0x2d8>
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
80023a8: 697b ldr r3, [r7, #20]
80023aa: 2b00 cmp r3, #0
80023ac: f040 80fc bne.w 80025a8 <HAL_ADC_Init+0x2d8>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
80023b0: 687b ldr r3, [r7, #4]
80023b2: 6ddb ldr r3, [r3, #92] @ 0x5c
80023b4: f423 7381 bic.w r3, r3, #258 @ 0x102
80023b8: f043 0202 orr.w r2, r3, #2
80023bc: 687b ldr r3, [r7, #4]
80023be: 65da str r2, [r3, #92] @ 0x5c
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80023c0: 687b ldr r3, [r7, #4]
80023c2: 681b ldr r3, [r3, #0]
80023c4: 4618 mov r0, r3
80023c6: f7ff fefb bl 80021c0 <LL_ADC_IsEnabled>
80023ca: 4603 mov r3, r0
80023cc: 2b00 cmp r3, #0
80023ce: d111 bne.n 80023f4 <HAL_ADC_Init+0x124>
{
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80023d0: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
80023d4: f7ff fef4 bl 80021c0 <LL_ADC_IsEnabled>
80023d8: 4604 mov r4, r0
80023da: 487c ldr r0, [pc, #496] @ (80025cc <HAL_ADC_Init+0x2fc>)
80023dc: f7ff fef0 bl 80021c0 <LL_ADC_IsEnabled>
80023e0: 4603 mov r3, r0
80023e2: 4323 orrs r3, r4
80023e4: 2b00 cmp r3, #0
80023e6: d105 bne.n 80023f4 <HAL_ADC_Init+0x124>
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
/* HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
80023e8: 687b ldr r3, [r7, #4]
80023ea: 685b ldr r3, [r3, #4]
80023ec: 4619 mov r1, r3
80023ee: 4878 ldr r0, [pc, #480] @ (80025d0 <HAL_ADC_Init+0x300>)
80023f0: f7ff fcf4 bl 8001ddc <LL_ADC_SetCommonClock>
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* - continuous conversion mode Init.ContinuousConvMode */
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80023f4: 687b ldr r3, [r7, #4]
80023f6: 7f5b ldrb r3, [r3, #29]
80023f8: 035a lsls r2, r3, #13
hadc->Init.Overrun |
80023fa: 687b ldr r3, [r7, #4]
80023fc: 6bdb ldr r3, [r3, #60] @ 0x3c
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80023fe: 431a orrs r2, r3
hadc->Init.DataAlign |
8002400: 687b ldr r3, [r7, #4]
8002402: 68db ldr r3, [r3, #12]
hadc->Init.Overrun |
8002404: 431a orrs r2, r3
hadc->Init.Resolution |
8002406: 687b ldr r3, [r7, #4]
8002408: 689b ldr r3, [r3, #8]
hadc->Init.DataAlign |
800240a: 431a orrs r2, r3
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
800240c: 687b ldr r3, [r7, #4]
800240e: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8002412: 041b lsls r3, r3, #16
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8002414: 4313 orrs r3, r2
8002416: 61bb str r3, [r7, #24]
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8002418: 687b ldr r3, [r7, #4]
800241a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
800241e: 2b01 cmp r3, #1
8002420: d106 bne.n 8002430 <HAL_ADC_Init+0x160>
{
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
8002422: 687b ldr r3, [r7, #4]
8002424: 6a9b ldr r3, [r3, #40] @ 0x28
8002426: 3b01 subs r3, #1
8002428: 045b lsls r3, r3, #17
800242a: 69ba ldr r2, [r7, #24]
800242c: 4313 orrs r3, r2
800242e: 61bb str r3, [r7, #24]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8002430: 687b ldr r3, [r7, #4]
8002432: 6adb ldr r3, [r3, #44] @ 0x2c
8002434: 2b00 cmp r3, #0
8002436: d009 beq.n 800244c <HAL_ADC_Init+0x17c>
{
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8002438: 687b ldr r3, [r7, #4]
800243a: 6adb ldr r3, [r3, #44] @ 0x2c
800243c: f403 7278 and.w r2, r3, #992 @ 0x3e0
| hadc->Init.ExternalTrigConvEdge
8002440: 687b ldr r3, [r7, #4]
8002442: 6b1b ldr r3, [r3, #48] @ 0x30
8002444: 4313 orrs r3, r2
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8002446: 69ba ldr r2, [r7, #24]
8002448: 4313 orrs r3, r2
800244a: 61bb str r3, [r7, #24]
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
800244c: 687b ldr r3, [r7, #4]
800244e: 681b ldr r3, [r3, #0]
8002450: 68da ldr r2, [r3, #12]
8002452: 4b60 ldr r3, [pc, #384] @ (80025d4 <HAL_ADC_Init+0x304>)
8002454: 4013 ands r3, r2
8002456: 687a ldr r2, [r7, #4]
8002458: 6812 ldr r2, [r2, #0]
800245a: 69b9 ldr r1, [r7, #24]
800245c: 430b orrs r3, r1
800245e: 60d3 str r3, [r2, #12]
/* Configuration of sampling mode */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
8002460: 687b ldr r3, [r7, #4]
8002462: 681b ldr r3, [r3, #0]
8002464: 691b ldr r3, [r3, #16]
8002466: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000
800246a: 687b ldr r3, [r7, #4]
800246c: 6b5a ldr r2, [r3, #52] @ 0x34
800246e: 687b ldr r3, [r7, #4]
8002470: 681b ldr r3, [r3, #0]
8002472: 430a orrs r2, r1
8002474: 611a str r2, [r3, #16]
/* conversion on going on regular and injected groups: */
/* - Gain Compensation Init.GainCompensation */
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002476: 687b ldr r3, [r7, #4]
8002478: 681b ldr r3, [r3, #0]
800247a: 4618 mov r0, r3
800247c: f7ff ff15 bl 80022aa <LL_ADC_INJ_IsConversionOngoing>
8002480: 6138 str r0, [r7, #16]
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8002482: 697b ldr r3, [r7, #20]
8002484: 2b00 cmp r3, #0
8002486: d16d bne.n 8002564 <HAL_ADC_Init+0x294>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8002488: 693b ldr r3, [r7, #16]
800248a: 2b00 cmp r3, #0
800248c: d16a bne.n 8002564 <HAL_ADC_Init+0x294>
)
{
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800248e: 687b ldr r3, [r7, #4]
8002490: 7f1b ldrb r3, [r3, #28]
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
8002492: 039a lsls r2, r3, #14
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
8002494: 687b ldr r3, [r7, #4]
8002496: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
800249a: 005b lsls r3, r3, #1
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
800249c: 4313 orrs r3, r2
800249e: 61bb str r3, [r7, #24]
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
80024a0: 687b ldr r3, [r7, #4]
80024a2: 681b ldr r3, [r3, #0]
80024a4: 68db ldr r3, [r3, #12]
80024a6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80024aa: f023 0302 bic.w r3, r3, #2
80024ae: 687a ldr r2, [r7, #4]
80024b0: 6812 ldr r2, [r2, #0]
80024b2: 69b9 ldr r1, [r7, #24]
80024b4: 430b orrs r3, r1
80024b6: 60d3 str r3, [r2, #12]
if (hadc->Init.GainCompensation != 0UL)
80024b8: 687b ldr r3, [r7, #4]
80024ba: 691b ldr r3, [r3, #16]
80024bc: 2b00 cmp r3, #0
80024be: d017 beq.n 80024f0 <HAL_ADC_Init+0x220>
{
SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
80024c0: 687b ldr r3, [r7, #4]
80024c2: 681b ldr r3, [r3, #0]
80024c4: 691a ldr r2, [r3, #16]
80024c6: 687b ldr r3, [r7, #4]
80024c8: 681b ldr r3, [r3, #0]
80024ca: f442 3280 orr.w r2, r2, #65536 @ 0x10000
80024ce: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
80024d0: 687b ldr r3, [r7, #4]
80024d2: 681b ldr r3, [r3, #0]
80024d4: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
80024d8: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
80024dc: f023 033f bic.w r3, r3, #63 @ 0x3f
80024e0: 687a ldr r2, [r7, #4]
80024e2: 6911 ldr r1, [r2, #16]
80024e4: 687a ldr r2, [r7, #4]
80024e6: 6812 ldr r2, [r2, #0]
80024e8: 430b orrs r3, r1
80024ea: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
80024ee: e013 b.n 8002518 <HAL_ADC_Init+0x248>
}
else
{
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
80024f0: 687b ldr r3, [r7, #4]
80024f2: 681b ldr r3, [r3, #0]
80024f4: 691a ldr r2, [r3, #16]
80024f6: 687b ldr r3, [r7, #4]
80024f8: 681b ldr r3, [r3, #0]
80024fa: f422 3280 bic.w r2, r2, #65536 @ 0x10000
80024fe: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
8002500: 687b ldr r3, [r7, #4]
8002502: 681b ldr r3, [r3, #0]
8002504: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
8002508: 687a ldr r2, [r7, #4]
800250a: 6812 ldr r2, [r2, #0]
800250c: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8002510: f023 033f bic.w r3, r3, #63 @ 0x3f
8002514: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
}
if (hadc->Init.OversamplingMode == ENABLE)
8002518: 687b ldr r3, [r7, #4]
800251a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
800251e: 2b01 cmp r3, #1
8002520: d118 bne.n 8002554 <HAL_ADC_Init+0x284>
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2,
8002522: 687b ldr r3, [r7, #4]
8002524: 681b ldr r3, [r3, #0]
8002526: 691b ldr r3, [r3, #16]
8002528: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
800252c: f023 0304 bic.w r3, r3, #4
8002530: 687a ldr r2, [r7, #4]
8002532: 6c51 ldr r1, [r2, #68] @ 0x44
8002534: 687a ldr r2, [r7, #4]
8002536: 6c92 ldr r2, [r2, #72] @ 0x48
8002538: 4311 orrs r1, r2
800253a: 687a ldr r2, [r7, #4]
800253c: 6cd2 ldr r2, [r2, #76] @ 0x4c
800253e: 4311 orrs r1, r2
8002540: 687a ldr r2, [r7, #4]
8002542: 6d12 ldr r2, [r2, #80] @ 0x50
8002544: 430a orrs r2, r1
8002546: 431a orrs r2, r3
8002548: 687b ldr r3, [r7, #4]
800254a: 681b ldr r3, [r3, #0]
800254c: f042 0201 orr.w r2, r2, #1
8002550: 611a str r2, [r3, #16]
8002552: e007 b.n 8002564 <HAL_ADC_Init+0x294>
);
}
else
{
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
8002554: 687b ldr r3, [r7, #4]
8002556: 681b ldr r3, [r3, #0]
8002558: 691a ldr r2, [r3, #16]
800255a: 687b ldr r3, [r7, #4]
800255c: 681b ldr r3, [r3, #0]
800255e: f022 0201 bic.w r2, r2, #1
8002562: 611a str r2, [r3, #16]
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8002564: 687b ldr r3, [r7, #4]
8002566: 695b ldr r3, [r3, #20]
8002568: 2b01 cmp r3, #1
800256a: d10c bne.n 8002586 <HAL_ADC_Init+0x2b6>
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
800256c: 687b ldr r3, [r7, #4]
800256e: 681b ldr r3, [r3, #0]
8002570: 6b1b ldr r3, [r3, #48] @ 0x30
8002572: f023 010f bic.w r1, r3, #15
8002576: 687b ldr r3, [r7, #4]
8002578: 6a1b ldr r3, [r3, #32]
800257a: 1e5a subs r2, r3, #1
800257c: 687b ldr r3, [r7, #4]
800257e: 681b ldr r3, [r3, #0]
8002580: 430a orrs r2, r1
8002582: 631a str r2, [r3, #48] @ 0x30
8002584: e007 b.n 8002596 <HAL_ADC_Init+0x2c6>
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
8002586: 687b ldr r3, [r7, #4]
8002588: 681b ldr r3, [r3, #0]
800258a: 6b1a ldr r2, [r3, #48] @ 0x30
800258c: 687b ldr r3, [r7, #4]
800258e: 681b ldr r3, [r3, #0]
8002590: f022 020f bic.w r2, r2, #15
8002594: 631a str r2, [r3, #48] @ 0x30
}
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
8002596: 687b ldr r3, [r7, #4]
8002598: 6ddb ldr r3, [r3, #92] @ 0x5c
800259a: f023 0303 bic.w r3, r3, #3
800259e: f043 0201 orr.w r2, r3, #1
80025a2: 687b ldr r3, [r7, #4]
80025a4: 65da str r2, [r3, #92] @ 0x5c
80025a6: e007 b.n 80025b8 <HAL_ADC_Init+0x2e8>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80025a8: 687b ldr r3, [r7, #4]
80025aa: 6ddb ldr r3, [r3, #92] @ 0x5c
80025ac: f043 0210 orr.w r2, r3, #16
80025b0: 687b ldr r3, [r7, #4]
80025b2: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
80025b4: 2301 movs r3, #1
80025b6: 77fb strb r3, [r7, #31]
}
/* Return function status */
return tmp_hal_status;
80025b8: 7ffb ldrb r3, [r7, #31]
}
80025ba: 4618 mov r0, r3
80025bc: 3724 adds r7, #36 @ 0x24
80025be: 46bd mov sp, r7
80025c0: bd90 pop {r4, r7, pc}
80025c2: bf00 nop
80025c4: 20000018 .word 0x20000018
80025c8: 053e2d63 .word 0x053e2d63
80025cc: 50000100 .word 0x50000100
80025d0: 50000300 .word 0x50000300
80025d4: fff04007 .word 0xfff04007
080025d8 <HAL_ADC_Start>:
* if ADC is master, ADC is enabled and multimode conversion is started.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
{
80025d8: b580 push {r7, lr}
80025da: b086 sub sp, #24
80025dc: af00 add r7, sp, #0
80025de: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80025e0: 4859 ldr r0, [pc, #356] @ (8002748 <HAL_ADC_Start+0x170>)
80025e2: f7ff fd5b bl 800209c <LL_ADC_GetMultimode>
80025e6: 6138 str r0, [r7, #16]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80025e8: 687b ldr r3, [r7, #4]
80025ea: 681b ldr r3, [r3, #0]
80025ec: 4618 mov r0, r3
80025ee: f7ff fe35 bl 800225c <LL_ADC_REG_IsConversionOngoing>
80025f2: 4603 mov r3, r0
80025f4: 2b00 cmp r3, #0
80025f6: f040 809f bne.w 8002738 <HAL_ADC_Start+0x160>
{
/* Process locked */
__HAL_LOCK(hadc);
80025fa: 687b ldr r3, [r7, #4]
80025fc: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8002600: 2b01 cmp r3, #1
8002602: d101 bne.n 8002608 <HAL_ADC_Start+0x30>
8002604: 2302 movs r3, #2
8002606: e09a b.n 800273e <HAL_ADC_Start+0x166>
8002608: 687b ldr r3, [r7, #4]
800260a: 2201 movs r2, #1
800260c: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
8002610: 6878 ldr r0, [r7, #4]
8002612: f000 fe63 bl 80032dc <ADC_Enable>
8002616: 4603 mov r3, r0
8002618: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
800261a: 7dfb ldrb r3, [r7, #23]
800261c: 2b00 cmp r3, #0
800261e: f040 8086 bne.w 800272e <HAL_ADC_Start+0x156>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
8002622: 687b ldr r3, [r7, #4]
8002624: 6ddb ldr r3, [r3, #92] @ 0x5c
8002626: f423 6370 bic.w r3, r3, #3840 @ 0xf00
800262a: f023 0301 bic.w r3, r3, #1
800262e: f443 7280 orr.w r2, r3, #256 @ 0x100
8002632: 687b ldr r3, [r7, #4]
8002634: 65da str r2, [r3, #92] @ 0x5c
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8002636: 687b ldr r3, [r7, #4]
8002638: 681b ldr r3, [r3, #0]
800263a: 4a44 ldr r2, [pc, #272] @ (800274c <HAL_ADC_Start+0x174>)
800263c: 4293 cmp r3, r2
800263e: d002 beq.n 8002646 <HAL_ADC_Start+0x6e>
8002640: 687b ldr r3, [r7, #4]
8002642: 681b ldr r3, [r3, #0]
8002644: e001 b.n 800264a <HAL_ADC_Start+0x72>
8002646: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
800264a: 687a ldr r2, [r7, #4]
800264c: 6812 ldr r2, [r2, #0]
800264e: 4293 cmp r3, r2
8002650: d002 beq.n 8002658 <HAL_ADC_Start+0x80>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8002652: 693b ldr r3, [r7, #16]
8002654: 2b00 cmp r3, #0
8002656: d105 bne.n 8002664 <HAL_ADC_Start+0x8c>
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8002658: 687b ldr r3, [r7, #4]
800265a: 6ddb ldr r3, [r3, #92] @ 0x5c
800265c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8002660: 687b ldr r3, [r7, #4]
8002662: 65da str r2, [r3, #92] @ 0x5c
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8002664: 687b ldr r3, [r7, #4]
8002666: 6ddb ldr r3, [r3, #92] @ 0x5c
8002668: f403 5380 and.w r3, r3, #4096 @ 0x1000
800266c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8002670: d106 bne.n 8002680 <HAL_ADC_Start+0xa8>
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8002672: 687b ldr r3, [r7, #4]
8002674: 6e1b ldr r3, [r3, #96] @ 0x60
8002676: f023 0206 bic.w r2, r3, #6
800267a: 687b ldr r3, [r7, #4]
800267c: 661a str r2, [r3, #96] @ 0x60
800267e: e002 b.n 8002686 <HAL_ADC_Start+0xae>
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8002680: 687b ldr r3, [r7, #4]
8002682: 2200 movs r2, #0
8002684: 661a str r2, [r3, #96] @ 0x60
}
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
8002686: 687b ldr r3, [r7, #4]
8002688: 681b ldr r3, [r3, #0]
800268a: 221c movs r2, #28
800268c: 601a str r2, [r3, #0]
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
800268e: 687b ldr r3, [r7, #4]
8002690: 2200 movs r2, #0
8002692: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Case of multimode enabled (when multimode feature is available): */
/* - if ADC is slave and dual regular conversions are enabled, ADC is */
/* enabled only (conversion is not started), */
/* - if ADC is master, ADC is enabled and conversion is started. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8002696: 687b ldr r3, [r7, #4]
8002698: 681b ldr r3, [r3, #0]
800269a: 4a2c ldr r2, [pc, #176] @ (800274c <HAL_ADC_Start+0x174>)
800269c: 4293 cmp r3, r2
800269e: d002 beq.n 80026a6 <HAL_ADC_Start+0xce>
80026a0: 687b ldr r3, [r7, #4]
80026a2: 681b ldr r3, [r3, #0]
80026a4: e001 b.n 80026aa <HAL_ADC_Start+0xd2>
80026a6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
80026aa: 687a ldr r2, [r7, #4]
80026ac: 6812 ldr r2, [r2, #0]
80026ae: 4293 cmp r3, r2
80026b0: d008 beq.n 80026c4 <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
80026b2: 693b ldr r3, [r7, #16]
80026b4: 2b00 cmp r3, #0
80026b6: d005 beq.n 80026c4 <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
80026b8: 693b ldr r3, [r7, #16]
80026ba: 2b05 cmp r3, #5
80026bc: d002 beq.n 80026c4 <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
80026be: 693b ldr r3, [r7, #16]
80026c0: 2b09 cmp r3, #9
80026c2: d114 bne.n 80026ee <HAL_ADC_Start+0x116>
)
{
/* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
80026c4: 687b ldr r3, [r7, #4]
80026c6: 681b ldr r3, [r3, #0]
80026c8: 68db ldr r3, [r3, #12]
80026ca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80026ce: 2b00 cmp r3, #0
80026d0: d007 beq.n 80026e2 <HAL_ADC_Start+0x10a>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
80026d2: 687b ldr r3, [r7, #4]
80026d4: 6ddb ldr r3, [r3, #92] @ 0x5c
80026d6: f423 5340 bic.w r3, r3, #12288 @ 0x3000
80026da: f443 5280 orr.w r2, r3, #4096 @ 0x1000
80026de: 687b ldr r3, [r7, #4]
80026e0: 65da str r2, [r3, #92] @ 0x5c
}
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
80026e2: 687b ldr r3, [r7, #4]
80026e4: 681b ldr r3, [r3, #0]
80026e6: 4618 mov r0, r3
80026e8: f7ff fd90 bl 800220c <LL_ADC_REG_StartConversion>
80026ec: e026 b.n 800273c <HAL_ADC_Start+0x164>
}
else
{
/* ADC instance is a multimode slave instance with multimode regular conversions enabled */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
80026ee: 687b ldr r3, [r7, #4]
80026f0: 6ddb ldr r3, [r3, #92] @ 0x5c
80026f2: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
80026f6: 687b ldr r3, [r7, #4]
80026f8: 65da str r2, [r3, #92] @ 0x5c
/* if Master ADC JAUTO bit is set, update Slave State in setting
HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
80026fa: 687b ldr r3, [r7, #4]
80026fc: 681b ldr r3, [r3, #0]
80026fe: 4a13 ldr r2, [pc, #76] @ (800274c <HAL_ADC_Start+0x174>)
8002700: 4293 cmp r3, r2
8002702: d002 beq.n 800270a <HAL_ADC_Start+0x132>
8002704: 687b ldr r3, [r7, #4]
8002706: 681b ldr r3, [r3, #0]
8002708: e001 b.n 800270e <HAL_ADC_Start+0x136>
800270a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
800270e: 60fb str r3, [r7, #12]
if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
8002710: 68fb ldr r3, [r7, #12]
8002712: 68db ldr r3, [r3, #12]
8002714: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002718: 2b00 cmp r3, #0
800271a: d00f beq.n 800273c <HAL_ADC_Start+0x164>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
800271c: 687b ldr r3, [r7, #4]
800271e: 6ddb ldr r3, [r3, #92] @ 0x5c
8002720: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8002724: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8002728: 687b ldr r3, [r7, #4]
800272a: 65da str r2, [r3, #92] @ 0x5c
800272c: e006 b.n 800273c <HAL_ADC_Start+0x164>
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
800272e: 687b ldr r3, [r7, #4]
8002730: 2200 movs r2, #0
8002732: f883 2058 strb.w r2, [r3, #88] @ 0x58
8002736: e001 b.n 800273c <HAL_ADC_Start+0x164>
}
}
else
{
tmp_hal_status = HAL_BUSY;
8002738: 2302 movs r3, #2
800273a: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800273c: 7dfb ldrb r3, [r7, #23]
}
800273e: 4618 mov r0, r3
8002740: 3718 adds r7, #24
8002742: 46bd mov sp, r7
8002744: bd80 pop {r7, pc}
8002746: bf00 nop
8002748: 50000300 .word 0x50000300
800274c: 50000100 .word 0x50000100
08002750 <HAL_ADC_Stop>:
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
{
8002750: b580 push {r7, lr}
8002752: b084 sub sp, #16
8002754: af00 add r7, sp, #0
8002756: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
8002758: 687b ldr r3, [r7, #4]
800275a: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
800275e: 2b01 cmp r3, #1
8002760: d101 bne.n 8002766 <HAL_ADC_Stop+0x16>
8002762: 2302 movs r3, #2
8002764: e023 b.n 80027ae <HAL_ADC_Stop+0x5e>
8002766: 687b ldr r3, [r7, #4]
8002768: 2201 movs r2, #1
800276a: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
800276e: 2103 movs r1, #3
8002770: 6878 ldr r0, [r7, #4]
8002772: f000 fcf7 bl 8003164 <ADC_ConversionStop>
8002776: 4603 mov r3, r0
8002778: 73fb strb r3, [r7, #15]
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
800277a: 7bfb ldrb r3, [r7, #15]
800277c: 2b00 cmp r3, #0
800277e: d111 bne.n 80027a4 <HAL_ADC_Stop+0x54>
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
8002780: 6878 ldr r0, [r7, #4]
8002782: f000 fe31 bl 80033e8 <ADC_Disable>
8002786: 4603 mov r3, r0
8002788: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
800278a: 7bfb ldrb r3, [r7, #15]
800278c: 2b00 cmp r3, #0
800278e: d109 bne.n 80027a4 <HAL_ADC_Stop+0x54>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002790: 687b ldr r3, [r7, #4]
8002792: 6ddb ldr r3, [r3, #92] @ 0x5c
8002794: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8002798: f023 0301 bic.w r3, r3, #1
800279c: f043 0201 orr.w r2, r3, #1
80027a0: 687b ldr r3, [r7, #4]
80027a2: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_READY);
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80027a4: 687b ldr r3, [r7, #4]
80027a6: 2200 movs r2, #0
80027a8: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
80027ac: 7bfb ldrb r3, [r7, #15]
}
80027ae: 4618 mov r0, r3
80027b0: 3710 adds r7, #16
80027b2: 46bd mov sp, r7
80027b4: bd80 pop {r7, pc}
...
080027b8 <HAL_ADC_PollForConversion>:
* @param hadc ADC handle
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
80027b8: b580 push {r7, lr}
80027ba: b088 sub sp, #32
80027bc: af00 add r7, sp, #0
80027be: 6078 str r0, [r7, #4]
80027c0: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t tmp_Flag_End;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80027c2: 4867 ldr r0, [pc, #412] @ (8002960 <HAL_ADC_PollForConversion+0x1a8>)
80027c4: f7ff fc6a bl 800209c <LL_ADC_GetMultimode>
80027c8: 6178 str r0, [r7, #20]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* If end of conversion selected to end of sequence conversions */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
80027ca: 687b ldr r3, [r7, #4]
80027cc: 699b ldr r3, [r3, #24]
80027ce: 2b08 cmp r3, #8
80027d0: d102 bne.n 80027d8 <HAL_ADC_PollForConversion+0x20>
{
tmp_Flag_End = ADC_FLAG_EOS;
80027d2: 2308 movs r3, #8
80027d4: 61fb str r3, [r7, #28]
80027d6: e02a b.n 800282e <HAL_ADC_PollForConversion+0x76>
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
80027d8: 697b ldr r3, [r7, #20]
80027da: 2b00 cmp r3, #0
80027dc: d005 beq.n 80027ea <HAL_ADC_PollForConversion+0x32>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
80027de: 697b ldr r3, [r7, #20]
80027e0: 2b05 cmp r3, #5
80027e2: d002 beq.n 80027ea <HAL_ADC_PollForConversion+0x32>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
80027e4: 697b ldr r3, [r7, #20]
80027e6: 2b09 cmp r3, #9
80027e8: d111 bne.n 800280e <HAL_ADC_PollForConversion+0x56>
)
{
/* Check ADC DMA mode in independent mode on ADC group regular */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
80027ea: 687b ldr r3, [r7, #4]
80027ec: 681b ldr r3, [r3, #0]
80027ee: 68db ldr r3, [r3, #12]
80027f0: f003 0301 and.w r3, r3, #1
80027f4: 2b00 cmp r3, #0
80027f6: d007 beq.n 8002808 <HAL_ADC_PollForConversion+0x50>
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80027f8: 687b ldr r3, [r7, #4]
80027fa: 6ddb ldr r3, [r3, #92] @ 0x5c
80027fc: f043 0220 orr.w r2, r3, #32
8002800: 687b ldr r3, [r7, #4]
8002802: 65da str r2, [r3, #92] @ 0x5c
return HAL_ERROR;
8002804: 2301 movs r3, #1
8002806: e0a6 b.n 8002956 <HAL_ADC_PollForConversion+0x19e>
}
else
{
tmp_Flag_End = (ADC_FLAG_EOC);
8002808: 2304 movs r3, #4
800280a: 61fb str r3, [r7, #28]
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
800280c: e00f b.n 800282e <HAL_ADC_PollForConversion+0x76>
}
}
else
{
/* Check ADC DMA mode in multimode on ADC group regular */
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
800280e: 4854 ldr r0, [pc, #336] @ (8002960 <HAL_ADC_PollForConversion+0x1a8>)
8002810: f7ff fc52 bl 80020b8 <LL_ADC_GetMultiDMATransfer>
8002814: 4603 mov r3, r0
8002816: 2b00 cmp r3, #0
8002818: d007 beq.n 800282a <HAL_ADC_PollForConversion+0x72>
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
800281a: 687b ldr r3, [r7, #4]
800281c: 6ddb ldr r3, [r3, #92] @ 0x5c
800281e: f043 0220 orr.w r2, r3, #32
8002822: 687b ldr r3, [r7, #4]
8002824: 65da str r2, [r3, #92] @ 0x5c
return HAL_ERROR;
8002826: 2301 movs r3, #1
8002828: e095 b.n 8002956 <HAL_ADC_PollForConversion+0x19e>
}
else
{
tmp_Flag_End = (ADC_FLAG_EOC);
800282a: 2304 movs r3, #4
800282c: 61fb str r3, [r7, #28]
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
/* Get tick count */
tickstart = HAL_GetTick();
800282e: f7ff fac9 bl 8001dc4 <HAL_GetTick>
8002832: 6138 str r0, [r7, #16]
/* Wait until End of unitary conversion or sequence conversions flag is raised */
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
8002834: e021 b.n 800287a <HAL_ADC_PollForConversion+0xc2>
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
8002836: 683b ldr r3, [r7, #0]
8002838: f1b3 3fff cmp.w r3, #4294967295
800283c: d01d beq.n 800287a <HAL_ADC_PollForConversion+0xc2>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
800283e: f7ff fac1 bl 8001dc4 <HAL_GetTick>
8002842: 4602 mov r2, r0
8002844: 693b ldr r3, [r7, #16]
8002846: 1ad3 subs r3, r2, r3
8002848: 683a ldr r2, [r7, #0]
800284a: 429a cmp r2, r3
800284c: d302 bcc.n 8002854 <HAL_ADC_PollForConversion+0x9c>
800284e: 683b ldr r3, [r7, #0]
8002850: 2b00 cmp r3, #0
8002852: d112 bne.n 800287a <HAL_ADC_PollForConversion+0xc2>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
8002854: 687b ldr r3, [r7, #4]
8002856: 681b ldr r3, [r3, #0]
8002858: 681a ldr r2, [r3, #0]
800285a: 69fb ldr r3, [r7, #28]
800285c: 4013 ands r3, r2
800285e: 2b00 cmp r3, #0
8002860: d10b bne.n 800287a <HAL_ADC_PollForConversion+0xc2>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
8002862: 687b ldr r3, [r7, #4]
8002864: 6ddb ldr r3, [r3, #92] @ 0x5c
8002866: f043 0204 orr.w r2, r3, #4
800286a: 687b ldr r3, [r7, #4]
800286c: 65da str r2, [r3, #92] @ 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
800286e: 687b ldr r3, [r7, #4]
8002870: 2200 movs r2, #0
8002872: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_TIMEOUT;
8002876: 2303 movs r3, #3
8002878: e06d b.n 8002956 <HAL_ADC_PollForConversion+0x19e>
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
800287a: 687b ldr r3, [r7, #4]
800287c: 681b ldr r3, [r3, #0]
800287e: 681a ldr r2, [r3, #0]
8002880: 69fb ldr r3, [r7, #28]
8002882: 4013 ands r3, r2
8002884: 2b00 cmp r3, #0
8002886: d0d6 beq.n 8002836 <HAL_ADC_PollForConversion+0x7e>
}
}
}
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8002888: 687b ldr r3, [r7, #4]
800288a: 6ddb ldr r3, [r3, #92] @ 0x5c
800288c: f443 7200 orr.w r2, r3, #512 @ 0x200
8002890: 687b ldr r3, [r7, #4]
8002892: 65da str r2, [r3, #92] @ 0x5c
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
8002894: 687b ldr r3, [r7, #4]
8002896: 681b ldr r3, [r3, #0]
8002898: 4618 mov r0, r3
800289a: f7ff fb71 bl 8001f80 <LL_ADC_REG_IsTriggerSourceSWStart>
800289e: 4603 mov r3, r0
80028a0: 2b00 cmp r3, #0
80028a2: d01c beq.n 80028de <HAL_ADC_PollForConversion+0x126>
&& (hadc->Init.ContinuousConvMode == DISABLE)
80028a4: 687b ldr r3, [r7, #4]
80028a6: 7f5b ldrb r3, [r3, #29]
80028a8: 2b00 cmp r3, #0
80028aa: d118 bne.n 80028de <HAL_ADC_PollForConversion+0x126>
)
{
/* Check whether end of sequence is reached */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
80028ac: 687b ldr r3, [r7, #4]
80028ae: 681b ldr r3, [r3, #0]
80028b0: 681b ldr r3, [r3, #0]
80028b2: f003 0308 and.w r3, r3, #8
80028b6: 2b08 cmp r3, #8
80028b8: d111 bne.n 80028de <HAL_ADC_PollForConversion+0x126>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80028ba: 687b ldr r3, [r7, #4]
80028bc: 6ddb ldr r3, [r3, #92] @ 0x5c
80028be: f423 7280 bic.w r2, r3, #256 @ 0x100
80028c2: 687b ldr r3, [r7, #4]
80028c4: 65da str r2, [r3, #92] @ 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
80028c6: 687b ldr r3, [r7, #4]
80028c8: 6ddb ldr r3, [r3, #92] @ 0x5c
80028ca: f403 5380 and.w r3, r3, #4096 @ 0x1000
80028ce: 2b00 cmp r3, #0
80028d0: d105 bne.n 80028de <HAL_ADC_PollForConversion+0x126>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
80028d2: 687b ldr r3, [r7, #4]
80028d4: 6ddb ldr r3, [r3, #92] @ 0x5c
80028d6: f043 0201 orr.w r2, r3, #1
80028da: 687b ldr r3, [r7, #4]
80028dc: 65da str r2, [r3, #92] @ 0x5c
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
80028de: 687b ldr r3, [r7, #4]
80028e0: 681b ldr r3, [r3, #0]
80028e2: 4a20 ldr r2, [pc, #128] @ (8002964 <HAL_ADC_PollForConversion+0x1ac>)
80028e4: 4293 cmp r3, r2
80028e6: d002 beq.n 80028ee <HAL_ADC_PollForConversion+0x136>
80028e8: 687b ldr r3, [r7, #4]
80028ea: 681b ldr r3, [r3, #0]
80028ec: e001 b.n 80028f2 <HAL_ADC_PollForConversion+0x13a>
80028ee: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
80028f2: 687a ldr r2, [r7, #4]
80028f4: 6812 ldr r2, [r2, #0]
80028f6: 4293 cmp r3, r2
80028f8: d008 beq.n 800290c <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
80028fa: 697b ldr r3, [r7, #20]
80028fc: 2b00 cmp r3, #0
80028fe: d005 beq.n 800290c <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
8002900: 697b ldr r3, [r7, #20]
8002902: 2b05 cmp r3, #5
8002904: d002 beq.n 800290c <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
8002906: 697b ldr r3, [r7, #20]
8002908: 2b09 cmp r3, #9
800290a: d104 bne.n 8002916 <HAL_ADC_PollForConversion+0x15e>
)
{
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
800290c: 687b ldr r3, [r7, #4]
800290e: 681b ldr r3, [r3, #0]
8002910: 68db ldr r3, [r3, #12]
8002912: 61bb str r3, [r7, #24]
8002914: e00d b.n 8002932 <HAL_ADC_PollForConversion+0x17a>
}
else
{
/* Retrieve Master ADC CFGR register */
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
8002916: 687b ldr r3, [r7, #4]
8002918: 681b ldr r3, [r3, #0]
800291a: 4a12 ldr r2, [pc, #72] @ (8002964 <HAL_ADC_PollForConversion+0x1ac>)
800291c: 4293 cmp r3, r2
800291e: d002 beq.n 8002926 <HAL_ADC_PollForConversion+0x16e>
8002920: 687b ldr r3, [r7, #4]
8002922: 681b ldr r3, [r3, #0]
8002924: e001 b.n 800292a <HAL_ADC_PollForConversion+0x172>
8002926: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
800292a: 60fb str r3, [r7, #12]
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
800292c: 68fb ldr r3, [r7, #12]
800292e: 68db ldr r3, [r3, #12]
8002930: 61bb str r3, [r7, #24]
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear polled flag */
if (tmp_Flag_End == ADC_FLAG_EOS)
8002932: 69fb ldr r3, [r7, #28]
8002934: 2b08 cmp r3, #8
8002936: d104 bne.n 8002942 <HAL_ADC_PollForConversion+0x18a>
{
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
8002938: 687b ldr r3, [r7, #4]
800293a: 681b ldr r3, [r3, #0]
800293c: 2208 movs r2, #8
800293e: 601a str r2, [r3, #0]
8002940: e008 b.n 8002954 <HAL_ADC_PollForConversion+0x19c>
else
{
/* Clear end of conversion EOC flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
8002942: 69bb ldr r3, [r7, #24]
8002944: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002948: 2b00 cmp r3, #0
800294a: d103 bne.n 8002954 <HAL_ADC_PollForConversion+0x19c>
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
800294c: 687b ldr r3, [r7, #4]
800294e: 681b ldr r3, [r3, #0]
8002950: 220c movs r2, #12
8002952: 601a str r2, [r3, #0]
}
}
/* Return function status */
return HAL_OK;
8002954: 2300 movs r3, #0
}
8002956: 4618 mov r0, r3
8002958: 3720 adds r7, #32
800295a: 46bd mov sp, r7
800295c: bd80 pop {r7, pc}
800295e: bf00 nop
8002960: 50000300 .word 0x50000300
8002964: 50000100 .word 0x50000100
08002968 <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
{
8002968: b480 push {r7}
800296a: b083 sub sp, #12
800296c: af00 add r7, sp, #0
800296e: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
8002970: 687b ldr r3, [r7, #4]
8002972: 681b ldr r3, [r3, #0]
8002974: 6c1b ldr r3, [r3, #64] @ 0x40
}
8002976: 4618 mov r0, r3
8002978: 370c adds r7, #12
800297a: 46bd mov sp, r7
800297c: f85d 7b04 ldr.w r7, [sp], #4
8002980: 4770 bx lr
...
08002984 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
{
8002984: b580 push {r7, lr}
8002986: b0b6 sub sp, #216 @ 0xd8
8002988: af00 add r7, sp, #0
800298a: 6078 str r0, [r7, #4]
800298c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800298e: 2300 movs r3, #0
8002990: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
8002994: 2300 movs r3, #0
8002996: 60fb str r3, [r7, #12]
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
}
/* Process locked */
__HAL_LOCK(hadc);
8002998: 687b ldr r3, [r7, #4]
800299a: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
800299e: 2b01 cmp r3, #1
80029a0: d101 bne.n 80029a6 <HAL_ADC_ConfigChannel+0x22>
80029a2: 2302 movs r3, #2
80029a4: e3c8 b.n 8003138 <HAL_ADC_ConfigChannel+0x7b4>
80029a6: 687b ldr r3, [r7, #4]
80029a8: 2201 movs r2, #1
80029aa: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80029ae: 687b ldr r3, [r7, #4]
80029b0: 681b ldr r3, [r3, #0]
80029b2: 4618 mov r0, r3
80029b4: f7ff fc52 bl 800225c <LL_ADC_REG_IsConversionOngoing>
80029b8: 4603 mov r3, r0
80029ba: 2b00 cmp r3, #0
80029bc: f040 83ad bne.w 800311a <HAL_ADC_ConfigChannel+0x796>
{
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
80029c0: 687b ldr r3, [r7, #4]
80029c2: 6818 ldr r0, [r3, #0]
80029c4: 683b ldr r3, [r7, #0]
80029c6: 6859 ldr r1, [r3, #4]
80029c8: 683b ldr r3, [r7, #0]
80029ca: 681b ldr r3, [r3, #0]
80029cc: 461a mov r2, r3
80029ce: f7ff faea bl 8001fa6 <LL_ADC_REG_SetSequencerRanks>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
80029d2: 687b ldr r3, [r7, #4]
80029d4: 681b ldr r3, [r3, #0]
80029d6: 4618 mov r0, r3
80029d8: f7ff fc40 bl 800225c <LL_ADC_REG_IsConversionOngoing>
80029dc: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
80029e0: 687b ldr r3, [r7, #4]
80029e2: 681b ldr r3, [r3, #0]
80029e4: 4618 mov r0, r3
80029e6: f7ff fc60 bl 80022aa <LL_ADC_INJ_IsConversionOngoing>
80029ea: f8c7 00cc str.w r0, [r7, #204] @ 0xcc
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
80029ee: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
80029f2: 2b00 cmp r3, #0
80029f4: f040 81d9 bne.w 8002daa <HAL_ADC_ConfigChannel+0x426>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
80029f8: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
80029fc: 2b00 cmp r3, #0
80029fe: f040 81d4 bne.w 8002daa <HAL_ADC_ConfigChannel+0x426>
)
{
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
8002a02: 683b ldr r3, [r7, #0]
8002a04: 689b ldr r3, [r3, #8]
8002a06: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8002a0a: d10f bne.n 8002a2c <HAL_ADC_ConfigChannel+0xa8>
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
8002a0c: 687b ldr r3, [r7, #4]
8002a0e: 6818 ldr r0, [r3, #0]
8002a10: 683b ldr r3, [r7, #0]
8002a12: 681b ldr r3, [r3, #0]
8002a14: 2200 movs r2, #0
8002a16: 4619 mov r1, r3
8002a18: f7ff faf1 bl 8001ffe <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
8002a1c: 687b ldr r3, [r7, #4]
8002a1e: 681b ldr r3, [r3, #0]
8002a20: f04f 4100 mov.w r1, #2147483648 @ 0x80000000
8002a24: 4618 mov r0, r3
8002a26: f7ff fa98 bl 8001f5a <LL_ADC_SetSamplingTimeCommonConfig>
8002a2a: e00e b.n 8002a4a <HAL_ADC_ConfigChannel+0xc6>
}
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
8002a2c: 687b ldr r3, [r7, #4]
8002a2e: 6818 ldr r0, [r3, #0]
8002a30: 683b ldr r3, [r7, #0]
8002a32: 6819 ldr r1, [r3, #0]
8002a34: 683b ldr r3, [r7, #0]
8002a36: 689b ldr r3, [r3, #8]
8002a38: 461a mov r2, r3
8002a3a: f7ff fae0 bl 8001ffe <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
8002a3e: 687b ldr r3, [r7, #4]
8002a40: 681b ldr r3, [r3, #0]
8002a42: 2100 movs r1, #0
8002a44: 4618 mov r0, r3
8002a46: f7ff fa88 bl 8001f5a <LL_ADC_SetSamplingTimeCommonConfig>
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
8002a4a: 683b ldr r3, [r7, #0]
8002a4c: 695a ldr r2, [r3, #20]
8002a4e: 687b ldr r3, [r7, #4]
8002a50: 681b ldr r3, [r3, #0]
8002a52: 68db ldr r3, [r3, #12]
8002a54: 08db lsrs r3, r3, #3
8002a56: f003 0303 and.w r3, r3, #3
8002a5a: 005b lsls r3, r3, #1
8002a5c: fa02 f303 lsl.w r3, r2, r3
8002a60: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
8002a64: 683b ldr r3, [r7, #0]
8002a66: 691b ldr r3, [r3, #16]
8002a68: 2b04 cmp r3, #4
8002a6a: d022 beq.n 8002ab2 <HAL_ADC_ConfigChannel+0x12e>
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
8002a6c: 687b ldr r3, [r7, #4]
8002a6e: 6818 ldr r0, [r3, #0]
8002a70: 683b ldr r3, [r7, #0]
8002a72: 6919 ldr r1, [r3, #16]
8002a74: 683b ldr r3, [r7, #0]
8002a76: 681a ldr r2, [r3, #0]
8002a78: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8002a7c: f7ff f9e2 bl 8001e44 <LL_ADC_SetOffset>
assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
/* Set ADC selected offset sign & saturation */
LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
8002a80: 687b ldr r3, [r7, #4]
8002a82: 6818 ldr r0, [r3, #0]
8002a84: 683b ldr r3, [r7, #0]
8002a86: 6919 ldr r1, [r3, #16]
8002a88: 683b ldr r3, [r7, #0]
8002a8a: 699b ldr r3, [r3, #24]
8002a8c: 461a mov r2, r3
8002a8e: f7ff fa2e bl 8001eee <LL_ADC_SetOffsetSign>
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
8002a92: 687b ldr r3, [r7, #4]
8002a94: 6818 ldr r0, [r3, #0]
8002a96: 683b ldr r3, [r7, #0]
8002a98: 6919 ldr r1, [r3, #16]
(pConfig->OffsetSaturation == ENABLE) ?
8002a9a: 683b ldr r3, [r7, #0]
8002a9c: 7f1b ldrb r3, [r3, #28]
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
8002a9e: 2b01 cmp r3, #1
8002aa0: d102 bne.n 8002aa8 <HAL_ADC_ConfigChannel+0x124>
8002aa2: f04f 7300 mov.w r3, #33554432 @ 0x2000000
8002aa6: e000 b.n 8002aaa <HAL_ADC_ConfigChannel+0x126>
8002aa8: 2300 movs r3, #0
8002aaa: 461a mov r2, r3
8002aac: f7ff fa3a bl 8001f24 <LL_ADC_SetOffsetSaturation>
8002ab0: e17b b.n 8002daa <HAL_ADC_ConfigChannel+0x426>
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 681b ldr r3, [r3, #0]
8002ab6: 2100 movs r1, #0
8002ab8: 4618 mov r0, r3
8002aba: f7ff f9e7 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002abe: 4603 mov r3, r0
8002ac0: f3c3 0312 ubfx r3, r3, #0, #19
8002ac4: 2b00 cmp r3, #0
8002ac6: d10a bne.n 8002ade <HAL_ADC_ConfigChannel+0x15a>
8002ac8: 687b ldr r3, [r7, #4]
8002aca: 681b ldr r3, [r3, #0]
8002acc: 2100 movs r1, #0
8002ace: 4618 mov r0, r3
8002ad0: f7ff f9dc bl 8001e8c <LL_ADC_GetOffsetChannel>
8002ad4: 4603 mov r3, r0
8002ad6: 0e9b lsrs r3, r3, #26
8002ad8: f003 021f and.w r2, r3, #31
8002adc: e01e b.n 8002b1c <HAL_ADC_ConfigChannel+0x198>
8002ade: 687b ldr r3, [r7, #4]
8002ae0: 681b ldr r3, [r3, #0]
8002ae2: 2100 movs r1, #0
8002ae4: 4618 mov r0, r3
8002ae6: f7ff f9d1 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002aea: 4603 mov r3, r0
8002aec: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002af0: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8002af4: fa93 f3a3 rbit r3, r3
8002af8: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8002afc: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002b00: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
8002b04: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8002b08: 2b00 cmp r3, #0
8002b0a: d101 bne.n 8002b10 <HAL_ADC_ConfigChannel+0x18c>
{
return 32U;
8002b0c: 2320 movs r3, #32
8002b0e: e004 b.n 8002b1a <HAL_ADC_ConfigChannel+0x196>
}
return __builtin_clz(value);
8002b10: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8002b14: fab3 f383 clz r3, r3
8002b18: b2db uxtb r3, r3
8002b1a: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002b1c: 683b ldr r3, [r7, #0]
8002b1e: 681b ldr r3, [r3, #0]
8002b20: f3c3 0312 ubfx r3, r3, #0, #19
8002b24: 2b00 cmp r3, #0
8002b26: d105 bne.n 8002b34 <HAL_ADC_ConfigChannel+0x1b0>
8002b28: 683b ldr r3, [r7, #0]
8002b2a: 681b ldr r3, [r3, #0]
8002b2c: 0e9b lsrs r3, r3, #26
8002b2e: f003 031f and.w r3, r3, #31
8002b32: e018 b.n 8002b66 <HAL_ADC_ConfigChannel+0x1e2>
8002b34: 683b ldr r3, [r7, #0]
8002b36: 681b ldr r3, [r3, #0]
8002b38: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b3c: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
8002b40: fa93 f3a3 rbit r3, r3
8002b44: f8c7 30ac str.w r3, [r7, #172] @ 0xac
return result;
8002b48: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8002b4c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
if (value == 0U)
8002b50: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8002b54: 2b00 cmp r3, #0
8002b56: d101 bne.n 8002b5c <HAL_ADC_ConfigChannel+0x1d8>
return 32U;
8002b58: 2320 movs r3, #32
8002b5a: e004 b.n 8002b66 <HAL_ADC_ConfigChannel+0x1e2>
return __builtin_clz(value);
8002b5c: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8002b60: fab3 f383 clz r3, r3
8002b64: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
8002b66: 429a cmp r2, r3
8002b68: d106 bne.n 8002b78 <HAL_ADC_ConfigChannel+0x1f4>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
8002b6a: 687b ldr r3, [r7, #4]
8002b6c: 681b ldr r3, [r3, #0]
8002b6e: 2200 movs r2, #0
8002b70: 2100 movs r1, #0
8002b72: 4618 mov r0, r3
8002b74: f7ff f9a0 bl 8001eb8 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002b78: 687b ldr r3, [r7, #4]
8002b7a: 681b ldr r3, [r3, #0]
8002b7c: 2101 movs r1, #1
8002b7e: 4618 mov r0, r3
8002b80: f7ff f984 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002b84: 4603 mov r3, r0
8002b86: f3c3 0312 ubfx r3, r3, #0, #19
8002b8a: 2b00 cmp r3, #0
8002b8c: d10a bne.n 8002ba4 <HAL_ADC_ConfigChannel+0x220>
8002b8e: 687b ldr r3, [r7, #4]
8002b90: 681b ldr r3, [r3, #0]
8002b92: 2101 movs r1, #1
8002b94: 4618 mov r0, r3
8002b96: f7ff f979 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002b9a: 4603 mov r3, r0
8002b9c: 0e9b lsrs r3, r3, #26
8002b9e: f003 021f and.w r2, r3, #31
8002ba2: e01e b.n 8002be2 <HAL_ADC_ConfigChannel+0x25e>
8002ba4: 687b ldr r3, [r7, #4]
8002ba6: 681b ldr r3, [r3, #0]
8002ba8: 2101 movs r1, #1
8002baa: 4618 mov r0, r3
8002bac: f7ff f96e bl 8001e8c <LL_ADC_GetOffsetChannel>
8002bb0: 4603 mov r3, r0
8002bb2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002bb6: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8002bba: fa93 f3a3 rbit r3, r3
8002bbe: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return result;
8002bc2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8002bc6: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
if (value == 0U)
8002bca: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8002bce: 2b00 cmp r3, #0
8002bd0: d101 bne.n 8002bd6 <HAL_ADC_ConfigChannel+0x252>
return 32U;
8002bd2: 2320 movs r3, #32
8002bd4: e004 b.n 8002be0 <HAL_ADC_ConfigChannel+0x25c>
return __builtin_clz(value);
8002bd6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8002bda: fab3 f383 clz r3, r3
8002bde: b2db uxtb r3, r3
8002be0: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002be2: 683b ldr r3, [r7, #0]
8002be4: 681b ldr r3, [r3, #0]
8002be6: f3c3 0312 ubfx r3, r3, #0, #19
8002bea: 2b00 cmp r3, #0
8002bec: d105 bne.n 8002bfa <HAL_ADC_ConfigChannel+0x276>
8002bee: 683b ldr r3, [r7, #0]
8002bf0: 681b ldr r3, [r3, #0]
8002bf2: 0e9b lsrs r3, r3, #26
8002bf4: f003 031f and.w r3, r3, #31
8002bf8: e018 b.n 8002c2c <HAL_ADC_ConfigChannel+0x2a8>
8002bfa: 683b ldr r3, [r7, #0]
8002bfc: 681b ldr r3, [r3, #0]
8002bfe: f8c7 3098 str.w r3, [r7, #152] @ 0x98
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c02: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8002c06: fa93 f3a3 rbit r3, r3
8002c0a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
return result;
8002c0e: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
8002c12: f8c7 309c str.w r3, [r7, #156] @ 0x9c
if (value == 0U)
8002c16: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8002c1a: 2b00 cmp r3, #0
8002c1c: d101 bne.n 8002c22 <HAL_ADC_ConfigChannel+0x29e>
return 32U;
8002c1e: 2320 movs r3, #32
8002c20: e004 b.n 8002c2c <HAL_ADC_ConfigChannel+0x2a8>
return __builtin_clz(value);
8002c22: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8002c26: fab3 f383 clz r3, r3
8002c2a: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002c2c: 429a cmp r2, r3
8002c2e: d106 bne.n 8002c3e <HAL_ADC_ConfigChannel+0x2ba>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
8002c30: 687b ldr r3, [r7, #4]
8002c32: 681b ldr r3, [r3, #0]
8002c34: 2200 movs r2, #0
8002c36: 2101 movs r1, #1
8002c38: 4618 mov r0, r3
8002c3a: f7ff f93d bl 8001eb8 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002c3e: 687b ldr r3, [r7, #4]
8002c40: 681b ldr r3, [r3, #0]
8002c42: 2102 movs r1, #2
8002c44: 4618 mov r0, r3
8002c46: f7ff f921 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002c4a: 4603 mov r3, r0
8002c4c: f3c3 0312 ubfx r3, r3, #0, #19
8002c50: 2b00 cmp r3, #0
8002c52: d10a bne.n 8002c6a <HAL_ADC_ConfigChannel+0x2e6>
8002c54: 687b ldr r3, [r7, #4]
8002c56: 681b ldr r3, [r3, #0]
8002c58: 2102 movs r1, #2
8002c5a: 4618 mov r0, r3
8002c5c: f7ff f916 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002c60: 4603 mov r3, r0
8002c62: 0e9b lsrs r3, r3, #26
8002c64: f003 021f and.w r2, r3, #31
8002c68: e01e b.n 8002ca8 <HAL_ADC_ConfigChannel+0x324>
8002c6a: 687b ldr r3, [r7, #4]
8002c6c: 681b ldr r3, [r3, #0]
8002c6e: 2102 movs r1, #2
8002c70: 4618 mov r0, r3
8002c72: f7ff f90b bl 8001e8c <LL_ADC_GetOffsetChannel>
8002c76: 4603 mov r3, r0
8002c78: f8c7 308c str.w r3, [r7, #140] @ 0x8c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c7c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8002c80: fa93 f3a3 rbit r3, r3
8002c84: f8c7 3088 str.w r3, [r7, #136] @ 0x88
return result;
8002c88: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8002c8c: f8c7 3090 str.w r3, [r7, #144] @ 0x90
if (value == 0U)
8002c90: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8002c94: 2b00 cmp r3, #0
8002c96: d101 bne.n 8002c9c <HAL_ADC_ConfigChannel+0x318>
return 32U;
8002c98: 2320 movs r3, #32
8002c9a: e004 b.n 8002ca6 <HAL_ADC_ConfigChannel+0x322>
return __builtin_clz(value);
8002c9c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8002ca0: fab3 f383 clz r3, r3
8002ca4: b2db uxtb r3, r3
8002ca6: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002ca8: 683b ldr r3, [r7, #0]
8002caa: 681b ldr r3, [r3, #0]
8002cac: f3c3 0312 ubfx r3, r3, #0, #19
8002cb0: 2b00 cmp r3, #0
8002cb2: d105 bne.n 8002cc0 <HAL_ADC_ConfigChannel+0x33c>
8002cb4: 683b ldr r3, [r7, #0]
8002cb6: 681b ldr r3, [r3, #0]
8002cb8: 0e9b lsrs r3, r3, #26
8002cba: f003 031f and.w r3, r3, #31
8002cbe: e016 b.n 8002cee <HAL_ADC_ConfigChannel+0x36a>
8002cc0: 683b ldr r3, [r7, #0]
8002cc2: 681b ldr r3, [r3, #0]
8002cc4: f8c7 3080 str.w r3, [r7, #128] @ 0x80
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002cc8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002ccc: fa93 f3a3 rbit r3, r3
8002cd0: 67fb str r3, [r7, #124] @ 0x7c
return result;
8002cd2: 6ffb ldr r3, [r7, #124] @ 0x7c
8002cd4: f8c7 3084 str.w r3, [r7, #132] @ 0x84
if (value == 0U)
8002cd8: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8002cdc: 2b00 cmp r3, #0
8002cde: d101 bne.n 8002ce4 <HAL_ADC_ConfigChannel+0x360>
return 32U;
8002ce0: 2320 movs r3, #32
8002ce2: e004 b.n 8002cee <HAL_ADC_ConfigChannel+0x36a>
return __builtin_clz(value);
8002ce4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8002ce8: fab3 f383 clz r3, r3
8002cec: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002cee: 429a cmp r2, r3
8002cf0: d106 bne.n 8002d00 <HAL_ADC_ConfigChannel+0x37c>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
8002cf2: 687b ldr r3, [r7, #4]
8002cf4: 681b ldr r3, [r3, #0]
8002cf6: 2200 movs r2, #0
8002cf8: 2102 movs r1, #2
8002cfa: 4618 mov r0, r3
8002cfc: f7ff f8dc bl 8001eb8 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002d00: 687b ldr r3, [r7, #4]
8002d02: 681b ldr r3, [r3, #0]
8002d04: 2103 movs r1, #3
8002d06: 4618 mov r0, r3
8002d08: f7ff f8c0 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002d0c: 4603 mov r3, r0
8002d0e: f3c3 0312 ubfx r3, r3, #0, #19
8002d12: 2b00 cmp r3, #0
8002d14: d10a bne.n 8002d2c <HAL_ADC_ConfigChannel+0x3a8>
8002d16: 687b ldr r3, [r7, #4]
8002d18: 681b ldr r3, [r3, #0]
8002d1a: 2103 movs r1, #3
8002d1c: 4618 mov r0, r3
8002d1e: f7ff f8b5 bl 8001e8c <LL_ADC_GetOffsetChannel>
8002d22: 4603 mov r3, r0
8002d24: 0e9b lsrs r3, r3, #26
8002d26: f003 021f and.w r2, r3, #31
8002d2a: e017 b.n 8002d5c <HAL_ADC_ConfigChannel+0x3d8>
8002d2c: 687b ldr r3, [r7, #4]
8002d2e: 681b ldr r3, [r3, #0]
8002d30: 2103 movs r1, #3
8002d32: 4618 mov r0, r3
8002d34: f7ff f8aa bl 8001e8c <LL_ADC_GetOffsetChannel>
8002d38: 4603 mov r3, r0
8002d3a: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d3c: 6f7b ldr r3, [r7, #116] @ 0x74
8002d3e: fa93 f3a3 rbit r3, r3
8002d42: 673b str r3, [r7, #112] @ 0x70
return result;
8002d44: 6f3b ldr r3, [r7, #112] @ 0x70
8002d46: 67bb str r3, [r7, #120] @ 0x78
if (value == 0U)
8002d48: 6fbb ldr r3, [r7, #120] @ 0x78
8002d4a: 2b00 cmp r3, #0
8002d4c: d101 bne.n 8002d52 <HAL_ADC_ConfigChannel+0x3ce>
return 32U;
8002d4e: 2320 movs r3, #32
8002d50: e003 b.n 8002d5a <HAL_ADC_ConfigChannel+0x3d6>
return __builtin_clz(value);
8002d52: 6fbb ldr r3, [r7, #120] @ 0x78
8002d54: fab3 f383 clz r3, r3
8002d58: b2db uxtb r3, r3
8002d5a: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002d5c: 683b ldr r3, [r7, #0]
8002d5e: 681b ldr r3, [r3, #0]
8002d60: f3c3 0312 ubfx r3, r3, #0, #19
8002d64: 2b00 cmp r3, #0
8002d66: d105 bne.n 8002d74 <HAL_ADC_ConfigChannel+0x3f0>
8002d68: 683b ldr r3, [r7, #0]
8002d6a: 681b ldr r3, [r3, #0]
8002d6c: 0e9b lsrs r3, r3, #26
8002d6e: f003 031f and.w r3, r3, #31
8002d72: e011 b.n 8002d98 <HAL_ADC_ConfigChannel+0x414>
8002d74: 683b ldr r3, [r7, #0]
8002d76: 681b ldr r3, [r3, #0]
8002d78: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002d7a: 6ebb ldr r3, [r7, #104] @ 0x68
8002d7c: fa93 f3a3 rbit r3, r3
8002d80: 667b str r3, [r7, #100] @ 0x64
return result;
8002d82: 6e7b ldr r3, [r7, #100] @ 0x64
8002d84: 66fb str r3, [r7, #108] @ 0x6c
if (value == 0U)
8002d86: 6efb ldr r3, [r7, #108] @ 0x6c
8002d88: 2b00 cmp r3, #0
8002d8a: d101 bne.n 8002d90 <HAL_ADC_ConfigChannel+0x40c>
return 32U;
8002d8c: 2320 movs r3, #32
8002d8e: e003 b.n 8002d98 <HAL_ADC_ConfigChannel+0x414>
return __builtin_clz(value);
8002d90: 6efb ldr r3, [r7, #108] @ 0x6c
8002d92: fab3 f383 clz r3, r3
8002d96: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002d98: 429a cmp r2, r3
8002d9a: d106 bne.n 8002daa <HAL_ADC_ConfigChannel+0x426>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
8002d9c: 687b ldr r3, [r7, #4]
8002d9e: 681b ldr r3, [r3, #0]
8002da0: 2200 movs r2, #0
8002da2: 2103 movs r1, #3
8002da4: 4618 mov r0, r3
8002da6: f7ff f887 bl 8001eb8 <LL_ADC_SetOffsetState>
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002daa: 687b ldr r3, [r7, #4]
8002dac: 681b ldr r3, [r3, #0]
8002dae: 4618 mov r0, r3
8002db0: f7ff fa06 bl 80021c0 <LL_ADC_IsEnabled>
8002db4: 4603 mov r3, r0
8002db6: 2b00 cmp r3, #0
8002db8: f040 8140 bne.w 800303c <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
8002dbc: 687b ldr r3, [r7, #4]
8002dbe: 6818 ldr r0, [r3, #0]
8002dc0: 683b ldr r3, [r7, #0]
8002dc2: 6819 ldr r1, [r3, #0]
8002dc4: 683b ldr r3, [r7, #0]
8002dc6: 68db ldr r3, [r3, #12]
8002dc8: 461a mov r2, r3
8002dca: f7ff f943 bl 8002054 <LL_ADC_SetChannelSingleDiff>
/* Configuration of differential mode */
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
8002dce: 683b ldr r3, [r7, #0]
8002dd0: 68db ldr r3, [r3, #12]
8002dd2: 4a8f ldr r2, [pc, #572] @ (8003010 <HAL_ADC_ConfigChannel+0x68c>)
8002dd4: 4293 cmp r3, r2
8002dd6: f040 8131 bne.w 800303c <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002dda: 687b ldr r3, [r7, #4]
8002ddc: 6818 ldr r0, [r3, #0]
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002dde: 683b ldr r3, [r7, #0]
8002de0: 681b ldr r3, [r3, #0]
8002de2: f3c3 0312 ubfx r3, r3, #0, #19
8002de6: 2b00 cmp r3, #0
8002de8: d10b bne.n 8002e02 <HAL_ADC_ConfigChannel+0x47e>
8002dea: 683b ldr r3, [r7, #0]
8002dec: 681b ldr r3, [r3, #0]
8002dee: 0e9b lsrs r3, r3, #26
8002df0: 3301 adds r3, #1
8002df2: f003 031f and.w r3, r3, #31
8002df6: 2b09 cmp r3, #9
8002df8: bf94 ite ls
8002dfa: 2301 movls r3, #1
8002dfc: 2300 movhi r3, #0
8002dfe: b2db uxtb r3, r3
8002e00: e019 b.n 8002e36 <HAL_ADC_ConfigChannel+0x4b2>
8002e02: 683b ldr r3, [r7, #0]
8002e04: 681b ldr r3, [r3, #0]
8002e06: 65fb str r3, [r7, #92] @ 0x5c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e08: 6dfb ldr r3, [r7, #92] @ 0x5c
8002e0a: fa93 f3a3 rbit r3, r3
8002e0e: 65bb str r3, [r7, #88] @ 0x58
return result;
8002e10: 6dbb ldr r3, [r7, #88] @ 0x58
8002e12: 663b str r3, [r7, #96] @ 0x60
if (value == 0U)
8002e14: 6e3b ldr r3, [r7, #96] @ 0x60
8002e16: 2b00 cmp r3, #0
8002e18: d101 bne.n 8002e1e <HAL_ADC_ConfigChannel+0x49a>
return 32U;
8002e1a: 2320 movs r3, #32
8002e1c: e003 b.n 8002e26 <HAL_ADC_ConfigChannel+0x4a2>
return __builtin_clz(value);
8002e1e: 6e3b ldr r3, [r7, #96] @ 0x60
8002e20: fab3 f383 clz r3, r3
8002e24: b2db uxtb r3, r3
8002e26: 3301 adds r3, #1
8002e28: f003 031f and.w r3, r3, #31
8002e2c: 2b09 cmp r3, #9
8002e2e: bf94 ite ls
8002e30: 2301 movls r3, #1
8002e32: 2300 movhi r3, #0
8002e34: b2db uxtb r3, r3
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002e36: 2b00 cmp r3, #0
8002e38: d079 beq.n 8002f2e <HAL_ADC_ConfigChannel+0x5aa>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002e3a: 683b ldr r3, [r7, #0]
8002e3c: 681b ldr r3, [r3, #0]
8002e3e: f3c3 0312 ubfx r3, r3, #0, #19
8002e42: 2b00 cmp r3, #0
8002e44: d107 bne.n 8002e56 <HAL_ADC_ConfigChannel+0x4d2>
8002e46: 683b ldr r3, [r7, #0]
8002e48: 681b ldr r3, [r3, #0]
8002e4a: 0e9b lsrs r3, r3, #26
8002e4c: 3301 adds r3, #1
8002e4e: 069b lsls r3, r3, #26
8002e50: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002e54: e015 b.n 8002e82 <HAL_ADC_ConfigChannel+0x4fe>
8002e56: 683b ldr r3, [r7, #0]
8002e58: 681b ldr r3, [r3, #0]
8002e5a: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e5c: 6d3b ldr r3, [r7, #80] @ 0x50
8002e5e: fa93 f3a3 rbit r3, r3
8002e62: 64fb str r3, [r7, #76] @ 0x4c
return result;
8002e64: 6cfb ldr r3, [r7, #76] @ 0x4c
8002e66: 657b str r3, [r7, #84] @ 0x54
if (value == 0U)
8002e68: 6d7b ldr r3, [r7, #84] @ 0x54
8002e6a: 2b00 cmp r3, #0
8002e6c: d101 bne.n 8002e72 <HAL_ADC_ConfigChannel+0x4ee>
return 32U;
8002e6e: 2320 movs r3, #32
8002e70: e003 b.n 8002e7a <HAL_ADC_ConfigChannel+0x4f6>
return __builtin_clz(value);
8002e72: 6d7b ldr r3, [r7, #84] @ 0x54
8002e74: fab3 f383 clz r3, r3
8002e78: b2db uxtb r3, r3
8002e7a: 3301 adds r3, #1
8002e7c: 069b lsls r3, r3, #26
8002e7e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002e82: 683b ldr r3, [r7, #0]
8002e84: 681b ldr r3, [r3, #0]
8002e86: f3c3 0312 ubfx r3, r3, #0, #19
8002e8a: 2b00 cmp r3, #0
8002e8c: d109 bne.n 8002ea2 <HAL_ADC_ConfigChannel+0x51e>
8002e8e: 683b ldr r3, [r7, #0]
8002e90: 681b ldr r3, [r3, #0]
8002e92: 0e9b lsrs r3, r3, #26
8002e94: 3301 adds r3, #1
8002e96: f003 031f and.w r3, r3, #31
8002e9a: 2101 movs r1, #1
8002e9c: fa01 f303 lsl.w r3, r1, r3
8002ea0: e017 b.n 8002ed2 <HAL_ADC_ConfigChannel+0x54e>
8002ea2: 683b ldr r3, [r7, #0]
8002ea4: 681b ldr r3, [r3, #0]
8002ea6: 647b str r3, [r7, #68] @ 0x44
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ea8: 6c7b ldr r3, [r7, #68] @ 0x44
8002eaa: fa93 f3a3 rbit r3, r3
8002eae: 643b str r3, [r7, #64] @ 0x40
return result;
8002eb0: 6c3b ldr r3, [r7, #64] @ 0x40
8002eb2: 64bb str r3, [r7, #72] @ 0x48
if (value == 0U)
8002eb4: 6cbb ldr r3, [r7, #72] @ 0x48
8002eb6: 2b00 cmp r3, #0
8002eb8: d101 bne.n 8002ebe <HAL_ADC_ConfigChannel+0x53a>
return 32U;
8002eba: 2320 movs r3, #32
8002ebc: e003 b.n 8002ec6 <HAL_ADC_ConfigChannel+0x542>
return __builtin_clz(value);
8002ebe: 6cbb ldr r3, [r7, #72] @ 0x48
8002ec0: fab3 f383 clz r3, r3
8002ec4: b2db uxtb r3, r3
8002ec6: 3301 adds r3, #1
8002ec8: f003 031f and.w r3, r3, #31
8002ecc: 2101 movs r1, #1
8002ece: fa01 f303 lsl.w r3, r1, r3
8002ed2: ea42 0103 orr.w r1, r2, r3
8002ed6: 683b ldr r3, [r7, #0]
8002ed8: 681b ldr r3, [r3, #0]
8002eda: f3c3 0312 ubfx r3, r3, #0, #19
8002ede: 2b00 cmp r3, #0
8002ee0: d10a bne.n 8002ef8 <HAL_ADC_ConfigChannel+0x574>
8002ee2: 683b ldr r3, [r7, #0]
8002ee4: 681b ldr r3, [r3, #0]
8002ee6: 0e9b lsrs r3, r3, #26
8002ee8: 3301 adds r3, #1
8002eea: f003 021f and.w r2, r3, #31
8002eee: 4613 mov r3, r2
8002ef0: 005b lsls r3, r3, #1
8002ef2: 4413 add r3, r2
8002ef4: 051b lsls r3, r3, #20
8002ef6: e018 b.n 8002f2a <HAL_ADC_ConfigChannel+0x5a6>
8002ef8: 683b ldr r3, [r7, #0]
8002efa: 681b ldr r3, [r3, #0]
8002efc: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002efe: 6bbb ldr r3, [r7, #56] @ 0x38
8002f00: fa93 f3a3 rbit r3, r3
8002f04: 637b str r3, [r7, #52] @ 0x34
return result;
8002f06: 6b7b ldr r3, [r7, #52] @ 0x34
8002f08: 63fb str r3, [r7, #60] @ 0x3c
if (value == 0U)
8002f0a: 6bfb ldr r3, [r7, #60] @ 0x3c
8002f0c: 2b00 cmp r3, #0
8002f0e: d101 bne.n 8002f14 <HAL_ADC_ConfigChannel+0x590>
return 32U;
8002f10: 2320 movs r3, #32
8002f12: e003 b.n 8002f1c <HAL_ADC_ConfigChannel+0x598>
return __builtin_clz(value);
8002f14: 6bfb ldr r3, [r7, #60] @ 0x3c
8002f16: fab3 f383 clz r3, r3
8002f1a: b2db uxtb r3, r3
8002f1c: 3301 adds r3, #1
8002f1e: f003 021f and.w r2, r3, #31
8002f22: 4613 mov r3, r2
8002f24: 005b lsls r3, r3, #1
8002f26: 4413 add r3, r2
8002f28: 051b lsls r3, r3, #20
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002f2a: 430b orrs r3, r1
8002f2c: e081 b.n 8003032 <HAL_ADC_ConfigChannel+0x6ae>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002f2e: 683b ldr r3, [r7, #0]
8002f30: 681b ldr r3, [r3, #0]
8002f32: f3c3 0312 ubfx r3, r3, #0, #19
8002f36: 2b00 cmp r3, #0
8002f38: d107 bne.n 8002f4a <HAL_ADC_ConfigChannel+0x5c6>
8002f3a: 683b ldr r3, [r7, #0]
8002f3c: 681b ldr r3, [r3, #0]
8002f3e: 0e9b lsrs r3, r3, #26
8002f40: 3301 adds r3, #1
8002f42: 069b lsls r3, r3, #26
8002f44: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002f48: e015 b.n 8002f76 <HAL_ADC_ConfigChannel+0x5f2>
8002f4a: 683b ldr r3, [r7, #0]
8002f4c: 681b ldr r3, [r3, #0]
8002f4e: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f50: 6afb ldr r3, [r7, #44] @ 0x2c
8002f52: fa93 f3a3 rbit r3, r3
8002f56: 62bb str r3, [r7, #40] @ 0x28
return result;
8002f58: 6abb ldr r3, [r7, #40] @ 0x28
8002f5a: 633b str r3, [r7, #48] @ 0x30
if (value == 0U)
8002f5c: 6b3b ldr r3, [r7, #48] @ 0x30
8002f5e: 2b00 cmp r3, #0
8002f60: d101 bne.n 8002f66 <HAL_ADC_ConfigChannel+0x5e2>
return 32U;
8002f62: 2320 movs r3, #32
8002f64: e003 b.n 8002f6e <HAL_ADC_ConfigChannel+0x5ea>
return __builtin_clz(value);
8002f66: 6b3b ldr r3, [r7, #48] @ 0x30
8002f68: fab3 f383 clz r3, r3
8002f6c: b2db uxtb r3, r3
8002f6e: 3301 adds r3, #1
8002f70: 069b lsls r3, r3, #26
8002f72: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002f76: 683b ldr r3, [r7, #0]
8002f78: 681b ldr r3, [r3, #0]
8002f7a: f3c3 0312 ubfx r3, r3, #0, #19
8002f7e: 2b00 cmp r3, #0
8002f80: d109 bne.n 8002f96 <HAL_ADC_ConfigChannel+0x612>
8002f82: 683b ldr r3, [r7, #0]
8002f84: 681b ldr r3, [r3, #0]
8002f86: 0e9b lsrs r3, r3, #26
8002f88: 3301 adds r3, #1
8002f8a: f003 031f and.w r3, r3, #31
8002f8e: 2101 movs r1, #1
8002f90: fa01 f303 lsl.w r3, r1, r3
8002f94: e017 b.n 8002fc6 <HAL_ADC_ConfigChannel+0x642>
8002f96: 683b ldr r3, [r7, #0]
8002f98: 681b ldr r3, [r3, #0]
8002f9a: 623b str r3, [r7, #32]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002f9c: 6a3b ldr r3, [r7, #32]
8002f9e: fa93 f3a3 rbit r3, r3
8002fa2: 61fb str r3, [r7, #28]
return result;
8002fa4: 69fb ldr r3, [r7, #28]
8002fa6: 627b str r3, [r7, #36] @ 0x24
if (value == 0U)
8002fa8: 6a7b ldr r3, [r7, #36] @ 0x24
8002faa: 2b00 cmp r3, #0
8002fac: d101 bne.n 8002fb2 <HAL_ADC_ConfigChannel+0x62e>
return 32U;
8002fae: 2320 movs r3, #32
8002fb0: e003 b.n 8002fba <HAL_ADC_ConfigChannel+0x636>
return __builtin_clz(value);
8002fb2: 6a7b ldr r3, [r7, #36] @ 0x24
8002fb4: fab3 f383 clz r3, r3
8002fb8: b2db uxtb r3, r3
8002fba: 3301 adds r3, #1
8002fbc: f003 031f and.w r3, r3, #31
8002fc0: 2101 movs r1, #1
8002fc2: fa01 f303 lsl.w r3, r1, r3
8002fc6: ea42 0103 orr.w r1, r2, r3
8002fca: 683b ldr r3, [r7, #0]
8002fcc: 681b ldr r3, [r3, #0]
8002fce: f3c3 0312 ubfx r3, r3, #0, #19
8002fd2: 2b00 cmp r3, #0
8002fd4: d10d bne.n 8002ff2 <HAL_ADC_ConfigChannel+0x66e>
8002fd6: 683b ldr r3, [r7, #0]
8002fd8: 681b ldr r3, [r3, #0]
8002fda: 0e9b lsrs r3, r3, #26
8002fdc: 3301 adds r3, #1
8002fde: f003 021f and.w r2, r3, #31
8002fe2: 4613 mov r3, r2
8002fe4: 005b lsls r3, r3, #1
8002fe6: 4413 add r3, r2
8002fe8: 3b1e subs r3, #30
8002fea: 051b lsls r3, r3, #20
8002fec: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8002ff0: e01e b.n 8003030 <HAL_ADC_ConfigChannel+0x6ac>
8002ff2: 683b ldr r3, [r7, #0]
8002ff4: 681b ldr r3, [r3, #0]
8002ff6: 617b str r3, [r7, #20]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ff8: 697b ldr r3, [r7, #20]
8002ffa: fa93 f3a3 rbit r3, r3
8002ffe: 613b str r3, [r7, #16]
return result;
8003000: 693b ldr r3, [r7, #16]
8003002: 61bb str r3, [r7, #24]
if (value == 0U)
8003004: 69bb ldr r3, [r7, #24]
8003006: 2b00 cmp r3, #0
8003008: d104 bne.n 8003014 <HAL_ADC_ConfigChannel+0x690>
return 32U;
800300a: 2320 movs r3, #32
800300c: e006 b.n 800301c <HAL_ADC_ConfigChannel+0x698>
800300e: bf00 nop
8003010: 407f0000 .word 0x407f0000
return __builtin_clz(value);
8003014: 69bb ldr r3, [r7, #24]
8003016: fab3 f383 clz r3, r3
800301a: b2db uxtb r3, r3
800301c: 3301 adds r3, #1
800301e: f003 021f and.w r2, r3, #31
8003022: 4613 mov r3, r2
8003024: 005b lsls r3, r3, #1
8003026: 4413 add r3, r2
8003028: 3b1e subs r3, #30
800302a: 051b lsls r3, r3, #20
800302c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8003030: 430b orrs r3, r1
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+ 1UL) & 0x1FUL)),
pConfig->SamplingTime);
8003032: 683a ldr r2, [r7, #0]
8003034: 6892 ldr r2, [r2, #8]
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8003036: 4619 mov r1, r3
8003038: f7fe ffe1 bl 8001ffe <LL_ADC_SetChannelSamplingTime>
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
800303c: 683b ldr r3, [r7, #0]
800303e: 681a ldr r2, [r3, #0]
8003040: 4b3f ldr r3, [pc, #252] @ (8003140 <HAL_ADC_ConfigChannel+0x7bc>)
8003042: 4013 ands r3, r2
8003044: 2b00 cmp r3, #0
8003046: d071 beq.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8003048: 483e ldr r0, [pc, #248] @ (8003144 <HAL_ADC_ConfigChannel+0x7c0>)
800304a: f7fe feed bl 8001e28 <LL_ADC_GetCommonPathInternalCh>
800304e: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
8003052: 683b ldr r3, [r7, #0]
8003054: 681b ldr r3, [r3, #0]
8003056: 4a3c ldr r2, [pc, #240] @ (8003148 <HAL_ADC_ConfigChannel+0x7c4>)
8003058: 4293 cmp r3, r2
800305a: d004 beq.n 8003066 <HAL_ADC_ConfigChannel+0x6e2>
800305c: 683b ldr r3, [r7, #0]
800305e: 681b ldr r3, [r3, #0]
8003060: 4a3a ldr r2, [pc, #232] @ (800314c <HAL_ADC_ConfigChannel+0x7c8>)
8003062: 4293 cmp r3, r2
8003064: d127 bne.n 80030b6 <HAL_ADC_ConfigChannel+0x732>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8003066: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
800306a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800306e: 2b00 cmp r3, #0
8003070: d121 bne.n 80030b6 <HAL_ADC_ConfigChannel+0x732>
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8003072: 687b ldr r3, [r7, #4]
8003074: 681b ldr r3, [r3, #0]
8003076: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800307a: d157 bne.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
800307c: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8003080: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8003084: 4619 mov r1, r3
8003086: 482f ldr r0, [pc, #188] @ (8003144 <HAL_ADC_ConfigChannel+0x7c0>)
8003088: f7fe febb bl 8001e02 <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
800308c: 4b30 ldr r3, [pc, #192] @ (8003150 <HAL_ADC_ConfigChannel+0x7cc>)
800308e: 681b ldr r3, [r3, #0]
8003090: 099b lsrs r3, r3, #6
8003092: 4a30 ldr r2, [pc, #192] @ (8003154 <HAL_ADC_ConfigChannel+0x7d0>)
8003094: fba2 2303 umull r2, r3, r2, r3
8003098: 099b lsrs r3, r3, #6
800309a: 1c5a adds r2, r3, #1
800309c: 4613 mov r3, r2
800309e: 005b lsls r3, r3, #1
80030a0: 4413 add r3, r2
80030a2: 009b lsls r3, r3, #2
80030a4: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
80030a6: e002 b.n 80030ae <HAL_ADC_ConfigChannel+0x72a>
{
wait_loop_index--;
80030a8: 68fb ldr r3, [r7, #12]
80030aa: 3b01 subs r3, #1
80030ac: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
80030ae: 68fb ldr r3, [r7, #12]
80030b0: 2b00 cmp r3, #0
80030b2: d1f9 bne.n 80030a8 <HAL_ADC_ConfigChannel+0x724>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
80030b4: e03a b.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
}
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
80030b6: 683b ldr r3, [r7, #0]
80030b8: 681b ldr r3, [r3, #0]
80030ba: 4a27 ldr r2, [pc, #156] @ (8003158 <HAL_ADC_ConfigChannel+0x7d4>)
80030bc: 4293 cmp r3, r2
80030be: d113 bne.n 80030e8 <HAL_ADC_ConfigChannel+0x764>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
80030c0: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
80030c4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
80030c8: 2b00 cmp r3, #0
80030ca: d10d bne.n 80030e8 <HAL_ADC_ConfigChannel+0x764>
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
80030cc: 687b ldr r3, [r7, #4]
80030ce: 681b ldr r3, [r3, #0]
80030d0: 4a22 ldr r2, [pc, #136] @ (800315c <HAL_ADC_ConfigChannel+0x7d8>)
80030d2: 4293 cmp r3, r2
80030d4: d02a beq.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
80030d6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
80030da: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80030de: 4619 mov r1, r3
80030e0: 4818 ldr r0, [pc, #96] @ (8003144 <HAL_ADC_ConfigChannel+0x7c0>)
80030e2: f7fe fe8e bl 8001e02 <LL_ADC_SetCommonPathInternalCh>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
80030e6: e021 b.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
80030e8: 683b ldr r3, [r7, #0]
80030ea: 681b ldr r3, [r3, #0]
80030ec: 4a1c ldr r2, [pc, #112] @ (8003160 <HAL_ADC_ConfigChannel+0x7dc>)
80030ee: 4293 cmp r3, r2
80030f0: d11c bne.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
80030f2: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
80030f6: f403 0380 and.w r3, r3, #4194304 @ 0x400000
80030fa: 2b00 cmp r3, #0
80030fc: d116 bne.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
{
if (ADC_VREFINT_INSTANCE(hadc))
80030fe: 687b ldr r3, [r7, #4]
8003100: 681b ldr r3, [r3, #0]
8003102: 4a16 ldr r2, [pc, #88] @ (800315c <HAL_ADC_ConfigChannel+0x7d8>)
8003104: 4293 cmp r3, r2
8003106: d011 beq.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8003108: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
800310c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8003110: 4619 mov r1, r3
8003112: 480c ldr r0, [pc, #48] @ (8003144 <HAL_ADC_ConfigChannel+0x7c0>)
8003114: f7fe fe75 bl 8001e02 <LL_ADC_SetCommonPathInternalCh>
8003118: e008 b.n 800312c <HAL_ADC_ConfigChannel+0x7a8>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
800311a: 687b ldr r3, [r7, #4]
800311c: 6ddb ldr r3, [r3, #92] @ 0x5c
800311e: f043 0220 orr.w r2, r3, #32
8003122: 687b ldr r3, [r7, #4]
8003124: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8003126: 2301 movs r3, #1
8003128: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
800312c: 687b ldr r3, [r7, #4]
800312e: 2200 movs r2, #0
8003130: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
8003134: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7
}
8003138: 4618 mov r0, r3
800313a: 37d8 adds r7, #216 @ 0xd8
800313c: 46bd mov sp, r7
800313e: bd80 pop {r7, pc}
8003140: 80080000 .word 0x80080000
8003144: 50000300 .word 0x50000300
8003148: c3210000 .word 0xc3210000
800314c: 90c00010 .word 0x90c00010
8003150: 20000018 .word 0x20000018
8003154: 053e2d63 .word 0x053e2d63
8003158: c7520000 .word 0xc7520000
800315c: 50000100 .word 0x50000100
8003160: cb840000 .word 0xcb840000
08003164 <ADC_ConversionStop>:
* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
{
8003164: b580 push {r7, lr}
8003166: b088 sub sp, #32
8003168: af00 add r7, sp, #0
800316a: 6078 str r0, [r7, #4]
800316c: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t Conversion_Timeout_CPU_cycles = 0UL;
800316e: 2300 movs r3, #0
8003170: 61fb str r3, [r7, #28]
uint32_t conversion_group_reassigned = ConversionGroup;
8003172: 683b ldr r3, [r7, #0]
8003174: 61bb str r3, [r7, #24]
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
/* Verification if ADC is not already stopped (on regular and injected */
/* groups) to bypass this function if not needed. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8003176: 687b ldr r3, [r7, #4]
8003178: 681b ldr r3, [r3, #0]
800317a: 4618 mov r0, r3
800317c: f7ff f86e bl 800225c <LL_ADC_REG_IsConversionOngoing>
8003180: 6138 str r0, [r7, #16]
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8003182: 687b ldr r3, [r7, #4]
8003184: 681b ldr r3, [r3, #0]
8003186: 4618 mov r0, r3
8003188: f7ff f88f bl 80022aa <LL_ADC_INJ_IsConversionOngoing>
800318c: 60f8 str r0, [r7, #12]
if ((tmp_adc_is_conversion_on_going_regular != 0UL)
800318e: 693b ldr r3, [r7, #16]
8003190: 2b00 cmp r3, #0
8003192: d103 bne.n 800319c <ADC_ConversionStop+0x38>
|| (tmp_adc_is_conversion_on_going_injected != 0UL)
8003194: 68fb ldr r3, [r7, #12]
8003196: 2b00 cmp r3, #0
8003198: f000 8098 beq.w 80032cc <ADC_ConversionStop+0x168>
/* auto-delay mode. */
/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
/* injected group stop ADC_CR_JADSTP). */
/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
/* (see reference manual). */
if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
800319c: 687b ldr r3, [r7, #4]
800319e: 681b ldr r3, [r3, #0]
80031a0: 68db ldr r3, [r3, #12]
80031a2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80031a6: 2b00 cmp r3, #0
80031a8: d02a beq.n 8003200 <ADC_ConversionStop+0x9c>
&& (hadc->Init.ContinuousConvMode == ENABLE)
80031aa: 687b ldr r3, [r7, #4]
80031ac: 7f5b ldrb r3, [r3, #29]
80031ae: 2b01 cmp r3, #1
80031b0: d126 bne.n 8003200 <ADC_ConversionStop+0x9c>
&& (hadc->Init.LowPowerAutoWait == ENABLE)
80031b2: 687b ldr r3, [r7, #4]
80031b4: 7f1b ldrb r3, [r3, #28]
80031b6: 2b01 cmp r3, #1
80031b8: d122 bne.n 8003200 <ADC_ConversionStop+0x9c>
)
{
/* Use stop of regular group */
conversion_group_reassigned = ADC_REGULAR_GROUP;
80031ba: 2301 movs r3, #1
80031bc: 61bb str r3, [r7, #24]
/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
80031be: e014 b.n 80031ea <ADC_ConversionStop+0x86>
{
if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
80031c0: 69fb ldr r3, [r7, #28]
80031c2: 4a45 ldr r2, [pc, #276] @ (80032d8 <ADC_ConversionStop+0x174>)
80031c4: 4293 cmp r3, r2
80031c6: d90d bls.n 80031e4 <ADC_ConversionStop+0x80>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80031c8: 687b ldr r3, [r7, #4]
80031ca: 6ddb ldr r3, [r3, #92] @ 0x5c
80031cc: f043 0210 orr.w r2, r3, #16
80031d0: 687b ldr r3, [r7, #4]
80031d2: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80031d4: 687b ldr r3, [r7, #4]
80031d6: 6e1b ldr r3, [r3, #96] @ 0x60
80031d8: f043 0201 orr.w r2, r3, #1
80031dc: 687b ldr r3, [r7, #4]
80031de: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
80031e0: 2301 movs r3, #1
80031e2: e074 b.n 80032ce <ADC_ConversionStop+0x16a>
}
Conversion_Timeout_CPU_cycles ++;
80031e4: 69fb ldr r3, [r7, #28]
80031e6: 3301 adds r3, #1
80031e8: 61fb str r3, [r7, #28]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
80031ea: 687b ldr r3, [r7, #4]
80031ec: 681b ldr r3, [r3, #0]
80031ee: 681b ldr r3, [r3, #0]
80031f0: f003 0340 and.w r3, r3, #64 @ 0x40
80031f4: 2b40 cmp r3, #64 @ 0x40
80031f6: d1e3 bne.n 80031c0 <ADC_ConversionStop+0x5c>
}
/* Clear JEOS */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
80031f8: 687b ldr r3, [r7, #4]
80031fa: 681b ldr r3, [r3, #0]
80031fc: 2240 movs r2, #64 @ 0x40
80031fe: 601a str r2, [r3, #0]
}
/* Stop potential conversion on going on ADC group regular */
if (conversion_group_reassigned != ADC_INJECTED_GROUP)
8003200: 69bb ldr r3, [r7, #24]
8003202: 2b02 cmp r3, #2
8003204: d014 beq.n 8003230 <ADC_ConversionStop+0xcc>
{
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
8003206: 687b ldr r3, [r7, #4]
8003208: 681b ldr r3, [r3, #0]
800320a: 4618 mov r0, r3
800320c: f7ff f826 bl 800225c <LL_ADC_REG_IsConversionOngoing>
8003210: 4603 mov r3, r0
8003212: 2b00 cmp r3, #0
8003214: d00c beq.n 8003230 <ADC_ConversionStop+0xcc>
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
8003216: 687b ldr r3, [r7, #4]
8003218: 681b ldr r3, [r3, #0]
800321a: 4618 mov r0, r3
800321c: f7fe ffe3 bl 80021e6 <LL_ADC_IsDisableOngoing>
8003220: 4603 mov r3, r0
8003222: 2b00 cmp r3, #0
8003224: d104 bne.n 8003230 <ADC_ConversionStop+0xcc>
{
/* Stop ADC group regular conversion */
LL_ADC_REG_StopConversion(hadc->Instance);
8003226: 687b ldr r3, [r7, #4]
8003228: 681b ldr r3, [r3, #0]
800322a: 4618 mov r0, r3
800322c: f7ff f802 bl 8002234 <LL_ADC_REG_StopConversion>
}
}
}
/* Stop potential conversion on going on ADC group injected */
if (conversion_group_reassigned != ADC_REGULAR_GROUP)
8003230: 69bb ldr r3, [r7, #24]
8003232: 2b01 cmp r3, #1
8003234: d014 beq.n 8003260 <ADC_ConversionStop+0xfc>
{
/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
8003236: 687b ldr r3, [r7, #4]
8003238: 681b ldr r3, [r3, #0]
800323a: 4618 mov r0, r3
800323c: f7ff f835 bl 80022aa <LL_ADC_INJ_IsConversionOngoing>
8003240: 4603 mov r3, r0
8003242: 2b00 cmp r3, #0
8003244: d00c beq.n 8003260 <ADC_ConversionStop+0xfc>
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
8003246: 687b ldr r3, [r7, #4]
8003248: 681b ldr r3, [r3, #0]
800324a: 4618 mov r0, r3
800324c: f7fe ffcb bl 80021e6 <LL_ADC_IsDisableOngoing>
8003250: 4603 mov r3, r0
8003252: 2b00 cmp r3, #0
8003254: d104 bne.n 8003260 <ADC_ConversionStop+0xfc>
{
/* Stop ADC group injected conversion */
LL_ADC_INJ_StopConversion(hadc->Instance);
8003256: 687b ldr r3, [r7, #4]
8003258: 681b ldr r3, [r3, #0]
800325a: 4618 mov r0, r3
800325c: f7ff f811 bl 8002282 <LL_ADC_INJ_StopConversion>
}
}
}
/* Selection of start and stop bits with respect to the regular or injected group */
switch (conversion_group_reassigned)
8003260: 69bb ldr r3, [r7, #24]
8003262: 2b02 cmp r3, #2
8003264: d005 beq.n 8003272 <ADC_ConversionStop+0x10e>
8003266: 69bb ldr r3, [r7, #24]
8003268: 2b03 cmp r3, #3
800326a: d105 bne.n 8003278 <ADC_ConversionStop+0x114>
{
case ADC_REGULAR_INJECTED_GROUP:
tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
800326c: 230c movs r3, #12
800326e: 617b str r3, [r7, #20]
break;
8003270: e005 b.n 800327e <ADC_ConversionStop+0x11a>
case ADC_INJECTED_GROUP:
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
8003272: 2308 movs r3, #8
8003274: 617b str r3, [r7, #20]
break;
8003276: e002 b.n 800327e <ADC_ConversionStop+0x11a>
/* Case ADC_REGULAR_GROUP only*/
default:
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
8003278: 2304 movs r3, #4
800327a: 617b str r3, [r7, #20]
break;
800327c: bf00 nop
}
/* Wait for conversion effectively stopped */
tickstart = HAL_GetTick();
800327e: f7fe fda1 bl 8001dc4 <HAL_GetTick>
8003282: 60b8 str r0, [r7, #8]
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
8003284: e01b b.n 80032be <ADC_ConversionStop+0x15a>
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
8003286: f7fe fd9d bl 8001dc4 <HAL_GetTick>
800328a: 4602 mov r2, r0
800328c: 68bb ldr r3, [r7, #8]
800328e: 1ad3 subs r3, r2, r3
8003290: 2b05 cmp r3, #5
8003292: d914 bls.n 80032be <ADC_ConversionStop+0x15a>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
8003294: 687b ldr r3, [r7, #4]
8003296: 681b ldr r3, [r3, #0]
8003298: 689a ldr r2, [r3, #8]
800329a: 697b ldr r3, [r7, #20]
800329c: 4013 ands r3, r2
800329e: 2b00 cmp r3, #0
80032a0: d00d beq.n 80032be <ADC_ConversionStop+0x15a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80032a2: 687b ldr r3, [r7, #4]
80032a4: 6ddb ldr r3, [r3, #92] @ 0x5c
80032a6: f043 0210 orr.w r2, r3, #16
80032aa: 687b ldr r3, [r7, #4]
80032ac: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80032ae: 687b ldr r3, [r7, #4]
80032b0: 6e1b ldr r3, [r3, #96] @ 0x60
80032b2: f043 0201 orr.w r2, r3, #1
80032b6: 687b ldr r3, [r7, #4]
80032b8: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
80032ba: 2301 movs r3, #1
80032bc: e007 b.n 80032ce <ADC_ConversionStop+0x16a>
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
80032be: 687b ldr r3, [r7, #4]
80032c0: 681b ldr r3, [r3, #0]
80032c2: 689a ldr r2, [r3, #8]
80032c4: 697b ldr r3, [r7, #20]
80032c6: 4013 ands r3, r2
80032c8: 2b00 cmp r3, #0
80032ca: d1dc bne.n 8003286 <ADC_ConversionStop+0x122>
}
}
/* Return HAL status */
return HAL_OK;
80032cc: 2300 movs r3, #0
}
80032ce: 4618 mov r0, r3
80032d0: 3720 adds r7, #32
80032d2: 46bd mov sp, r7
80032d4: bd80 pop {r7, pc}
80032d6: bf00 nop
80032d8: a33fffff .word 0xa33fffff
080032dc <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
80032dc: b580 push {r7, lr}
80032de: b084 sub sp, #16
80032e0: af00 add r7, sp, #0
80032e2: 6078 str r0, [r7, #4]
uint32_t tickstart;
__IO uint32_t wait_loop_index = 0UL;
80032e4: 2300 movs r3, #0
80032e6: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80032e8: 687b ldr r3, [r7, #4]
80032ea: 681b ldr r3, [r3, #0]
80032ec: 4618 mov r0, r3
80032ee: f7fe ff67 bl 80021c0 <LL_ADC_IsEnabled>
80032f2: 4603 mov r3, r0
80032f4: 2b00 cmp r3, #0
80032f6: d169 bne.n 80033cc <ADC_Enable+0xf0>
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
80032f8: 687b ldr r3, [r7, #4]
80032fa: 681b ldr r3, [r3, #0]
80032fc: 689a ldr r2, [r3, #8]
80032fe: 4b36 ldr r3, [pc, #216] @ (80033d8 <ADC_Enable+0xfc>)
8003300: 4013 ands r3, r2
8003302: 2b00 cmp r3, #0
8003304: d00d beq.n 8003322 <ADC_Enable+0x46>
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003306: 687b ldr r3, [r7, #4]
8003308: 6ddb ldr r3, [r3, #92] @ 0x5c
800330a: f043 0210 orr.w r2, r3, #16
800330e: 687b ldr r3, [r7, #4]
8003310: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003312: 687b ldr r3, [r7, #4]
8003314: 6e1b ldr r3, [r3, #96] @ 0x60
8003316: f043 0201 orr.w r2, r3, #1
800331a: 687b ldr r3, [r7, #4]
800331c: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
800331e: 2301 movs r3, #1
8003320: e055 b.n 80033ce <ADC_Enable+0xf2>
}
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
8003322: 687b ldr r3, [r7, #4]
8003324: 681b ldr r3, [r3, #0]
8003326: 4618 mov r0, r3
8003328: f7fe ff22 bl 8002170 <LL_ADC_Enable>
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
800332c: 482b ldr r0, [pc, #172] @ (80033dc <ADC_Enable+0x100>)
800332e: f7fe fd7b bl 8001e28 <LL_ADC_GetCommonPathInternalCh>
8003332: 4603 mov r3, r0
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
8003334: f403 0300 and.w r3, r3, #8388608 @ 0x800000
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
8003338: 2b00 cmp r3, #0
800333a: d013 beq.n 8003364 <ADC_Enable+0x88>
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
800333c: 4b28 ldr r3, [pc, #160] @ (80033e0 <ADC_Enable+0x104>)
800333e: 681b ldr r3, [r3, #0]
8003340: 099b lsrs r3, r3, #6
8003342: 4a28 ldr r2, [pc, #160] @ (80033e4 <ADC_Enable+0x108>)
8003344: fba2 2303 umull r2, r3, r2, r3
8003348: 099b lsrs r3, r3, #6
800334a: 1c5a adds r2, r3, #1
800334c: 4613 mov r3, r2
800334e: 005b lsls r3, r3, #1
8003350: 4413 add r3, r2
8003352: 009b lsls r3, r3, #2
8003354: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8003356: e002 b.n 800335e <ADC_Enable+0x82>
{
wait_loop_index--;
8003358: 68bb ldr r3, [r7, #8]
800335a: 3b01 subs r3, #1
800335c: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
800335e: 68bb ldr r3, [r7, #8]
8003360: 2b00 cmp r3, #0
8003362: d1f9 bne.n 8003358 <ADC_Enable+0x7c>
}
}
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
8003364: f7fe fd2e bl 8001dc4 <HAL_GetTick>
8003368: 60f8 str r0, [r7, #12]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
800336a: e028 b.n 80033be <ADC_Enable+0xe2>
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
800336c: 687b ldr r3, [r7, #4]
800336e: 681b ldr r3, [r3, #0]
8003370: 4618 mov r0, r3
8003372: f7fe ff25 bl 80021c0 <LL_ADC_IsEnabled>
8003376: 4603 mov r3, r0
8003378: 2b00 cmp r3, #0
800337a: d104 bne.n 8003386 <ADC_Enable+0xaa>
{
LL_ADC_Enable(hadc->Instance);
800337c: 687b ldr r3, [r7, #4]
800337e: 681b ldr r3, [r3, #0]
8003380: 4618 mov r0, r3
8003382: f7fe fef5 bl 8002170 <LL_ADC_Enable>
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
8003386: f7fe fd1d bl 8001dc4 <HAL_GetTick>
800338a: 4602 mov r2, r0
800338c: 68fb ldr r3, [r7, #12]
800338e: 1ad3 subs r3, r2, r3
8003390: 2b02 cmp r3, #2
8003392: d914 bls.n 80033be <ADC_Enable+0xe2>
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8003394: 687b ldr r3, [r7, #4]
8003396: 681b ldr r3, [r3, #0]
8003398: 681b ldr r3, [r3, #0]
800339a: f003 0301 and.w r3, r3, #1
800339e: 2b01 cmp r3, #1
80033a0: d00d beq.n 80033be <ADC_Enable+0xe2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80033a2: 687b ldr r3, [r7, #4]
80033a4: 6ddb ldr r3, [r3, #92] @ 0x5c
80033a6: f043 0210 orr.w r2, r3, #16
80033aa: 687b ldr r3, [r7, #4]
80033ac: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80033ae: 687b ldr r3, [r7, #4]
80033b0: 6e1b ldr r3, [r3, #96] @ 0x60
80033b2: f043 0201 orr.w r2, r3, #1
80033b6: 687b ldr r3, [r7, #4]
80033b8: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
80033ba: 2301 movs r3, #1
80033bc: e007 b.n 80033ce <ADC_Enable+0xf2>
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
80033be: 687b ldr r3, [r7, #4]
80033c0: 681b ldr r3, [r3, #0]
80033c2: 681b ldr r3, [r3, #0]
80033c4: f003 0301 and.w r3, r3, #1
80033c8: 2b01 cmp r3, #1
80033ca: d1cf bne.n 800336c <ADC_Enable+0x90>
}
}
}
/* Return HAL status */
return HAL_OK;
80033cc: 2300 movs r3, #0
}
80033ce: 4618 mov r0, r3
80033d0: 3710 adds r7, #16
80033d2: 46bd mov sp, r7
80033d4: bd80 pop {r7, pc}
80033d6: bf00 nop
80033d8: 8000003f .word 0x8000003f
80033dc: 50000300 .word 0x50000300
80033e0: 20000018 .word 0x20000018
80033e4: 053e2d63 .word 0x053e2d63
080033e8 <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
80033e8: b580 push {r7, lr}
80033ea: b084 sub sp, #16
80033ec: af00 add r7, sp, #0
80033ee: 6078 str r0, [r7, #4]
uint32_t tickstart;
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
80033f0: 687b ldr r3, [r7, #4]
80033f2: 681b ldr r3, [r3, #0]
80033f4: 4618 mov r0, r3
80033f6: f7fe fef6 bl 80021e6 <LL_ADC_IsDisableOngoing>
80033fa: 60f8 str r0, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
80033fc: 687b ldr r3, [r7, #4]
80033fe: 681b ldr r3, [r3, #0]
8003400: 4618 mov r0, r3
8003402: f7fe fedd bl 80021c0 <LL_ADC_IsEnabled>
8003406: 4603 mov r3, r0
8003408: 2b00 cmp r3, #0
800340a: d047 beq.n 800349c <ADC_Disable+0xb4>
&& (tmp_adc_is_disable_on_going == 0UL)
800340c: 68fb ldr r3, [r7, #12]
800340e: 2b00 cmp r3, #0
8003410: d144 bne.n 800349c <ADC_Disable+0xb4>
)
{
/* Check if conditions to disable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
8003412: 687b ldr r3, [r7, #4]
8003414: 681b ldr r3, [r3, #0]
8003416: 689b ldr r3, [r3, #8]
8003418: f003 030d and.w r3, r3, #13
800341c: 2b01 cmp r3, #1
800341e: d10c bne.n 800343a <ADC_Disable+0x52>
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
8003420: 687b ldr r3, [r7, #4]
8003422: 681b ldr r3, [r3, #0]
8003424: 4618 mov r0, r3
8003426: f7fe feb7 bl 8002198 <LL_ADC_Disable>
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
800342a: 687b ldr r3, [r7, #4]
800342c: 681b ldr r3, [r3, #0]
800342e: 2203 movs r2, #3
8003430: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
8003432: f7fe fcc7 bl 8001dc4 <HAL_GetTick>
8003436: 60b8 str r0, [r7, #8]
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8003438: e029 b.n 800348e <ADC_Disable+0xa6>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800343a: 687b ldr r3, [r7, #4]
800343c: 6ddb ldr r3, [r3, #92] @ 0x5c
800343e: f043 0210 orr.w r2, r3, #16
8003442: 687b ldr r3, [r7, #4]
8003444: 65da str r2, [r3, #92] @ 0x5c
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003446: 687b ldr r3, [r7, #4]
8003448: 6e1b ldr r3, [r3, #96] @ 0x60
800344a: f043 0201 orr.w r2, r3, #1
800344e: 687b ldr r3, [r7, #4]
8003450: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8003452: 2301 movs r3, #1
8003454: e023 b.n 800349e <ADC_Disable+0xb6>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8003456: f7fe fcb5 bl 8001dc4 <HAL_GetTick>
800345a: 4602 mov r2, r0
800345c: 68bb ldr r3, [r7, #8]
800345e: 1ad3 subs r3, r2, r3
8003460: 2b02 cmp r3, #2
8003462: d914 bls.n 800348e <ADC_Disable+0xa6>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8003464: 687b ldr r3, [r7, #4]
8003466: 681b ldr r3, [r3, #0]
8003468: 689b ldr r3, [r3, #8]
800346a: f003 0301 and.w r3, r3, #1
800346e: 2b00 cmp r3, #0
8003470: d00d beq.n 800348e <ADC_Disable+0xa6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003472: 687b ldr r3, [r7, #4]
8003474: 6ddb ldr r3, [r3, #92] @ 0x5c
8003476: f043 0210 orr.w r2, r3, #16
800347a: 687b ldr r3, [r7, #4]
800347c: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800347e: 687b ldr r3, [r7, #4]
8003480: 6e1b ldr r3, [r3, #96] @ 0x60
8003482: f043 0201 orr.w r2, r3, #1
8003486: 687b ldr r3, [r7, #4]
8003488: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
800348a: 2301 movs r3, #1
800348c: e007 b.n 800349e <ADC_Disable+0xb6>
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
800348e: 687b ldr r3, [r7, #4]
8003490: 681b ldr r3, [r3, #0]
8003492: 689b ldr r3, [r3, #8]
8003494: f003 0301 and.w r3, r3, #1
8003498: 2b00 cmp r3, #0
800349a: d1dc bne.n 8003456 <ADC_Disable+0x6e>
}
}
}
/* Return HAL status */
return HAL_OK;
800349c: 2300 movs r3, #0
}
800349e: 4618 mov r0, r3
80034a0: 3710 adds r7, #16
80034a2: 46bd mov sp, r7
80034a4: bd80 pop {r7, pc}
080034a6 <LL_ADC_IsEnabled>:
{
80034a6: b480 push {r7}
80034a8: b083 sub sp, #12
80034aa: af00 add r7, sp, #0
80034ac: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80034ae: 687b ldr r3, [r7, #4]
80034b0: 689b ldr r3, [r3, #8]
80034b2: f003 0301 and.w r3, r3, #1
80034b6: 2b01 cmp r3, #1
80034b8: d101 bne.n 80034be <LL_ADC_IsEnabled+0x18>
80034ba: 2301 movs r3, #1
80034bc: e000 b.n 80034c0 <LL_ADC_IsEnabled+0x1a>
80034be: 2300 movs r3, #0
}
80034c0: 4618 mov r0, r3
80034c2: 370c adds r7, #12
80034c4: 46bd mov sp, r7
80034c6: f85d 7b04 ldr.w r7, [sp], #4
80034ca: 4770 bx lr
080034cc <LL_ADC_StartCalibration>:
{
80034cc: b480 push {r7}
80034ce: b083 sub sp, #12
80034d0: af00 add r7, sp, #0
80034d2: 6078 str r0, [r7, #4]
80034d4: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->CR,
80034d6: 687b ldr r3, [r7, #4]
80034d8: 689b ldr r3, [r3, #8]
80034da: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000
80034de: f023 033f bic.w r3, r3, #63 @ 0x3f
80034e2: 683a ldr r2, [r7, #0]
80034e4: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
80034e8: 4313 orrs r3, r2
80034ea: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
80034ee: 687b ldr r3, [r7, #4]
80034f0: 609a str r2, [r3, #8]
}
80034f2: bf00 nop
80034f4: 370c adds r7, #12
80034f6: 46bd mov sp, r7
80034f8: f85d 7b04 ldr.w r7, [sp], #4
80034fc: 4770 bx lr
080034fe <LL_ADC_IsCalibrationOnGoing>:
{
80034fe: b480 push {r7}
8003500: b083 sub sp, #12
8003502: af00 add r7, sp, #0
8003504: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
8003506: 687b ldr r3, [r7, #4]
8003508: 689b ldr r3, [r3, #8]
800350a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800350e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8003512: d101 bne.n 8003518 <LL_ADC_IsCalibrationOnGoing+0x1a>
8003514: 2301 movs r3, #1
8003516: e000 b.n 800351a <LL_ADC_IsCalibrationOnGoing+0x1c>
8003518: 2300 movs r3, #0
}
800351a: 4618 mov r0, r3
800351c: 370c adds r7, #12
800351e: 46bd mov sp, r7
8003520: f85d 7b04 ldr.w r7, [sp], #4
8003524: 4770 bx lr
08003526 <LL_ADC_REG_IsConversionOngoing>:
{
8003526: b480 push {r7}
8003528: b083 sub sp, #12
800352a: af00 add r7, sp, #0
800352c: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
800352e: 687b ldr r3, [r7, #4]
8003530: 689b ldr r3, [r3, #8]
8003532: f003 0304 and.w r3, r3, #4
8003536: 2b04 cmp r3, #4
8003538: d101 bne.n 800353e <LL_ADC_REG_IsConversionOngoing+0x18>
800353a: 2301 movs r3, #1
800353c: e000 b.n 8003540 <LL_ADC_REG_IsConversionOngoing+0x1a>
800353e: 2300 movs r3, #0
}
8003540: 4618 mov r0, r3
8003542: 370c adds r7, #12
8003544: 46bd mov sp, r7
8003546: f85d 7b04 ldr.w r7, [sp], #4
800354a: 4770 bx lr
0800354c <HAL_ADCEx_Calibration_Start>:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
800354c: b580 push {r7, lr}
800354e: b084 sub sp, #16
8003550: af00 add r7, sp, #0
8003552: 6078 str r0, [r7, #4]
8003554: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
8003556: 2300 movs r3, #0
8003558: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Process locked */
__HAL_LOCK(hadc);
800355a: 687b ldr r3, [r7, #4]
800355c: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8003560: 2b01 cmp r3, #1
8003562: d101 bne.n 8003568 <HAL_ADCEx_Calibration_Start+0x1c>
8003564: 2302 movs r3, #2
8003566: e04d b.n 8003604 <HAL_ADCEx_Calibration_Start+0xb8>
8003568: 687b ldr r3, [r7, #4]
800356a: 2201 movs r2, #1
800356c: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Calibration prerequisite: ADC must be disabled. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
8003570: 6878 ldr r0, [r7, #4]
8003572: f7ff ff39 bl 80033e8 <ADC_Disable>
8003576: 4603 mov r3, r0
8003578: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
800357a: 7bfb ldrb r3, [r7, #15]
800357c: 2b00 cmp r3, #0
800357e: d136 bne.n 80035ee <HAL_ADCEx_Calibration_Start+0xa2>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8003580: 687b ldr r3, [r7, #4]
8003582: 6ddb ldr r3, [r3, #92] @ 0x5c
8003584: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8003588: f023 0302 bic.w r3, r3, #2
800358c: f043 0202 orr.w r2, r3, #2
8003590: 687b ldr r3, [r7, #4]
8003592: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration in mode single-ended or differential */
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
8003594: 687b ldr r3, [r7, #4]
8003596: 681b ldr r3, [r3, #0]
8003598: 6839 ldr r1, [r7, #0]
800359a: 4618 mov r0, r3
800359c: f7ff ff96 bl 80034cc <LL_ADC_StartCalibration>
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
80035a0: e014 b.n 80035cc <HAL_ADCEx_Calibration_Start+0x80>
{
wait_loop_index++;
80035a2: 68bb ldr r3, [r7, #8]
80035a4: 3301 adds r3, #1
80035a6: 60bb str r3, [r7, #8]
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
80035a8: 68bb ldr r3, [r7, #8]
80035aa: 4a18 ldr r2, [pc, #96] @ (800360c <HAL_ADCEx_Calibration_Start+0xc0>)
80035ac: 4293 cmp r3, r2
80035ae: d90d bls.n 80035cc <HAL_ADCEx_Calibration_Start+0x80>
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
80035b0: 687b ldr r3, [r7, #4]
80035b2: 6ddb ldr r3, [r3, #92] @ 0x5c
80035b4: f023 0312 bic.w r3, r3, #18
80035b8: f043 0210 orr.w r2, r3, #16
80035bc: 687b ldr r3, [r7, #4]
80035be: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Process unlocked */
__HAL_UNLOCK(hadc);
80035c0: 687b ldr r3, [r7, #4]
80035c2: 2200 movs r2, #0
80035c4: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
80035c8: 2301 movs r3, #1
80035ca: e01b b.n 8003604 <HAL_ADCEx_Calibration_Start+0xb8>
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
80035cc: 687b ldr r3, [r7, #4]
80035ce: 681b ldr r3, [r3, #0]
80035d0: 4618 mov r0, r3
80035d2: f7ff ff94 bl 80034fe <LL_ADC_IsCalibrationOnGoing>
80035d6: 4603 mov r3, r0
80035d8: 2b00 cmp r3, #0
80035da: d1e2 bne.n 80035a2 <HAL_ADCEx_Calibration_Start+0x56>
}
}
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
80035dc: 687b ldr r3, [r7, #4]
80035de: 6ddb ldr r3, [r3, #92] @ 0x5c
80035e0: f023 0303 bic.w r3, r3, #3
80035e4: f043 0201 orr.w r2, r3, #1
80035e8: 687b ldr r3, [r7, #4]
80035ea: 65da str r2, [r3, #92] @ 0x5c
80035ec: e005 b.n 80035fa <HAL_ADCEx_Calibration_Start+0xae>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80035ee: 687b ldr r3, [r7, #4]
80035f0: 6ddb ldr r3, [r3, #92] @ 0x5c
80035f2: f043 0210 orr.w r2, r3, #16
80035f6: 687b ldr r3, [r7, #4]
80035f8: 65da str r2, [r3, #92] @ 0x5c
/* Note: No need to update variable "tmp_hal_status" here: already set */
/* to state "HAL_ERROR" by function disabling the ADC. */
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80035fa: 687b ldr r3, [r7, #4]
80035fc: 2200 movs r2, #0
80035fe: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
8003602: 7bfb ldrb r3, [r7, #15]
}
8003604: 4618 mov r0, r3
8003606: 3710 adds r7, #16
8003608: 46bd mov sp, r7
800360a: bd80 pop {r7, pc}
800360c: 0004de01 .word 0x0004de01
08003610 <HAL_ADCEx_MultiModeConfigChannel>:
* @param hadc Master ADC handle
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
{
8003610: b590 push {r4, r7, lr}
8003612: b0a1 sub sp, #132 @ 0x84
8003614: af00 add r7, sp, #0
8003616: 6078 str r0, [r7, #4]
8003618: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800361a: 2300 movs r3, #0
800361c: f887 307f strb.w r3, [r7, #127] @ 0x7f
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
8003620: 687b ldr r3, [r7, #4]
8003622: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8003626: 2b01 cmp r3, #1
8003628: d101 bne.n 800362e <HAL_ADCEx_MultiModeConfigChannel+0x1e>
800362a: 2302 movs r3, #2
800362c: e08b b.n 8003746 <HAL_ADCEx_MultiModeConfigChannel+0x136>
800362e: 687b ldr r3, [r7, #4]
8003630: 2201 movs r2, #1
8003632: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
8003636: 2300 movs r3, #0
8003638: 667b str r3, [r7, #100] @ 0x64
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
800363a: 2300 movs r3, #0
800363c: 66bb str r3, [r7, #104] @ 0x68
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
800363e: 687b ldr r3, [r7, #4]
8003640: 681b ldr r3, [r3, #0]
8003642: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8003646: d102 bne.n 800364e <HAL_ADCEx_MultiModeConfigChannel+0x3e>
8003648: 4b41 ldr r3, [pc, #260] @ (8003750 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
800364a: 60bb str r3, [r7, #8]
800364c: e001 b.n 8003652 <HAL_ADCEx_MultiModeConfigChannel+0x42>
800364e: 2300 movs r3, #0
8003650: 60bb str r3, [r7, #8]
if (tmp_hadc_slave.Instance == NULL)
8003652: 68bb ldr r3, [r7, #8]
8003654: 2b00 cmp r3, #0
8003656: d10b bne.n 8003670 <HAL_ADCEx_MultiModeConfigChannel+0x60>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003658: 687b ldr r3, [r7, #4]
800365a: 6ddb ldr r3, [r3, #92] @ 0x5c
800365c: f043 0220 orr.w r2, r3, #32
8003660: 687b ldr r3, [r7, #4]
8003662: 65da str r2, [r3, #92] @ 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003664: 687b ldr r3, [r7, #4]
8003666: 2200 movs r2, #0
8003668: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
800366c: 2301 movs r3, #1
800366e: e06a b.n 8003746 <HAL_ADCEx_MultiModeConfigChannel+0x136>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
8003670: 68bb ldr r3, [r7, #8]
8003672: 4618 mov r0, r3
8003674: f7ff ff57 bl 8003526 <LL_ADC_REG_IsConversionOngoing>
8003678: 67b8 str r0, [r7, #120] @ 0x78
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
800367a: 687b ldr r3, [r7, #4]
800367c: 681b ldr r3, [r3, #0]
800367e: 4618 mov r0, r3
8003680: f7ff ff51 bl 8003526 <LL_ADC_REG_IsConversionOngoing>
8003684: 4603 mov r3, r0
8003686: 2b00 cmp r3, #0
8003688: d14c bne.n 8003724 <HAL_ADCEx_MultiModeConfigChannel+0x114>
&& (tmp_hadc_slave_conversion_on_going == 0UL))
800368a: 6fbb ldr r3, [r7, #120] @ 0x78
800368c: 2b00 cmp r3, #0
800368e: d149 bne.n 8003724 <HAL_ADCEx_MultiModeConfigChannel+0x114>
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
8003690: 4b30 ldr r3, [pc, #192] @ (8003754 <HAL_ADCEx_MultiModeConfigChannel+0x144>)
8003692: 677b str r3, [r7, #116] @ 0x74
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003694: 683b ldr r3, [r7, #0]
8003696: 681b ldr r3, [r3, #0]
8003698: 2b00 cmp r3, #0
800369a: d028 beq.n 80036ee <HAL_ADCEx_MultiModeConfigChannel+0xde>
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
800369c: 6f7b ldr r3, [r7, #116] @ 0x74
800369e: 689b ldr r3, [r3, #8]
80036a0: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80036a4: 683b ldr r3, [r7, #0]
80036a6: 6859 ldr r1, [r3, #4]
80036a8: 687b ldr r3, [r7, #4]
80036aa: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
80036ae: 035b lsls r3, r3, #13
80036b0: 430b orrs r3, r1
80036b2: 431a orrs r2, r3
80036b4: 6f7b ldr r3, [r7, #116] @ 0x74
80036b6: 609a str r2, [r3, #8]
/* from 1 to 10 clock cycles for 10 bits, */
/* from 1 to 8 clock cycles for 8 bits */
/* from 1 to 6 clock cycles for 6 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80036b8: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
80036bc: f7ff fef3 bl 80034a6 <LL_ADC_IsEnabled>
80036c0: 4604 mov r4, r0
80036c2: 4823 ldr r0, [pc, #140] @ (8003750 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
80036c4: f7ff feef bl 80034a6 <LL_ADC_IsEnabled>
80036c8: 4603 mov r3, r0
80036ca: 4323 orrs r3, r4
80036cc: 2b00 cmp r3, #0
80036ce: d133 bne.n 8003738 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
MODIFY_REG(tmpADC_Common->CCR,
80036d0: 6f7b ldr r3, [r7, #116] @ 0x74
80036d2: 689b ldr r3, [r3, #8]
80036d4: f423 6371 bic.w r3, r3, #3856 @ 0xf10
80036d8: f023 030f bic.w r3, r3, #15
80036dc: 683a ldr r2, [r7, #0]
80036de: 6811 ldr r1, [r2, #0]
80036e0: 683a ldr r2, [r7, #0]
80036e2: 6892 ldr r2, [r2, #8]
80036e4: 430a orrs r2, r1
80036e6: 431a orrs r2, r3
80036e8: 6f7b ldr r3, [r7, #116] @ 0x74
80036ea: 609a str r2, [r3, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
80036ec: e024 b.n 8003738 <HAL_ADCEx_MultiModeConfigChannel+0x128>
);
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
80036ee: 6f7b ldr r3, [r7, #116] @ 0x74
80036f0: 689b ldr r3, [r3, #8]
80036f2: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80036f6: 6f7b ldr r3, [r7, #116] @ 0x74
80036f8: 609a str r2, [r3, #8]
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80036fa: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
80036fe: f7ff fed2 bl 80034a6 <LL_ADC_IsEnabled>
8003702: 4604 mov r4, r0
8003704: 4812 ldr r0, [pc, #72] @ (8003750 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
8003706: f7ff fece bl 80034a6 <LL_ADC_IsEnabled>
800370a: 4603 mov r3, r0
800370c: 4323 orrs r3, r4
800370e: 2b00 cmp r3, #0
8003710: d112 bne.n 8003738 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
8003712: 6f7b ldr r3, [r7, #116] @ 0x74
8003714: 689b ldr r3, [r3, #8]
8003716: f423 6371 bic.w r3, r3, #3856 @ 0xf10
800371a: f023 030f bic.w r3, r3, #15
800371e: 6f7a ldr r2, [r7, #116] @ 0x74
8003720: 6093 str r3, [r2, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003722: e009 b.n 8003738 <HAL_ADCEx_MultiModeConfigChannel+0x128>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003724: 687b ldr r3, [r7, #4]
8003726: 6ddb ldr r3, [r3, #92] @ 0x5c
8003728: f043 0220 orr.w r2, r3, #32
800372c: 687b ldr r3, [r7, #4]
800372e: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8003730: 2301 movs r3, #1
8003732: f887 307f strb.w r3, [r7, #127] @ 0x7f
8003736: e000 b.n 800373a <HAL_ADCEx_MultiModeConfigChannel+0x12a>
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003738: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
800373a: 687b ldr r3, [r7, #4]
800373c: 2200 movs r2, #0
800373e: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
8003742: f897 307f ldrb.w r3, [r7, #127] @ 0x7f
}
8003746: 4618 mov r0, r3
8003748: 3784 adds r7, #132 @ 0x84
800374a: 46bd mov sp, r7
800374c: bd90 pop {r4, r7, pc}
800374e: bf00 nop
8003750: 50000100 .word 0x50000100
8003754: 50000300 .word 0x50000300
08003758 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003758: b480 push {r7}
800375a: b085 sub sp, #20
800375c: af00 add r7, sp, #0
800375e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003760: 687b ldr r3, [r7, #4]
8003762: f003 0307 and.w r3, r3, #7
8003766: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8003768: 4b0c ldr r3, [pc, #48] @ (800379c <__NVIC_SetPriorityGrouping+0x44>)
800376a: 68db ldr r3, [r3, #12]
800376c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800376e: 68ba ldr r2, [r7, #8]
8003770: f64f 03ff movw r3, #63743 @ 0xf8ff
8003774: 4013 ands r3, r2
8003776: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8003778: 68fb ldr r3, [r7, #12]
800377a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800377c: 68bb ldr r3, [r7, #8]
800377e: 4313 orrs r3, r2
reg_value = (reg_value |
8003780: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003784: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003788: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800378a: 4a04 ldr r2, [pc, #16] @ (800379c <__NVIC_SetPriorityGrouping+0x44>)
800378c: 68bb ldr r3, [r7, #8]
800378e: 60d3 str r3, [r2, #12]
}
8003790: bf00 nop
8003792: 3714 adds r7, #20
8003794: 46bd mov sp, r7
8003796: f85d 7b04 ldr.w r7, [sp], #4
800379a: 4770 bx lr
800379c: e000ed00 .word 0xe000ed00
080037a0 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80037a0: b480 push {r7}
80037a2: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80037a4: 4b04 ldr r3, [pc, #16] @ (80037b8 <__NVIC_GetPriorityGrouping+0x18>)
80037a6: 68db ldr r3, [r3, #12]
80037a8: 0a1b lsrs r3, r3, #8
80037aa: f003 0307 and.w r3, r3, #7
}
80037ae: 4618 mov r0, r3
80037b0: 46bd mov sp, r7
80037b2: f85d 7b04 ldr.w r7, [sp], #4
80037b6: 4770 bx lr
80037b8: e000ed00 .word 0xe000ed00
080037bc <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80037bc: b480 push {r7}
80037be: b083 sub sp, #12
80037c0: af00 add r7, sp, #0
80037c2: 4603 mov r3, r0
80037c4: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80037c6: f997 3007 ldrsb.w r3, [r7, #7]
80037ca: 2b00 cmp r3, #0
80037cc: db0b blt.n 80037e6 <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80037ce: 79fb ldrb r3, [r7, #7]
80037d0: f003 021f and.w r2, r3, #31
80037d4: 4907 ldr r1, [pc, #28] @ (80037f4 <__NVIC_EnableIRQ+0x38>)
80037d6: f997 3007 ldrsb.w r3, [r7, #7]
80037da: 095b lsrs r3, r3, #5
80037dc: 2001 movs r0, #1
80037de: fa00 f202 lsl.w r2, r0, r2
80037e2: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
80037e6: bf00 nop
80037e8: 370c adds r7, #12
80037ea: 46bd mov sp, r7
80037ec: f85d 7b04 ldr.w r7, [sp], #4
80037f0: 4770 bx lr
80037f2: bf00 nop
80037f4: e000e100 .word 0xe000e100
080037f8 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80037f8: b480 push {r7}
80037fa: b083 sub sp, #12
80037fc: af00 add r7, sp, #0
80037fe: 4603 mov r3, r0
8003800: 6039 str r1, [r7, #0]
8003802: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003804: f997 3007 ldrsb.w r3, [r7, #7]
8003808: 2b00 cmp r3, #0
800380a: db0a blt.n 8003822 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800380c: 683b ldr r3, [r7, #0]
800380e: b2da uxtb r2, r3
8003810: 490c ldr r1, [pc, #48] @ (8003844 <__NVIC_SetPriority+0x4c>)
8003812: f997 3007 ldrsb.w r3, [r7, #7]
8003816: 0112 lsls r2, r2, #4
8003818: b2d2 uxtb r2, r2
800381a: 440b add r3, r1
800381c: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8003820: e00a b.n 8003838 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003822: 683b ldr r3, [r7, #0]
8003824: b2da uxtb r2, r3
8003826: 4908 ldr r1, [pc, #32] @ (8003848 <__NVIC_SetPriority+0x50>)
8003828: 79fb ldrb r3, [r7, #7]
800382a: f003 030f and.w r3, r3, #15
800382e: 3b04 subs r3, #4
8003830: 0112 lsls r2, r2, #4
8003832: b2d2 uxtb r2, r2
8003834: 440b add r3, r1
8003836: 761a strb r2, [r3, #24]
}
8003838: bf00 nop
800383a: 370c adds r7, #12
800383c: 46bd mov sp, r7
800383e: f85d 7b04 ldr.w r7, [sp], #4
8003842: 4770 bx lr
8003844: e000e100 .word 0xe000e100
8003848: e000ed00 .word 0xe000ed00
0800384c <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
800384c: b480 push {r7}
800384e: b089 sub sp, #36 @ 0x24
8003850: af00 add r7, sp, #0
8003852: 60f8 str r0, [r7, #12]
8003854: 60b9 str r1, [r7, #8]
8003856: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003858: 68fb ldr r3, [r7, #12]
800385a: f003 0307 and.w r3, r3, #7
800385e: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8003860: 69fb ldr r3, [r7, #28]
8003862: f1c3 0307 rsb r3, r3, #7
8003866: 2b04 cmp r3, #4
8003868: bf28 it cs
800386a: 2304 movcs r3, #4
800386c: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800386e: 69fb ldr r3, [r7, #28]
8003870: 3304 adds r3, #4
8003872: 2b06 cmp r3, #6
8003874: d902 bls.n 800387c <NVIC_EncodePriority+0x30>
8003876: 69fb ldr r3, [r7, #28]
8003878: 3b03 subs r3, #3
800387a: e000 b.n 800387e <NVIC_EncodePriority+0x32>
800387c: 2300 movs r3, #0
800387e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003880: f04f 32ff mov.w r2, #4294967295
8003884: 69bb ldr r3, [r7, #24]
8003886: fa02 f303 lsl.w r3, r2, r3
800388a: 43da mvns r2, r3
800388c: 68bb ldr r3, [r7, #8]
800388e: 401a ands r2, r3
8003890: 697b ldr r3, [r7, #20]
8003892: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8003894: f04f 31ff mov.w r1, #4294967295
8003898: 697b ldr r3, [r7, #20]
800389a: fa01 f303 lsl.w r3, r1, r3
800389e: 43d9 mvns r1, r3
80038a0: 687b ldr r3, [r7, #4]
80038a2: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80038a4: 4313 orrs r3, r2
);
}
80038a6: 4618 mov r0, r3
80038a8: 3724 adds r7, #36 @ 0x24
80038aa: 46bd mov sp, r7
80038ac: f85d 7b04 ldr.w r7, [sp], #4
80038b0: 4770 bx lr
...
080038b4 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80038b4: b580 push {r7, lr}
80038b6: b082 sub sp, #8
80038b8: af00 add r7, sp, #0
80038ba: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80038bc: 687b ldr r3, [r7, #4]
80038be: 3b01 subs r3, #1
80038c0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80038c4: d301 bcc.n 80038ca <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80038c6: 2301 movs r3, #1
80038c8: e00f b.n 80038ea <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80038ca: 4a0a ldr r2, [pc, #40] @ (80038f4 <SysTick_Config+0x40>)
80038cc: 687b ldr r3, [r7, #4]
80038ce: 3b01 subs r3, #1
80038d0: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80038d2: 210f movs r1, #15
80038d4: f04f 30ff mov.w r0, #4294967295
80038d8: f7ff ff8e bl 80037f8 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80038dc: 4b05 ldr r3, [pc, #20] @ (80038f4 <SysTick_Config+0x40>)
80038de: 2200 movs r2, #0
80038e0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80038e2: 4b04 ldr r3, [pc, #16] @ (80038f4 <SysTick_Config+0x40>)
80038e4: 2207 movs r2, #7
80038e6: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80038e8: 2300 movs r3, #0
}
80038ea: 4618 mov r0, r3
80038ec: 3708 adds r7, #8
80038ee: 46bd mov sp, r7
80038f0: bd80 pop {r7, pc}
80038f2: bf00 nop
80038f4: e000e010 .word 0xe000e010
080038f8 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80038f8: b580 push {r7, lr}
80038fa: b082 sub sp, #8
80038fc: af00 add r7, sp, #0
80038fe: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003900: 6878 ldr r0, [r7, #4]
8003902: f7ff ff29 bl 8003758 <__NVIC_SetPriorityGrouping>
}
8003906: bf00 nop
8003908: 3708 adds r7, #8
800390a: 46bd mov sp, r7
800390c: bd80 pop {r7, pc}
0800390e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800390e: b580 push {r7, lr}
8003910: b086 sub sp, #24
8003912: af00 add r7, sp, #0
8003914: 4603 mov r3, r0
8003916: 60b9 str r1, [r7, #8]
8003918: 607a str r2, [r7, #4]
800391a: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
800391c: f7ff ff40 bl 80037a0 <__NVIC_GetPriorityGrouping>
8003920: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8003922: 687a ldr r2, [r7, #4]
8003924: 68b9 ldr r1, [r7, #8]
8003926: 6978 ldr r0, [r7, #20]
8003928: f7ff ff90 bl 800384c <NVIC_EncodePriority>
800392c: 4602 mov r2, r0
800392e: f997 300f ldrsb.w r3, [r7, #15]
8003932: 4611 mov r1, r2
8003934: 4618 mov r0, r3
8003936: f7ff ff5f bl 80037f8 <__NVIC_SetPriority>
}
800393a: bf00 nop
800393c: 3718 adds r7, #24
800393e: 46bd mov sp, r7
8003940: bd80 pop {r7, pc}
08003942 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003942: b580 push {r7, lr}
8003944: b082 sub sp, #8
8003946: af00 add r7, sp, #0
8003948: 4603 mov r3, r0
800394a: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
800394c: f997 3007 ldrsb.w r3, [r7, #7]
8003950: 4618 mov r0, r3
8003952: f7ff ff33 bl 80037bc <__NVIC_EnableIRQ>
}
8003956: bf00 nop
8003958: 3708 adds r7, #8
800395a: 46bd mov sp, r7
800395c: bd80 pop {r7, pc}
0800395e <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800395e: b580 push {r7, lr}
8003960: b082 sub sp, #8
8003962: af00 add r7, sp, #0
8003964: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8003966: 6878 ldr r0, [r7, #4]
8003968: f7ff ffa4 bl 80038b4 <SysTick_Config>
800396c: 4603 mov r3, r0
}
800396e: 4618 mov r0, r3
8003970: 3708 adds r7, #8
8003972: 46bd mov sp, r7
8003974: bd80 pop {r7, pc}
08003976 <HAL_DMA_Abort>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8003976: b480 push {r7}
8003978: b085 sub sp, #20
800397a: af00 add r7, sp, #0
800397c: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800397e: 2300 movs r3, #0
8003980: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
8003982: 687b ldr r3, [r7, #4]
8003984: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8003988: b2db uxtb r3, r3
800398a: 2b02 cmp r3, #2
800398c: d005 beq.n 800399a <HAL_DMA_Abort+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800398e: 687b ldr r3, [r7, #4]
8003990: 2204 movs r2, #4
8003992: 63da str r2, [r3, #60] @ 0x3c
status = HAL_ERROR;
8003994: 2301 movs r3, #1
8003996: 73fb strb r3, [r7, #15]
8003998: e037 b.n 8003a0a <HAL_DMA_Abort+0x94>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800399a: 687b ldr r3, [r7, #4]
800399c: 681b ldr r3, [r3, #0]
800399e: 681a ldr r2, [r3, #0]
80039a0: 687b ldr r3, [r7, #4]
80039a2: 681b ldr r3, [r3, #0]
80039a4: f022 020e bic.w r2, r2, #14
80039a8: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
80039aa: 687b ldr r3, [r7, #4]
80039ac: 6c9b ldr r3, [r3, #72] @ 0x48
80039ae: 681a ldr r2, [r3, #0]
80039b0: 687b ldr r3, [r7, #4]
80039b2: 6c9b ldr r3, [r3, #72] @ 0x48
80039b4: f422 7280 bic.w r2, r2, #256 @ 0x100
80039b8: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
80039ba: 687b ldr r3, [r7, #4]
80039bc: 681b ldr r3, [r3, #0]
80039be: 681a ldr r2, [r3, #0]
80039c0: 687b ldr r3, [r7, #4]
80039c2: 681b ldr r3, [r3, #0]
80039c4: f022 0201 bic.w r2, r2, #1
80039c8: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
80039ca: 687b ldr r3, [r7, #4]
80039cc: 6c5b ldr r3, [r3, #68] @ 0x44
80039ce: f003 021f and.w r2, r3, #31
80039d2: 687b ldr r3, [r7, #4]
80039d4: 6c1b ldr r3, [r3, #64] @ 0x40
80039d6: 2101 movs r1, #1
80039d8: fa01 f202 lsl.w r2, r1, r2
80039dc: 605a str r2, [r3, #4]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
80039de: 687b ldr r3, [r7, #4]
80039e0: 6cdb ldr r3, [r3, #76] @ 0x4c
80039e2: 687a ldr r2, [r7, #4]
80039e4: 6d12 ldr r2, [r2, #80] @ 0x50
80039e6: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
80039e8: 687b ldr r3, [r7, #4]
80039ea: 6d5b ldr r3, [r3, #84] @ 0x54
80039ec: 2b00 cmp r3, #0
80039ee: d00c beq.n 8003a0a <HAL_DMA_Abort+0x94>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
80039f0: 687b ldr r3, [r7, #4]
80039f2: 6d5b ldr r3, [r3, #84] @ 0x54
80039f4: 681a ldr r2, [r3, #0]
80039f6: 687b ldr r3, [r7, #4]
80039f8: 6d5b ldr r3, [r3, #84] @ 0x54
80039fa: f422 7280 bic.w r2, r2, #256 @ 0x100
80039fe: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003a00: 687b ldr r3, [r7, #4]
8003a02: 6d9b ldr r3, [r3, #88] @ 0x58
8003a04: 687a ldr r2, [r7, #4]
8003a06: 6dd2 ldr r2, [r2, #92] @ 0x5c
8003a08: 605a str r2, [r3, #4]
}
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003a0a: 687b ldr r3, [r7, #4]
8003a0c: 2201 movs r2, #1
8003a0e: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003a12: 687b ldr r3, [r7, #4]
8003a14: 2200 movs r2, #0
8003a16: f883 2024 strb.w r2, [r3, #36] @ 0x24
return status;
8003a1a: 7bfb ldrb r3, [r7, #15]
}
8003a1c: 4618 mov r0, r3
8003a1e: 3714 adds r7, #20
8003a20: 46bd mov sp, r7
8003a22: f85d 7b04 ldr.w r7, [sp], #4
8003a26: 4770 bx lr
08003a28 <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8003a28: b580 push {r7, lr}
8003a2a: b084 sub sp, #16
8003a2c: af00 add r7, sp, #0
8003a2e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003a30: 2300 movs r3, #0
8003a32: 73fb strb r3, [r7, #15]
if (HAL_DMA_STATE_BUSY != hdma->State)
8003a34: 687b ldr r3, [r7, #4]
8003a36: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8003a3a: b2db uxtb r3, r3
8003a3c: 2b02 cmp r3, #2
8003a3e: d00d beq.n 8003a5c <HAL_DMA_Abort_IT+0x34>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003a40: 687b ldr r3, [r7, #4]
8003a42: 2204 movs r2, #4
8003a44: 63da str r2, [r3, #60] @ 0x3c
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003a46: 687b ldr r3, [r7, #4]
8003a48: 2201 movs r2, #1
8003a4a: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003a4e: 687b ldr r3, [r7, #4]
8003a50: 2200 movs r2, #0
8003a52: f883 2024 strb.w r2, [r3, #36] @ 0x24
status = HAL_ERROR;
8003a56: 2301 movs r3, #1
8003a58: 73fb strb r3, [r7, #15]
8003a5a: e047 b.n 8003aec <HAL_DMA_Abort_IT+0xc4>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003a5c: 687b ldr r3, [r7, #4]
8003a5e: 681b ldr r3, [r3, #0]
8003a60: 681a ldr r2, [r3, #0]
8003a62: 687b ldr r3, [r7, #4]
8003a64: 681b ldr r3, [r3, #0]
8003a66: f022 020e bic.w r2, r2, #14
8003a6a: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003a6c: 687b ldr r3, [r7, #4]
8003a6e: 681b ldr r3, [r3, #0]
8003a70: 681a ldr r2, [r3, #0]
8003a72: 687b ldr r3, [r7, #4]
8003a74: 681b ldr r3, [r3, #0]
8003a76: f022 0201 bic.w r2, r2, #1
8003a7a: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003a7c: 687b ldr r3, [r7, #4]
8003a7e: 6c9b ldr r3, [r3, #72] @ 0x48
8003a80: 681a ldr r2, [r3, #0]
8003a82: 687b ldr r3, [r7, #4]
8003a84: 6c9b ldr r3, [r3, #72] @ 0x48
8003a86: f422 7280 bic.w r2, r2, #256 @ 0x100
8003a8a: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
8003a8c: 687b ldr r3, [r7, #4]
8003a8e: 6c5b ldr r3, [r3, #68] @ 0x44
8003a90: f003 021f and.w r2, r3, #31
8003a94: 687b ldr r3, [r7, #4]
8003a96: 6c1b ldr r3, [r3, #64] @ 0x40
8003a98: 2101 movs r1, #1
8003a9a: fa01 f202 lsl.w r2, r1, r2
8003a9e: 605a str r2, [r3, #4]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003aa0: 687b ldr r3, [r7, #4]
8003aa2: 6cdb ldr r3, [r3, #76] @ 0x4c
8003aa4: 687a ldr r2, [r7, #4]
8003aa6: 6d12 ldr r2, [r2, #80] @ 0x50
8003aa8: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003aaa: 687b ldr r3, [r7, #4]
8003aac: 6d5b ldr r3, [r3, #84] @ 0x54
8003aae: 2b00 cmp r3, #0
8003ab0: d00c beq.n 8003acc <HAL_DMA_Abort_IT+0xa4>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8003ab2: 687b ldr r3, [r7, #4]
8003ab4: 6d5b ldr r3, [r3, #84] @ 0x54
8003ab6: 681a ldr r2, [r3, #0]
8003ab8: 687b ldr r3, [r7, #4]
8003aba: 6d5b ldr r3, [r3, #84] @ 0x54
8003abc: f422 7280 bic.w r2, r2, #256 @ 0x100
8003ac0: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003ac2: 687b ldr r3, [r7, #4]
8003ac4: 6d9b ldr r3, [r3, #88] @ 0x58
8003ac6: 687a ldr r2, [r7, #4]
8003ac8: 6dd2 ldr r2, [r2, #92] @ 0x5c
8003aca: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003acc: 687b ldr r3, [r7, #4]
8003ace: 2201 movs r2, #1
8003ad0: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003ad4: 687b ldr r3, [r7, #4]
8003ad6: 2200 movs r2, #0
8003ad8: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
8003adc: 687b ldr r3, [r7, #4]
8003ade: 6b9b ldr r3, [r3, #56] @ 0x38
8003ae0: 2b00 cmp r3, #0
8003ae2: d003 beq.n 8003aec <HAL_DMA_Abort_IT+0xc4>
{
hdma->XferAbortCallback(hdma);
8003ae4: 687b ldr r3, [r7, #4]
8003ae6: 6b9b ldr r3, [r3, #56] @ 0x38
8003ae8: 6878 ldr r0, [r7, #4]
8003aea: 4798 blx r3
}
}
return status;
8003aec: 7bfb ldrb r3, [r7, #15]
}
8003aee: 4618 mov r0, r3
8003af0: 3710 adds r7, #16
8003af2: 46bd mov sp, r7
8003af4: bd80 pop {r7, pc}
...
08003af8 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8003af8: b480 push {r7}
8003afa: b087 sub sp, #28
8003afc: af00 add r7, sp, #0
8003afe: 6078 str r0, [r7, #4]
8003b00: 6039 str r1, [r7, #0]
uint32_t position = 0x00U;
8003b02: 2300 movs r3, #0
8003b04: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0U)
8003b06: e15a b.n 8003dbe <HAL_GPIO_Init+0x2c6>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8003b08: 683b ldr r3, [r7, #0]
8003b0a: 681a ldr r2, [r3, #0]
8003b0c: 2101 movs r1, #1
8003b0e: 697b ldr r3, [r7, #20]
8003b10: fa01 f303 lsl.w r3, r1, r3
8003b14: 4013 ands r3, r2
8003b16: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8003b18: 68fb ldr r3, [r7, #12]
8003b1a: 2b00 cmp r3, #0
8003b1c: f000 814c beq.w 8003db8 <HAL_GPIO_Init+0x2c0>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8003b20: 683b ldr r3, [r7, #0]
8003b22: 685b ldr r3, [r3, #4]
8003b24: f003 0303 and.w r3, r3, #3
8003b28: 2b01 cmp r3, #1
8003b2a: d005 beq.n 8003b38 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8003b2c: 683b ldr r3, [r7, #0]
8003b2e: 685b ldr r3, [r3, #4]
8003b30: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8003b34: 2b02 cmp r3, #2
8003b36: d130 bne.n 8003b9a <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8003b38: 687b ldr r3, [r7, #4]
8003b3a: 689b ldr r3, [r3, #8]
8003b3c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8003b3e: 697b ldr r3, [r7, #20]
8003b40: 005b lsls r3, r3, #1
8003b42: 2203 movs r2, #3
8003b44: fa02 f303 lsl.w r3, r2, r3
8003b48: 43db mvns r3, r3
8003b4a: 693a ldr r2, [r7, #16]
8003b4c: 4013 ands r3, r2
8003b4e: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2U));
8003b50: 683b ldr r3, [r7, #0]
8003b52: 68da ldr r2, [r3, #12]
8003b54: 697b ldr r3, [r7, #20]
8003b56: 005b lsls r3, r3, #1
8003b58: fa02 f303 lsl.w r3, r2, r3
8003b5c: 693a ldr r2, [r7, #16]
8003b5e: 4313 orrs r3, r2
8003b60: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8003b62: 687b ldr r3, [r7, #4]
8003b64: 693a ldr r2, [r7, #16]
8003b66: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8003b68: 687b ldr r3, [r7, #4]
8003b6a: 685b ldr r3, [r3, #4]
8003b6c: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8003b6e: 2201 movs r2, #1
8003b70: 697b ldr r3, [r7, #20]
8003b72: fa02 f303 lsl.w r3, r2, r3
8003b76: 43db mvns r3, r3
8003b78: 693a ldr r2, [r7, #16]
8003b7a: 4013 ands r3, r2
8003b7c: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8003b7e: 683b ldr r3, [r7, #0]
8003b80: 685b ldr r3, [r3, #4]
8003b82: 091b lsrs r3, r3, #4
8003b84: f003 0201 and.w r2, r3, #1
8003b88: 697b ldr r3, [r7, #20]
8003b8a: fa02 f303 lsl.w r3, r2, r3
8003b8e: 693a ldr r2, [r7, #16]
8003b90: 4313 orrs r3, r2
8003b92: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8003b94: 687b ldr r3, [r7, #4]
8003b96: 693a ldr r2, [r7, #16]
8003b98: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8003b9a: 683b ldr r3, [r7, #0]
8003b9c: 685b ldr r3, [r3, #4]
8003b9e: f003 0303 and.w r3, r3, #3
8003ba2: 2b03 cmp r3, #3
8003ba4: d017 beq.n 8003bd6 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8003ba6: 687b ldr r3, [r7, #4]
8003ba8: 68db ldr r3, [r3, #12]
8003baa: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8003bac: 697b ldr r3, [r7, #20]
8003bae: 005b lsls r3, r3, #1
8003bb0: 2203 movs r2, #3
8003bb2: fa02 f303 lsl.w r3, r2, r3
8003bb6: 43db mvns r3, r3
8003bb8: 693a ldr r2, [r7, #16]
8003bba: 4013 ands r3, r2
8003bbc: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8003bbe: 683b ldr r3, [r7, #0]
8003bc0: 689a ldr r2, [r3, #8]
8003bc2: 697b ldr r3, [r7, #20]
8003bc4: 005b lsls r3, r3, #1
8003bc6: fa02 f303 lsl.w r3, r2, r3
8003bca: 693a ldr r2, [r7, #16]
8003bcc: 4313 orrs r3, r2
8003bce: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8003bd0: 687b ldr r3, [r7, #4]
8003bd2: 693a ldr r2, [r7, #16]
8003bd4: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8003bd6: 683b ldr r3, [r7, #0]
8003bd8: 685b ldr r3, [r3, #4]
8003bda: f003 0303 and.w r3, r3, #3
8003bde: 2b02 cmp r3, #2
8003be0: d123 bne.n 8003c2a <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8003be2: 697b ldr r3, [r7, #20]
8003be4: 08da lsrs r2, r3, #3
8003be6: 687b ldr r3, [r7, #4]
8003be8: 3208 adds r2, #8
8003bea: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8003bee: 613b str r3, [r7, #16]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8003bf0: 697b ldr r3, [r7, #20]
8003bf2: f003 0307 and.w r3, r3, #7
8003bf6: 009b lsls r3, r3, #2
8003bf8: 220f movs r2, #15
8003bfa: fa02 f303 lsl.w r3, r2, r3
8003bfe: 43db mvns r3, r3
8003c00: 693a ldr r2, [r7, #16]
8003c02: 4013 ands r3, r2
8003c04: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8003c06: 683b ldr r3, [r7, #0]
8003c08: 691a ldr r2, [r3, #16]
8003c0a: 697b ldr r3, [r7, #20]
8003c0c: f003 0307 and.w r3, r3, #7
8003c10: 009b lsls r3, r3, #2
8003c12: fa02 f303 lsl.w r3, r2, r3
8003c16: 693a ldr r2, [r7, #16]
8003c18: 4313 orrs r3, r2
8003c1a: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3U] = temp;
8003c1c: 697b ldr r3, [r7, #20]
8003c1e: 08da lsrs r2, r3, #3
8003c20: 687b ldr r3, [r7, #4]
8003c22: 3208 adds r2, #8
8003c24: 6939 ldr r1, [r7, #16]
8003c26: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8003c2a: 687b ldr r3, [r7, #4]
8003c2c: 681b ldr r3, [r3, #0]
8003c2e: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8003c30: 697b ldr r3, [r7, #20]
8003c32: 005b lsls r3, r3, #1
8003c34: 2203 movs r2, #3
8003c36: fa02 f303 lsl.w r3, r2, r3
8003c3a: 43db mvns r3, r3
8003c3c: 693a ldr r2, [r7, #16]
8003c3e: 4013 ands r3, r2
8003c40: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8003c42: 683b ldr r3, [r7, #0]
8003c44: 685b ldr r3, [r3, #4]
8003c46: f003 0203 and.w r2, r3, #3
8003c4a: 697b ldr r3, [r7, #20]
8003c4c: 005b lsls r3, r3, #1
8003c4e: fa02 f303 lsl.w r3, r2, r3
8003c52: 693a ldr r2, [r7, #16]
8003c54: 4313 orrs r3, r2
8003c56: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8003c58: 687b ldr r3, [r7, #4]
8003c5a: 693a ldr r2, [r7, #16]
8003c5c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8003c5e: 683b ldr r3, [r7, #0]
8003c60: 685b ldr r3, [r3, #4]
8003c62: f403 3340 and.w r3, r3, #196608 @ 0x30000
8003c66: 2b00 cmp r3, #0
8003c68: f000 80a6 beq.w 8003db8 <HAL_GPIO_Init+0x2c0>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003c6c: 4b5b ldr r3, [pc, #364] @ (8003ddc <HAL_GPIO_Init+0x2e4>)
8003c6e: 6e1b ldr r3, [r3, #96] @ 0x60
8003c70: 4a5a ldr r2, [pc, #360] @ (8003ddc <HAL_GPIO_Init+0x2e4>)
8003c72: f043 0301 orr.w r3, r3, #1
8003c76: 6613 str r3, [r2, #96] @ 0x60
8003c78: 4b58 ldr r3, [pc, #352] @ (8003ddc <HAL_GPIO_Init+0x2e4>)
8003c7a: 6e1b ldr r3, [r3, #96] @ 0x60
8003c7c: f003 0301 and.w r3, r3, #1
8003c80: 60bb str r3, [r7, #8]
8003c82: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2U];
8003c84: 4a56 ldr r2, [pc, #344] @ (8003de0 <HAL_GPIO_Init+0x2e8>)
8003c86: 697b ldr r3, [r7, #20]
8003c88: 089b lsrs r3, r3, #2
8003c8a: 3302 adds r3, #2
8003c8c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003c90: 613b str r3, [r7, #16]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8003c92: 697b ldr r3, [r7, #20]
8003c94: f003 0303 and.w r3, r3, #3
8003c98: 009b lsls r3, r3, #2
8003c9a: 220f movs r2, #15
8003c9c: fa02 f303 lsl.w r3, r2, r3
8003ca0: 43db mvns r3, r3
8003ca2: 693a ldr r2, [r7, #16]
8003ca4: 4013 ands r3, r2
8003ca6: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8003ca8: 687b ldr r3, [r7, #4]
8003caa: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8003cae: d01f beq.n 8003cf0 <HAL_GPIO_Init+0x1f8>
8003cb0: 687b ldr r3, [r7, #4]
8003cb2: 4a4c ldr r2, [pc, #304] @ (8003de4 <HAL_GPIO_Init+0x2ec>)
8003cb4: 4293 cmp r3, r2
8003cb6: d019 beq.n 8003cec <HAL_GPIO_Init+0x1f4>
8003cb8: 687b ldr r3, [r7, #4]
8003cba: 4a4b ldr r2, [pc, #300] @ (8003de8 <HAL_GPIO_Init+0x2f0>)
8003cbc: 4293 cmp r3, r2
8003cbe: d013 beq.n 8003ce8 <HAL_GPIO_Init+0x1f0>
8003cc0: 687b ldr r3, [r7, #4]
8003cc2: 4a4a ldr r2, [pc, #296] @ (8003dec <HAL_GPIO_Init+0x2f4>)
8003cc4: 4293 cmp r3, r2
8003cc6: d00d beq.n 8003ce4 <HAL_GPIO_Init+0x1ec>
8003cc8: 687b ldr r3, [r7, #4]
8003cca: 4a49 ldr r2, [pc, #292] @ (8003df0 <HAL_GPIO_Init+0x2f8>)
8003ccc: 4293 cmp r3, r2
8003cce: d007 beq.n 8003ce0 <HAL_GPIO_Init+0x1e8>
8003cd0: 687b ldr r3, [r7, #4]
8003cd2: 4a48 ldr r2, [pc, #288] @ (8003df4 <HAL_GPIO_Init+0x2fc>)
8003cd4: 4293 cmp r3, r2
8003cd6: d101 bne.n 8003cdc <HAL_GPIO_Init+0x1e4>
8003cd8: 2305 movs r3, #5
8003cda: e00a b.n 8003cf2 <HAL_GPIO_Init+0x1fa>
8003cdc: 2306 movs r3, #6
8003cde: e008 b.n 8003cf2 <HAL_GPIO_Init+0x1fa>
8003ce0: 2304 movs r3, #4
8003ce2: e006 b.n 8003cf2 <HAL_GPIO_Init+0x1fa>
8003ce4: 2303 movs r3, #3
8003ce6: e004 b.n 8003cf2 <HAL_GPIO_Init+0x1fa>
8003ce8: 2302 movs r3, #2
8003cea: e002 b.n 8003cf2 <HAL_GPIO_Init+0x1fa>
8003cec: 2301 movs r3, #1
8003cee: e000 b.n 8003cf2 <HAL_GPIO_Init+0x1fa>
8003cf0: 2300 movs r3, #0
8003cf2: 697a ldr r2, [r7, #20]
8003cf4: f002 0203 and.w r2, r2, #3
8003cf8: 0092 lsls r2, r2, #2
8003cfa: 4093 lsls r3, r2
8003cfc: 693a ldr r2, [r7, #16]
8003cfe: 4313 orrs r3, r2
8003d00: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2U] = temp;
8003d02: 4937 ldr r1, [pc, #220] @ (8003de0 <HAL_GPIO_Init+0x2e8>)
8003d04: 697b ldr r3, [r7, #20]
8003d06: 089b lsrs r3, r3, #2
8003d08: 3302 adds r3, #2
8003d0a: 693a ldr r2, [r7, #16]
8003d0c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8003d10: 4b39 ldr r3, [pc, #228] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003d12: 689b ldr r3, [r3, #8]
8003d14: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003d16: 68fb ldr r3, [r7, #12]
8003d18: 43db mvns r3, r3
8003d1a: 693a ldr r2, [r7, #16]
8003d1c: 4013 ands r3, r2
8003d1e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8003d20: 683b ldr r3, [r7, #0]
8003d22: 685b ldr r3, [r3, #4]
8003d24: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003d28: 2b00 cmp r3, #0
8003d2a: d003 beq.n 8003d34 <HAL_GPIO_Init+0x23c>
{
temp |= iocurrent;
8003d2c: 693a ldr r2, [r7, #16]
8003d2e: 68fb ldr r3, [r7, #12]
8003d30: 4313 orrs r3, r2
8003d32: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8003d34: 4a30 ldr r2, [pc, #192] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003d36: 693b ldr r3, [r7, #16]
8003d38: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8003d3a: 4b2f ldr r3, [pc, #188] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003d3c: 68db ldr r3, [r3, #12]
8003d3e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003d40: 68fb ldr r3, [r7, #12]
8003d42: 43db mvns r3, r3
8003d44: 693a ldr r2, [r7, #16]
8003d46: 4013 ands r3, r2
8003d48: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8003d4a: 683b ldr r3, [r7, #0]
8003d4c: 685b ldr r3, [r3, #4]
8003d4e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8003d52: 2b00 cmp r3, #0
8003d54: d003 beq.n 8003d5e <HAL_GPIO_Init+0x266>
{
temp |= iocurrent;
8003d56: 693a ldr r2, [r7, #16]
8003d58: 68fb ldr r3, [r7, #12]
8003d5a: 4313 orrs r3, r2
8003d5c: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8003d5e: 4a26 ldr r2, [pc, #152] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003d60: 693b ldr r3, [r7, #16]
8003d62: 60d3 str r3, [r2, #12]
temp = EXTI->EMR1;
8003d64: 4b24 ldr r3, [pc, #144] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003d66: 685b ldr r3, [r3, #4]
8003d68: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003d6a: 68fb ldr r3, [r7, #12]
8003d6c: 43db mvns r3, r3
8003d6e: 693a ldr r2, [r7, #16]
8003d70: 4013 ands r3, r2
8003d72: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8003d74: 683b ldr r3, [r7, #0]
8003d76: 685b ldr r3, [r3, #4]
8003d78: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003d7c: 2b00 cmp r3, #0
8003d7e: d003 beq.n 8003d88 <HAL_GPIO_Init+0x290>
{
temp |= iocurrent;
8003d80: 693a ldr r2, [r7, #16]
8003d82: 68fb ldr r3, [r7, #12]
8003d84: 4313 orrs r3, r2
8003d86: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8003d88: 4a1b ldr r2, [pc, #108] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003d8a: 693b ldr r3, [r7, #16]
8003d8c: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
8003d8e: 4b1a ldr r3, [pc, #104] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003d90: 681b ldr r3, [r3, #0]
8003d92: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003d94: 68fb ldr r3, [r7, #12]
8003d96: 43db mvns r3, r3
8003d98: 693a ldr r2, [r7, #16]
8003d9a: 4013 ands r3, r2
8003d9c: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8003d9e: 683b ldr r3, [r7, #0]
8003da0: 685b ldr r3, [r3, #4]
8003da2: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003da6: 2b00 cmp r3, #0
8003da8: d003 beq.n 8003db2 <HAL_GPIO_Init+0x2ba>
{
temp |= iocurrent;
8003daa: 693a ldr r2, [r7, #16]
8003dac: 68fb ldr r3, [r7, #12]
8003dae: 4313 orrs r3, r2
8003db0: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8003db2: 4a11 ldr r2, [pc, #68] @ (8003df8 <HAL_GPIO_Init+0x300>)
8003db4: 693b ldr r3, [r7, #16]
8003db6: 6013 str r3, [r2, #0]
}
}
position++;
8003db8: 697b ldr r3, [r7, #20]
8003dba: 3301 adds r3, #1
8003dbc: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0U)
8003dbe: 683b ldr r3, [r7, #0]
8003dc0: 681a ldr r2, [r3, #0]
8003dc2: 697b ldr r3, [r7, #20]
8003dc4: fa22 f303 lsr.w r3, r2, r3
8003dc8: 2b00 cmp r3, #0
8003dca: f47f ae9d bne.w 8003b08 <HAL_GPIO_Init+0x10>
}
}
8003dce: bf00 nop
8003dd0: bf00 nop
8003dd2: 371c adds r7, #28
8003dd4: 46bd mov sp, r7
8003dd6: f85d 7b04 ldr.w r7, [sp], #4
8003dda: 4770 bx lr
8003ddc: 40021000 .word 0x40021000
8003de0: 40010000 .word 0x40010000
8003de4: 48000400 .word 0x48000400
8003de8: 48000800 .word 0x48000800
8003dec: 48000c00 .word 0x48000c00
8003df0: 48001000 .word 0x48001000
8003df4: 48001400 .word 0x48001400
8003df8: 40010400 .word 0x40010400
08003dfc <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8003dfc: b480 push {r7}
8003dfe: b083 sub sp, #12
8003e00: af00 add r7, sp, #0
8003e02: 6078 str r0, [r7, #4]
8003e04: 460b mov r3, r1
8003e06: 807b strh r3, [r7, #2]
8003e08: 4613 mov r3, r2
8003e0a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003e0c: 787b ldrb r3, [r7, #1]
8003e0e: 2b00 cmp r3, #0
8003e10: d003 beq.n 8003e1a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8003e12: 887a ldrh r2, [r7, #2]
8003e14: 687b ldr r3, [r7, #4]
8003e16: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8003e18: e002 b.n 8003e20 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8003e1a: 887a ldrh r2, [r7, #2]
8003e1c: 687b ldr r3, [r7, #4]
8003e1e: 629a str r2, [r3, #40] @ 0x28
}
8003e20: bf00 nop
8003e22: 370c adds r7, #12
8003e24: 46bd mov sp, r7
8003e26: f85d 7b04 ldr.w r7, [sp], #4
8003e2a: 4770 bx lr
08003e2c <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8003e2c: b480 push {r7}
8003e2e: b085 sub sp, #20
8003e30: af00 add r7, sp, #0
8003e32: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
8003e34: 687b ldr r3, [r7, #4]
8003e36: 2b00 cmp r3, #0
8003e38: d141 bne.n 8003ebe <HAL_PWREx_ControlVoltageScaling+0x92>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8003e3a: 4b4b ldr r3, [pc, #300] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003e3c: 681b ldr r3, [r3, #0]
8003e3e: f403 63c0 and.w r3, r3, #1536 @ 0x600
8003e42: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003e46: d131 bne.n 8003eac <HAL_PWREx_ControlVoltageScaling+0x80>
{
/* Make sure Range 1 Boost is enabled */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003e48: 4b47 ldr r3, [pc, #284] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003e4a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003e4e: 4a46 ldr r2, [pc, #280] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003e50: f423 7380 bic.w r3, r3, #256 @ 0x100
8003e54: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8003e58: 4b43 ldr r3, [pc, #268] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003e5a: 681b ldr r3, [r3, #0]
8003e5c: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8003e60: 4a41 ldr r2, [pc, #260] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003e62: f443 7300 orr.w r3, r3, #512 @ 0x200
8003e66: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8003e68: 4b40 ldr r3, [pc, #256] @ (8003f6c <HAL_PWREx_ControlVoltageScaling+0x140>)
8003e6a: 681b ldr r3, [r3, #0]
8003e6c: 2232 movs r2, #50 @ 0x32
8003e6e: fb02 f303 mul.w r3, r2, r3
8003e72: 4a3f ldr r2, [pc, #252] @ (8003f70 <HAL_PWREx_ControlVoltageScaling+0x144>)
8003e74: fba2 2303 umull r2, r3, r2, r3
8003e78: 0c9b lsrs r3, r3, #18
8003e7a: 3301 adds r3, #1
8003e7c: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003e7e: e002 b.n 8003e86 <HAL_PWREx_ControlVoltageScaling+0x5a>
{
wait_loop_index--;
8003e80: 68fb ldr r3, [r7, #12]
8003e82: 3b01 subs r3, #1
8003e84: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003e86: 4b38 ldr r3, [pc, #224] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003e88: 695b ldr r3, [r3, #20]
8003e8a: f403 6380 and.w r3, r3, #1024 @ 0x400
8003e8e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003e92: d102 bne.n 8003e9a <HAL_PWREx_ControlVoltageScaling+0x6e>
8003e94: 68fb ldr r3, [r7, #12]
8003e96: 2b00 cmp r3, #0
8003e98: d1f2 bne.n 8003e80 <HAL_PWREx_ControlVoltageScaling+0x54>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8003e9a: 4b33 ldr r3, [pc, #204] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003e9c: 695b ldr r3, [r3, #20]
8003e9e: f403 6380 and.w r3, r3, #1024 @ 0x400
8003ea2: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003ea6: d158 bne.n 8003f5a <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8003ea8: 2303 movs r3, #3
8003eaa: e057 b.n 8003f5c <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Enable Range 1 Boost (no issue if bit already reset) */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003eac: 4b2e ldr r3, [pc, #184] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003eae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003eb2: 4a2d ldr r2, [pc, #180] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003eb4: f423 7380 bic.w r3, r3, #256 @ 0x100
8003eb8: f8c2 3080 str.w r3, [r2, #128] @ 0x80
8003ebc: e04d b.n 8003f5a <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8003ebe: 687b ldr r3, [r7, #4]
8003ec0: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003ec4: d141 bne.n 8003f4a <HAL_PWREx_ControlVoltageScaling+0x11e>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8003ec6: 4b28 ldr r3, [pc, #160] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003ec8: 681b ldr r3, [r3, #0]
8003eca: f403 63c0 and.w r3, r3, #1536 @ 0x600
8003ece: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003ed2: d131 bne.n 8003f38 <HAL_PWREx_ControlVoltageScaling+0x10c>
{
/* Make sure Range 1 Boost is disabled */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003ed4: 4b24 ldr r3, [pc, #144] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003ed6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003eda: 4a23 ldr r2, [pc, #140] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003edc: f443 7380 orr.w r3, r3, #256 @ 0x100
8003ee0: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8003ee4: 4b20 ldr r3, [pc, #128] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003ee6: 681b ldr r3, [r3, #0]
8003ee8: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8003eec: 4a1e ldr r2, [pc, #120] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003eee: f443 7300 orr.w r3, r3, #512 @ 0x200
8003ef2: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8003ef4: 4b1d ldr r3, [pc, #116] @ (8003f6c <HAL_PWREx_ControlVoltageScaling+0x140>)
8003ef6: 681b ldr r3, [r3, #0]
8003ef8: 2232 movs r2, #50 @ 0x32
8003efa: fb02 f303 mul.w r3, r2, r3
8003efe: 4a1c ldr r2, [pc, #112] @ (8003f70 <HAL_PWREx_ControlVoltageScaling+0x144>)
8003f00: fba2 2303 umull r2, r3, r2, r3
8003f04: 0c9b lsrs r3, r3, #18
8003f06: 3301 adds r3, #1
8003f08: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003f0a: e002 b.n 8003f12 <HAL_PWREx_ControlVoltageScaling+0xe6>
{
wait_loop_index--;
8003f0c: 68fb ldr r3, [r7, #12]
8003f0e: 3b01 subs r3, #1
8003f10: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003f12: 4b15 ldr r3, [pc, #84] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f14: 695b ldr r3, [r3, #20]
8003f16: f403 6380 and.w r3, r3, #1024 @ 0x400
8003f1a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003f1e: d102 bne.n 8003f26 <HAL_PWREx_ControlVoltageScaling+0xfa>
8003f20: 68fb ldr r3, [r7, #12]
8003f22: 2b00 cmp r3, #0
8003f24: d1f2 bne.n 8003f0c <HAL_PWREx_ControlVoltageScaling+0xe0>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8003f26: 4b10 ldr r3, [pc, #64] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f28: 695b ldr r3, [r3, #20]
8003f2a: f403 6380 and.w r3, r3, #1024 @ 0x400
8003f2e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003f32: d112 bne.n 8003f5a <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8003f34: 2303 movs r3, #3
8003f36: e011 b.n 8003f5c <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Disable Range 1 Boost (no issue if bit already set) */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003f38: 4b0b ldr r3, [pc, #44] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f3a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003f3e: 4a0a ldr r2, [pc, #40] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f40: f443 7380 orr.w r3, r3, #256 @ 0x100
8003f44: f8c2 3080 str.w r3, [r2, #128] @ 0x80
8003f48: e007 b.n 8003f5a <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8003f4a: 4b07 ldr r3, [pc, #28] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f4c: 681b ldr r3, [r3, #0]
8003f4e: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8003f52: 4a05 ldr r2, [pc, #20] @ (8003f68 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003f54: f443 6380 orr.w r3, r3, #1024 @ 0x400
8003f58: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
}
return HAL_OK;
8003f5a: 2300 movs r3, #0
}
8003f5c: 4618 mov r0, r3
8003f5e: 3714 adds r7, #20
8003f60: 46bd mov sp, r7
8003f62: f85d 7b04 ldr.w r7, [sp], #4
8003f66: 4770 bx lr
8003f68: 40007000 .word 0x40007000
8003f6c: 20000018 .word 0x20000018
8003f70: 431bde83 .word 0x431bde83
08003f74 <HAL_PWREx_DisableUCPDDeadBattery>:
* or to hand over control to the UCPD (which should therefore be
* initialized before doing the disable).
* @retval None
*/
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
8003f74: b480 push {r7}
8003f76: af00 add r7, sp, #0
/* Write 1 to disable the USB Type-C dead battery pull-down behavior */
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
8003f78: 4b05 ldr r3, [pc, #20] @ (8003f90 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
8003f7a: 689b ldr r3, [r3, #8]
8003f7c: 4a04 ldr r2, [pc, #16] @ (8003f90 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
8003f7e: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8003f82: 6093 str r3, [r2, #8]
}
8003f84: bf00 nop
8003f86: 46bd mov sp, r7
8003f88: f85d 7b04 ldr.w r7, [sp], #4
8003f8c: 4770 bx lr
8003f8e: bf00 nop
8003f90: 40007000 .word 0x40007000
08003f94 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8003f94: b580 push {r7, lr}
8003f96: b088 sub sp, #32
8003f98: af00 add r7, sp, #0
8003f9a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8003f9c: 687b ldr r3, [r7, #4]
8003f9e: 2b00 cmp r3, #0
8003fa0: d101 bne.n 8003fa6 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8003fa2: 2301 movs r3, #1
8003fa4: e2fe b.n 80045a4 <HAL_RCC_OscConfig+0x610>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8003fa6: 687b ldr r3, [r7, #4]
8003fa8: 681b ldr r3, [r3, #0]
8003faa: f003 0301 and.w r3, r3, #1
8003fae: 2b00 cmp r3, #0
8003fb0: d075 beq.n 800409e <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8003fb2: 4b97 ldr r3, [pc, #604] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8003fb4: 689b ldr r3, [r3, #8]
8003fb6: f003 030c and.w r3, r3, #12
8003fba: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8003fbc: 4b94 ldr r3, [pc, #592] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8003fbe: 68db ldr r3, [r3, #12]
8003fc0: f003 0303 and.w r3, r3, #3
8003fc4: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
8003fc6: 69bb ldr r3, [r7, #24]
8003fc8: 2b0c cmp r3, #12
8003fca: d102 bne.n 8003fd2 <HAL_RCC_OscConfig+0x3e>
8003fcc: 697b ldr r3, [r7, #20]
8003fce: 2b03 cmp r3, #3
8003fd0: d002 beq.n 8003fd8 <HAL_RCC_OscConfig+0x44>
8003fd2: 69bb ldr r3, [r7, #24]
8003fd4: 2b08 cmp r3, #8
8003fd6: d10b bne.n 8003ff0 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003fd8: 4b8d ldr r3, [pc, #564] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8003fda: 681b ldr r3, [r3, #0]
8003fdc: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003fe0: 2b00 cmp r3, #0
8003fe2: d05b beq.n 800409c <HAL_RCC_OscConfig+0x108>
8003fe4: 687b ldr r3, [r7, #4]
8003fe6: 685b ldr r3, [r3, #4]
8003fe8: 2b00 cmp r3, #0
8003fea: d157 bne.n 800409c <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8003fec: 2301 movs r3, #1
8003fee: e2d9 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8003ff0: 687b ldr r3, [r7, #4]
8003ff2: 685b ldr r3, [r3, #4]
8003ff4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003ff8: d106 bne.n 8004008 <HAL_RCC_OscConfig+0x74>
8003ffa: 4b85 ldr r3, [pc, #532] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8003ffc: 681b ldr r3, [r3, #0]
8003ffe: 4a84 ldr r2, [pc, #528] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004000: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004004: 6013 str r3, [r2, #0]
8004006: e01d b.n 8004044 <HAL_RCC_OscConfig+0xb0>
8004008: 687b ldr r3, [r7, #4]
800400a: 685b ldr r3, [r3, #4]
800400c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8004010: d10c bne.n 800402c <HAL_RCC_OscConfig+0x98>
8004012: 4b7f ldr r3, [pc, #508] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004014: 681b ldr r3, [r3, #0]
8004016: 4a7e ldr r2, [pc, #504] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004018: f443 2380 orr.w r3, r3, #262144 @ 0x40000
800401c: 6013 str r3, [r2, #0]
800401e: 4b7c ldr r3, [pc, #496] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004020: 681b ldr r3, [r3, #0]
8004022: 4a7b ldr r2, [pc, #492] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004024: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004028: 6013 str r3, [r2, #0]
800402a: e00b b.n 8004044 <HAL_RCC_OscConfig+0xb0>
800402c: 4b78 ldr r3, [pc, #480] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
800402e: 681b ldr r3, [r3, #0]
8004030: 4a77 ldr r2, [pc, #476] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004032: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004036: 6013 str r3, [r2, #0]
8004038: 4b75 ldr r3, [pc, #468] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
800403a: 681b ldr r3, [r3, #0]
800403c: 4a74 ldr r2, [pc, #464] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
800403e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8004042: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8004044: 687b ldr r3, [r7, #4]
8004046: 685b ldr r3, [r3, #4]
8004048: 2b00 cmp r3, #0
800404a: d013 beq.n 8004074 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800404c: f7fd feba bl 8001dc4 <HAL_GetTick>
8004050: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8004052: e008 b.n 8004066 <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004054: f7fd feb6 bl 8001dc4 <HAL_GetTick>
8004058: 4602 mov r2, r0
800405a: 693b ldr r3, [r7, #16]
800405c: 1ad3 subs r3, r2, r3
800405e: 2b64 cmp r3, #100 @ 0x64
8004060: d901 bls.n 8004066 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8004062: 2303 movs r3, #3
8004064: e29e b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8004066: 4b6a ldr r3, [pc, #424] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004068: 681b ldr r3, [r3, #0]
800406a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800406e: 2b00 cmp r3, #0
8004070: d0f0 beq.n 8004054 <HAL_RCC_OscConfig+0xc0>
8004072: e014 b.n 800409e <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004074: f7fd fea6 bl 8001dc4 <HAL_GetTick>
8004078: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
800407a: e008 b.n 800408e <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800407c: f7fd fea2 bl 8001dc4 <HAL_GetTick>
8004080: 4602 mov r2, r0
8004082: 693b ldr r3, [r7, #16]
8004084: 1ad3 subs r3, r2, r3
8004086: 2b64 cmp r3, #100 @ 0x64
8004088: d901 bls.n 800408e <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
800408a: 2303 movs r3, #3
800408c: e28a b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
800408e: 4b60 ldr r3, [pc, #384] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004090: 681b ldr r3, [r3, #0]
8004092: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004096: 2b00 cmp r3, #0
8004098: d1f0 bne.n 800407c <HAL_RCC_OscConfig+0xe8>
800409a: e000 b.n 800409e <HAL_RCC_OscConfig+0x10a>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800409c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800409e: 687b ldr r3, [r7, #4]
80040a0: 681b ldr r3, [r3, #0]
80040a2: f003 0302 and.w r3, r3, #2
80040a6: 2b00 cmp r3, #0
80040a8: d075 beq.n 8004196 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80040aa: 4b59 ldr r3, [pc, #356] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80040ac: 689b ldr r3, [r3, #8]
80040ae: f003 030c and.w r3, r3, #12
80040b2: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
80040b4: 4b56 ldr r3, [pc, #344] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80040b6: 68db ldr r3, [r3, #12]
80040b8: f003 0303 and.w r3, r3, #3
80040bc: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
80040be: 69bb ldr r3, [r7, #24]
80040c0: 2b0c cmp r3, #12
80040c2: d102 bne.n 80040ca <HAL_RCC_OscConfig+0x136>
80040c4: 697b ldr r3, [r7, #20]
80040c6: 2b02 cmp r3, #2
80040c8: d002 beq.n 80040d0 <HAL_RCC_OscConfig+0x13c>
80040ca: 69bb ldr r3, [r7, #24]
80040cc: 2b04 cmp r3, #4
80040ce: d11f bne.n 8004110 <HAL_RCC_OscConfig+0x17c>
{
/* When HSI is used as system clock it will not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80040d0: 4b4f ldr r3, [pc, #316] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80040d2: 681b ldr r3, [r3, #0]
80040d4: f403 6380 and.w r3, r3, #1024 @ 0x400
80040d8: 2b00 cmp r3, #0
80040da: d005 beq.n 80040e8 <HAL_RCC_OscConfig+0x154>
80040dc: 687b ldr r3, [r7, #4]
80040de: 68db ldr r3, [r3, #12]
80040e0: 2b00 cmp r3, #0
80040e2: d101 bne.n 80040e8 <HAL_RCC_OscConfig+0x154>
{
return HAL_ERROR;
80040e4: 2301 movs r3, #1
80040e6: e25d b.n 80045a4 <HAL_RCC_OscConfig+0x610>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80040e8: 4b49 ldr r3, [pc, #292] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80040ea: 685b ldr r3, [r3, #4]
80040ec: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
80040f0: 687b ldr r3, [r7, #4]
80040f2: 691b ldr r3, [r3, #16]
80040f4: 061b lsls r3, r3, #24
80040f6: 4946 ldr r1, [pc, #280] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80040f8: 4313 orrs r3, r2
80040fa: 604b str r3, [r1, #4]
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
80040fc: 4b45 ldr r3, [pc, #276] @ (8004214 <HAL_RCC_OscConfig+0x280>)
80040fe: 681b ldr r3, [r3, #0]
8004100: 4618 mov r0, r3
8004102: f7fd fe13 bl 8001d2c <HAL_InitTick>
8004106: 4603 mov r3, r0
8004108: 2b00 cmp r3, #0
800410a: d043 beq.n 8004194 <HAL_RCC_OscConfig+0x200>
{
return HAL_ERROR;
800410c: 2301 movs r3, #1
800410e: e249 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8004110: 687b ldr r3, [r7, #4]
8004112: 68db ldr r3, [r3, #12]
8004114: 2b00 cmp r3, #0
8004116: d023 beq.n 8004160 <HAL_RCC_OscConfig+0x1cc>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8004118: 4b3d ldr r3, [pc, #244] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
800411a: 681b ldr r3, [r3, #0]
800411c: 4a3c ldr r2, [pc, #240] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
800411e: f443 7380 orr.w r3, r3, #256 @ 0x100
8004122: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004124: f7fd fe4e bl 8001dc4 <HAL_GetTick>
8004128: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800412a: e008 b.n 800413e <HAL_RCC_OscConfig+0x1aa>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800412c: f7fd fe4a bl 8001dc4 <HAL_GetTick>
8004130: 4602 mov r2, r0
8004132: 693b ldr r3, [r7, #16]
8004134: 1ad3 subs r3, r2, r3
8004136: 2b02 cmp r3, #2
8004138: d901 bls.n 800413e <HAL_RCC_OscConfig+0x1aa>
{
return HAL_TIMEOUT;
800413a: 2303 movs r3, #3
800413c: e232 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800413e: 4b34 ldr r3, [pc, #208] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004140: 681b ldr r3, [r3, #0]
8004142: f403 6380 and.w r3, r3, #1024 @ 0x400
8004146: 2b00 cmp r3, #0
8004148: d0f0 beq.n 800412c <HAL_RCC_OscConfig+0x198>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800414a: 4b31 ldr r3, [pc, #196] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
800414c: 685b ldr r3, [r3, #4]
800414e: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
8004152: 687b ldr r3, [r7, #4]
8004154: 691b ldr r3, [r3, #16]
8004156: 061b lsls r3, r3, #24
8004158: 492d ldr r1, [pc, #180] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
800415a: 4313 orrs r3, r2
800415c: 604b str r3, [r1, #4]
800415e: e01a b.n 8004196 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8004160: 4b2b ldr r3, [pc, #172] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004162: 681b ldr r3, [r3, #0]
8004164: 4a2a ldr r2, [pc, #168] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004166: f423 7380 bic.w r3, r3, #256 @ 0x100
800416a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800416c: f7fd fe2a bl 8001dc4 <HAL_GetTick>
8004170: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8004172: e008 b.n 8004186 <HAL_RCC_OscConfig+0x1f2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8004174: f7fd fe26 bl 8001dc4 <HAL_GetTick>
8004178: 4602 mov r2, r0
800417a: 693b ldr r3, [r7, #16]
800417c: 1ad3 subs r3, r2, r3
800417e: 2b02 cmp r3, #2
8004180: d901 bls.n 8004186 <HAL_RCC_OscConfig+0x1f2>
{
return HAL_TIMEOUT;
8004182: 2303 movs r3, #3
8004184: e20e b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8004186: 4b22 ldr r3, [pc, #136] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
8004188: 681b ldr r3, [r3, #0]
800418a: f403 6380 and.w r3, r3, #1024 @ 0x400
800418e: 2b00 cmp r3, #0
8004190: d1f0 bne.n 8004174 <HAL_RCC_OscConfig+0x1e0>
8004192: e000 b.n 8004196 <HAL_RCC_OscConfig+0x202>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8004194: bf00 nop
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8004196: 687b ldr r3, [r7, #4]
8004198: 681b ldr r3, [r3, #0]
800419a: f003 0308 and.w r3, r3, #8
800419e: 2b00 cmp r3, #0
80041a0: d041 beq.n 8004226 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80041a2: 687b ldr r3, [r7, #4]
80041a4: 695b ldr r3, [r3, #20]
80041a6: 2b00 cmp r3, #0
80041a8: d01c beq.n 80041e4 <HAL_RCC_OscConfig+0x250>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80041aa: 4b19 ldr r3, [pc, #100] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80041ac: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80041b0: 4a17 ldr r2, [pc, #92] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80041b2: f043 0301 orr.w r3, r3, #1
80041b6: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80041ba: f7fd fe03 bl 8001dc4 <HAL_GetTick>
80041be: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80041c0: e008 b.n 80041d4 <HAL_RCC_OscConfig+0x240>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80041c2: f7fd fdff bl 8001dc4 <HAL_GetTick>
80041c6: 4602 mov r2, r0
80041c8: 693b ldr r3, [r7, #16]
80041ca: 1ad3 subs r3, r2, r3
80041cc: 2b02 cmp r3, #2
80041ce: d901 bls.n 80041d4 <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
80041d0: 2303 movs r3, #3
80041d2: e1e7 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80041d4: 4b0e ldr r3, [pc, #56] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80041d6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80041da: f003 0302 and.w r3, r3, #2
80041de: 2b00 cmp r3, #0
80041e0: d0ef beq.n 80041c2 <HAL_RCC_OscConfig+0x22e>
80041e2: e020 b.n 8004226 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80041e4: 4b0a ldr r3, [pc, #40] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80041e6: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80041ea: 4a09 ldr r2, [pc, #36] @ (8004210 <HAL_RCC_OscConfig+0x27c>)
80041ec: f023 0301 bic.w r3, r3, #1
80041f0: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
80041f4: f7fd fde6 bl 8001dc4 <HAL_GetTick>
80041f8: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80041fa: e00d b.n 8004218 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80041fc: f7fd fde2 bl 8001dc4 <HAL_GetTick>
8004200: 4602 mov r2, r0
8004202: 693b ldr r3, [r7, #16]
8004204: 1ad3 subs r3, r2, r3
8004206: 2b02 cmp r3, #2
8004208: d906 bls.n 8004218 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
800420a: 2303 movs r3, #3
800420c: e1ca b.n 80045a4 <HAL_RCC_OscConfig+0x610>
800420e: bf00 nop
8004210: 40021000 .word 0x40021000
8004214: 2000001c .word 0x2000001c
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8004218: 4b8c ldr r3, [pc, #560] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
800421a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800421e: f003 0302 and.w r3, r3, #2
8004222: 2b00 cmp r3, #0
8004224: d1ea bne.n 80041fc <HAL_RCC_OscConfig+0x268>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8004226: 687b ldr r3, [r7, #4]
8004228: 681b ldr r3, [r3, #0]
800422a: f003 0304 and.w r3, r3, #4
800422e: 2b00 cmp r3, #0
8004230: f000 80a6 beq.w 8004380 <HAL_RCC_OscConfig+0x3ec>
{
FlagStatus pwrclkchanged = RESET;
8004234: 2300 movs r3, #0
8004236: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain if necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8004238: 4b84 ldr r3, [pc, #528] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
800423a: 6d9b ldr r3, [r3, #88] @ 0x58
800423c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004240: 2b00 cmp r3, #0
8004242: d101 bne.n 8004248 <HAL_RCC_OscConfig+0x2b4>
8004244: 2301 movs r3, #1
8004246: e000 b.n 800424a <HAL_RCC_OscConfig+0x2b6>
8004248: 2300 movs r3, #0
800424a: 2b00 cmp r3, #0
800424c: d00d beq.n 800426a <HAL_RCC_OscConfig+0x2d6>
{
__HAL_RCC_PWR_CLK_ENABLE();
800424e: 4b7f ldr r3, [pc, #508] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004250: 6d9b ldr r3, [r3, #88] @ 0x58
8004252: 4a7e ldr r2, [pc, #504] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004254: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004258: 6593 str r3, [r2, #88] @ 0x58
800425a: 4b7c ldr r3, [pc, #496] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
800425c: 6d9b ldr r3, [r3, #88] @ 0x58
800425e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004262: 60fb str r3, [r7, #12]
8004264: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8004266: 2301 movs r3, #1
8004268: 77fb strb r3, [r7, #31]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800426a: 4b79 ldr r3, [pc, #484] @ (8004450 <HAL_RCC_OscConfig+0x4bc>)
800426c: 681b ldr r3, [r3, #0]
800426e: f403 7380 and.w r3, r3, #256 @ 0x100
8004272: 2b00 cmp r3, #0
8004274: d118 bne.n 80042a8 <HAL_RCC_OscConfig+0x314>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8004276: 4b76 ldr r3, [pc, #472] @ (8004450 <HAL_RCC_OscConfig+0x4bc>)
8004278: 681b ldr r3, [r3, #0]
800427a: 4a75 ldr r2, [pc, #468] @ (8004450 <HAL_RCC_OscConfig+0x4bc>)
800427c: f443 7380 orr.w r3, r3, #256 @ 0x100
8004280: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004282: f7fd fd9f bl 8001dc4 <HAL_GetTick>
8004286: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8004288: e008 b.n 800429c <HAL_RCC_OscConfig+0x308>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800428a: f7fd fd9b bl 8001dc4 <HAL_GetTick>
800428e: 4602 mov r2, r0
8004290: 693b ldr r3, [r7, #16]
8004292: 1ad3 subs r3, r2, r3
8004294: 2b02 cmp r3, #2
8004296: d901 bls.n 800429c <HAL_RCC_OscConfig+0x308>
{
return HAL_TIMEOUT;
8004298: 2303 movs r3, #3
800429a: e183 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800429c: 4b6c ldr r3, [pc, #432] @ (8004450 <HAL_RCC_OscConfig+0x4bc>)
800429e: 681b ldr r3, [r3, #0]
80042a0: f403 7380 and.w r3, r3, #256 @ 0x100
80042a4: 2b00 cmp r3, #0
80042a6: d0f0 beq.n 800428a <HAL_RCC_OscConfig+0x2f6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80042a8: 687b ldr r3, [r7, #4]
80042aa: 689b ldr r3, [r3, #8]
80042ac: 2b01 cmp r3, #1
80042ae: d108 bne.n 80042c2 <HAL_RCC_OscConfig+0x32e>
80042b0: 4b66 ldr r3, [pc, #408] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042b2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80042b6: 4a65 ldr r2, [pc, #404] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042b8: f043 0301 orr.w r3, r3, #1
80042bc: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80042c0: e024 b.n 800430c <HAL_RCC_OscConfig+0x378>
80042c2: 687b ldr r3, [r7, #4]
80042c4: 689b ldr r3, [r3, #8]
80042c6: 2b05 cmp r3, #5
80042c8: d110 bne.n 80042ec <HAL_RCC_OscConfig+0x358>
80042ca: 4b60 ldr r3, [pc, #384] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042cc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80042d0: 4a5e ldr r2, [pc, #376] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042d2: f043 0304 orr.w r3, r3, #4
80042d6: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80042da: 4b5c ldr r3, [pc, #368] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042dc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80042e0: 4a5a ldr r2, [pc, #360] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042e2: f043 0301 orr.w r3, r3, #1
80042e6: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80042ea: e00f b.n 800430c <HAL_RCC_OscConfig+0x378>
80042ec: 4b57 ldr r3, [pc, #348] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042ee: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80042f2: 4a56 ldr r2, [pc, #344] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042f4: f023 0301 bic.w r3, r3, #1
80042f8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
80042fc: 4b53 ldr r3, [pc, #332] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80042fe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004302: 4a52 ldr r2, [pc, #328] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004304: f023 0304 bic.w r3, r3, #4
8004308: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
800430c: 687b ldr r3, [r7, #4]
800430e: 689b ldr r3, [r3, #8]
8004310: 2b00 cmp r3, #0
8004312: d016 beq.n 8004342 <HAL_RCC_OscConfig+0x3ae>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004314: f7fd fd56 bl 8001dc4 <HAL_GetTick>
8004318: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800431a: e00a b.n 8004332 <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800431c: f7fd fd52 bl 8001dc4 <HAL_GetTick>
8004320: 4602 mov r2, r0
8004322: 693b ldr r3, [r7, #16]
8004324: 1ad3 subs r3, r2, r3
8004326: f241 3288 movw r2, #5000 @ 0x1388
800432a: 4293 cmp r3, r2
800432c: d901 bls.n 8004332 <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
800432e: 2303 movs r3, #3
8004330: e138 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004332: 4b46 ldr r3, [pc, #280] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004334: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004338: f003 0302 and.w r3, r3, #2
800433c: 2b00 cmp r3, #0
800433e: d0ed beq.n 800431c <HAL_RCC_OscConfig+0x388>
8004340: e015 b.n 800436e <HAL_RCC_OscConfig+0x3da>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004342: f7fd fd3f bl 8001dc4 <HAL_GetTick>
8004346: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8004348: e00a b.n 8004360 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800434a: f7fd fd3b bl 8001dc4 <HAL_GetTick>
800434e: 4602 mov r2, r0
8004350: 693b ldr r3, [r7, #16]
8004352: 1ad3 subs r3, r2, r3
8004354: f241 3288 movw r2, #5000 @ 0x1388
8004358: 4293 cmp r3, r2
800435a: d901 bls.n 8004360 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
800435c: 2303 movs r3, #3
800435e: e121 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8004360: 4b3a ldr r3, [pc, #232] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004362: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004366: f003 0302 and.w r3, r3, #2
800436a: 2b00 cmp r3, #0
800436c: d1ed bne.n 800434a <HAL_RCC_OscConfig+0x3b6>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
800436e: 7ffb ldrb r3, [r7, #31]
8004370: 2b01 cmp r3, #1
8004372: d105 bne.n 8004380 <HAL_RCC_OscConfig+0x3ec>
{
__HAL_RCC_PWR_CLK_DISABLE();
8004374: 4b35 ldr r3, [pc, #212] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004376: 6d9b ldr r3, [r3, #88] @ 0x58
8004378: 4a34 ldr r2, [pc, #208] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
800437a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800437e: 6593 str r3, [r2, #88] @ 0x58
}
}
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
8004380: 687b ldr r3, [r7, #4]
8004382: 681b ldr r3, [r3, #0]
8004384: f003 0320 and.w r3, r3, #32
8004388: 2b00 cmp r3, #0
800438a: d03c beq.n 8004406 <HAL_RCC_OscConfig+0x472>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
800438c: 687b ldr r3, [r7, #4]
800438e: 699b ldr r3, [r3, #24]
8004390: 2b00 cmp r3, #0
8004392: d01c beq.n 80043ce <HAL_RCC_OscConfig+0x43a>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8004394: 4b2d ldr r3, [pc, #180] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004396: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
800439a: 4a2c ldr r2, [pc, #176] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
800439c: f043 0301 orr.w r3, r3, #1
80043a0: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
80043a4: f7fd fd0e bl 8001dc4 <HAL_GetTick>
80043a8: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
80043aa: e008 b.n 80043be <HAL_RCC_OscConfig+0x42a>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
80043ac: f7fd fd0a bl 8001dc4 <HAL_GetTick>
80043b0: 4602 mov r2, r0
80043b2: 693b ldr r3, [r7, #16]
80043b4: 1ad3 subs r3, r2, r3
80043b6: 2b02 cmp r3, #2
80043b8: d901 bls.n 80043be <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
80043ba: 2303 movs r3, #3
80043bc: e0f2 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
80043be: 4b23 ldr r3, [pc, #140] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80043c0: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
80043c4: f003 0302 and.w r3, r3, #2
80043c8: 2b00 cmp r3, #0
80043ca: d0ef beq.n 80043ac <HAL_RCC_OscConfig+0x418>
80043cc: e01b b.n 8004406 <HAL_RCC_OscConfig+0x472>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
80043ce: 4b1f ldr r3, [pc, #124] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80043d0: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
80043d4: 4a1d ldr r2, [pc, #116] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80043d6: f023 0301 bic.w r3, r3, #1
80043da: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
80043de: f7fd fcf1 bl 8001dc4 <HAL_GetTick>
80043e2: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
80043e4: e008 b.n 80043f8 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
80043e6: f7fd fced bl 8001dc4 <HAL_GetTick>
80043ea: 4602 mov r2, r0
80043ec: 693b ldr r3, [r7, #16]
80043ee: 1ad3 subs r3, r2, r3
80043f0: 2b02 cmp r3, #2
80043f2: d901 bls.n 80043f8 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
80043f4: 2303 movs r3, #3
80043f6: e0d5 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
80043f8: 4b14 ldr r3, [pc, #80] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
80043fa: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
80043fe: f003 0302 and.w r3, r3, #2
8004402: 2b00 cmp r3, #0
8004404: d1ef bne.n 80043e6 <HAL_RCC_OscConfig+0x452>
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8004406: 687b ldr r3, [r7, #4]
8004408: 69db ldr r3, [r3, #28]
800440a: 2b00 cmp r3, #0
800440c: f000 80c9 beq.w 80045a2 <HAL_RCC_OscConfig+0x60e>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8004410: 4b0e ldr r3, [pc, #56] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004412: 689b ldr r3, [r3, #8]
8004414: f003 030c and.w r3, r3, #12
8004418: 2b0c cmp r3, #12
800441a: f000 8083 beq.w 8004524 <HAL_RCC_OscConfig+0x590>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
800441e: 687b ldr r3, [r7, #4]
8004420: 69db ldr r3, [r3, #28]
8004422: 2b02 cmp r3, #2
8004424: d15e bne.n 80044e4 <HAL_RCC_OscConfig+0x550>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8004426: 4b09 ldr r3, [pc, #36] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
8004428: 681b ldr r3, [r3, #0]
800442a: 4a08 ldr r2, [pc, #32] @ (800444c <HAL_RCC_OscConfig+0x4b8>)
800442c: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8004430: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004432: f7fd fcc7 bl 8001dc4 <HAL_GetTick>
8004436: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8004438: e00c b.n 8004454 <HAL_RCC_OscConfig+0x4c0>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800443a: f7fd fcc3 bl 8001dc4 <HAL_GetTick>
800443e: 4602 mov r2, r0
8004440: 693b ldr r3, [r7, #16]
8004442: 1ad3 subs r3, r2, r3
8004444: 2b02 cmp r3, #2
8004446: d905 bls.n 8004454 <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
8004448: 2303 movs r3, #3
800444a: e0ab b.n 80045a4 <HAL_RCC_OscConfig+0x610>
800444c: 40021000 .word 0x40021000
8004450: 40007000 .word 0x40007000
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8004454: 4b55 ldr r3, [pc, #340] @ (80045ac <HAL_RCC_OscConfig+0x618>)
8004456: 681b ldr r3, [r3, #0]
8004458: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800445c: 2b00 cmp r3, #0
800445e: d1ec bne.n 800443a <HAL_RCC_OscConfig+0x4a6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8004460: 4b52 ldr r3, [pc, #328] @ (80045ac <HAL_RCC_OscConfig+0x618>)
8004462: 68da ldr r2, [r3, #12]
8004464: 4b52 ldr r3, [pc, #328] @ (80045b0 <HAL_RCC_OscConfig+0x61c>)
8004466: 4013 ands r3, r2
8004468: 687a ldr r2, [r7, #4]
800446a: 6a11 ldr r1, [r2, #32]
800446c: 687a ldr r2, [r7, #4]
800446e: 6a52 ldr r2, [r2, #36] @ 0x24
8004470: 3a01 subs r2, #1
8004472: 0112 lsls r2, r2, #4
8004474: 4311 orrs r1, r2
8004476: 687a ldr r2, [r7, #4]
8004478: 6a92 ldr r2, [r2, #40] @ 0x28
800447a: 0212 lsls r2, r2, #8
800447c: 4311 orrs r1, r2
800447e: 687a ldr r2, [r7, #4]
8004480: 6b12 ldr r2, [r2, #48] @ 0x30
8004482: 0852 lsrs r2, r2, #1
8004484: 3a01 subs r2, #1
8004486: 0552 lsls r2, r2, #21
8004488: 4311 orrs r1, r2
800448a: 687a ldr r2, [r7, #4]
800448c: 6b52 ldr r2, [r2, #52] @ 0x34
800448e: 0852 lsrs r2, r2, #1
8004490: 3a01 subs r2, #1
8004492: 0652 lsls r2, r2, #25
8004494: 4311 orrs r1, r2
8004496: 687a ldr r2, [r7, #4]
8004498: 6ad2 ldr r2, [r2, #44] @ 0x2c
800449a: 06d2 lsls r2, r2, #27
800449c: 430a orrs r2, r1
800449e: 4943 ldr r1, [pc, #268] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044a0: 4313 orrs r3, r2
80044a2: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80044a4: 4b41 ldr r3, [pc, #260] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044a6: 681b ldr r3, [r3, #0]
80044a8: 4a40 ldr r2, [pc, #256] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044aa: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80044ae: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
80044b0: 4b3e ldr r3, [pc, #248] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044b2: 68db ldr r3, [r3, #12]
80044b4: 4a3d ldr r2, [pc, #244] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044b6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80044ba: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80044bc: f7fd fc82 bl 8001dc4 <HAL_GetTick>
80044c0: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80044c2: e008 b.n 80044d6 <HAL_RCC_OscConfig+0x542>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80044c4: f7fd fc7e bl 8001dc4 <HAL_GetTick>
80044c8: 4602 mov r2, r0
80044ca: 693b ldr r3, [r7, #16]
80044cc: 1ad3 subs r3, r2, r3
80044ce: 2b02 cmp r3, #2
80044d0: d901 bls.n 80044d6 <HAL_RCC_OscConfig+0x542>
{
return HAL_TIMEOUT;
80044d2: 2303 movs r3, #3
80044d4: e066 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
80044d6: 4b35 ldr r3, [pc, #212] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044d8: 681b ldr r3, [r3, #0]
80044da: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80044de: 2b00 cmp r3, #0
80044e0: d0f0 beq.n 80044c4 <HAL_RCC_OscConfig+0x530>
80044e2: e05e b.n 80045a2 <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80044e4: 4b31 ldr r3, [pc, #196] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044e6: 681b ldr r3, [r3, #0]
80044e8: 4a30 ldr r2, [pc, #192] @ (80045ac <HAL_RCC_OscConfig+0x618>)
80044ea: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80044ee: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80044f0: f7fd fc68 bl 8001dc4 <HAL_GetTick>
80044f4: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80044f6: e008 b.n 800450a <HAL_RCC_OscConfig+0x576>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80044f8: f7fd fc64 bl 8001dc4 <HAL_GetTick>
80044fc: 4602 mov r2, r0
80044fe: 693b ldr r3, [r7, #16]
8004500: 1ad3 subs r3, r2, r3
8004502: 2b02 cmp r3, #2
8004504: d901 bls.n 800450a <HAL_RCC_OscConfig+0x576>
{
return HAL_TIMEOUT;
8004506: 2303 movs r3, #3
8004508: e04c b.n 80045a4 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
800450a: 4b28 ldr r3, [pc, #160] @ (80045ac <HAL_RCC_OscConfig+0x618>)
800450c: 681b ldr r3, [r3, #0]
800450e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004512: 2b00 cmp r3, #0
8004514: d1f0 bne.n 80044f8 <HAL_RCC_OscConfig+0x564>
}
}
/* Unselect PLL clock source and disable outputs to save power */
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
8004516: 4b25 ldr r3, [pc, #148] @ (80045ac <HAL_RCC_OscConfig+0x618>)
8004518: 68da ldr r2, [r3, #12]
800451a: 4924 ldr r1, [pc, #144] @ (80045ac <HAL_RCC_OscConfig+0x618>)
800451c: 4b25 ldr r3, [pc, #148] @ (80045b4 <HAL_RCC_OscConfig+0x620>)
800451e: 4013 ands r3, r2
8004520: 60cb str r3, [r1, #12]
8004522: e03e b.n 80045a2 <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8004524: 687b ldr r3, [r7, #4]
8004526: 69db ldr r3, [r3, #28]
8004528: 2b01 cmp r3, #1
800452a: d101 bne.n 8004530 <HAL_RCC_OscConfig+0x59c>
{
return HAL_ERROR;
800452c: 2301 movs r3, #1
800452e: e039 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8004530: 4b1e ldr r3, [pc, #120] @ (80045ac <HAL_RCC_OscConfig+0x618>)
8004532: 68db ldr r3, [r3, #12]
8004534: 617b str r3, [r7, #20]
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8004536: 697b ldr r3, [r7, #20]
8004538: f003 0203 and.w r2, r3, #3
800453c: 687b ldr r3, [r7, #4]
800453e: 6a1b ldr r3, [r3, #32]
8004540: 429a cmp r2, r3
8004542: d12c bne.n 800459e <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8004544: 697b ldr r3, [r7, #20]
8004546: f003 02f0 and.w r2, r3, #240 @ 0xf0
800454a: 687b ldr r3, [r7, #4]
800454c: 6a5b ldr r3, [r3, #36] @ 0x24
800454e: 3b01 subs r3, #1
8004550: 011b lsls r3, r3, #4
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8004552: 429a cmp r2, r3
8004554: d123 bne.n 800459e <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8004556: 697b ldr r3, [r7, #20]
8004558: f403 42fe and.w r2, r3, #32512 @ 0x7f00
800455c: 687b ldr r3, [r7, #4]
800455e: 6a9b ldr r3, [r3, #40] @ 0x28
8004560: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8004562: 429a cmp r2, r3
8004564: d11b bne.n 800459e <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8004566: 697b ldr r3, [r7, #20]
8004568: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000
800456c: 687b ldr r3, [r7, #4]
800456e: 6adb ldr r3, [r3, #44] @ 0x2c
8004570: 06db lsls r3, r3, #27
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8004572: 429a cmp r2, r3
8004574: d113 bne.n 800459e <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8004576: 697b ldr r3, [r7, #20]
8004578: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
800457c: 687b ldr r3, [r7, #4]
800457e: 6b1b ldr r3, [r3, #48] @ 0x30
8004580: 085b lsrs r3, r3, #1
8004582: 3b01 subs r3, #1
8004584: 055b lsls r3, r3, #21
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8004586: 429a cmp r2, r3
8004588: d109 bne.n 800459e <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
800458a: 697b ldr r3, [r7, #20]
800458c: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
8004590: 687b ldr r3, [r7, #4]
8004592: 6b5b ldr r3, [r3, #52] @ 0x34
8004594: 085b lsrs r3, r3, #1
8004596: 3b01 subs r3, #1
8004598: 065b lsls r3, r3, #25
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
800459a: 429a cmp r2, r3
800459c: d001 beq.n 80045a2 <HAL_RCC_OscConfig+0x60e>
{
return HAL_ERROR;
800459e: 2301 movs r3, #1
80045a0: e000 b.n 80045a4 <HAL_RCC_OscConfig+0x610>
}
}
}
}
return HAL_OK;
80045a2: 2300 movs r3, #0
}
80045a4: 4618 mov r0, r3
80045a6: 3720 adds r7, #32
80045a8: 46bd mov sp, r7
80045aa: bd80 pop {r7, pc}
80045ac: 40021000 .word 0x40021000
80045b0: 019f800c .word 0x019f800c
80045b4: feeefffc .word 0xfeeefffc
080045b8 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80045b8: b580 push {r7, lr}
80045ba: b086 sub sp, #24
80045bc: af00 add r7, sp, #0
80045be: 6078 str r0, [r7, #4]
80045c0: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t pllfreq;
uint32_t hpre = RCC_SYSCLK_DIV1;
80045c2: 2300 movs r3, #0
80045c4: 617b str r3, [r7, #20]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80045c6: 687b ldr r3, [r7, #4]
80045c8: 2b00 cmp r3, #0
80045ca: d101 bne.n 80045d0 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
80045cc: 2301 movs r3, #1
80045ce: e11e b.n 800480e <HAL_RCC_ClockConfig+0x256>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80045d0: 4b91 ldr r3, [pc, #580] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
80045d2: 681b ldr r3, [r3, #0]
80045d4: f003 030f and.w r3, r3, #15
80045d8: 683a ldr r2, [r7, #0]
80045da: 429a cmp r2, r3
80045dc: d910 bls.n 8004600 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80045de: 4b8e ldr r3, [pc, #568] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
80045e0: 681b ldr r3, [r3, #0]
80045e2: f023 020f bic.w r2, r3, #15
80045e6: 498c ldr r1, [pc, #560] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
80045e8: 683b ldr r3, [r7, #0]
80045ea: 4313 orrs r3, r2
80045ec: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80045ee: 4b8a ldr r3, [pc, #552] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
80045f0: 681b ldr r3, [r3, #0]
80045f2: f003 030f and.w r3, r3, #15
80045f6: 683a ldr r2, [r7, #0]
80045f8: 429a cmp r2, r3
80045fa: d001 beq.n 8004600 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
80045fc: 2301 movs r3, #1
80045fe: e106 b.n 800480e <HAL_RCC_ClockConfig+0x256>
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8004600: 687b ldr r3, [r7, #4]
8004602: 681b ldr r3, [r3, #0]
8004604: f003 0301 and.w r3, r3, #1
8004608: 2b00 cmp r3, #0
800460a: d073 beq.n 80046f4 <HAL_RCC_ClockConfig+0x13c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800460c: 687b ldr r3, [r7, #4]
800460e: 685b ldr r3, [r3, #4]
8004610: 2b03 cmp r3, #3
8004612: d129 bne.n 8004668 <HAL_RCC_ClockConfig+0xb0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8004614: 4b81 ldr r3, [pc, #516] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004616: 681b ldr r3, [r3, #0]
8004618: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800461c: 2b00 cmp r3, #0
800461e: d101 bne.n 8004624 <HAL_RCC_ClockConfig+0x6c>
{
return HAL_ERROR;
8004620: 2301 movs r3, #1
8004622: e0f4 b.n 800480e <HAL_RCC_ClockConfig+0x256>
}
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
/* Compute target PLL output frequency */
pllfreq = RCC_GetSysClockFreqFromPLLSource();
8004624: f000 f99e bl 8004964 <RCC_GetSysClockFreqFromPLLSource>
8004628: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
if(pllfreq > 80000000U)
800462a: 693b ldr r3, [r7, #16]
800462c: 4a7c ldr r2, [pc, #496] @ (8004820 <HAL_RCC_ClockConfig+0x268>)
800462e: 4293 cmp r3, r2
8004630: d93f bls.n 80046b2 <HAL_RCC_ClockConfig+0xfa>
{
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8004632: 4b7a ldr r3, [pc, #488] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004634: 689b ldr r3, [r3, #8]
8004636: f003 03f0 and.w r3, r3, #240 @ 0xf0
800463a: 2b00 cmp r3, #0
800463c: d009 beq.n 8004652 <HAL_RCC_ClockConfig+0x9a>
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
800463e: 687b ldr r3, [r7, #4]
8004640: 681b ldr r3, [r3, #0]
8004642: f003 0302 and.w r3, r3, #2
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8004646: 2b00 cmp r3, #0
8004648: d033 beq.n 80046b2 <HAL_RCC_ClockConfig+0xfa>
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
800464a: 687b ldr r3, [r7, #4]
800464c: 689b ldr r3, [r3, #8]
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
800464e: 2b00 cmp r3, #0
8004650: d12f bne.n 80046b2 <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
8004652: 4b72 ldr r3, [pc, #456] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004654: 689b ldr r3, [r3, #8]
8004656: f023 03f0 bic.w r3, r3, #240 @ 0xf0
800465a: 4a70 ldr r2, [pc, #448] @ (800481c <HAL_RCC_ClockConfig+0x264>)
800465c: f043 0380 orr.w r3, r3, #128 @ 0x80
8004660: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
8004662: 2380 movs r3, #128 @ 0x80
8004664: 617b str r3, [r7, #20]
8004666: e024 b.n 80046b2 <HAL_RCC_ClockConfig+0xfa>
}
}
else
{
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8004668: 687b ldr r3, [r7, #4]
800466a: 685b ldr r3, [r3, #4]
800466c: 2b02 cmp r3, #2
800466e: d107 bne.n 8004680 <HAL_RCC_ClockConfig+0xc8>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8004670: 4b6a ldr r3, [pc, #424] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004672: 681b ldr r3, [r3, #0]
8004674: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004678: 2b00 cmp r3, #0
800467a: d109 bne.n 8004690 <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
800467c: 2301 movs r3, #1
800467e: e0c6 b.n 800480e <HAL_RCC_ClockConfig+0x256>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8004680: 4b66 ldr r3, [pc, #408] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004682: 681b ldr r3, [r3, #0]
8004684: f403 6380 and.w r3, r3, #1024 @ 0x400
8004688: 2b00 cmp r3, #0
800468a: d101 bne.n 8004690 <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
800468c: 2301 movs r3, #1
800468e: e0be b.n 800480e <HAL_RCC_ClockConfig+0x256>
}
}
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
pllfreq = HAL_RCC_GetSysClockFreq();
8004690: f000 f8ce bl 8004830 <HAL_RCC_GetSysClockFreq>
8004694: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
if(pllfreq > 80000000U)
8004696: 693b ldr r3, [r7, #16]
8004698: 4a61 ldr r2, [pc, #388] @ (8004820 <HAL_RCC_ClockConfig+0x268>)
800469a: 4293 cmp r3, r2
800469c: d909 bls.n 80046b2 <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
800469e: 4b5f ldr r3, [pc, #380] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80046a0: 689b ldr r3, [r3, #8]
80046a2: f023 03f0 bic.w r3, r3, #240 @ 0xf0
80046a6: 4a5d ldr r2, [pc, #372] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80046a8: f043 0380 orr.w r3, r3, #128 @ 0x80
80046ac: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
80046ae: 2380 movs r3, #128 @ 0x80
80046b0: 617b str r3, [r7, #20]
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
80046b2: 4b5a ldr r3, [pc, #360] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80046b4: 689b ldr r3, [r3, #8]
80046b6: f023 0203 bic.w r2, r3, #3
80046ba: 687b ldr r3, [r7, #4]
80046bc: 685b ldr r3, [r3, #4]
80046be: 4957 ldr r1, [pc, #348] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80046c0: 4313 orrs r3, r2
80046c2: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80046c4: f7fd fb7e bl 8001dc4 <HAL_GetTick>
80046c8: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80046ca: e00a b.n 80046e2 <HAL_RCC_ClockConfig+0x12a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80046cc: f7fd fb7a bl 8001dc4 <HAL_GetTick>
80046d0: 4602 mov r2, r0
80046d2: 68fb ldr r3, [r7, #12]
80046d4: 1ad3 subs r3, r2, r3
80046d6: f241 3288 movw r2, #5000 @ 0x1388
80046da: 4293 cmp r3, r2
80046dc: d901 bls.n 80046e2 <HAL_RCC_ClockConfig+0x12a>
{
return HAL_TIMEOUT;
80046de: 2303 movs r3, #3
80046e0: e095 b.n 800480e <HAL_RCC_ClockConfig+0x256>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80046e2: 4b4e ldr r3, [pc, #312] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80046e4: 689b ldr r3, [r3, #8]
80046e6: f003 020c and.w r2, r3, #12
80046ea: 687b ldr r3, [r7, #4]
80046ec: 685b ldr r3, [r3, #4]
80046ee: 009b lsls r3, r3, #2
80046f0: 429a cmp r2, r3
80046f2: d1eb bne.n 80046cc <HAL_RCC_ClockConfig+0x114>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80046f4: 687b ldr r3, [r7, #4]
80046f6: 681b ldr r3, [r3, #0]
80046f8: f003 0302 and.w r3, r3, #2
80046fc: 2b00 cmp r3, #0
80046fe: d023 beq.n 8004748 <HAL_RCC_ClockConfig+0x190>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004700: 687b ldr r3, [r7, #4]
8004702: 681b ldr r3, [r3, #0]
8004704: f003 0304 and.w r3, r3, #4
8004708: 2b00 cmp r3, #0
800470a: d005 beq.n 8004718 <HAL_RCC_ClockConfig+0x160>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
800470c: 4b43 ldr r3, [pc, #268] @ (800481c <HAL_RCC_ClockConfig+0x264>)
800470e: 689b ldr r3, [r3, #8]
8004710: 4a42 ldr r2, [pc, #264] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004712: f443 63e0 orr.w r3, r3, #1792 @ 0x700
8004716: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8004718: 687b ldr r3, [r7, #4]
800471a: 681b ldr r3, [r3, #0]
800471c: f003 0308 and.w r3, r3, #8
8004720: 2b00 cmp r3, #0
8004722: d007 beq.n 8004734 <HAL_RCC_ClockConfig+0x17c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
8004724: 4b3d ldr r3, [pc, #244] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004726: 689b ldr r3, [r3, #8]
8004728: f423 537c bic.w r3, r3, #16128 @ 0x3f00
800472c: 4a3b ldr r2, [pc, #236] @ (800481c <HAL_RCC_ClockConfig+0x264>)
800472e: f443 63e0 orr.w r3, r3, #1792 @ 0x700
8004732: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8004734: 4b39 ldr r3, [pc, #228] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004736: 689b ldr r3, [r3, #8]
8004738: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800473c: 687b ldr r3, [r7, #4]
800473e: 689b ldr r3, [r3, #8]
8004740: 4936 ldr r1, [pc, #216] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004742: 4313 orrs r3, r2
8004744: 608b str r3, [r1, #8]
8004746: e008 b.n 800475a <HAL_RCC_ClockConfig+0x1a2>
}
else
{
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
8004748: 697b ldr r3, [r7, #20]
800474a: 2b80 cmp r3, #128 @ 0x80
800474c: d105 bne.n 800475a <HAL_RCC_ClockConfig+0x1a2>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
800474e: 4b33 ldr r3, [pc, #204] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004750: 689b ldr r3, [r3, #8]
8004752: 4a32 ldr r2, [pc, #200] @ (800481c <HAL_RCC_ClockConfig+0x264>)
8004754: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8004758: 6093 str r3, [r2, #8]
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
800475a: 4b2f ldr r3, [pc, #188] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
800475c: 681b ldr r3, [r3, #0]
800475e: f003 030f and.w r3, r3, #15
8004762: 683a ldr r2, [r7, #0]
8004764: 429a cmp r2, r3
8004766: d21d bcs.n 80047a4 <HAL_RCC_ClockConfig+0x1ec>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004768: 4b2b ldr r3, [pc, #172] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
800476a: 681b ldr r3, [r3, #0]
800476c: f023 020f bic.w r2, r3, #15
8004770: 4929 ldr r1, [pc, #164] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
8004772: 683b ldr r3, [r7, #0]
8004774: 4313 orrs r3, r2
8004776: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8004778: f7fd fb24 bl 8001dc4 <HAL_GetTick>
800477c: 60f8 str r0, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
800477e: e00a b.n 8004796 <HAL_RCC_ClockConfig+0x1de>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004780: f7fd fb20 bl 8001dc4 <HAL_GetTick>
8004784: 4602 mov r2, r0
8004786: 68fb ldr r3, [r7, #12]
8004788: 1ad3 subs r3, r2, r3
800478a: f241 3288 movw r2, #5000 @ 0x1388
800478e: 4293 cmp r3, r2
8004790: d901 bls.n 8004796 <HAL_RCC_ClockConfig+0x1de>
{
return HAL_TIMEOUT;
8004792: 2303 movs r3, #3
8004794: e03b b.n 800480e <HAL_RCC_ClockConfig+0x256>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8004796: 4b20 ldr r3, [pc, #128] @ (8004818 <HAL_RCC_ClockConfig+0x260>)
8004798: 681b ldr r3, [r3, #0]
800479a: f003 030f and.w r3, r3, #15
800479e: 683a ldr r2, [r7, #0]
80047a0: 429a cmp r2, r3
80047a2: d1ed bne.n 8004780 <HAL_RCC_ClockConfig+0x1c8>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80047a4: 687b ldr r3, [r7, #4]
80047a6: 681b ldr r3, [r3, #0]
80047a8: f003 0304 and.w r3, r3, #4
80047ac: 2b00 cmp r3, #0
80047ae: d008 beq.n 80047c2 <HAL_RCC_ClockConfig+0x20a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80047b0: 4b1a ldr r3, [pc, #104] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80047b2: 689b ldr r3, [r3, #8]
80047b4: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80047b8: 687b ldr r3, [r7, #4]
80047ba: 68db ldr r3, [r3, #12]
80047bc: 4917 ldr r1, [pc, #92] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80047be: 4313 orrs r3, r2
80047c0: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80047c2: 687b ldr r3, [r7, #4]
80047c4: 681b ldr r3, [r3, #0]
80047c6: f003 0308 and.w r3, r3, #8
80047ca: 2b00 cmp r3, #0
80047cc: d009 beq.n 80047e2 <HAL_RCC_ClockConfig+0x22a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80047ce: 4b13 ldr r3, [pc, #76] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80047d0: 689b ldr r3, [r3, #8]
80047d2: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80047d6: 687b ldr r3, [r7, #4]
80047d8: 691b ldr r3, [r3, #16]
80047da: 00db lsls r3, r3, #3
80047dc: 490f ldr r1, [pc, #60] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80047de: 4313 orrs r3, r2
80047e0: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
80047e2: f000 f825 bl 8004830 <HAL_RCC_GetSysClockFreq>
80047e6: 4602 mov r2, r0
80047e8: 4b0c ldr r3, [pc, #48] @ (800481c <HAL_RCC_ClockConfig+0x264>)
80047ea: 689b ldr r3, [r3, #8]
80047ec: 091b lsrs r3, r3, #4
80047ee: f003 030f and.w r3, r3, #15
80047f2: 490c ldr r1, [pc, #48] @ (8004824 <HAL_RCC_ClockConfig+0x26c>)
80047f4: 5ccb ldrb r3, [r1, r3]
80047f6: f003 031f and.w r3, r3, #31
80047fa: fa22 f303 lsr.w r3, r2, r3
80047fe: 4a0a ldr r2, [pc, #40] @ (8004828 <HAL_RCC_ClockConfig+0x270>)
8004800: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
8004802: 4b0a ldr r3, [pc, #40] @ (800482c <HAL_RCC_ClockConfig+0x274>)
8004804: 681b ldr r3, [r3, #0]
8004806: 4618 mov r0, r3
8004808: f7fd fa90 bl 8001d2c <HAL_InitTick>
800480c: 4603 mov r3, r0
}
800480e: 4618 mov r0, r3
8004810: 3718 adds r7, #24
8004812: 46bd mov sp, r7
8004814: bd80 pop {r7, pc}
8004816: bf00 nop
8004818: 40022000 .word 0x40022000
800481c: 40021000 .word 0x40021000
8004820: 04c4b400 .word 0x04c4b400
8004824: 08008640 .word 0x08008640
8004828: 20000018 .word 0x20000018
800482c: 2000001c .word 0x2000001c
08004830 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8004830: b480 push {r7}
8004832: b087 sub sp, #28
8004834: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
8004836: 4b2c ldr r3, [pc, #176] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
8004838: 689b ldr r3, [r3, #8]
800483a: f003 030c and.w r3, r3, #12
800483e: 2b04 cmp r3, #4
8004840: d102 bne.n 8004848 <HAL_RCC_GetSysClockFreq+0x18>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
8004842: 4b2a ldr r3, [pc, #168] @ (80048ec <HAL_RCC_GetSysClockFreq+0xbc>)
8004844: 613b str r3, [r7, #16]
8004846: e047 b.n 80048d8 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
8004848: 4b27 ldr r3, [pc, #156] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
800484a: 689b ldr r3, [r3, #8]
800484c: f003 030c and.w r3, r3, #12
8004850: 2b08 cmp r3, #8
8004852: d102 bne.n 800485a <HAL_RCC_GetSysClockFreq+0x2a>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8004854: 4b26 ldr r3, [pc, #152] @ (80048f0 <HAL_RCC_GetSysClockFreq+0xc0>)
8004856: 613b str r3, [r7, #16]
8004858: e03e b.n 80048d8 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
800485a: 4b23 ldr r3, [pc, #140] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
800485c: 689b ldr r3, [r3, #8]
800485e: f003 030c and.w r3, r3, #12
8004862: 2b0c cmp r3, #12
8004864: d136 bne.n 80048d4 <HAL_RCC_GetSysClockFreq+0xa4>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8004866: 4b20 ldr r3, [pc, #128] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
8004868: 68db ldr r3, [r3, #12]
800486a: f003 0303 and.w r3, r3, #3
800486e: 60fb str r3, [r7, #12]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8004870: 4b1d ldr r3, [pc, #116] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
8004872: 68db ldr r3, [r3, #12]
8004874: 091b lsrs r3, r3, #4
8004876: f003 030f and.w r3, r3, #15
800487a: 3301 adds r3, #1
800487c: 60bb str r3, [r7, #8]
switch (pllsource)
800487e: 68fb ldr r3, [r7, #12]
8004880: 2b03 cmp r3, #3
8004882: d10c bne.n 800489e <HAL_RCC_GetSysClockFreq+0x6e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8004884: 4a1a ldr r2, [pc, #104] @ (80048f0 <HAL_RCC_GetSysClockFreq+0xc0>)
8004886: 68bb ldr r3, [r7, #8]
8004888: fbb2 f3f3 udiv r3, r2, r3
800488c: 4a16 ldr r2, [pc, #88] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
800488e: 68d2 ldr r2, [r2, #12]
8004890: 0a12 lsrs r2, r2, #8
8004892: f002 027f and.w r2, r2, #127 @ 0x7f
8004896: fb02 f303 mul.w r3, r2, r3
800489a: 617b str r3, [r7, #20]
break;
800489c: e00c b.n 80048b8 <HAL_RCC_GetSysClockFreq+0x88>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
800489e: 4a13 ldr r2, [pc, #76] @ (80048ec <HAL_RCC_GetSysClockFreq+0xbc>)
80048a0: 68bb ldr r3, [r7, #8]
80048a2: fbb2 f3f3 udiv r3, r2, r3
80048a6: 4a10 ldr r2, [pc, #64] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
80048a8: 68d2 ldr r2, [r2, #12]
80048aa: 0a12 lsrs r2, r2, #8
80048ac: f002 027f and.w r2, r2, #127 @ 0x7f
80048b0: fb02 f303 mul.w r3, r2, r3
80048b4: 617b str r3, [r7, #20]
break;
80048b6: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
80048b8: 4b0b ldr r3, [pc, #44] @ (80048e8 <HAL_RCC_GetSysClockFreq+0xb8>)
80048ba: 68db ldr r3, [r3, #12]
80048bc: 0e5b lsrs r3, r3, #25
80048be: f003 0303 and.w r3, r3, #3
80048c2: 3301 adds r3, #1
80048c4: 005b lsls r3, r3, #1
80048c6: 607b str r3, [r7, #4]
sysclockfreq = pllvco/pllr;
80048c8: 697a ldr r2, [r7, #20]
80048ca: 687b ldr r3, [r7, #4]
80048cc: fbb2 f3f3 udiv r3, r2, r3
80048d0: 613b str r3, [r7, #16]
80048d2: e001 b.n 80048d8 <HAL_RCC_GetSysClockFreq+0xa8>
}
else
{
sysclockfreq = 0U;
80048d4: 2300 movs r3, #0
80048d6: 613b str r3, [r7, #16]
}
return sysclockfreq;
80048d8: 693b ldr r3, [r7, #16]
}
80048da: 4618 mov r0, r3
80048dc: 371c adds r7, #28
80048de: 46bd mov sp, r7
80048e0: f85d 7b04 ldr.w r7, [sp], #4
80048e4: 4770 bx lr
80048e6: bf00 nop
80048e8: 40021000 .word 0x40021000
80048ec: 00f42400 .word 0x00f42400
80048f0: 007a1200 .word 0x007a1200
080048f4 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80048f4: b480 push {r7}
80048f6: af00 add r7, sp, #0
return SystemCoreClock;
80048f8: 4b03 ldr r3, [pc, #12] @ (8004908 <HAL_RCC_GetHCLKFreq+0x14>)
80048fa: 681b ldr r3, [r3, #0]
}
80048fc: 4618 mov r0, r3
80048fe: 46bd mov sp, r7
8004900: f85d 7b04 ldr.w r7, [sp], #4
8004904: 4770 bx lr
8004906: bf00 nop
8004908: 20000018 .word 0x20000018
0800490c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
800490c: b580 push {r7, lr}
800490e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
8004910: f7ff fff0 bl 80048f4 <HAL_RCC_GetHCLKFreq>
8004914: 4602 mov r2, r0
8004916: 4b06 ldr r3, [pc, #24] @ (8004930 <HAL_RCC_GetPCLK1Freq+0x24>)
8004918: 689b ldr r3, [r3, #8]
800491a: 0a1b lsrs r3, r3, #8
800491c: f003 0307 and.w r3, r3, #7
8004920: 4904 ldr r1, [pc, #16] @ (8004934 <HAL_RCC_GetPCLK1Freq+0x28>)
8004922: 5ccb ldrb r3, [r1, r3]
8004924: f003 031f and.w r3, r3, #31
8004928: fa22 f303 lsr.w r3, r2, r3
}
800492c: 4618 mov r0, r3
800492e: bd80 pop {r7, pc}
8004930: 40021000 .word 0x40021000
8004934: 08008650 .word 0x08008650
08004938 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8004938: b580 push {r7, lr}
800493a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
800493c: f7ff ffda bl 80048f4 <HAL_RCC_GetHCLKFreq>
8004940: 4602 mov r2, r0
8004942: 4b06 ldr r3, [pc, #24] @ (800495c <HAL_RCC_GetPCLK2Freq+0x24>)
8004944: 689b ldr r3, [r3, #8]
8004946: 0adb lsrs r3, r3, #11
8004948: f003 0307 and.w r3, r3, #7
800494c: 4904 ldr r1, [pc, #16] @ (8004960 <HAL_RCC_GetPCLK2Freq+0x28>)
800494e: 5ccb ldrb r3, [r1, r3]
8004950: f003 031f and.w r3, r3, #31
8004954: fa22 f303 lsr.w r3, r2, r3
}
8004958: 4618 mov r0, r3
800495a: bd80 pop {r7, pc}
800495c: 40021000 .word 0x40021000
8004960: 08008650 .word 0x08008650
08004964 <RCC_GetSysClockFreqFromPLLSource>:
/**
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
* @retval SYSCLK frequency
*/
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
{
8004964: b480 push {r7}
8004966: b087 sub sp, #28
8004968: af00 add r7, sp, #0
uint32_t sysclockfreq;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
800496a: 4b1e ldr r3, [pc, #120] @ (80049e4 <RCC_GetSysClockFreqFromPLLSource+0x80>)
800496c: 68db ldr r3, [r3, #12]
800496e: f003 0303 and.w r3, r3, #3
8004972: 613b str r3, [r7, #16]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8004974: 4b1b ldr r3, [pc, #108] @ (80049e4 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8004976: 68db ldr r3, [r3, #12]
8004978: 091b lsrs r3, r3, #4
800497a: f003 030f and.w r3, r3, #15
800497e: 3301 adds r3, #1
8004980: 60fb str r3, [r7, #12]
switch (pllsource)
8004982: 693b ldr r3, [r7, #16]
8004984: 2b03 cmp r3, #3
8004986: d10c bne.n 80049a2 <RCC_GetSysClockFreqFromPLLSource+0x3e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8004988: 4a17 ldr r2, [pc, #92] @ (80049e8 <RCC_GetSysClockFreqFromPLLSource+0x84>)
800498a: 68fb ldr r3, [r7, #12]
800498c: fbb2 f3f3 udiv r3, r2, r3
8004990: 4a14 ldr r2, [pc, #80] @ (80049e4 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8004992: 68d2 ldr r2, [r2, #12]
8004994: 0a12 lsrs r2, r2, #8
8004996: f002 027f and.w r2, r2, #127 @ 0x7f
800499a: fb02 f303 mul.w r3, r2, r3
800499e: 617b str r3, [r7, #20]
break;
80049a0: e00c b.n 80049bc <RCC_GetSysClockFreqFromPLLSource+0x58>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
80049a2: 4a12 ldr r2, [pc, #72] @ (80049ec <RCC_GetSysClockFreqFromPLLSource+0x88>)
80049a4: 68fb ldr r3, [r7, #12]
80049a6: fbb2 f3f3 udiv r3, r2, r3
80049aa: 4a0e ldr r2, [pc, #56] @ (80049e4 <RCC_GetSysClockFreqFromPLLSource+0x80>)
80049ac: 68d2 ldr r2, [r2, #12]
80049ae: 0a12 lsrs r2, r2, #8
80049b0: f002 027f and.w r2, r2, #127 @ 0x7f
80049b4: fb02 f303 mul.w r3, r2, r3
80049b8: 617b str r3, [r7, #20]
break;
80049ba: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
80049bc: 4b09 ldr r3, [pc, #36] @ (80049e4 <RCC_GetSysClockFreqFromPLLSource+0x80>)
80049be: 68db ldr r3, [r3, #12]
80049c0: 0e5b lsrs r3, r3, #25
80049c2: f003 0303 and.w r3, r3, #3
80049c6: 3301 adds r3, #1
80049c8: 005b lsls r3, r3, #1
80049ca: 60bb str r3, [r7, #8]
sysclockfreq = pllvco/pllr;
80049cc: 697a ldr r2, [r7, #20]
80049ce: 68bb ldr r3, [r7, #8]
80049d0: fbb2 f3f3 udiv r3, r2, r3
80049d4: 607b str r3, [r7, #4]
return sysclockfreq;
80049d6: 687b ldr r3, [r7, #4]
}
80049d8: 4618 mov r0, r3
80049da: 371c adds r7, #28
80049dc: 46bd mov sp, r7
80049de: f85d 7b04 ldr.w r7, [sp], #4
80049e2: 4770 bx lr
80049e4: 40021000 .word 0x40021000
80049e8: 007a1200 .word 0x007a1200
80049ec: 00f42400 .word 0x00f42400
080049f0 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
80049f0: b580 push {r7, lr}
80049f2: b086 sub sp, #24
80049f4: af00 add r7, sp, #0
80049f6: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
80049f8: 2300 movs r3, #0
80049fa: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
80049fc: 2300 movs r3, #0
80049fe: 74bb strb r3, [r7, #18]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8004a00: 687b ldr r3, [r7, #4]
8004a02: 681b ldr r3, [r3, #0]
8004a04: f403 2300 and.w r3, r3, #524288 @ 0x80000
8004a08: 2b00 cmp r3, #0
8004a0a: f000 8098 beq.w 8004b3e <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
FlagStatus pwrclkchanged = RESET;
8004a0e: 2300 movs r3, #0
8004a10: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8004a12: 4b43 ldr r3, [pc, #268] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004a14: 6d9b ldr r3, [r3, #88] @ 0x58
8004a16: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004a1a: 2b00 cmp r3, #0
8004a1c: d10d bne.n 8004a3a <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004a1e: 4b40 ldr r3, [pc, #256] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004a20: 6d9b ldr r3, [r3, #88] @ 0x58
8004a22: 4a3f ldr r2, [pc, #252] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004a24: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004a28: 6593 str r3, [r2, #88] @ 0x58
8004a2a: 4b3d ldr r3, [pc, #244] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004a2c: 6d9b ldr r3, [r3, #88] @ 0x58
8004a2e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004a32: 60bb str r3, [r7, #8]
8004a34: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8004a36: 2301 movs r3, #1
8004a38: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8004a3a: 4b3a ldr r3, [pc, #232] @ (8004b24 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004a3c: 681b ldr r3, [r3, #0]
8004a3e: 4a39 ldr r2, [pc, #228] @ (8004b24 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004a40: f443 7380 orr.w r3, r3, #256 @ 0x100
8004a44: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8004a46: f7fd f9bd bl 8001dc4 <HAL_GetTick>
8004a4a: 60f8 str r0, [r7, #12]
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8004a4c: e009 b.n 8004a62 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004a4e: f7fd f9b9 bl 8001dc4 <HAL_GetTick>
8004a52: 4602 mov r2, r0
8004a54: 68fb ldr r3, [r7, #12]
8004a56: 1ad3 subs r3, r2, r3
8004a58: 2b02 cmp r3, #2
8004a5a: d902 bls.n 8004a62 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
ret = HAL_TIMEOUT;
8004a5c: 2303 movs r3, #3
8004a5e: 74fb strb r3, [r7, #19]
break;
8004a60: e005 b.n 8004a6e <HAL_RCCEx_PeriphCLKConfig+0x7e>
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8004a62: 4b30 ldr r3, [pc, #192] @ (8004b24 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004a64: 681b ldr r3, [r3, #0]
8004a66: f403 7380 and.w r3, r3, #256 @ 0x100
8004a6a: 2b00 cmp r3, #0
8004a6c: d0ef beq.n 8004a4e <HAL_RCCEx_PeriphCLKConfig+0x5e>
}
}
if(ret == HAL_OK)
8004a6e: 7cfb ldrb r3, [r7, #19]
8004a70: 2b00 cmp r3, #0
8004a72: d159 bne.n 8004b28 <HAL_RCCEx_PeriphCLKConfig+0x138>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8004a74: 4b2a ldr r3, [pc, #168] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004a76: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004a7a: f403 7340 and.w r3, r3, #768 @ 0x300
8004a7e: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8004a80: 697b ldr r3, [r7, #20]
8004a82: 2b00 cmp r3, #0
8004a84: d01e beq.n 8004ac4 <HAL_RCCEx_PeriphCLKConfig+0xd4>
8004a86: 687b ldr r3, [r7, #4]
8004a88: 6c1b ldr r3, [r3, #64] @ 0x40
8004a8a: 697a ldr r2, [r7, #20]
8004a8c: 429a cmp r2, r3
8004a8e: d019 beq.n 8004ac4 <HAL_RCCEx_PeriphCLKConfig+0xd4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8004a90: 4b23 ldr r3, [pc, #140] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004a92: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004a96: f423 7340 bic.w r3, r3, #768 @ 0x300
8004a9a: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8004a9c: 4b20 ldr r3, [pc, #128] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004a9e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004aa2: 4a1f ldr r2, [pc, #124] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004aa4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004aa8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8004aac: 4b1c ldr r3, [pc, #112] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004aae: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004ab2: 4a1b ldr r2, [pc, #108] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004ab4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8004ab8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8004abc: 4a18 ldr r2, [pc, #96] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004abe: 697b ldr r3, [r7, #20]
8004ac0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8004ac4: 697b ldr r3, [r7, #20]
8004ac6: f003 0301 and.w r3, r3, #1
8004aca: 2b00 cmp r3, #0
8004acc: d016 beq.n 8004afc <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004ace: f7fd f979 bl 8001dc4 <HAL_GetTick>
8004ad2: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004ad4: e00b b.n 8004aee <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004ad6: f7fd f975 bl 8001dc4 <HAL_GetTick>
8004ada: 4602 mov r2, r0
8004adc: 68fb ldr r3, [r7, #12]
8004ade: 1ad3 subs r3, r2, r3
8004ae0: f241 3288 movw r2, #5000 @ 0x1388
8004ae4: 4293 cmp r3, r2
8004ae6: d902 bls.n 8004aee <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
ret = HAL_TIMEOUT;
8004ae8: 2303 movs r3, #3
8004aea: 74fb strb r3, [r7, #19]
break;
8004aec: e006 b.n 8004afc <HAL_RCCEx_PeriphCLKConfig+0x10c>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004aee: 4b0c ldr r3, [pc, #48] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004af0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004af4: f003 0302 and.w r3, r3, #2
8004af8: 2b00 cmp r3, #0
8004afa: d0ec beq.n 8004ad6 <HAL_RCCEx_PeriphCLKConfig+0xe6>
}
}
}
if(ret == HAL_OK)
8004afc: 7cfb ldrb r3, [r7, #19]
8004afe: 2b00 cmp r3, #0
8004b00: d10b bne.n 8004b1a <HAL_RCCEx_PeriphCLKConfig+0x12a>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8004b02: 4b07 ldr r3, [pc, #28] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b04: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004b08: f423 7240 bic.w r2, r3, #768 @ 0x300
8004b0c: 687b ldr r3, [r7, #4]
8004b0e: 6c1b ldr r3, [r3, #64] @ 0x40
8004b10: 4903 ldr r1, [pc, #12] @ (8004b20 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004b12: 4313 orrs r3, r2
8004b14: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8004b18: e008 b.n 8004b2c <HAL_RCCEx_PeriphCLKConfig+0x13c>
}
else
{
/* set overall return value */
status = ret;
8004b1a: 7cfb ldrb r3, [r7, #19]
8004b1c: 74bb strb r3, [r7, #18]
8004b1e: e005 b.n 8004b2c <HAL_RCCEx_PeriphCLKConfig+0x13c>
8004b20: 40021000 .word 0x40021000
8004b24: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8004b28: 7cfb ldrb r3, [r7, #19]
8004b2a: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8004b2c: 7c7b ldrb r3, [r7, #17]
8004b2e: 2b01 cmp r3, #1
8004b30: d105 bne.n 8004b3e <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8004b32: 4ba6 ldr r3, [pc, #664] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b34: 6d9b ldr r3, [r3, #88] @ 0x58
8004b36: 4aa5 ldr r2, [pc, #660] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b38: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8004b3c: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8004b3e: 687b ldr r3, [r7, #4]
8004b40: 681b ldr r3, [r3, #0]
8004b42: f003 0301 and.w r3, r3, #1
8004b46: 2b00 cmp r3, #0
8004b48: d00a beq.n 8004b60 <HAL_RCCEx_PeriphCLKConfig+0x170>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8004b4a: 4ba0 ldr r3, [pc, #640] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b4c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004b50: f023 0203 bic.w r2, r3, #3
8004b54: 687b ldr r3, [r7, #4]
8004b56: 685b ldr r3, [r3, #4]
8004b58: 499c ldr r1, [pc, #624] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b5a: 4313 orrs r3, r2
8004b5c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8004b60: 687b ldr r3, [r7, #4]
8004b62: 681b ldr r3, [r3, #0]
8004b64: f003 0302 and.w r3, r3, #2
8004b68: 2b00 cmp r3, #0
8004b6a: d00a beq.n 8004b82 <HAL_RCCEx_PeriphCLKConfig+0x192>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8004b6c: 4b97 ldr r3, [pc, #604] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b6e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004b72: f023 020c bic.w r2, r3, #12
8004b76: 687b ldr r3, [r7, #4]
8004b78: 689b ldr r3, [r3, #8]
8004b7a: 4994 ldr r1, [pc, #592] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b7c: 4313 orrs r3, r2
8004b7e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8004b82: 687b ldr r3, [r7, #4]
8004b84: 681b ldr r3, [r3, #0]
8004b86: f003 0304 and.w r3, r3, #4
8004b8a: 2b00 cmp r3, #0
8004b8c: d00a beq.n 8004ba4 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8004b8e: 4b8f ldr r3, [pc, #572] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b90: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004b94: f023 0230 bic.w r2, r3, #48 @ 0x30
8004b98: 687b ldr r3, [r7, #4]
8004b9a: 68db ldr r3, [r3, #12]
8004b9c: 498b ldr r1, [pc, #556] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004b9e: 4313 orrs r3, r2
8004ba0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8004ba4: 687b ldr r3, [r7, #4]
8004ba6: 681b ldr r3, [r3, #0]
8004ba8: f003 0308 and.w r3, r3, #8
8004bac: 2b00 cmp r3, #0
8004bae: d00a beq.n 8004bc6 <HAL_RCCEx_PeriphCLKConfig+0x1d6>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8004bb0: 4b86 ldr r3, [pc, #536] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004bb2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004bb6: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8004bba: 687b ldr r3, [r7, #4]
8004bbc: 691b ldr r3, [r3, #16]
8004bbe: 4983 ldr r1, [pc, #524] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004bc0: 4313 orrs r3, r2
8004bc2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8004bc6: 687b ldr r3, [r7, #4]
8004bc8: 681b ldr r3, [r3, #0]
8004bca: f003 0320 and.w r3, r3, #32
8004bce: 2b00 cmp r3, #0
8004bd0: d00a beq.n 8004be8 <HAL_RCCEx_PeriphCLKConfig+0x1f8>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8004bd2: 4b7e ldr r3, [pc, #504] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004bd4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004bd8: f423 6240 bic.w r2, r3, #3072 @ 0xc00
8004bdc: 687b ldr r3, [r7, #4]
8004bde: 695b ldr r3, [r3, #20]
8004be0: 497a ldr r1, [pc, #488] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004be2: 4313 orrs r3, r2
8004be4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8004be8: 687b ldr r3, [r7, #4]
8004bea: 681b ldr r3, [r3, #0]
8004bec: f003 0340 and.w r3, r3, #64 @ 0x40
8004bf0: 2b00 cmp r3, #0
8004bf2: d00a beq.n 8004c0a <HAL_RCCEx_PeriphCLKConfig+0x21a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8004bf4: 4b75 ldr r3, [pc, #468] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004bf6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004bfa: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8004bfe: 687b ldr r3, [r7, #4]
8004c00: 699b ldr r3, [r3, #24]
8004c02: 4972 ldr r1, [pc, #456] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c04: 4313 orrs r3, r2
8004c06: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8004c0a: 687b ldr r3, [r7, #4]
8004c0c: 681b ldr r3, [r3, #0]
8004c0e: f003 0380 and.w r3, r3, #128 @ 0x80
8004c12: 2b00 cmp r3, #0
8004c14: d00a beq.n 8004c2c <HAL_RCCEx_PeriphCLKConfig+0x23c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8004c16: 4b6d ldr r3, [pc, #436] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c18: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c1c: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8004c20: 687b ldr r3, [r7, #4]
8004c22: 69db ldr r3, [r3, #28]
8004c24: 4969 ldr r1, [pc, #420] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c26: 4313 orrs r3, r2
8004c28: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C3)
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8004c2c: 687b ldr r3, [r7, #4]
8004c2e: 681b ldr r3, [r3, #0]
8004c30: f403 7380 and.w r3, r3, #256 @ 0x100
8004c34: 2b00 cmp r3, #0
8004c36: d00a beq.n 8004c4e <HAL_RCCEx_PeriphCLKConfig+0x25e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8004c38: 4b64 ldr r3, [pc, #400] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c3a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c3e: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8004c42: 687b ldr r3, [r7, #4]
8004c44: 6a1b ldr r3, [r3, #32]
8004c46: 4961 ldr r1, [pc, #388] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c48: 4313 orrs r3, r2
8004c4a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* I2C4 */
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8004c4e: 687b ldr r3, [r7, #4]
8004c50: 681b ldr r3, [r3, #0]
8004c52: f403 7300 and.w r3, r3, #512 @ 0x200
8004c56: 2b00 cmp r3, #0
8004c58: d00a beq.n 8004c70 <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8004c5a: 4b5c ldr r3, [pc, #368] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c5c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c60: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
8004c64: 687b ldr r3, [r7, #4]
8004c66: 6a5b ldr r3, [r3, #36] @ 0x24
8004c68: 4958 ldr r1, [pc, #352] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c6a: 4313 orrs r3, r2
8004c6c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
8004c70: 687b ldr r3, [r7, #4]
8004c72: 681b ldr r3, [r3, #0]
8004c74: f403 6380 and.w r3, r3, #1024 @ 0x400
8004c78: 2b00 cmp r3, #0
8004c7a: d015 beq.n 8004ca8 <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure the SAI1 interface clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8004c7c: 4b53 ldr r3, [pc, #332] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c7e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004c82: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8004c86: 687b ldr r3, [r7, #4]
8004c88: 6a9b ldr r3, [r3, #40] @ 0x28
8004c8a: 4950 ldr r1, [pc, #320] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c8c: 4313 orrs r3, r2
8004c8e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
8004c92: 687b ldr r3, [r7, #4]
8004c94: 6a9b ldr r3, [r3, #40] @ 0x28
8004c96: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004c9a: d105 bne.n 8004ca8 <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004c9c: 4b4b ldr r3, [pc, #300] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004c9e: 68db ldr r3, [r3, #12]
8004ca0: 4a4a ldr r2, [pc, #296] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004ca2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004ca6: 60d3 str r3, [r2, #12]
#endif /* SAI1 */
#if defined(SPI_I2S_SUPPORT)
/*-------------------------- I2S clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
8004ca8: 687b ldr r3, [r7, #4]
8004caa: 681b ldr r3, [r3, #0]
8004cac: f403 6300 and.w r3, r3, #2048 @ 0x800
8004cb0: 2b00 cmp r3, #0
8004cb2: d015 beq.n 8004ce0 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S interface clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8004cb4: 4b45 ldr r3, [pc, #276] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cb6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004cba: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8004cbe: 687b ldr r3, [r7, #4]
8004cc0: 6adb ldr r3, [r3, #44] @ 0x2c
8004cc2: 4942 ldr r1, [pc, #264] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cc4: 4313 orrs r3, r2
8004cc6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
8004cca: 687b ldr r3, [r7, #4]
8004ccc: 6adb ldr r3, [r3, #44] @ 0x2c
8004cce: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8004cd2: d105 bne.n 8004ce0 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004cd4: 4b3d ldr r3, [pc, #244] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cd6: 68db ldr r3, [r3, #12]
8004cd8: 4a3c ldr r2, [pc, #240] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cda: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004cde: 60d3 str r3, [r2, #12]
#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/*-------------------------- FDCAN clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
8004ce0: 687b ldr r3, [r7, #4]
8004ce2: 681b ldr r3, [r3, #0]
8004ce4: f403 5380 and.w r3, r3, #4096 @ 0x1000
8004ce8: 2b00 cmp r3, #0
8004cea: d015 beq.n 8004d18 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
/* Configure the FDCAN interface clock source */
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
8004cec: 4b37 ldr r3, [pc, #220] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cee: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004cf2: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8004cf6: 687b ldr r3, [r7, #4]
8004cf8: 6b1b ldr r3, [r3, #48] @ 0x30
8004cfa: 4934 ldr r1, [pc, #208] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004cfc: 4313 orrs r3, r2
8004cfe: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
8004d02: 687b ldr r3, [r7, #4]
8004d04: 6b1b ldr r3, [r3, #48] @ 0x30
8004d06: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8004d0a: d105 bne.n 8004d18 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004d0c: 4b2f ldr r3, [pc, #188] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d0e: 68db ldr r3, [r3, #12]
8004d10: 4a2e ldr r2, [pc, #184] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d12: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004d16: 60d3 str r3, [r2, #12]
#endif /* FDCAN1 */
#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
8004d18: 687b ldr r3, [r7, #4]
8004d1a: 681b ldr r3, [r3, #0]
8004d1c: f403 5300 and.w r3, r3, #8192 @ 0x2000
8004d20: 2b00 cmp r3, #0
8004d22: d015 beq.n 8004d50 <HAL_RCCEx_PeriphCLKConfig+0x360>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
8004d24: 4b29 ldr r3, [pc, #164] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d26: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004d2a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8004d2e: 687b ldr r3, [r7, #4]
8004d30: 6b5b ldr r3, [r3, #52] @ 0x34
8004d32: 4926 ldr r1, [pc, #152] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d34: 4313 orrs r3, r2
8004d36: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
8004d3a: 687b ldr r3, [r7, #4]
8004d3c: 6b5b ldr r3, [r3, #52] @ 0x34
8004d3e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8004d42: d105 bne.n 8004d50 <HAL_RCCEx_PeriphCLKConfig+0x360>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004d44: 4b21 ldr r3, [pc, #132] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d46: 68db ldr r3, [r3, #12]
8004d48: 4a20 ldr r2, [pc, #128] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d4a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004d4e: 60d3 str r3, [r2, #12]
}
#endif /* USB */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
8004d50: 687b ldr r3, [r7, #4]
8004d52: 681b ldr r3, [r3, #0]
8004d54: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004d58: 2b00 cmp r3, #0
8004d5a: d015 beq.n 8004d88 <HAL_RCCEx_PeriphCLKConfig+0x398>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
8004d5c: 4b1b ldr r3, [pc, #108] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d5e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004d62: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8004d66: 687b ldr r3, [r7, #4]
8004d68: 6b9b ldr r3, [r3, #56] @ 0x38
8004d6a: 4918 ldr r1, [pc, #96] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d6c: 4313 orrs r3, r2
8004d6e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
8004d72: 687b ldr r3, [r7, #4]
8004d74: 6b9b ldr r3, [r3, #56] @ 0x38
8004d76: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8004d7a: d105 bne.n 8004d88 <HAL_RCCEx_PeriphCLKConfig+0x398>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004d7c: 4b13 ldr r3, [pc, #76] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d7e: 68db ldr r3, [r3, #12]
8004d80: 4a12 ldr r2, [pc, #72] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d82: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004d86: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- ADC12 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
8004d88: 687b ldr r3, [r7, #4]
8004d8a: 681b ldr r3, [r3, #0]
8004d8c: f403 4300 and.w r3, r3, #32768 @ 0x8000
8004d90: 2b00 cmp r3, #0
8004d92: d015 beq.n 8004dc0 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Check the parameters */
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
/* Configure the ADC12 interface clock source */
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
8004d94: 4b0d ldr r3, [pc, #52] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004d96: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004d9a: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
8004d9e: 687b ldr r3, [r7, #4]
8004da0: 6bdb ldr r3, [r3, #60] @ 0x3c
8004da2: 490a ldr r1, [pc, #40] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004da4: 4313 orrs r3, r2
8004da6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
8004daa: 687b ldr r3, [r7, #4]
8004dac: 6bdb ldr r3, [r3, #60] @ 0x3c
8004dae: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8004db2: d105 bne.n 8004dc0 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
8004db4: 4b05 ldr r3, [pc, #20] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004db6: 68db ldr r3, [r3, #12]
8004db8: 4a04 ldr r2, [pc, #16] @ (8004dcc <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004dba: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004dbe: 60d3 str r3, [r2, #12]
}
}
#endif /* QUADSPI */
return status;
8004dc0: 7cbb ldrb r3, [r7, #18]
}
8004dc2: 4618 mov r0, r3
8004dc4: 3718 adds r7, #24
8004dc6: 46bd mov sp, r7
8004dc8: bd80 pop {r7, pc}
8004dca: bf00 nop
8004dcc: 40021000 .word 0x40021000
08004dd0 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8004dd0: b580 push {r7, lr}
8004dd2: b082 sub sp, #8
8004dd4: af00 add r7, sp, #0
8004dd6: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004dd8: 687b ldr r3, [r7, #4]
8004dda: 2b00 cmp r3, #0
8004ddc: d101 bne.n 8004de2 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8004dde: 2301 movs r3, #1
8004de0: e049 b.n 8004e76 <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8004de2: 687b ldr r3, [r7, #4]
8004de4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004de8: b2db uxtb r3, r3
8004dea: 2b00 cmp r3, #0
8004dec: d106 bne.n 8004dfc <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8004dee: 687b ldr r3, [r7, #4]
8004df0: 2200 movs r2, #0
8004df2: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8004df6: 6878 ldr r0, [r7, #4]
8004df8: f7fc fe30 bl 8001a5c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8004dfc: 687b ldr r3, [r7, #4]
8004dfe: 2202 movs r2, #2
8004e00: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8004e04: 687b ldr r3, [r7, #4]
8004e06: 681a ldr r2, [r3, #0]
8004e08: 687b ldr r3, [r7, #4]
8004e0a: 3304 adds r3, #4
8004e0c: 4619 mov r1, r3
8004e0e: 4610 mov r0, r2
8004e10: f000 fd26 bl 8005860 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8004e14: 687b ldr r3, [r7, #4]
8004e16: 2201 movs r2, #1
8004e18: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004e1c: 687b ldr r3, [r7, #4]
8004e1e: 2201 movs r2, #1
8004e20: f883 203e strb.w r2, [r3, #62] @ 0x3e
8004e24: 687b ldr r3, [r7, #4]
8004e26: 2201 movs r2, #1
8004e28: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004e2c: 687b ldr r3, [r7, #4]
8004e2e: 2201 movs r2, #1
8004e30: f883 2040 strb.w r2, [r3, #64] @ 0x40
8004e34: 687b ldr r3, [r7, #4]
8004e36: 2201 movs r2, #1
8004e38: f883 2041 strb.w r2, [r3, #65] @ 0x41
8004e3c: 687b ldr r3, [r7, #4]
8004e3e: 2201 movs r2, #1
8004e40: f883 2042 strb.w r2, [r3, #66] @ 0x42
8004e44: 687b ldr r3, [r7, #4]
8004e46: 2201 movs r2, #1
8004e48: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004e4c: 687b ldr r3, [r7, #4]
8004e4e: 2201 movs r2, #1
8004e50: f883 2044 strb.w r2, [r3, #68] @ 0x44
8004e54: 687b ldr r3, [r7, #4]
8004e56: 2201 movs r2, #1
8004e58: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004e5c: 687b ldr r3, [r7, #4]
8004e5e: 2201 movs r2, #1
8004e60: f883 2046 strb.w r2, [r3, #70] @ 0x46
8004e64: 687b ldr r3, [r7, #4]
8004e66: 2201 movs r2, #1
8004e68: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8004e6c: 687b ldr r3, [r7, #4]
8004e6e: 2201 movs r2, #1
8004e70: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8004e74: 2300 movs r3, #0
}
8004e76: 4618 mov r0, r3
8004e78: 3708 adds r7, #8
8004e7a: 46bd mov sp, r7
8004e7c: bd80 pop {r7, pc}
08004e7e <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8004e7e: b580 push {r7, lr}
8004e80: b082 sub sp, #8
8004e82: af00 add r7, sp, #0
8004e84: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004e86: 687b ldr r3, [r7, #4]
8004e88: 2b00 cmp r3, #0
8004e8a: d101 bne.n 8004e90 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8004e8c: 2301 movs r3, #1
8004e8e: e049 b.n 8004f24 <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8004e90: 687b ldr r3, [r7, #4]
8004e92: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004e96: b2db uxtb r3, r3
8004e98: 2b00 cmp r3, #0
8004e9a: d106 bne.n 8004eaa <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8004e9c: 687b ldr r3, [r7, #4]
8004e9e: 2200 movs r2, #0
8004ea0: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8004ea4: 6878 ldr r0, [r7, #4]
8004ea6: f000 f841 bl 8004f2c <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8004eaa: 687b ldr r3, [r7, #4]
8004eac: 2202 movs r2, #2
8004eae: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8004eb2: 687b ldr r3, [r7, #4]
8004eb4: 681a ldr r2, [r3, #0]
8004eb6: 687b ldr r3, [r7, #4]
8004eb8: 3304 adds r3, #4
8004eba: 4619 mov r1, r3
8004ebc: 4610 mov r0, r2
8004ebe: f000 fccf bl 8005860 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8004ec2: 687b ldr r3, [r7, #4]
8004ec4: 2201 movs r2, #1
8004ec6: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004eca: 687b ldr r3, [r7, #4]
8004ecc: 2201 movs r2, #1
8004ece: f883 203e strb.w r2, [r3, #62] @ 0x3e
8004ed2: 687b ldr r3, [r7, #4]
8004ed4: 2201 movs r2, #1
8004ed6: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004eda: 687b ldr r3, [r7, #4]
8004edc: 2201 movs r2, #1
8004ede: f883 2040 strb.w r2, [r3, #64] @ 0x40
8004ee2: 687b ldr r3, [r7, #4]
8004ee4: 2201 movs r2, #1
8004ee6: f883 2041 strb.w r2, [r3, #65] @ 0x41
8004eea: 687b ldr r3, [r7, #4]
8004eec: 2201 movs r2, #1
8004eee: f883 2042 strb.w r2, [r3, #66] @ 0x42
8004ef2: 687b ldr r3, [r7, #4]
8004ef4: 2201 movs r2, #1
8004ef6: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004efa: 687b ldr r3, [r7, #4]
8004efc: 2201 movs r2, #1
8004efe: f883 2044 strb.w r2, [r3, #68] @ 0x44
8004f02: 687b ldr r3, [r7, #4]
8004f04: 2201 movs r2, #1
8004f06: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004f0a: 687b ldr r3, [r7, #4]
8004f0c: 2201 movs r2, #1
8004f0e: f883 2046 strb.w r2, [r3, #70] @ 0x46
8004f12: 687b ldr r3, [r7, #4]
8004f14: 2201 movs r2, #1
8004f16: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8004f1a: 687b ldr r3, [r7, #4]
8004f1c: 2201 movs r2, #1
8004f1e: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8004f22: 2300 movs r3, #0
}
8004f24: 4618 mov r0, r3
8004f26: 3708 adds r7, #8
8004f28: 46bd mov sp, r7
8004f2a: bd80 pop {r7, pc}
08004f2c <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8004f2c: b480 push {r7}
8004f2e: b083 sub sp, #12
8004f30: af00 add r7, sp, #0
8004f32: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8004f34: bf00 nop
8004f36: 370c adds r7, #12
8004f38: 46bd mov sp, r7
8004f3a: f85d 7b04 ldr.w r7, [sp], #4
8004f3e: 4770 bx lr
08004f40 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8004f40: b580 push {r7, lr}
8004f42: b084 sub sp, #16
8004f44: af00 add r7, sp, #0
8004f46: 6078 str r0, [r7, #4]
8004f48: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8004f4a: 683b ldr r3, [r7, #0]
8004f4c: 2b00 cmp r3, #0
8004f4e: d109 bne.n 8004f64 <HAL_TIM_PWM_Start+0x24>
8004f50: 687b ldr r3, [r7, #4]
8004f52: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
8004f56: b2db uxtb r3, r3
8004f58: 2b01 cmp r3, #1
8004f5a: bf14 ite ne
8004f5c: 2301 movne r3, #1
8004f5e: 2300 moveq r3, #0
8004f60: b2db uxtb r3, r3
8004f62: e03c b.n 8004fde <HAL_TIM_PWM_Start+0x9e>
8004f64: 683b ldr r3, [r7, #0]
8004f66: 2b04 cmp r3, #4
8004f68: d109 bne.n 8004f7e <HAL_TIM_PWM_Start+0x3e>
8004f6a: 687b ldr r3, [r7, #4]
8004f6c: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
8004f70: b2db uxtb r3, r3
8004f72: 2b01 cmp r3, #1
8004f74: bf14 ite ne
8004f76: 2301 movne r3, #1
8004f78: 2300 moveq r3, #0
8004f7a: b2db uxtb r3, r3
8004f7c: e02f b.n 8004fde <HAL_TIM_PWM_Start+0x9e>
8004f7e: 683b ldr r3, [r7, #0]
8004f80: 2b08 cmp r3, #8
8004f82: d109 bne.n 8004f98 <HAL_TIM_PWM_Start+0x58>
8004f84: 687b ldr r3, [r7, #4]
8004f86: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8004f8a: b2db uxtb r3, r3
8004f8c: 2b01 cmp r3, #1
8004f8e: bf14 ite ne
8004f90: 2301 movne r3, #1
8004f92: 2300 moveq r3, #0
8004f94: b2db uxtb r3, r3
8004f96: e022 b.n 8004fde <HAL_TIM_PWM_Start+0x9e>
8004f98: 683b ldr r3, [r7, #0]
8004f9a: 2b0c cmp r3, #12
8004f9c: d109 bne.n 8004fb2 <HAL_TIM_PWM_Start+0x72>
8004f9e: 687b ldr r3, [r7, #4]
8004fa0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8004fa4: b2db uxtb r3, r3
8004fa6: 2b01 cmp r3, #1
8004fa8: bf14 ite ne
8004faa: 2301 movne r3, #1
8004fac: 2300 moveq r3, #0
8004fae: b2db uxtb r3, r3
8004fb0: e015 b.n 8004fde <HAL_TIM_PWM_Start+0x9e>
8004fb2: 683b ldr r3, [r7, #0]
8004fb4: 2b10 cmp r3, #16
8004fb6: d109 bne.n 8004fcc <HAL_TIM_PWM_Start+0x8c>
8004fb8: 687b ldr r3, [r7, #4]
8004fba: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
8004fbe: b2db uxtb r3, r3
8004fc0: 2b01 cmp r3, #1
8004fc2: bf14 ite ne
8004fc4: 2301 movne r3, #1
8004fc6: 2300 moveq r3, #0
8004fc8: b2db uxtb r3, r3
8004fca: e008 b.n 8004fde <HAL_TIM_PWM_Start+0x9e>
8004fcc: 687b ldr r3, [r7, #4]
8004fce: f893 3043 ldrb.w r3, [r3, #67] @ 0x43
8004fd2: b2db uxtb r3, r3
8004fd4: 2b01 cmp r3, #1
8004fd6: bf14 ite ne
8004fd8: 2301 movne r3, #1
8004fda: 2300 moveq r3, #0
8004fdc: b2db uxtb r3, r3
8004fde: 2b00 cmp r3, #0
8004fe0: d001 beq.n 8004fe6 <HAL_TIM_PWM_Start+0xa6>
{
return HAL_ERROR;
8004fe2: 2301 movs r3, #1
8004fe4: e097 b.n 8005116 <HAL_TIM_PWM_Start+0x1d6>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8004fe6: 683b ldr r3, [r7, #0]
8004fe8: 2b00 cmp r3, #0
8004fea: d104 bne.n 8004ff6 <HAL_TIM_PWM_Start+0xb6>
8004fec: 687b ldr r3, [r7, #4]
8004fee: 2202 movs r2, #2
8004ff0: f883 203e strb.w r2, [r3, #62] @ 0x3e
8004ff4: e023 b.n 800503e <HAL_TIM_PWM_Start+0xfe>
8004ff6: 683b ldr r3, [r7, #0]
8004ff8: 2b04 cmp r3, #4
8004ffa: d104 bne.n 8005006 <HAL_TIM_PWM_Start+0xc6>
8004ffc: 687b ldr r3, [r7, #4]
8004ffe: 2202 movs r2, #2
8005000: f883 203f strb.w r2, [r3, #63] @ 0x3f
8005004: e01b b.n 800503e <HAL_TIM_PWM_Start+0xfe>
8005006: 683b ldr r3, [r7, #0]
8005008: 2b08 cmp r3, #8
800500a: d104 bne.n 8005016 <HAL_TIM_PWM_Start+0xd6>
800500c: 687b ldr r3, [r7, #4]
800500e: 2202 movs r2, #2
8005010: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005014: e013 b.n 800503e <HAL_TIM_PWM_Start+0xfe>
8005016: 683b ldr r3, [r7, #0]
8005018: 2b0c cmp r3, #12
800501a: d104 bne.n 8005026 <HAL_TIM_PWM_Start+0xe6>
800501c: 687b ldr r3, [r7, #4]
800501e: 2202 movs r2, #2
8005020: f883 2041 strb.w r2, [r3, #65] @ 0x41
8005024: e00b b.n 800503e <HAL_TIM_PWM_Start+0xfe>
8005026: 683b ldr r3, [r7, #0]
8005028: 2b10 cmp r3, #16
800502a: d104 bne.n 8005036 <HAL_TIM_PWM_Start+0xf6>
800502c: 687b ldr r3, [r7, #4]
800502e: 2202 movs r2, #2
8005030: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005034: e003 b.n 800503e <HAL_TIM_PWM_Start+0xfe>
8005036: 687b ldr r3, [r7, #4]
8005038: 2202 movs r2, #2
800503a: f883 2043 strb.w r2, [r3, #67] @ 0x43
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
800503e: 687b ldr r3, [r7, #4]
8005040: 681b ldr r3, [r3, #0]
8005042: 2201 movs r2, #1
8005044: 6839 ldr r1, [r7, #0]
8005046: 4618 mov r0, r3
8005048: f001 f838 bl 80060bc <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
800504c: 687b ldr r3, [r7, #4]
800504e: 681b ldr r3, [r3, #0]
8005050: 4a33 ldr r2, [pc, #204] @ (8005120 <HAL_TIM_PWM_Start+0x1e0>)
8005052: 4293 cmp r3, r2
8005054: d013 beq.n 800507e <HAL_TIM_PWM_Start+0x13e>
8005056: 687b ldr r3, [r7, #4]
8005058: 681b ldr r3, [r3, #0]
800505a: 4a32 ldr r2, [pc, #200] @ (8005124 <HAL_TIM_PWM_Start+0x1e4>)
800505c: 4293 cmp r3, r2
800505e: d00e beq.n 800507e <HAL_TIM_PWM_Start+0x13e>
8005060: 687b ldr r3, [r7, #4]
8005062: 681b ldr r3, [r3, #0]
8005064: 4a30 ldr r2, [pc, #192] @ (8005128 <HAL_TIM_PWM_Start+0x1e8>)
8005066: 4293 cmp r3, r2
8005068: d009 beq.n 800507e <HAL_TIM_PWM_Start+0x13e>
800506a: 687b ldr r3, [r7, #4]
800506c: 681b ldr r3, [r3, #0]
800506e: 4a2f ldr r2, [pc, #188] @ (800512c <HAL_TIM_PWM_Start+0x1ec>)
8005070: 4293 cmp r3, r2
8005072: d004 beq.n 800507e <HAL_TIM_PWM_Start+0x13e>
8005074: 687b ldr r3, [r7, #4]
8005076: 681b ldr r3, [r3, #0]
8005078: 4a2d ldr r2, [pc, #180] @ (8005130 <HAL_TIM_PWM_Start+0x1f0>)
800507a: 4293 cmp r3, r2
800507c: d101 bne.n 8005082 <HAL_TIM_PWM_Start+0x142>
800507e: 2301 movs r3, #1
8005080: e000 b.n 8005084 <HAL_TIM_PWM_Start+0x144>
8005082: 2300 movs r3, #0
8005084: 2b00 cmp r3, #0
8005086: d007 beq.n 8005098 <HAL_TIM_PWM_Start+0x158>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8005088: 687b ldr r3, [r7, #4]
800508a: 681b ldr r3, [r3, #0]
800508c: 6c5a ldr r2, [r3, #68] @ 0x44
800508e: 687b ldr r3, [r7, #4]
8005090: 681b ldr r3, [r3, #0]
8005092: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8005096: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005098: 687b ldr r3, [r7, #4]
800509a: 681b ldr r3, [r3, #0]
800509c: 4a20 ldr r2, [pc, #128] @ (8005120 <HAL_TIM_PWM_Start+0x1e0>)
800509e: 4293 cmp r3, r2
80050a0: d018 beq.n 80050d4 <HAL_TIM_PWM_Start+0x194>
80050a2: 687b ldr r3, [r7, #4]
80050a4: 681b ldr r3, [r3, #0]
80050a6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80050aa: d013 beq.n 80050d4 <HAL_TIM_PWM_Start+0x194>
80050ac: 687b ldr r3, [r7, #4]
80050ae: 681b ldr r3, [r3, #0]
80050b0: 4a20 ldr r2, [pc, #128] @ (8005134 <HAL_TIM_PWM_Start+0x1f4>)
80050b2: 4293 cmp r3, r2
80050b4: d00e beq.n 80050d4 <HAL_TIM_PWM_Start+0x194>
80050b6: 687b ldr r3, [r7, #4]
80050b8: 681b ldr r3, [r3, #0]
80050ba: 4a1f ldr r2, [pc, #124] @ (8005138 <HAL_TIM_PWM_Start+0x1f8>)
80050bc: 4293 cmp r3, r2
80050be: d009 beq.n 80050d4 <HAL_TIM_PWM_Start+0x194>
80050c0: 687b ldr r3, [r7, #4]
80050c2: 681b ldr r3, [r3, #0]
80050c4: 4a17 ldr r2, [pc, #92] @ (8005124 <HAL_TIM_PWM_Start+0x1e4>)
80050c6: 4293 cmp r3, r2
80050c8: d004 beq.n 80050d4 <HAL_TIM_PWM_Start+0x194>
80050ca: 687b ldr r3, [r7, #4]
80050cc: 681b ldr r3, [r3, #0]
80050ce: 4a16 ldr r2, [pc, #88] @ (8005128 <HAL_TIM_PWM_Start+0x1e8>)
80050d0: 4293 cmp r3, r2
80050d2: d115 bne.n 8005100 <HAL_TIM_PWM_Start+0x1c0>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80050d4: 687b ldr r3, [r7, #4]
80050d6: 681b ldr r3, [r3, #0]
80050d8: 689a ldr r2, [r3, #8]
80050da: 4b18 ldr r3, [pc, #96] @ (800513c <HAL_TIM_PWM_Start+0x1fc>)
80050dc: 4013 ands r3, r2
80050de: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80050e0: 68fb ldr r3, [r7, #12]
80050e2: 2b06 cmp r3, #6
80050e4: d015 beq.n 8005112 <HAL_TIM_PWM_Start+0x1d2>
80050e6: 68fb ldr r3, [r7, #12]
80050e8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80050ec: d011 beq.n 8005112 <HAL_TIM_PWM_Start+0x1d2>
{
__HAL_TIM_ENABLE(htim);
80050ee: 687b ldr r3, [r7, #4]
80050f0: 681b ldr r3, [r3, #0]
80050f2: 681a ldr r2, [r3, #0]
80050f4: 687b ldr r3, [r7, #4]
80050f6: 681b ldr r3, [r3, #0]
80050f8: f042 0201 orr.w r2, r2, #1
80050fc: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80050fe: e008 b.n 8005112 <HAL_TIM_PWM_Start+0x1d2>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8005100: 687b ldr r3, [r7, #4]
8005102: 681b ldr r3, [r3, #0]
8005104: 681a ldr r2, [r3, #0]
8005106: 687b ldr r3, [r7, #4]
8005108: 681b ldr r3, [r3, #0]
800510a: f042 0201 orr.w r2, r2, #1
800510e: 601a str r2, [r3, #0]
8005110: e000 b.n 8005114 <HAL_TIM_PWM_Start+0x1d4>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8005112: bf00 nop
}
/* Return function status */
return HAL_OK;
8005114: 2300 movs r3, #0
}
8005116: 4618 mov r0, r3
8005118: 3710 adds r7, #16
800511a: 46bd mov sp, r7
800511c: bd80 pop {r7, pc}
800511e: bf00 nop
8005120: 40012c00 .word 0x40012c00
8005124: 40013400 .word 0x40013400
8005128: 40014000 .word 0x40014000
800512c: 40014400 .word 0x40014400
8005130: 40014800 .word 0x40014800
8005134: 40000400 .word 0x40000400
8005138: 40000800 .word 0x40000800
800513c: 00010007 .word 0x00010007
08005140 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8005140: b580 push {r7, lr}
8005142: b084 sub sp, #16
8005144: af00 add r7, sp, #0
8005146: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8005148: 687b ldr r3, [r7, #4]
800514a: 681b ldr r3, [r3, #0]
800514c: 68db ldr r3, [r3, #12]
800514e: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8005150: 687b ldr r3, [r7, #4]
8005152: 681b ldr r3, [r3, #0]
8005154: 691b ldr r3, [r3, #16]
8005156: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8005158: 68bb ldr r3, [r7, #8]
800515a: f003 0302 and.w r3, r3, #2
800515e: 2b00 cmp r3, #0
8005160: d020 beq.n 80051a4 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8005162: 68fb ldr r3, [r7, #12]
8005164: f003 0302 and.w r3, r3, #2
8005168: 2b00 cmp r3, #0
800516a: d01b beq.n 80051a4 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
800516c: 687b ldr r3, [r7, #4]
800516e: 681b ldr r3, [r3, #0]
8005170: f06f 0202 mvn.w r2, #2
8005174: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8005176: 687b ldr r3, [r7, #4]
8005178: 2201 movs r2, #1
800517a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
800517c: 687b ldr r3, [r7, #4]
800517e: 681b ldr r3, [r3, #0]
8005180: 699b ldr r3, [r3, #24]
8005182: f003 0303 and.w r3, r3, #3
8005186: 2b00 cmp r3, #0
8005188: d003 beq.n 8005192 <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800518a: 6878 ldr r0, [r7, #4]
800518c: f000 fb4a bl 8005824 <HAL_TIM_IC_CaptureCallback>
8005190: e005 b.n 800519e <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005192: 6878 ldr r0, [r7, #4]
8005194: f000 fb3c bl 8005810 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005198: 6878 ldr r0, [r7, #4]
800519a: f000 fb4d bl 8005838 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800519e: 687b ldr r3, [r7, #4]
80051a0: 2200 movs r2, #0
80051a2: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
80051a4: 68bb ldr r3, [r7, #8]
80051a6: f003 0304 and.w r3, r3, #4
80051aa: 2b00 cmp r3, #0
80051ac: d020 beq.n 80051f0 <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
80051ae: 68fb ldr r3, [r7, #12]
80051b0: f003 0304 and.w r3, r3, #4
80051b4: 2b00 cmp r3, #0
80051b6: d01b beq.n 80051f0 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
80051b8: 687b ldr r3, [r7, #4]
80051ba: 681b ldr r3, [r3, #0]
80051bc: f06f 0204 mvn.w r2, #4
80051c0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80051c2: 687b ldr r3, [r7, #4]
80051c4: 2202 movs r2, #2
80051c6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80051c8: 687b ldr r3, [r7, #4]
80051ca: 681b ldr r3, [r3, #0]
80051cc: 699b ldr r3, [r3, #24]
80051ce: f403 7340 and.w r3, r3, #768 @ 0x300
80051d2: 2b00 cmp r3, #0
80051d4: d003 beq.n 80051de <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80051d6: 6878 ldr r0, [r7, #4]
80051d8: f000 fb24 bl 8005824 <HAL_TIM_IC_CaptureCallback>
80051dc: e005 b.n 80051ea <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80051de: 6878 ldr r0, [r7, #4]
80051e0: f000 fb16 bl 8005810 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80051e4: 6878 ldr r0, [r7, #4]
80051e6: f000 fb27 bl 8005838 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80051ea: 687b ldr r3, [r7, #4]
80051ec: 2200 movs r2, #0
80051ee: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80051f0: 68bb ldr r3, [r7, #8]
80051f2: f003 0308 and.w r3, r3, #8
80051f6: 2b00 cmp r3, #0
80051f8: d020 beq.n 800523c <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80051fa: 68fb ldr r3, [r7, #12]
80051fc: f003 0308 and.w r3, r3, #8
8005200: 2b00 cmp r3, #0
8005202: d01b beq.n 800523c <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8005204: 687b ldr r3, [r7, #4]
8005206: 681b ldr r3, [r3, #0]
8005208: f06f 0208 mvn.w r2, #8
800520c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
800520e: 687b ldr r3, [r7, #4]
8005210: 2204 movs r2, #4
8005212: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8005214: 687b ldr r3, [r7, #4]
8005216: 681b ldr r3, [r3, #0]
8005218: 69db ldr r3, [r3, #28]
800521a: f003 0303 and.w r3, r3, #3
800521e: 2b00 cmp r3, #0
8005220: d003 beq.n 800522a <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005222: 6878 ldr r0, [r7, #4]
8005224: f000 fafe bl 8005824 <HAL_TIM_IC_CaptureCallback>
8005228: e005 b.n 8005236 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800522a: 6878 ldr r0, [r7, #4]
800522c: f000 faf0 bl 8005810 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005230: 6878 ldr r0, [r7, #4]
8005232: f000 fb01 bl 8005838 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8005236: 687b ldr r3, [r7, #4]
8005238: 2200 movs r2, #0
800523a: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
800523c: 68bb ldr r3, [r7, #8]
800523e: f003 0310 and.w r3, r3, #16
8005242: 2b00 cmp r3, #0
8005244: d020 beq.n 8005288 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8005246: 68fb ldr r3, [r7, #12]
8005248: f003 0310 and.w r3, r3, #16
800524c: 2b00 cmp r3, #0
800524e: d01b beq.n 8005288 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8005250: 687b ldr r3, [r7, #4]
8005252: 681b ldr r3, [r3, #0]
8005254: f06f 0210 mvn.w r2, #16
8005258: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
800525a: 687b ldr r3, [r7, #4]
800525c: 2208 movs r2, #8
800525e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8005260: 687b ldr r3, [r7, #4]
8005262: 681b ldr r3, [r3, #0]
8005264: 69db ldr r3, [r3, #28]
8005266: f403 7340 and.w r3, r3, #768 @ 0x300
800526a: 2b00 cmp r3, #0
800526c: d003 beq.n 8005276 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800526e: 6878 ldr r0, [r7, #4]
8005270: f000 fad8 bl 8005824 <HAL_TIM_IC_CaptureCallback>
8005274: e005 b.n 8005282 <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005276: 6878 ldr r0, [r7, #4]
8005278: f000 faca bl 8005810 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800527c: 6878 ldr r0, [r7, #4]
800527e: f000 fadb bl 8005838 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8005282: 687b ldr r3, [r7, #4]
8005284: 2200 movs r2, #0
8005286: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8005288: 68bb ldr r3, [r7, #8]
800528a: f003 0301 and.w r3, r3, #1
800528e: 2b00 cmp r3, #0
8005290: d00c beq.n 80052ac <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8005292: 68fb ldr r3, [r7, #12]
8005294: f003 0301 and.w r3, r3, #1
8005298: 2b00 cmp r3, #0
800529a: d007 beq.n 80052ac <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
800529c: 687b ldr r3, [r7, #4]
800529e: 681b ldr r3, [r3, #0]
80052a0: f06f 0201 mvn.w r2, #1
80052a4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
80052a6: 6878 ldr r0, [r7, #4]
80052a8: f000 faa8 bl 80057fc <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
80052ac: 68bb ldr r3, [r7, #8]
80052ae: f003 0380 and.w r3, r3, #128 @ 0x80
80052b2: 2b00 cmp r3, #0
80052b4: d104 bne.n 80052c0 <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
80052b6: 68bb ldr r3, [r7, #8]
80052b8: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
80052bc: 2b00 cmp r3, #0
80052be: d00c beq.n 80052da <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80052c0: 68fb ldr r3, [r7, #12]
80052c2: f003 0380 and.w r3, r3, #128 @ 0x80
80052c6: 2b00 cmp r3, #0
80052c8: d007 beq.n 80052da <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
80052ca: 687b ldr r3, [r7, #4]
80052cc: 681b ldr r3, [r3, #0]
80052ce: f46f 5202 mvn.w r2, #8320 @ 0x2080
80052d2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80052d4: 6878 ldr r0, [r7, #4]
80052d6: f001 f82f bl 8006338 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
80052da: 68bb ldr r3, [r7, #8]
80052dc: f403 7380 and.w r3, r3, #256 @ 0x100
80052e0: 2b00 cmp r3, #0
80052e2: d00c beq.n 80052fe <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80052e4: 68fb ldr r3, [r7, #12]
80052e6: f003 0380 and.w r3, r3, #128 @ 0x80
80052ea: 2b00 cmp r3, #0
80052ec: d007 beq.n 80052fe <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
80052ee: 687b ldr r3, [r7, #4]
80052f0: 681b ldr r3, [r3, #0]
80052f2: f46f 7280 mvn.w r2, #256 @ 0x100
80052f6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
80052f8: 6878 ldr r0, [r7, #4]
80052fa: f001 f827 bl 800634c <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80052fe: 68bb ldr r3, [r7, #8]
8005300: f003 0340 and.w r3, r3, #64 @ 0x40
8005304: 2b00 cmp r3, #0
8005306: d00c beq.n 8005322 <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8005308: 68fb ldr r3, [r7, #12]
800530a: f003 0340 and.w r3, r3, #64 @ 0x40
800530e: 2b00 cmp r3, #0
8005310: d007 beq.n 8005322 <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8005312: 687b ldr r3, [r7, #4]
8005314: 681b ldr r3, [r3, #0]
8005316: f06f 0240 mvn.w r2, #64 @ 0x40
800531a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
800531c: 6878 ldr r0, [r7, #4]
800531e: f000 fa95 bl 800584c <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8005322: 68bb ldr r3, [r7, #8]
8005324: f003 0320 and.w r3, r3, #32
8005328: 2b00 cmp r3, #0
800532a: d00c beq.n 8005346 <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
800532c: 68fb ldr r3, [r7, #12]
800532e: f003 0320 and.w r3, r3, #32
8005332: 2b00 cmp r3, #0
8005334: d007 beq.n 8005346 <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8005336: 687b ldr r3, [r7, #4]
8005338: 681b ldr r3, [r3, #0]
800533a: f06f 0220 mvn.w r2, #32
800533e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8005340: 6878 ldr r0, [r7, #4]
8005342: f000 ffef bl 8006324 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Encoder index event */
if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
8005346: 68bb ldr r3, [r7, #8]
8005348: f403 1380 and.w r3, r3, #1048576 @ 0x100000
800534c: 2b00 cmp r3, #0
800534e: d00c beq.n 800536a <HAL_TIM_IRQHandler+0x22a>
{
if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
8005350: 68fb ldr r3, [r7, #12]
8005352: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8005356: 2b00 cmp r3, #0
8005358: d007 beq.n 800536a <HAL_TIM_IRQHandler+0x22a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
800535a: 687b ldr r3, [r7, #4]
800535c: 681b ldr r3, [r3, #0]
800535e: f46f 1280 mvn.w r2, #1048576 @ 0x100000
8005362: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->EncoderIndexCallback(htim);
#else
HAL_TIMEx_EncoderIndexCallback(htim);
8005364: 6878 ldr r0, [r7, #4]
8005366: f000 fffb bl 8006360 <HAL_TIMEx_EncoderIndexCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Direction change event */
if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
800536a: 68bb ldr r3, [r7, #8]
800536c: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8005370: 2b00 cmp r3, #0
8005372: d00c beq.n 800538e <HAL_TIM_IRQHandler+0x24e>
{
if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
8005374: 68fb ldr r3, [r7, #12]
8005376: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800537a: 2b00 cmp r3, #0
800537c: d007 beq.n 800538e <HAL_TIM_IRQHandler+0x24e>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
800537e: 687b ldr r3, [r7, #4]
8005380: 681b ldr r3, [r3, #0]
8005382: f46f 1200 mvn.w r2, #2097152 @ 0x200000
8005386: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->DirectionChangeCallback(htim);
#else
HAL_TIMEx_DirectionChangeCallback(htim);
8005388: 6878 ldr r0, [r7, #4]
800538a: f000 fff3 bl 8006374 <HAL_TIMEx_DirectionChangeCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Index error event */
if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
800538e: 68bb ldr r3, [r7, #8]
8005390: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8005394: 2b00 cmp r3, #0
8005396: d00c beq.n 80053b2 <HAL_TIM_IRQHandler+0x272>
{
if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
8005398: 68fb ldr r3, [r7, #12]
800539a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800539e: 2b00 cmp r3, #0
80053a0: d007 beq.n 80053b2 <HAL_TIM_IRQHandler+0x272>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
80053a2: 687b ldr r3, [r7, #4]
80053a4: 681b ldr r3, [r3, #0]
80053a6: f46f 0280 mvn.w r2, #4194304 @ 0x400000
80053aa: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IndexErrorCallback(htim);
#else
HAL_TIMEx_IndexErrorCallback(htim);
80053ac: 6878 ldr r0, [r7, #4]
80053ae: f000 ffeb bl 8006388 <HAL_TIMEx_IndexErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Transition error event */
if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
80053b2: 68bb ldr r3, [r7, #8]
80053b4: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80053b8: 2b00 cmp r3, #0
80053ba: d00c beq.n 80053d6 <HAL_TIM_IRQHandler+0x296>
{
if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
80053bc: 68fb ldr r3, [r7, #12]
80053be: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80053c2: 2b00 cmp r3, #0
80053c4: d007 beq.n 80053d6 <HAL_TIM_IRQHandler+0x296>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
80053c6: 687b ldr r3, [r7, #4]
80053c8: 681b ldr r3, [r3, #0]
80053ca: f46f 0200 mvn.w r2, #8388608 @ 0x800000
80053ce: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TransitionErrorCallback(htim);
#else
HAL_TIMEx_TransitionErrorCallback(htim);
80053d0: 6878 ldr r0, [r7, #4]
80053d2: f000 ffe3 bl 800639c <HAL_TIMEx_TransitionErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
80053d6: bf00 nop
80053d8: 3710 adds r7, #16
80053da: 46bd mov sp, r7
80053dc: bd80 pop {r7, pc}
...
080053e0 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
80053e0: b580 push {r7, lr}
80053e2: b086 sub sp, #24
80053e4: af00 add r7, sp, #0
80053e6: 60f8 str r0, [r7, #12]
80053e8: 60b9 str r1, [r7, #8]
80053ea: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80053ec: 2300 movs r3, #0
80053ee: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
80053f0: 68fb ldr r3, [r7, #12]
80053f2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80053f6: 2b01 cmp r3, #1
80053f8: d101 bne.n 80053fe <HAL_TIM_PWM_ConfigChannel+0x1e>
80053fa: 2302 movs r3, #2
80053fc: e0ff b.n 80055fe <HAL_TIM_PWM_ConfigChannel+0x21e>
80053fe: 68fb ldr r3, [r7, #12]
8005400: 2201 movs r2, #1
8005402: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8005406: 687b ldr r3, [r7, #4]
8005408: 2b14 cmp r3, #20
800540a: f200 80f0 bhi.w 80055ee <HAL_TIM_PWM_ConfigChannel+0x20e>
800540e: a201 add r2, pc, #4 @ (adr r2, 8005414 <HAL_TIM_PWM_ConfigChannel+0x34>)
8005410: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005414: 08005469 .word 0x08005469
8005418: 080055ef .word 0x080055ef
800541c: 080055ef .word 0x080055ef
8005420: 080055ef .word 0x080055ef
8005424: 080054a9 .word 0x080054a9
8005428: 080055ef .word 0x080055ef
800542c: 080055ef .word 0x080055ef
8005430: 080055ef .word 0x080055ef
8005434: 080054eb .word 0x080054eb
8005438: 080055ef .word 0x080055ef
800543c: 080055ef .word 0x080055ef
8005440: 080055ef .word 0x080055ef
8005444: 0800552b .word 0x0800552b
8005448: 080055ef .word 0x080055ef
800544c: 080055ef .word 0x080055ef
8005450: 080055ef .word 0x080055ef
8005454: 0800556d .word 0x0800556d
8005458: 080055ef .word 0x080055ef
800545c: 080055ef .word 0x080055ef
8005460: 080055ef .word 0x080055ef
8005464: 080055ad .word 0x080055ad
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8005468: 68fb ldr r3, [r7, #12]
800546a: 681b ldr r3, [r3, #0]
800546c: 68b9 ldr r1, [r7, #8]
800546e: 4618 mov r0, r3
8005470: f000 fa92 bl 8005998 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8005474: 68fb ldr r3, [r7, #12]
8005476: 681b ldr r3, [r3, #0]
8005478: 699a ldr r2, [r3, #24]
800547a: 68fb ldr r3, [r7, #12]
800547c: 681b ldr r3, [r3, #0]
800547e: f042 0208 orr.w r2, r2, #8
8005482: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8005484: 68fb ldr r3, [r7, #12]
8005486: 681b ldr r3, [r3, #0]
8005488: 699a ldr r2, [r3, #24]
800548a: 68fb ldr r3, [r7, #12]
800548c: 681b ldr r3, [r3, #0]
800548e: f022 0204 bic.w r2, r2, #4
8005492: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8005494: 68fb ldr r3, [r7, #12]
8005496: 681b ldr r3, [r3, #0]
8005498: 6999 ldr r1, [r3, #24]
800549a: 68bb ldr r3, [r7, #8]
800549c: 691a ldr r2, [r3, #16]
800549e: 68fb ldr r3, [r7, #12]
80054a0: 681b ldr r3, [r3, #0]
80054a2: 430a orrs r2, r1
80054a4: 619a str r2, [r3, #24]
break;
80054a6: e0a5 b.n 80055f4 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
80054a8: 68fb ldr r3, [r7, #12]
80054aa: 681b ldr r3, [r3, #0]
80054ac: 68b9 ldr r1, [r7, #8]
80054ae: 4618 mov r0, r3
80054b0: f000 fb02 bl 8005ab8 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
80054b4: 68fb ldr r3, [r7, #12]
80054b6: 681b ldr r3, [r3, #0]
80054b8: 699a ldr r2, [r3, #24]
80054ba: 68fb ldr r3, [r7, #12]
80054bc: 681b ldr r3, [r3, #0]
80054be: f442 6200 orr.w r2, r2, #2048 @ 0x800
80054c2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
80054c4: 68fb ldr r3, [r7, #12]
80054c6: 681b ldr r3, [r3, #0]
80054c8: 699a ldr r2, [r3, #24]
80054ca: 68fb ldr r3, [r7, #12]
80054cc: 681b ldr r3, [r3, #0]
80054ce: f422 6280 bic.w r2, r2, #1024 @ 0x400
80054d2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80054d4: 68fb ldr r3, [r7, #12]
80054d6: 681b ldr r3, [r3, #0]
80054d8: 6999 ldr r1, [r3, #24]
80054da: 68bb ldr r3, [r7, #8]
80054dc: 691b ldr r3, [r3, #16]
80054de: 021a lsls r2, r3, #8
80054e0: 68fb ldr r3, [r7, #12]
80054e2: 681b ldr r3, [r3, #0]
80054e4: 430a orrs r2, r1
80054e6: 619a str r2, [r3, #24]
break;
80054e8: e084 b.n 80055f4 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80054ea: 68fb ldr r3, [r7, #12]
80054ec: 681b ldr r3, [r3, #0]
80054ee: 68b9 ldr r1, [r7, #8]
80054f0: 4618 mov r0, r3
80054f2: f000 fb6b bl 8005bcc <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
80054f6: 68fb ldr r3, [r7, #12]
80054f8: 681b ldr r3, [r3, #0]
80054fa: 69da ldr r2, [r3, #28]
80054fc: 68fb ldr r3, [r7, #12]
80054fe: 681b ldr r3, [r3, #0]
8005500: f042 0208 orr.w r2, r2, #8
8005504: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8005506: 68fb ldr r3, [r7, #12]
8005508: 681b ldr r3, [r3, #0]
800550a: 69da ldr r2, [r3, #28]
800550c: 68fb ldr r3, [r7, #12]
800550e: 681b ldr r3, [r3, #0]
8005510: f022 0204 bic.w r2, r2, #4
8005514: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8005516: 68fb ldr r3, [r7, #12]
8005518: 681b ldr r3, [r3, #0]
800551a: 69d9 ldr r1, [r3, #28]
800551c: 68bb ldr r3, [r7, #8]
800551e: 691a ldr r2, [r3, #16]
8005520: 68fb ldr r3, [r7, #12]
8005522: 681b ldr r3, [r3, #0]
8005524: 430a orrs r2, r1
8005526: 61da str r2, [r3, #28]
break;
8005528: e064 b.n 80055f4 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800552a: 68fb ldr r3, [r7, #12]
800552c: 681b ldr r3, [r3, #0]
800552e: 68b9 ldr r1, [r7, #8]
8005530: 4618 mov r0, r3
8005532: f000 fbd3 bl 8005cdc <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8005536: 68fb ldr r3, [r7, #12]
8005538: 681b ldr r3, [r3, #0]
800553a: 69da ldr r2, [r3, #28]
800553c: 68fb ldr r3, [r7, #12]
800553e: 681b ldr r3, [r3, #0]
8005540: f442 6200 orr.w r2, r2, #2048 @ 0x800
8005544: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8005546: 68fb ldr r3, [r7, #12]
8005548: 681b ldr r3, [r3, #0]
800554a: 69da ldr r2, [r3, #28]
800554c: 68fb ldr r3, [r7, #12]
800554e: 681b ldr r3, [r3, #0]
8005550: f422 6280 bic.w r2, r2, #1024 @ 0x400
8005554: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8005556: 68fb ldr r3, [r7, #12]
8005558: 681b ldr r3, [r3, #0]
800555a: 69d9 ldr r1, [r3, #28]
800555c: 68bb ldr r3, [r7, #8]
800555e: 691b ldr r3, [r3, #16]
8005560: 021a lsls r2, r3, #8
8005562: 68fb ldr r3, [r7, #12]
8005564: 681b ldr r3, [r3, #0]
8005566: 430a orrs r2, r1
8005568: 61da str r2, [r3, #28]
break;
800556a: e043 b.n 80055f4 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
800556c: 68fb ldr r3, [r7, #12]
800556e: 681b ldr r3, [r3, #0]
8005570: 68b9 ldr r1, [r7, #8]
8005572: 4618 mov r0, r3
8005574: f000 fc3c bl 8005df0 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8005578: 68fb ldr r3, [r7, #12]
800557a: 681b ldr r3, [r3, #0]
800557c: 6d1a ldr r2, [r3, #80] @ 0x50
800557e: 68fb ldr r3, [r7, #12]
8005580: 681b ldr r3, [r3, #0]
8005582: f042 0208 orr.w r2, r2, #8
8005586: 651a str r2, [r3, #80] @ 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8005588: 68fb ldr r3, [r7, #12]
800558a: 681b ldr r3, [r3, #0]
800558c: 6d1a ldr r2, [r3, #80] @ 0x50
800558e: 68fb ldr r3, [r7, #12]
8005590: 681b ldr r3, [r3, #0]
8005592: f022 0204 bic.w r2, r2, #4
8005596: 651a str r2, [r3, #80] @ 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8005598: 68fb ldr r3, [r7, #12]
800559a: 681b ldr r3, [r3, #0]
800559c: 6d19 ldr r1, [r3, #80] @ 0x50
800559e: 68bb ldr r3, [r7, #8]
80055a0: 691a ldr r2, [r3, #16]
80055a2: 68fb ldr r3, [r7, #12]
80055a4: 681b ldr r3, [r3, #0]
80055a6: 430a orrs r2, r1
80055a8: 651a str r2, [r3, #80] @ 0x50
break;
80055aa: e023 b.n 80055f4 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
80055ac: 68fb ldr r3, [r7, #12]
80055ae: 681b ldr r3, [r3, #0]
80055b0: 68b9 ldr r1, [r7, #8]
80055b2: 4618 mov r0, r3
80055b4: f000 fc80 bl 8005eb8 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
80055b8: 68fb ldr r3, [r7, #12]
80055ba: 681b ldr r3, [r3, #0]
80055bc: 6d1a ldr r2, [r3, #80] @ 0x50
80055be: 68fb ldr r3, [r7, #12]
80055c0: 681b ldr r3, [r3, #0]
80055c2: f442 6200 orr.w r2, r2, #2048 @ 0x800
80055c6: 651a str r2, [r3, #80] @ 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
80055c8: 68fb ldr r3, [r7, #12]
80055ca: 681b ldr r3, [r3, #0]
80055cc: 6d1a ldr r2, [r3, #80] @ 0x50
80055ce: 68fb ldr r3, [r7, #12]
80055d0: 681b ldr r3, [r3, #0]
80055d2: f422 6280 bic.w r2, r2, #1024 @ 0x400
80055d6: 651a str r2, [r3, #80] @ 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
80055d8: 68fb ldr r3, [r7, #12]
80055da: 681b ldr r3, [r3, #0]
80055dc: 6d19 ldr r1, [r3, #80] @ 0x50
80055de: 68bb ldr r3, [r7, #8]
80055e0: 691b ldr r3, [r3, #16]
80055e2: 021a lsls r2, r3, #8
80055e4: 68fb ldr r3, [r7, #12]
80055e6: 681b ldr r3, [r3, #0]
80055e8: 430a orrs r2, r1
80055ea: 651a str r2, [r3, #80] @ 0x50
break;
80055ec: e002 b.n 80055f4 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
80055ee: 2301 movs r3, #1
80055f0: 75fb strb r3, [r7, #23]
break;
80055f2: bf00 nop
}
__HAL_UNLOCK(htim);
80055f4: 68fb ldr r3, [r7, #12]
80055f6: 2200 movs r2, #0
80055f8: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80055fc: 7dfb ldrb r3, [r7, #23]
}
80055fe: 4618 mov r0, r3
8005600: 3718 adds r7, #24
8005602: 46bd mov sp, r7
8005604: bd80 pop {r7, pc}
8005606: bf00 nop
08005608 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8005608: b580 push {r7, lr}
800560a: b084 sub sp, #16
800560c: af00 add r7, sp, #0
800560e: 6078 str r0, [r7, #4]
8005610: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8005612: 2300 movs r3, #0
8005614: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8005616: 687b ldr r3, [r7, #4]
8005618: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800561c: 2b01 cmp r3, #1
800561e: d101 bne.n 8005624 <HAL_TIM_ConfigClockSource+0x1c>
8005620: 2302 movs r3, #2
8005622: e0de b.n 80057e2 <HAL_TIM_ConfigClockSource+0x1da>
8005624: 687b ldr r3, [r7, #4]
8005626: 2201 movs r2, #1
8005628: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800562c: 687b ldr r3, [r7, #4]
800562e: 2202 movs r2, #2
8005630: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8005634: 687b ldr r3, [r7, #4]
8005636: 681b ldr r3, [r3, #0]
8005638: 689b ldr r3, [r3, #8]
800563a: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
800563c: 68bb ldr r3, [r7, #8]
800563e: f423 1344 bic.w r3, r3, #3211264 @ 0x310000
8005642: f023 0377 bic.w r3, r3, #119 @ 0x77
8005646: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005648: 68bb ldr r3, [r7, #8]
800564a: f423 437f bic.w r3, r3, #65280 @ 0xff00
800564e: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8005650: 687b ldr r3, [r7, #4]
8005652: 681b ldr r3, [r3, #0]
8005654: 68ba ldr r2, [r7, #8]
8005656: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8005658: 683b ldr r3, [r7, #0]
800565a: 681b ldr r3, [r3, #0]
800565c: 4a63 ldr r2, [pc, #396] @ (80057ec <HAL_TIM_ConfigClockSource+0x1e4>)
800565e: 4293 cmp r3, r2
8005660: f000 80a9 beq.w 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
8005664: 4a61 ldr r2, [pc, #388] @ (80057ec <HAL_TIM_ConfigClockSource+0x1e4>)
8005666: 4293 cmp r3, r2
8005668: f200 80ae bhi.w 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
800566c: 4a60 ldr r2, [pc, #384] @ (80057f0 <HAL_TIM_ConfigClockSource+0x1e8>)
800566e: 4293 cmp r3, r2
8005670: f000 80a1 beq.w 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
8005674: 4a5e ldr r2, [pc, #376] @ (80057f0 <HAL_TIM_ConfigClockSource+0x1e8>)
8005676: 4293 cmp r3, r2
8005678: f200 80a6 bhi.w 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
800567c: 4a5d ldr r2, [pc, #372] @ (80057f4 <HAL_TIM_ConfigClockSource+0x1ec>)
800567e: 4293 cmp r3, r2
8005680: f000 8099 beq.w 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
8005684: 4a5b ldr r2, [pc, #364] @ (80057f4 <HAL_TIM_ConfigClockSource+0x1ec>)
8005686: 4293 cmp r3, r2
8005688: f200 809e bhi.w 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
800568c: 4a5a ldr r2, [pc, #360] @ (80057f8 <HAL_TIM_ConfigClockSource+0x1f0>)
800568e: 4293 cmp r3, r2
8005690: f000 8091 beq.w 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
8005694: 4a58 ldr r2, [pc, #352] @ (80057f8 <HAL_TIM_ConfigClockSource+0x1f0>)
8005696: 4293 cmp r3, r2
8005698: f200 8096 bhi.w 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
800569c: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
80056a0: f000 8089 beq.w 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
80056a4: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
80056a8: f200 808e bhi.w 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056ac: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80056b0: d03e beq.n 8005730 <HAL_TIM_ConfigClockSource+0x128>
80056b2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80056b6: f200 8087 bhi.w 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056ba: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80056be: f000 8086 beq.w 80057ce <HAL_TIM_ConfigClockSource+0x1c6>
80056c2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80056c6: d87f bhi.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056c8: 2b70 cmp r3, #112 @ 0x70
80056ca: d01a beq.n 8005702 <HAL_TIM_ConfigClockSource+0xfa>
80056cc: 2b70 cmp r3, #112 @ 0x70
80056ce: d87b bhi.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056d0: 2b60 cmp r3, #96 @ 0x60
80056d2: d050 beq.n 8005776 <HAL_TIM_ConfigClockSource+0x16e>
80056d4: 2b60 cmp r3, #96 @ 0x60
80056d6: d877 bhi.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056d8: 2b50 cmp r3, #80 @ 0x50
80056da: d03c beq.n 8005756 <HAL_TIM_ConfigClockSource+0x14e>
80056dc: 2b50 cmp r3, #80 @ 0x50
80056de: d873 bhi.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056e0: 2b40 cmp r3, #64 @ 0x40
80056e2: d058 beq.n 8005796 <HAL_TIM_ConfigClockSource+0x18e>
80056e4: 2b40 cmp r3, #64 @ 0x40
80056e6: d86f bhi.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056e8: 2b30 cmp r3, #48 @ 0x30
80056ea: d064 beq.n 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
80056ec: 2b30 cmp r3, #48 @ 0x30
80056ee: d86b bhi.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056f0: 2b20 cmp r3, #32
80056f2: d060 beq.n 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
80056f4: 2b20 cmp r3, #32
80056f6: d867 bhi.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
80056f8: 2b00 cmp r3, #0
80056fa: d05c beq.n 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
80056fc: 2b10 cmp r3, #16
80056fe: d05a beq.n 80057b6 <HAL_TIM_ConfigClockSource+0x1ae>
8005700: e062 b.n 80057c8 <HAL_TIM_ConfigClockSource+0x1c0>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8005702: 687b ldr r3, [r7, #4]
8005704: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8005706: 683b ldr r3, [r7, #0]
8005708: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800570a: 683b ldr r3, [r7, #0]
800570c: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800570e: 683b ldr r3, [r7, #0]
8005710: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8005712: f000 fcb3 bl 800607c <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8005716: 687b ldr r3, [r7, #4]
8005718: 681b ldr r3, [r3, #0]
800571a: 689b ldr r3, [r3, #8]
800571c: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800571e: 68bb ldr r3, [r7, #8]
8005720: f043 0377 orr.w r3, r3, #119 @ 0x77
8005724: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8005726: 687b ldr r3, [r7, #4]
8005728: 681b ldr r3, [r3, #0]
800572a: 68ba ldr r2, [r7, #8]
800572c: 609a str r2, [r3, #8]
break;
800572e: e04f b.n 80057d0 <HAL_TIM_ConfigClockSource+0x1c8>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8005730: 687b ldr r3, [r7, #4]
8005732: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8005734: 683b ldr r3, [r7, #0]
8005736: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8005738: 683b ldr r3, [r7, #0]
800573a: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800573c: 683b ldr r3, [r7, #0]
800573e: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8005740: f000 fc9c bl 800607c <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8005744: 687b ldr r3, [r7, #4]
8005746: 681b ldr r3, [r3, #0]
8005748: 689a ldr r2, [r3, #8]
800574a: 687b ldr r3, [r7, #4]
800574c: 681b ldr r3, [r3, #0]
800574e: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8005752: 609a str r2, [r3, #8]
break;
8005754: e03c b.n 80057d0 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005756: 687b ldr r3, [r7, #4]
8005758: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800575a: 683b ldr r3, [r7, #0]
800575c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800575e: 683b ldr r3, [r7, #0]
8005760: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8005762: 461a mov r2, r3
8005764: f000 fc0e bl 8005f84 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8005768: 687b ldr r3, [r7, #4]
800576a: 681b ldr r3, [r3, #0]
800576c: 2150 movs r1, #80 @ 0x50
800576e: 4618 mov r0, r3
8005770: f000 fc67 bl 8006042 <TIM_ITRx_SetConfig>
break;
8005774: e02c b.n 80057d0 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8005776: 687b ldr r3, [r7, #4]
8005778: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800577a: 683b ldr r3, [r7, #0]
800577c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800577e: 683b ldr r3, [r7, #0]
8005780: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8005782: 461a mov r2, r3
8005784: f000 fc2d bl 8005fe2 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8005788: 687b ldr r3, [r7, #4]
800578a: 681b ldr r3, [r3, #0]
800578c: 2160 movs r1, #96 @ 0x60
800578e: 4618 mov r0, r3
8005790: f000 fc57 bl 8006042 <TIM_ITRx_SetConfig>
break;
8005794: e01c b.n 80057d0 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005796: 687b ldr r3, [r7, #4]
8005798: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800579a: 683b ldr r3, [r7, #0]
800579c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800579e: 683b ldr r3, [r7, #0]
80057a0: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80057a2: 461a mov r2, r3
80057a4: f000 fbee bl 8005f84 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80057a8: 687b ldr r3, [r7, #4]
80057aa: 681b ldr r3, [r3, #0]
80057ac: 2140 movs r1, #64 @ 0x40
80057ae: 4618 mov r0, r3
80057b0: f000 fc47 bl 8006042 <TIM_ITRx_SetConfig>
break;
80057b4: e00c b.n 80057d0 <HAL_TIM_ConfigClockSource+0x1c8>
case TIM_CLOCKSOURCE_ITR11:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80057b6: 687b ldr r3, [r7, #4]
80057b8: 681a ldr r2, [r3, #0]
80057ba: 683b ldr r3, [r7, #0]
80057bc: 681b ldr r3, [r3, #0]
80057be: 4619 mov r1, r3
80057c0: 4610 mov r0, r2
80057c2: f000 fc3e bl 8006042 <TIM_ITRx_SetConfig>
break;
80057c6: e003 b.n 80057d0 <HAL_TIM_ConfigClockSource+0x1c8>
}
default:
status = HAL_ERROR;
80057c8: 2301 movs r3, #1
80057ca: 73fb strb r3, [r7, #15]
break;
80057cc: e000 b.n 80057d0 <HAL_TIM_ConfigClockSource+0x1c8>
break;
80057ce: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
80057d0: 687b ldr r3, [r7, #4]
80057d2: 2201 movs r2, #1
80057d4: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
80057d8: 687b ldr r3, [r7, #4]
80057da: 2200 movs r2, #0
80057dc: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
80057e0: 7bfb ldrb r3, [r7, #15]
}
80057e2: 4618 mov r0, r3
80057e4: 3710 adds r7, #16
80057e6: 46bd mov sp, r7
80057e8: bd80 pop {r7, pc}
80057ea: bf00 nop
80057ec: 00100070 .word 0x00100070
80057f0: 00100040 .word 0x00100040
80057f4: 00100030 .word 0x00100030
80057f8: 00100020 .word 0x00100020
080057fc <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
80057fc: b480 push {r7}
80057fe: b083 sub sp, #12
8005800: af00 add r7, sp, #0
8005802: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
8005804: bf00 nop
8005806: 370c adds r7, #12
8005808: 46bd mov sp, r7
800580a: f85d 7b04 ldr.w r7, [sp], #4
800580e: 4770 bx lr
08005810 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8005810: b480 push {r7}
8005812: b083 sub sp, #12
8005814: af00 add r7, sp, #0
8005816: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8005818: bf00 nop
800581a: 370c adds r7, #12
800581c: 46bd mov sp, r7
800581e: f85d 7b04 ldr.w r7, [sp], #4
8005822: 4770 bx lr
08005824 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8005824: b480 push {r7}
8005826: b083 sub sp, #12
8005828: af00 add r7, sp, #0
800582a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800582c: bf00 nop
800582e: 370c adds r7, #12
8005830: 46bd mov sp, r7
8005832: f85d 7b04 ldr.w r7, [sp], #4
8005836: 4770 bx lr
08005838 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8005838: b480 push {r7}
800583a: b083 sub sp, #12
800583c: af00 add r7, sp, #0
800583e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8005840: bf00 nop
8005842: 370c adds r7, #12
8005844: 46bd mov sp, r7
8005846: f85d 7b04 ldr.w r7, [sp], #4
800584a: 4770 bx lr
0800584c <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800584c: b480 push {r7}
800584e: b083 sub sp, #12
8005850: af00 add r7, sp, #0
8005852: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8005854: bf00 nop
8005856: 370c adds r7, #12
8005858: 46bd mov sp, r7
800585a: f85d 7b04 ldr.w r7, [sp], #4
800585e: 4770 bx lr
08005860 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8005860: b480 push {r7}
8005862: b085 sub sp, #20
8005864: af00 add r7, sp, #0
8005866: 6078 str r0, [r7, #4]
8005868: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800586a: 687b ldr r3, [r7, #4]
800586c: 681b ldr r3, [r3, #0]
800586e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8005870: 687b ldr r3, [r7, #4]
8005872: 4a42 ldr r2, [pc, #264] @ (800597c <TIM_Base_SetConfig+0x11c>)
8005874: 4293 cmp r3, r2
8005876: d00f beq.n 8005898 <TIM_Base_SetConfig+0x38>
8005878: 687b ldr r3, [r7, #4]
800587a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800587e: d00b beq.n 8005898 <TIM_Base_SetConfig+0x38>
8005880: 687b ldr r3, [r7, #4]
8005882: 4a3f ldr r2, [pc, #252] @ (8005980 <TIM_Base_SetConfig+0x120>)
8005884: 4293 cmp r3, r2
8005886: d007 beq.n 8005898 <TIM_Base_SetConfig+0x38>
8005888: 687b ldr r3, [r7, #4]
800588a: 4a3e ldr r2, [pc, #248] @ (8005984 <TIM_Base_SetConfig+0x124>)
800588c: 4293 cmp r3, r2
800588e: d003 beq.n 8005898 <TIM_Base_SetConfig+0x38>
8005890: 687b ldr r3, [r7, #4]
8005892: 4a3d ldr r2, [pc, #244] @ (8005988 <TIM_Base_SetConfig+0x128>)
8005894: 4293 cmp r3, r2
8005896: d108 bne.n 80058aa <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8005898: 68fb ldr r3, [r7, #12]
800589a: f023 0370 bic.w r3, r3, #112 @ 0x70
800589e: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80058a0: 683b ldr r3, [r7, #0]
80058a2: 685b ldr r3, [r3, #4]
80058a4: 68fa ldr r2, [r7, #12]
80058a6: 4313 orrs r3, r2
80058a8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80058aa: 687b ldr r3, [r7, #4]
80058ac: 4a33 ldr r2, [pc, #204] @ (800597c <TIM_Base_SetConfig+0x11c>)
80058ae: 4293 cmp r3, r2
80058b0: d01b beq.n 80058ea <TIM_Base_SetConfig+0x8a>
80058b2: 687b ldr r3, [r7, #4]
80058b4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80058b8: d017 beq.n 80058ea <TIM_Base_SetConfig+0x8a>
80058ba: 687b ldr r3, [r7, #4]
80058bc: 4a30 ldr r2, [pc, #192] @ (8005980 <TIM_Base_SetConfig+0x120>)
80058be: 4293 cmp r3, r2
80058c0: d013 beq.n 80058ea <TIM_Base_SetConfig+0x8a>
80058c2: 687b ldr r3, [r7, #4]
80058c4: 4a2f ldr r2, [pc, #188] @ (8005984 <TIM_Base_SetConfig+0x124>)
80058c6: 4293 cmp r3, r2
80058c8: d00f beq.n 80058ea <TIM_Base_SetConfig+0x8a>
80058ca: 687b ldr r3, [r7, #4]
80058cc: 4a2e ldr r2, [pc, #184] @ (8005988 <TIM_Base_SetConfig+0x128>)
80058ce: 4293 cmp r3, r2
80058d0: d00b beq.n 80058ea <TIM_Base_SetConfig+0x8a>
80058d2: 687b ldr r3, [r7, #4]
80058d4: 4a2d ldr r2, [pc, #180] @ (800598c <TIM_Base_SetConfig+0x12c>)
80058d6: 4293 cmp r3, r2
80058d8: d007 beq.n 80058ea <TIM_Base_SetConfig+0x8a>
80058da: 687b ldr r3, [r7, #4]
80058dc: 4a2c ldr r2, [pc, #176] @ (8005990 <TIM_Base_SetConfig+0x130>)
80058de: 4293 cmp r3, r2
80058e0: d003 beq.n 80058ea <TIM_Base_SetConfig+0x8a>
80058e2: 687b ldr r3, [r7, #4]
80058e4: 4a2b ldr r2, [pc, #172] @ (8005994 <TIM_Base_SetConfig+0x134>)
80058e6: 4293 cmp r3, r2
80058e8: d108 bne.n 80058fc <TIM_Base_SetConfig+0x9c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80058ea: 68fb ldr r3, [r7, #12]
80058ec: f423 7340 bic.w r3, r3, #768 @ 0x300
80058f0: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80058f2: 683b ldr r3, [r7, #0]
80058f4: 68db ldr r3, [r3, #12]
80058f6: 68fa ldr r2, [r7, #12]
80058f8: 4313 orrs r3, r2
80058fa: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80058fc: 68fb ldr r3, [r7, #12]
80058fe: f023 0280 bic.w r2, r3, #128 @ 0x80
8005902: 683b ldr r3, [r7, #0]
8005904: 695b ldr r3, [r3, #20]
8005906: 4313 orrs r3, r2
8005908: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800590a: 687b ldr r3, [r7, #4]
800590c: 68fa ldr r2, [r7, #12]
800590e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8005910: 683b ldr r3, [r7, #0]
8005912: 689a ldr r2, [r3, #8]
8005914: 687b ldr r3, [r7, #4]
8005916: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8005918: 683b ldr r3, [r7, #0]
800591a: 681a ldr r2, [r3, #0]
800591c: 687b ldr r3, [r7, #4]
800591e: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8005920: 687b ldr r3, [r7, #4]
8005922: 4a16 ldr r2, [pc, #88] @ (800597c <TIM_Base_SetConfig+0x11c>)
8005924: 4293 cmp r3, r2
8005926: d00f beq.n 8005948 <TIM_Base_SetConfig+0xe8>
8005928: 687b ldr r3, [r7, #4]
800592a: 4a17 ldr r2, [pc, #92] @ (8005988 <TIM_Base_SetConfig+0x128>)
800592c: 4293 cmp r3, r2
800592e: d00b beq.n 8005948 <TIM_Base_SetConfig+0xe8>
8005930: 687b ldr r3, [r7, #4]
8005932: 4a16 ldr r2, [pc, #88] @ (800598c <TIM_Base_SetConfig+0x12c>)
8005934: 4293 cmp r3, r2
8005936: d007 beq.n 8005948 <TIM_Base_SetConfig+0xe8>
8005938: 687b ldr r3, [r7, #4]
800593a: 4a15 ldr r2, [pc, #84] @ (8005990 <TIM_Base_SetConfig+0x130>)
800593c: 4293 cmp r3, r2
800593e: d003 beq.n 8005948 <TIM_Base_SetConfig+0xe8>
8005940: 687b ldr r3, [r7, #4]
8005942: 4a14 ldr r2, [pc, #80] @ (8005994 <TIM_Base_SetConfig+0x134>)
8005944: 4293 cmp r3, r2
8005946: d103 bne.n 8005950 <TIM_Base_SetConfig+0xf0>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8005948: 683b ldr r3, [r7, #0]
800594a: 691a ldr r2, [r3, #16]
800594c: 687b ldr r3, [r7, #4]
800594e: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8005950: 687b ldr r3, [r7, #4]
8005952: 2201 movs r2, #1
8005954: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8005956: 687b ldr r3, [r7, #4]
8005958: 691b ldr r3, [r3, #16]
800595a: f003 0301 and.w r3, r3, #1
800595e: 2b01 cmp r3, #1
8005960: d105 bne.n 800596e <TIM_Base_SetConfig+0x10e>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8005962: 687b ldr r3, [r7, #4]
8005964: 691b ldr r3, [r3, #16]
8005966: f023 0201 bic.w r2, r3, #1
800596a: 687b ldr r3, [r7, #4]
800596c: 611a str r2, [r3, #16]
}
}
800596e: bf00 nop
8005970: 3714 adds r7, #20
8005972: 46bd mov sp, r7
8005974: f85d 7b04 ldr.w r7, [sp], #4
8005978: 4770 bx lr
800597a: bf00 nop
800597c: 40012c00 .word 0x40012c00
8005980: 40000400 .word 0x40000400
8005984: 40000800 .word 0x40000800
8005988: 40013400 .word 0x40013400
800598c: 40014000 .word 0x40014000
8005990: 40014400 .word 0x40014400
8005994: 40014800 .word 0x40014800
08005998 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005998: b480 push {r7}
800599a: b087 sub sp, #28
800599c: af00 add r7, sp, #0
800599e: 6078 str r0, [r7, #4]
80059a0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80059a2: 687b ldr r3, [r7, #4]
80059a4: 6a1b ldr r3, [r3, #32]
80059a6: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80059a8: 687b ldr r3, [r7, #4]
80059aa: 6a1b ldr r3, [r3, #32]
80059ac: f023 0201 bic.w r2, r3, #1
80059b0: 687b ldr r3, [r7, #4]
80059b2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80059b4: 687b ldr r3, [r7, #4]
80059b6: 685b ldr r3, [r3, #4]
80059b8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80059ba: 687b ldr r3, [r7, #4]
80059bc: 699b ldr r3, [r3, #24]
80059be: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
80059c0: 68fb ldr r3, [r7, #12]
80059c2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80059c6: f023 0370 bic.w r3, r3, #112 @ 0x70
80059ca: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
80059cc: 68fb ldr r3, [r7, #12]
80059ce: f023 0303 bic.w r3, r3, #3
80059d2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80059d4: 683b ldr r3, [r7, #0]
80059d6: 681b ldr r3, [r3, #0]
80059d8: 68fa ldr r2, [r7, #12]
80059da: 4313 orrs r3, r2
80059dc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
80059de: 697b ldr r3, [r7, #20]
80059e0: f023 0302 bic.w r3, r3, #2
80059e4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
80059e6: 683b ldr r3, [r7, #0]
80059e8: 689b ldr r3, [r3, #8]
80059ea: 697a ldr r2, [r7, #20]
80059ec: 4313 orrs r3, r2
80059ee: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
80059f0: 687b ldr r3, [r7, #4]
80059f2: 4a2c ldr r2, [pc, #176] @ (8005aa4 <TIM_OC1_SetConfig+0x10c>)
80059f4: 4293 cmp r3, r2
80059f6: d00f beq.n 8005a18 <TIM_OC1_SetConfig+0x80>
80059f8: 687b ldr r3, [r7, #4]
80059fa: 4a2b ldr r2, [pc, #172] @ (8005aa8 <TIM_OC1_SetConfig+0x110>)
80059fc: 4293 cmp r3, r2
80059fe: d00b beq.n 8005a18 <TIM_OC1_SetConfig+0x80>
8005a00: 687b ldr r3, [r7, #4]
8005a02: 4a2a ldr r2, [pc, #168] @ (8005aac <TIM_OC1_SetConfig+0x114>)
8005a04: 4293 cmp r3, r2
8005a06: d007 beq.n 8005a18 <TIM_OC1_SetConfig+0x80>
8005a08: 687b ldr r3, [r7, #4]
8005a0a: 4a29 ldr r2, [pc, #164] @ (8005ab0 <TIM_OC1_SetConfig+0x118>)
8005a0c: 4293 cmp r3, r2
8005a0e: d003 beq.n 8005a18 <TIM_OC1_SetConfig+0x80>
8005a10: 687b ldr r3, [r7, #4]
8005a12: 4a28 ldr r2, [pc, #160] @ (8005ab4 <TIM_OC1_SetConfig+0x11c>)
8005a14: 4293 cmp r3, r2
8005a16: d10c bne.n 8005a32 <TIM_OC1_SetConfig+0x9a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8005a18: 697b ldr r3, [r7, #20]
8005a1a: f023 0308 bic.w r3, r3, #8
8005a1e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8005a20: 683b ldr r3, [r7, #0]
8005a22: 68db ldr r3, [r3, #12]
8005a24: 697a ldr r2, [r7, #20]
8005a26: 4313 orrs r3, r2
8005a28: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8005a2a: 697b ldr r3, [r7, #20]
8005a2c: f023 0304 bic.w r3, r3, #4
8005a30: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005a32: 687b ldr r3, [r7, #4]
8005a34: 4a1b ldr r2, [pc, #108] @ (8005aa4 <TIM_OC1_SetConfig+0x10c>)
8005a36: 4293 cmp r3, r2
8005a38: d00f beq.n 8005a5a <TIM_OC1_SetConfig+0xc2>
8005a3a: 687b ldr r3, [r7, #4]
8005a3c: 4a1a ldr r2, [pc, #104] @ (8005aa8 <TIM_OC1_SetConfig+0x110>)
8005a3e: 4293 cmp r3, r2
8005a40: d00b beq.n 8005a5a <TIM_OC1_SetConfig+0xc2>
8005a42: 687b ldr r3, [r7, #4]
8005a44: 4a19 ldr r2, [pc, #100] @ (8005aac <TIM_OC1_SetConfig+0x114>)
8005a46: 4293 cmp r3, r2
8005a48: d007 beq.n 8005a5a <TIM_OC1_SetConfig+0xc2>
8005a4a: 687b ldr r3, [r7, #4]
8005a4c: 4a18 ldr r2, [pc, #96] @ (8005ab0 <TIM_OC1_SetConfig+0x118>)
8005a4e: 4293 cmp r3, r2
8005a50: d003 beq.n 8005a5a <TIM_OC1_SetConfig+0xc2>
8005a52: 687b ldr r3, [r7, #4]
8005a54: 4a17 ldr r2, [pc, #92] @ (8005ab4 <TIM_OC1_SetConfig+0x11c>)
8005a56: 4293 cmp r3, r2
8005a58: d111 bne.n 8005a7e <TIM_OC1_SetConfig+0xe6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8005a5a: 693b ldr r3, [r7, #16]
8005a5c: f423 7380 bic.w r3, r3, #256 @ 0x100
8005a60: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8005a62: 693b ldr r3, [r7, #16]
8005a64: f423 7300 bic.w r3, r3, #512 @ 0x200
8005a68: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8005a6a: 683b ldr r3, [r7, #0]
8005a6c: 695b ldr r3, [r3, #20]
8005a6e: 693a ldr r2, [r7, #16]
8005a70: 4313 orrs r3, r2
8005a72: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8005a74: 683b ldr r3, [r7, #0]
8005a76: 699b ldr r3, [r3, #24]
8005a78: 693a ldr r2, [r7, #16]
8005a7a: 4313 orrs r3, r2
8005a7c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005a7e: 687b ldr r3, [r7, #4]
8005a80: 693a ldr r2, [r7, #16]
8005a82: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8005a84: 687b ldr r3, [r7, #4]
8005a86: 68fa ldr r2, [r7, #12]
8005a88: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8005a8a: 683b ldr r3, [r7, #0]
8005a8c: 685a ldr r2, [r3, #4]
8005a8e: 687b ldr r3, [r7, #4]
8005a90: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005a92: 687b ldr r3, [r7, #4]
8005a94: 697a ldr r2, [r7, #20]
8005a96: 621a str r2, [r3, #32]
}
8005a98: bf00 nop
8005a9a: 371c adds r7, #28
8005a9c: 46bd mov sp, r7
8005a9e: f85d 7b04 ldr.w r7, [sp], #4
8005aa2: 4770 bx lr
8005aa4: 40012c00 .word 0x40012c00
8005aa8: 40013400 .word 0x40013400
8005aac: 40014000 .word 0x40014000
8005ab0: 40014400 .word 0x40014400
8005ab4: 40014800 .word 0x40014800
08005ab8 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005ab8: b480 push {r7}
8005aba: b087 sub sp, #28
8005abc: af00 add r7, sp, #0
8005abe: 6078 str r0, [r7, #4]
8005ac0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005ac2: 687b ldr r3, [r7, #4]
8005ac4: 6a1b ldr r3, [r3, #32]
8005ac6: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8005ac8: 687b ldr r3, [r7, #4]
8005aca: 6a1b ldr r3, [r3, #32]
8005acc: f023 0210 bic.w r2, r3, #16
8005ad0: 687b ldr r3, [r7, #4]
8005ad2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005ad4: 687b ldr r3, [r7, #4]
8005ad6: 685b ldr r3, [r3, #4]
8005ad8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8005ada: 687b ldr r3, [r7, #4]
8005adc: 699b ldr r3, [r3, #24]
8005ade: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8005ae0: 68fb ldr r3, [r7, #12]
8005ae2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005ae6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005aea: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8005aec: 68fb ldr r3, [r7, #12]
8005aee: f423 7340 bic.w r3, r3, #768 @ 0x300
8005af2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005af4: 683b ldr r3, [r7, #0]
8005af6: 681b ldr r3, [r3, #0]
8005af8: 021b lsls r3, r3, #8
8005afa: 68fa ldr r2, [r7, #12]
8005afc: 4313 orrs r3, r2
8005afe: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8005b00: 697b ldr r3, [r7, #20]
8005b02: f023 0320 bic.w r3, r3, #32
8005b06: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8005b08: 683b ldr r3, [r7, #0]
8005b0a: 689b ldr r3, [r3, #8]
8005b0c: 011b lsls r3, r3, #4
8005b0e: 697a ldr r2, [r7, #20]
8005b10: 4313 orrs r3, r2
8005b12: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8005b14: 687b ldr r3, [r7, #4]
8005b16: 4a28 ldr r2, [pc, #160] @ (8005bb8 <TIM_OC2_SetConfig+0x100>)
8005b18: 4293 cmp r3, r2
8005b1a: d003 beq.n 8005b24 <TIM_OC2_SetConfig+0x6c>
8005b1c: 687b ldr r3, [r7, #4]
8005b1e: 4a27 ldr r2, [pc, #156] @ (8005bbc <TIM_OC2_SetConfig+0x104>)
8005b20: 4293 cmp r3, r2
8005b22: d10d bne.n 8005b40 <TIM_OC2_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8005b24: 697b ldr r3, [r7, #20]
8005b26: f023 0380 bic.w r3, r3, #128 @ 0x80
8005b2a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8005b2c: 683b ldr r3, [r7, #0]
8005b2e: 68db ldr r3, [r3, #12]
8005b30: 011b lsls r3, r3, #4
8005b32: 697a ldr r2, [r7, #20]
8005b34: 4313 orrs r3, r2
8005b36: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8005b38: 697b ldr r3, [r7, #20]
8005b3a: f023 0340 bic.w r3, r3, #64 @ 0x40
8005b3e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005b40: 687b ldr r3, [r7, #4]
8005b42: 4a1d ldr r2, [pc, #116] @ (8005bb8 <TIM_OC2_SetConfig+0x100>)
8005b44: 4293 cmp r3, r2
8005b46: d00f beq.n 8005b68 <TIM_OC2_SetConfig+0xb0>
8005b48: 687b ldr r3, [r7, #4]
8005b4a: 4a1c ldr r2, [pc, #112] @ (8005bbc <TIM_OC2_SetConfig+0x104>)
8005b4c: 4293 cmp r3, r2
8005b4e: d00b beq.n 8005b68 <TIM_OC2_SetConfig+0xb0>
8005b50: 687b ldr r3, [r7, #4]
8005b52: 4a1b ldr r2, [pc, #108] @ (8005bc0 <TIM_OC2_SetConfig+0x108>)
8005b54: 4293 cmp r3, r2
8005b56: d007 beq.n 8005b68 <TIM_OC2_SetConfig+0xb0>
8005b58: 687b ldr r3, [r7, #4]
8005b5a: 4a1a ldr r2, [pc, #104] @ (8005bc4 <TIM_OC2_SetConfig+0x10c>)
8005b5c: 4293 cmp r3, r2
8005b5e: d003 beq.n 8005b68 <TIM_OC2_SetConfig+0xb0>
8005b60: 687b ldr r3, [r7, #4]
8005b62: 4a19 ldr r2, [pc, #100] @ (8005bc8 <TIM_OC2_SetConfig+0x110>)
8005b64: 4293 cmp r3, r2
8005b66: d113 bne.n 8005b90 <TIM_OC2_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8005b68: 693b ldr r3, [r7, #16]
8005b6a: f423 6380 bic.w r3, r3, #1024 @ 0x400
8005b6e: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8005b70: 693b ldr r3, [r7, #16]
8005b72: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005b76: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8005b78: 683b ldr r3, [r7, #0]
8005b7a: 695b ldr r3, [r3, #20]
8005b7c: 009b lsls r3, r3, #2
8005b7e: 693a ldr r2, [r7, #16]
8005b80: 4313 orrs r3, r2
8005b82: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8005b84: 683b ldr r3, [r7, #0]
8005b86: 699b ldr r3, [r3, #24]
8005b88: 009b lsls r3, r3, #2
8005b8a: 693a ldr r2, [r7, #16]
8005b8c: 4313 orrs r3, r2
8005b8e: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005b90: 687b ldr r3, [r7, #4]
8005b92: 693a ldr r2, [r7, #16]
8005b94: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8005b96: 687b ldr r3, [r7, #4]
8005b98: 68fa ldr r2, [r7, #12]
8005b9a: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8005b9c: 683b ldr r3, [r7, #0]
8005b9e: 685a ldr r2, [r3, #4]
8005ba0: 687b ldr r3, [r7, #4]
8005ba2: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005ba4: 687b ldr r3, [r7, #4]
8005ba6: 697a ldr r2, [r7, #20]
8005ba8: 621a str r2, [r3, #32]
}
8005baa: bf00 nop
8005bac: 371c adds r7, #28
8005bae: 46bd mov sp, r7
8005bb0: f85d 7b04 ldr.w r7, [sp], #4
8005bb4: 4770 bx lr
8005bb6: bf00 nop
8005bb8: 40012c00 .word 0x40012c00
8005bbc: 40013400 .word 0x40013400
8005bc0: 40014000 .word 0x40014000
8005bc4: 40014400 .word 0x40014400
8005bc8: 40014800 .word 0x40014800
08005bcc <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005bcc: b480 push {r7}
8005bce: b087 sub sp, #28
8005bd0: af00 add r7, sp, #0
8005bd2: 6078 str r0, [r7, #4]
8005bd4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005bd6: 687b ldr r3, [r7, #4]
8005bd8: 6a1b ldr r3, [r3, #32]
8005bda: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8005bdc: 687b ldr r3, [r7, #4]
8005bde: 6a1b ldr r3, [r3, #32]
8005be0: f423 7280 bic.w r2, r3, #256 @ 0x100
8005be4: 687b ldr r3, [r7, #4]
8005be6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005be8: 687b ldr r3, [r7, #4]
8005bea: 685b ldr r3, [r3, #4]
8005bec: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8005bee: 687b ldr r3, [r7, #4]
8005bf0: 69db ldr r3, [r3, #28]
8005bf2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8005bf4: 68fb ldr r3, [r7, #12]
8005bf6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005bfa: f023 0370 bic.w r3, r3, #112 @ 0x70
8005bfe: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8005c00: 68fb ldr r3, [r7, #12]
8005c02: f023 0303 bic.w r3, r3, #3
8005c06: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8005c08: 683b ldr r3, [r7, #0]
8005c0a: 681b ldr r3, [r3, #0]
8005c0c: 68fa ldr r2, [r7, #12]
8005c0e: 4313 orrs r3, r2
8005c10: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8005c12: 697b ldr r3, [r7, #20]
8005c14: f423 7300 bic.w r3, r3, #512 @ 0x200
8005c18: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8005c1a: 683b ldr r3, [r7, #0]
8005c1c: 689b ldr r3, [r3, #8]
8005c1e: 021b lsls r3, r3, #8
8005c20: 697a ldr r2, [r7, #20]
8005c22: 4313 orrs r3, r2
8005c24: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8005c26: 687b ldr r3, [r7, #4]
8005c28: 4a27 ldr r2, [pc, #156] @ (8005cc8 <TIM_OC3_SetConfig+0xfc>)
8005c2a: 4293 cmp r3, r2
8005c2c: d003 beq.n 8005c36 <TIM_OC3_SetConfig+0x6a>
8005c2e: 687b ldr r3, [r7, #4]
8005c30: 4a26 ldr r2, [pc, #152] @ (8005ccc <TIM_OC3_SetConfig+0x100>)
8005c32: 4293 cmp r3, r2
8005c34: d10d bne.n 8005c52 <TIM_OC3_SetConfig+0x86>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8005c36: 697b ldr r3, [r7, #20]
8005c38: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005c3c: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8005c3e: 683b ldr r3, [r7, #0]
8005c40: 68db ldr r3, [r3, #12]
8005c42: 021b lsls r3, r3, #8
8005c44: 697a ldr r2, [r7, #20]
8005c46: 4313 orrs r3, r2
8005c48: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8005c4a: 697b ldr r3, [r7, #20]
8005c4c: f423 6380 bic.w r3, r3, #1024 @ 0x400
8005c50: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005c52: 687b ldr r3, [r7, #4]
8005c54: 4a1c ldr r2, [pc, #112] @ (8005cc8 <TIM_OC3_SetConfig+0xfc>)
8005c56: 4293 cmp r3, r2
8005c58: d00f beq.n 8005c7a <TIM_OC3_SetConfig+0xae>
8005c5a: 687b ldr r3, [r7, #4]
8005c5c: 4a1b ldr r2, [pc, #108] @ (8005ccc <TIM_OC3_SetConfig+0x100>)
8005c5e: 4293 cmp r3, r2
8005c60: d00b beq.n 8005c7a <TIM_OC3_SetConfig+0xae>
8005c62: 687b ldr r3, [r7, #4]
8005c64: 4a1a ldr r2, [pc, #104] @ (8005cd0 <TIM_OC3_SetConfig+0x104>)
8005c66: 4293 cmp r3, r2
8005c68: d007 beq.n 8005c7a <TIM_OC3_SetConfig+0xae>
8005c6a: 687b ldr r3, [r7, #4]
8005c6c: 4a19 ldr r2, [pc, #100] @ (8005cd4 <TIM_OC3_SetConfig+0x108>)
8005c6e: 4293 cmp r3, r2
8005c70: d003 beq.n 8005c7a <TIM_OC3_SetConfig+0xae>
8005c72: 687b ldr r3, [r7, #4]
8005c74: 4a18 ldr r2, [pc, #96] @ (8005cd8 <TIM_OC3_SetConfig+0x10c>)
8005c76: 4293 cmp r3, r2
8005c78: d113 bne.n 8005ca2 <TIM_OC3_SetConfig+0xd6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8005c7a: 693b ldr r3, [r7, #16]
8005c7c: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8005c80: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8005c82: 693b ldr r3, [r7, #16]
8005c84: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8005c88: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8005c8a: 683b ldr r3, [r7, #0]
8005c8c: 695b ldr r3, [r3, #20]
8005c8e: 011b lsls r3, r3, #4
8005c90: 693a ldr r2, [r7, #16]
8005c92: 4313 orrs r3, r2
8005c94: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8005c96: 683b ldr r3, [r7, #0]
8005c98: 699b ldr r3, [r3, #24]
8005c9a: 011b lsls r3, r3, #4
8005c9c: 693a ldr r2, [r7, #16]
8005c9e: 4313 orrs r3, r2
8005ca0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005ca2: 687b ldr r3, [r7, #4]
8005ca4: 693a ldr r2, [r7, #16]
8005ca6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8005ca8: 687b ldr r3, [r7, #4]
8005caa: 68fa ldr r2, [r7, #12]
8005cac: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8005cae: 683b ldr r3, [r7, #0]
8005cb0: 685a ldr r2, [r3, #4]
8005cb2: 687b ldr r3, [r7, #4]
8005cb4: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005cb6: 687b ldr r3, [r7, #4]
8005cb8: 697a ldr r2, [r7, #20]
8005cba: 621a str r2, [r3, #32]
}
8005cbc: bf00 nop
8005cbe: 371c adds r7, #28
8005cc0: 46bd mov sp, r7
8005cc2: f85d 7b04 ldr.w r7, [sp], #4
8005cc6: 4770 bx lr
8005cc8: 40012c00 .word 0x40012c00
8005ccc: 40013400 .word 0x40013400
8005cd0: 40014000 .word 0x40014000
8005cd4: 40014400 .word 0x40014400
8005cd8: 40014800 .word 0x40014800
08005cdc <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005cdc: b480 push {r7}
8005cde: b087 sub sp, #28
8005ce0: af00 add r7, sp, #0
8005ce2: 6078 str r0, [r7, #4]
8005ce4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005ce6: 687b ldr r3, [r7, #4]
8005ce8: 6a1b ldr r3, [r3, #32]
8005cea: 617b str r3, [r7, #20]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8005cec: 687b ldr r3, [r7, #4]
8005cee: 6a1b ldr r3, [r3, #32]
8005cf0: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8005cf4: 687b ldr r3, [r7, #4]
8005cf6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005cf8: 687b ldr r3, [r7, #4]
8005cfa: 685b ldr r3, [r3, #4]
8005cfc: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8005cfe: 687b ldr r3, [r7, #4]
8005d00: 69db ldr r3, [r3, #28]
8005d02: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8005d04: 68fb ldr r3, [r7, #12]
8005d06: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005d0a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005d0e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8005d10: 68fb ldr r3, [r7, #12]
8005d12: f423 7340 bic.w r3, r3, #768 @ 0x300
8005d16: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005d18: 683b ldr r3, [r7, #0]
8005d1a: 681b ldr r3, [r3, #0]
8005d1c: 021b lsls r3, r3, #8
8005d1e: 68fa ldr r2, [r7, #12]
8005d20: 4313 orrs r3, r2
8005d22: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8005d24: 697b ldr r3, [r7, #20]
8005d26: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8005d2a: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8005d2c: 683b ldr r3, [r7, #0]
8005d2e: 689b ldr r3, [r3, #8]
8005d30: 031b lsls r3, r3, #12
8005d32: 697a ldr r2, [r7, #20]
8005d34: 4313 orrs r3, r2
8005d36: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
8005d38: 687b ldr r3, [r7, #4]
8005d3a: 4a28 ldr r2, [pc, #160] @ (8005ddc <TIM_OC4_SetConfig+0x100>)
8005d3c: 4293 cmp r3, r2
8005d3e: d003 beq.n 8005d48 <TIM_OC4_SetConfig+0x6c>
8005d40: 687b ldr r3, [r7, #4]
8005d42: 4a27 ldr r2, [pc, #156] @ (8005de0 <TIM_OC4_SetConfig+0x104>)
8005d44: 4293 cmp r3, r2
8005d46: d10d bne.n 8005d64 <TIM_OC4_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC4NP;
8005d48: 697b ldr r3, [r7, #20]
8005d4a: f423 4300 bic.w r3, r3, #32768 @ 0x8000
8005d4e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 12U);
8005d50: 683b ldr r3, [r7, #0]
8005d52: 68db ldr r3, [r3, #12]
8005d54: 031b lsls r3, r3, #12
8005d56: 697a ldr r2, [r7, #20]
8005d58: 4313 orrs r3, r2
8005d5a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC4NE;
8005d5c: 697b ldr r3, [r7, #20]
8005d5e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005d62: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005d64: 687b ldr r3, [r7, #4]
8005d66: 4a1d ldr r2, [pc, #116] @ (8005ddc <TIM_OC4_SetConfig+0x100>)
8005d68: 4293 cmp r3, r2
8005d6a: d00f beq.n 8005d8c <TIM_OC4_SetConfig+0xb0>
8005d6c: 687b ldr r3, [r7, #4]
8005d6e: 4a1c ldr r2, [pc, #112] @ (8005de0 <TIM_OC4_SetConfig+0x104>)
8005d70: 4293 cmp r3, r2
8005d72: d00b beq.n 8005d8c <TIM_OC4_SetConfig+0xb0>
8005d74: 687b ldr r3, [r7, #4]
8005d76: 4a1b ldr r2, [pc, #108] @ (8005de4 <TIM_OC4_SetConfig+0x108>)
8005d78: 4293 cmp r3, r2
8005d7a: d007 beq.n 8005d8c <TIM_OC4_SetConfig+0xb0>
8005d7c: 687b ldr r3, [r7, #4]
8005d7e: 4a1a ldr r2, [pc, #104] @ (8005de8 <TIM_OC4_SetConfig+0x10c>)
8005d80: 4293 cmp r3, r2
8005d82: d003 beq.n 8005d8c <TIM_OC4_SetConfig+0xb0>
8005d84: 687b ldr r3, [r7, #4]
8005d86: 4a19 ldr r2, [pc, #100] @ (8005dec <TIM_OC4_SetConfig+0x110>)
8005d88: 4293 cmp r3, r2
8005d8a: d113 bne.n 8005db4 <TIM_OC4_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8005d8c: 693b ldr r3, [r7, #16]
8005d8e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005d92: 613b str r3, [r7, #16]
/* Reset the Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4N;
8005d94: 693b ldr r3, [r7, #16]
8005d96: f423 4300 bic.w r3, r3, #32768 @ 0x8000
8005d9a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8005d9c: 683b ldr r3, [r7, #0]
8005d9e: 695b ldr r3, [r3, #20]
8005da0: 019b lsls r3, r3, #6
8005da2: 693a ldr r2, [r7, #16]
8005da4: 4313 orrs r3, r2
8005da6: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 6U);
8005da8: 683b ldr r3, [r7, #0]
8005daa: 699b ldr r3, [r3, #24]
8005dac: 019b lsls r3, r3, #6
8005dae: 693a ldr r2, [r7, #16]
8005db0: 4313 orrs r3, r2
8005db2: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005db4: 687b ldr r3, [r7, #4]
8005db6: 693a ldr r2, [r7, #16]
8005db8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8005dba: 687b ldr r3, [r7, #4]
8005dbc: 68fa ldr r2, [r7, #12]
8005dbe: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8005dc0: 683b ldr r3, [r7, #0]
8005dc2: 685a ldr r2, [r3, #4]
8005dc4: 687b ldr r3, [r7, #4]
8005dc6: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005dc8: 687b ldr r3, [r7, #4]
8005dca: 697a ldr r2, [r7, #20]
8005dcc: 621a str r2, [r3, #32]
}
8005dce: bf00 nop
8005dd0: 371c adds r7, #28
8005dd2: 46bd mov sp, r7
8005dd4: f85d 7b04 ldr.w r7, [sp], #4
8005dd8: 4770 bx lr
8005dda: bf00 nop
8005ddc: 40012c00 .word 0x40012c00
8005de0: 40013400 .word 0x40013400
8005de4: 40014000 .word 0x40014000
8005de8: 40014400 .word 0x40014400
8005dec: 40014800 .word 0x40014800
08005df0 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8005df0: b480 push {r7}
8005df2: b087 sub sp, #28
8005df4: af00 add r7, sp, #0
8005df6: 6078 str r0, [r7, #4]
8005df8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005dfa: 687b ldr r3, [r7, #4]
8005dfc: 6a1b ldr r3, [r3, #32]
8005dfe: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8005e00: 687b ldr r3, [r7, #4]
8005e02: 6a1b ldr r3, [r3, #32]
8005e04: f423 3280 bic.w r2, r3, #65536 @ 0x10000
8005e08: 687b ldr r3, [r7, #4]
8005e0a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005e0c: 687b ldr r3, [r7, #4]
8005e0e: 685b ldr r3, [r3, #4]
8005e10: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8005e12: 687b ldr r3, [r7, #4]
8005e14: 6d1b ldr r3, [r3, #80] @ 0x50
8005e16: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8005e18: 68fb ldr r3, [r7, #12]
8005e1a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005e1e: f023 0370 bic.w r3, r3, #112 @ 0x70
8005e22: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8005e24: 683b ldr r3, [r7, #0]
8005e26: 681b ldr r3, [r3, #0]
8005e28: 68fa ldr r2, [r7, #12]
8005e2a: 4313 orrs r3, r2
8005e2c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8005e2e: 693b ldr r3, [r7, #16]
8005e30: f423 3300 bic.w r3, r3, #131072 @ 0x20000
8005e34: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
8005e36: 683b ldr r3, [r7, #0]
8005e38: 689b ldr r3, [r3, #8]
8005e3a: 041b lsls r3, r3, #16
8005e3c: 693a ldr r2, [r7, #16]
8005e3e: 4313 orrs r3, r2
8005e40: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005e42: 687b ldr r3, [r7, #4]
8005e44: 4a17 ldr r2, [pc, #92] @ (8005ea4 <TIM_OC5_SetConfig+0xb4>)
8005e46: 4293 cmp r3, r2
8005e48: d00f beq.n 8005e6a <TIM_OC5_SetConfig+0x7a>
8005e4a: 687b ldr r3, [r7, #4]
8005e4c: 4a16 ldr r2, [pc, #88] @ (8005ea8 <TIM_OC5_SetConfig+0xb8>)
8005e4e: 4293 cmp r3, r2
8005e50: d00b beq.n 8005e6a <TIM_OC5_SetConfig+0x7a>
8005e52: 687b ldr r3, [r7, #4]
8005e54: 4a15 ldr r2, [pc, #84] @ (8005eac <TIM_OC5_SetConfig+0xbc>)
8005e56: 4293 cmp r3, r2
8005e58: d007 beq.n 8005e6a <TIM_OC5_SetConfig+0x7a>
8005e5a: 687b ldr r3, [r7, #4]
8005e5c: 4a14 ldr r2, [pc, #80] @ (8005eb0 <TIM_OC5_SetConfig+0xc0>)
8005e5e: 4293 cmp r3, r2
8005e60: d003 beq.n 8005e6a <TIM_OC5_SetConfig+0x7a>
8005e62: 687b ldr r3, [r7, #4]
8005e64: 4a13 ldr r2, [pc, #76] @ (8005eb4 <TIM_OC5_SetConfig+0xc4>)
8005e66: 4293 cmp r3, r2
8005e68: d109 bne.n 8005e7e <TIM_OC5_SetConfig+0x8e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
8005e6a: 697b ldr r3, [r7, #20]
8005e6c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005e70: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8005e72: 683b ldr r3, [r7, #0]
8005e74: 695b ldr r3, [r3, #20]
8005e76: 021b lsls r3, r3, #8
8005e78: 697a ldr r2, [r7, #20]
8005e7a: 4313 orrs r3, r2
8005e7c: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005e7e: 687b ldr r3, [r7, #4]
8005e80: 697a ldr r2, [r7, #20]
8005e82: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8005e84: 687b ldr r3, [r7, #4]
8005e86: 68fa ldr r2, [r7, #12]
8005e88: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8005e8a: 683b ldr r3, [r7, #0]
8005e8c: 685a ldr r2, [r3, #4]
8005e8e: 687b ldr r3, [r7, #4]
8005e90: 649a str r2, [r3, #72] @ 0x48
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005e92: 687b ldr r3, [r7, #4]
8005e94: 693a ldr r2, [r7, #16]
8005e96: 621a str r2, [r3, #32]
}
8005e98: bf00 nop
8005e9a: 371c adds r7, #28
8005e9c: 46bd mov sp, r7
8005e9e: f85d 7b04 ldr.w r7, [sp], #4
8005ea2: 4770 bx lr
8005ea4: 40012c00 .word 0x40012c00
8005ea8: 40013400 .word 0x40013400
8005eac: 40014000 .word 0x40014000
8005eb0: 40014400 .word 0x40014400
8005eb4: 40014800 .word 0x40014800
08005eb8 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8005eb8: b480 push {r7}
8005eba: b087 sub sp, #28
8005ebc: af00 add r7, sp, #0
8005ebe: 6078 str r0, [r7, #4]
8005ec0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005ec2: 687b ldr r3, [r7, #4]
8005ec4: 6a1b ldr r3, [r3, #32]
8005ec6: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8005ec8: 687b ldr r3, [r7, #4]
8005eca: 6a1b ldr r3, [r3, #32]
8005ecc: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8005ed0: 687b ldr r3, [r7, #4]
8005ed2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005ed4: 687b ldr r3, [r7, #4]
8005ed6: 685b ldr r3, [r3, #4]
8005ed8: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8005eda: 687b ldr r3, [r7, #4]
8005edc: 6d1b ldr r3, [r3, #80] @ 0x50
8005ede: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8005ee0: 68fb ldr r3, [r7, #12]
8005ee2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005ee6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005eea: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005eec: 683b ldr r3, [r7, #0]
8005eee: 681b ldr r3, [r3, #0]
8005ef0: 021b lsls r3, r3, #8
8005ef2: 68fa ldr r2, [r7, #12]
8005ef4: 4313 orrs r3, r2
8005ef6: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8005ef8: 693b ldr r3, [r7, #16]
8005efa: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8005efe: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8005f00: 683b ldr r3, [r7, #0]
8005f02: 689b ldr r3, [r3, #8]
8005f04: 051b lsls r3, r3, #20
8005f06: 693a ldr r2, [r7, #16]
8005f08: 4313 orrs r3, r2
8005f0a: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005f0c: 687b ldr r3, [r7, #4]
8005f0e: 4a18 ldr r2, [pc, #96] @ (8005f70 <TIM_OC6_SetConfig+0xb8>)
8005f10: 4293 cmp r3, r2
8005f12: d00f beq.n 8005f34 <TIM_OC6_SetConfig+0x7c>
8005f14: 687b ldr r3, [r7, #4]
8005f16: 4a17 ldr r2, [pc, #92] @ (8005f74 <TIM_OC6_SetConfig+0xbc>)
8005f18: 4293 cmp r3, r2
8005f1a: d00b beq.n 8005f34 <TIM_OC6_SetConfig+0x7c>
8005f1c: 687b ldr r3, [r7, #4]
8005f1e: 4a16 ldr r2, [pc, #88] @ (8005f78 <TIM_OC6_SetConfig+0xc0>)
8005f20: 4293 cmp r3, r2
8005f22: d007 beq.n 8005f34 <TIM_OC6_SetConfig+0x7c>
8005f24: 687b ldr r3, [r7, #4]
8005f26: 4a15 ldr r2, [pc, #84] @ (8005f7c <TIM_OC6_SetConfig+0xc4>)
8005f28: 4293 cmp r3, r2
8005f2a: d003 beq.n 8005f34 <TIM_OC6_SetConfig+0x7c>
8005f2c: 687b ldr r3, [r7, #4]
8005f2e: 4a14 ldr r2, [pc, #80] @ (8005f80 <TIM_OC6_SetConfig+0xc8>)
8005f30: 4293 cmp r3, r2
8005f32: d109 bne.n 8005f48 <TIM_OC6_SetConfig+0x90>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8005f34: 697b ldr r3, [r7, #20]
8005f36: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005f3a: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8005f3c: 683b ldr r3, [r7, #0]
8005f3e: 695b ldr r3, [r3, #20]
8005f40: 029b lsls r3, r3, #10
8005f42: 697a ldr r2, [r7, #20]
8005f44: 4313 orrs r3, r2
8005f46: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005f48: 687b ldr r3, [r7, #4]
8005f4a: 697a ldr r2, [r7, #20]
8005f4c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8005f4e: 687b ldr r3, [r7, #4]
8005f50: 68fa ldr r2, [r7, #12]
8005f52: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8005f54: 683b ldr r3, [r7, #0]
8005f56: 685a ldr r2, [r3, #4]
8005f58: 687b ldr r3, [r7, #4]
8005f5a: 64da str r2, [r3, #76] @ 0x4c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005f5c: 687b ldr r3, [r7, #4]
8005f5e: 693a ldr r2, [r7, #16]
8005f60: 621a str r2, [r3, #32]
}
8005f62: bf00 nop
8005f64: 371c adds r7, #28
8005f66: 46bd mov sp, r7
8005f68: f85d 7b04 ldr.w r7, [sp], #4
8005f6c: 4770 bx lr
8005f6e: bf00 nop
8005f70: 40012c00 .word 0x40012c00
8005f74: 40013400 .word 0x40013400
8005f78: 40014000 .word 0x40014000
8005f7c: 40014400 .word 0x40014400
8005f80: 40014800 .word 0x40014800
08005f84 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005f84: b480 push {r7}
8005f86: b087 sub sp, #28
8005f88: af00 add r7, sp, #0
8005f8a: 60f8 str r0, [r7, #12]
8005f8c: 60b9 str r1, [r7, #8]
8005f8e: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8005f90: 68fb ldr r3, [r7, #12]
8005f92: 6a1b ldr r3, [r3, #32]
8005f94: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8005f96: 68fb ldr r3, [r7, #12]
8005f98: 6a1b ldr r3, [r3, #32]
8005f9a: f023 0201 bic.w r2, r3, #1
8005f9e: 68fb ldr r3, [r7, #12]
8005fa0: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8005fa2: 68fb ldr r3, [r7, #12]
8005fa4: 699b ldr r3, [r3, #24]
8005fa6: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8005fa8: 693b ldr r3, [r7, #16]
8005faa: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8005fae: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8005fb0: 687b ldr r3, [r7, #4]
8005fb2: 011b lsls r3, r3, #4
8005fb4: 693a ldr r2, [r7, #16]
8005fb6: 4313 orrs r3, r2
8005fb8: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8005fba: 697b ldr r3, [r7, #20]
8005fbc: f023 030a bic.w r3, r3, #10
8005fc0: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8005fc2: 697a ldr r2, [r7, #20]
8005fc4: 68bb ldr r3, [r7, #8]
8005fc6: 4313 orrs r3, r2
8005fc8: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8005fca: 68fb ldr r3, [r7, #12]
8005fcc: 693a ldr r2, [r7, #16]
8005fce: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005fd0: 68fb ldr r3, [r7, #12]
8005fd2: 697a ldr r2, [r7, #20]
8005fd4: 621a str r2, [r3, #32]
}
8005fd6: bf00 nop
8005fd8: 371c adds r7, #28
8005fda: 46bd mov sp, r7
8005fdc: f85d 7b04 ldr.w r7, [sp], #4
8005fe0: 4770 bx lr
08005fe2 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005fe2: b480 push {r7}
8005fe4: b087 sub sp, #28
8005fe6: af00 add r7, sp, #0
8005fe8: 60f8 str r0, [r7, #12]
8005fea: 60b9 str r1, [r7, #8]
8005fec: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8005fee: 68fb ldr r3, [r7, #12]
8005ff0: 6a1b ldr r3, [r3, #32]
8005ff2: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8005ff4: 68fb ldr r3, [r7, #12]
8005ff6: 6a1b ldr r3, [r3, #32]
8005ff8: f023 0210 bic.w r2, r3, #16
8005ffc: 68fb ldr r3, [r7, #12]
8005ffe: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8006000: 68fb ldr r3, [r7, #12]
8006002: 699b ldr r3, [r3, #24]
8006004: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8006006: 693b ldr r3, [r7, #16]
8006008: f423 4370 bic.w r3, r3, #61440 @ 0xf000
800600c: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
800600e: 687b ldr r3, [r7, #4]
8006010: 031b lsls r3, r3, #12
8006012: 693a ldr r2, [r7, #16]
8006014: 4313 orrs r3, r2
8006016: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8006018: 697b ldr r3, [r7, #20]
800601a: f023 03a0 bic.w r3, r3, #160 @ 0xa0
800601e: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8006020: 68bb ldr r3, [r7, #8]
8006022: 011b lsls r3, r3, #4
8006024: 697a ldr r2, [r7, #20]
8006026: 4313 orrs r3, r2
8006028: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800602a: 68fb ldr r3, [r7, #12]
800602c: 693a ldr r2, [r7, #16]
800602e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8006030: 68fb ldr r3, [r7, #12]
8006032: 697a ldr r2, [r7, #20]
8006034: 621a str r2, [r3, #32]
}
8006036: bf00 nop
8006038: 371c adds r7, #28
800603a: 46bd mov sp, r7
800603c: f85d 7b04 ldr.w r7, [sp], #4
8006040: 4770 bx lr
08006042 <TIM_ITRx_SetConfig>:
* (*) Value not defined in all devices.
*
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8006042: b480 push {r7}
8006044: b085 sub sp, #20
8006046: af00 add r7, sp, #0
8006048: 6078 str r0, [r7, #4]
800604a: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
800604c: 687b ldr r3, [r7, #4]
800604e: 689b ldr r3, [r3, #8]
8006050: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8006052: 68fb ldr r3, [r7, #12]
8006054: f423 1340 bic.w r3, r3, #3145728 @ 0x300000
8006058: f023 0370 bic.w r3, r3, #112 @ 0x70
800605c: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800605e: 683a ldr r2, [r7, #0]
8006060: 68fb ldr r3, [r7, #12]
8006062: 4313 orrs r3, r2
8006064: f043 0307 orr.w r3, r3, #7
8006068: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800606a: 687b ldr r3, [r7, #4]
800606c: 68fa ldr r2, [r7, #12]
800606e: 609a str r2, [r3, #8]
}
8006070: bf00 nop
8006072: 3714 adds r7, #20
8006074: 46bd mov sp, r7
8006076: f85d 7b04 ldr.w r7, [sp], #4
800607a: 4770 bx lr
0800607c <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800607c: b480 push {r7}
800607e: b087 sub sp, #28
8006080: af00 add r7, sp, #0
8006082: 60f8 str r0, [r7, #12]
8006084: 60b9 str r1, [r7, #8]
8006086: 607a str r2, [r7, #4]
8006088: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800608a: 68fb ldr r3, [r7, #12]
800608c: 689b ldr r3, [r3, #8]
800608e: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8006090: 697b ldr r3, [r7, #20]
8006092: f423 437f bic.w r3, r3, #65280 @ 0xff00
8006096: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8006098: 683b ldr r3, [r7, #0]
800609a: 021a lsls r2, r3, #8
800609c: 687b ldr r3, [r7, #4]
800609e: 431a orrs r2, r3
80060a0: 68bb ldr r3, [r7, #8]
80060a2: 4313 orrs r3, r2
80060a4: 697a ldr r2, [r7, #20]
80060a6: 4313 orrs r3, r2
80060a8: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80060aa: 68fb ldr r3, [r7, #12]
80060ac: 697a ldr r2, [r7, #20]
80060ae: 609a str r2, [r3, #8]
}
80060b0: bf00 nop
80060b2: 371c adds r7, #28
80060b4: 46bd mov sp, r7
80060b6: f85d 7b04 ldr.w r7, [sp], #4
80060ba: 4770 bx lr
080060bc <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
80060bc: b480 push {r7}
80060be: b087 sub sp, #28
80060c0: af00 add r7, sp, #0
80060c2: 60f8 str r0, [r7, #12]
80060c4: 60b9 str r1, [r7, #8]
80060c6: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
80060c8: 68bb ldr r3, [r7, #8]
80060ca: f003 031f and.w r3, r3, #31
80060ce: 2201 movs r2, #1
80060d0: fa02 f303 lsl.w r3, r2, r3
80060d4: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
80060d6: 68fb ldr r3, [r7, #12]
80060d8: 6a1a ldr r2, [r3, #32]
80060da: 697b ldr r3, [r7, #20]
80060dc: 43db mvns r3, r3
80060de: 401a ands r2, r3
80060e0: 68fb ldr r3, [r7, #12]
80060e2: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
80060e4: 68fb ldr r3, [r7, #12]
80060e6: 6a1a ldr r2, [r3, #32]
80060e8: 68bb ldr r3, [r7, #8]
80060ea: f003 031f and.w r3, r3, #31
80060ee: 6879 ldr r1, [r7, #4]
80060f0: fa01 f303 lsl.w r3, r1, r3
80060f4: 431a orrs r2, r3
80060f6: 68fb ldr r3, [r7, #12]
80060f8: 621a str r2, [r3, #32]
}
80060fa: bf00 nop
80060fc: 371c adds r7, #28
80060fe: 46bd mov sp, r7
8006100: f85d 7b04 ldr.w r7, [sp], #4
8006104: 4770 bx lr
...
08006108 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8006108: b480 push {r7}
800610a: b085 sub sp, #20
800610c: af00 add r7, sp, #0
800610e: 6078 str r0, [r7, #4]
8006110: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8006112: 687b ldr r3, [r7, #4]
8006114: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8006118: 2b01 cmp r3, #1
800611a: d101 bne.n 8006120 <HAL_TIMEx_MasterConfigSynchronization+0x18>
800611c: 2302 movs r3, #2
800611e: e065 b.n 80061ec <HAL_TIMEx_MasterConfigSynchronization+0xe4>
8006120: 687b ldr r3, [r7, #4]
8006122: 2201 movs r2, #1
8006124: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8006128: 687b ldr r3, [r7, #4]
800612a: 2202 movs r2, #2
800612c: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8006130: 687b ldr r3, [r7, #4]
8006132: 681b ldr r3, [r3, #0]
8006134: 685b ldr r3, [r3, #4]
8006136: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8006138: 687b ldr r3, [r7, #4]
800613a: 681b ldr r3, [r3, #0]
800613c: 689b ldr r3, [r3, #8]
800613e: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8006140: 687b ldr r3, [r7, #4]
8006142: 681b ldr r3, [r3, #0]
8006144: 4a2c ldr r2, [pc, #176] @ (80061f8 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8006146: 4293 cmp r3, r2
8006148: d004 beq.n 8006154 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
800614a: 687b ldr r3, [r7, #4]
800614c: 681b ldr r3, [r3, #0]
800614e: 4a2b ldr r2, [pc, #172] @ (80061fc <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8006150: 4293 cmp r3, r2
8006152: d108 bne.n 8006166 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8006154: 68fb ldr r3, [r7, #12]
8006156: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
800615a: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
800615c: 683b ldr r3, [r7, #0]
800615e: 685b ldr r3, [r3, #4]
8006160: 68fa ldr r2, [r7, #12]
8006162: 4313 orrs r3, r2
8006164: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8006166: 68fb ldr r3, [r7, #12]
8006168: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000
800616c: f023 0370 bic.w r3, r3, #112 @ 0x70
8006170: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8006172: 683b ldr r3, [r7, #0]
8006174: 681b ldr r3, [r3, #0]
8006176: 68fa ldr r2, [r7, #12]
8006178: 4313 orrs r3, r2
800617a: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800617c: 687b ldr r3, [r7, #4]
800617e: 681b ldr r3, [r3, #0]
8006180: 68fa ldr r2, [r7, #12]
8006182: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8006184: 687b ldr r3, [r7, #4]
8006186: 681b ldr r3, [r3, #0]
8006188: 4a1b ldr r2, [pc, #108] @ (80061f8 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
800618a: 4293 cmp r3, r2
800618c: d018 beq.n 80061c0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
800618e: 687b ldr r3, [r7, #4]
8006190: 681b ldr r3, [r3, #0]
8006192: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8006196: d013 beq.n 80061c0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8006198: 687b ldr r3, [r7, #4]
800619a: 681b ldr r3, [r3, #0]
800619c: 4a18 ldr r2, [pc, #96] @ (8006200 <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
800619e: 4293 cmp r3, r2
80061a0: d00e beq.n 80061c0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
80061a2: 687b ldr r3, [r7, #4]
80061a4: 681b ldr r3, [r3, #0]
80061a6: 4a17 ldr r2, [pc, #92] @ (8006204 <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
80061a8: 4293 cmp r3, r2
80061aa: d009 beq.n 80061c0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
80061ac: 687b ldr r3, [r7, #4]
80061ae: 681b ldr r3, [r3, #0]
80061b0: 4a12 ldr r2, [pc, #72] @ (80061fc <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
80061b2: 4293 cmp r3, r2
80061b4: d004 beq.n 80061c0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
80061b6: 687b ldr r3, [r7, #4]
80061b8: 681b ldr r3, [r3, #0]
80061ba: 4a13 ldr r2, [pc, #76] @ (8006208 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
80061bc: 4293 cmp r3, r2
80061be: d10c bne.n 80061da <HAL_TIMEx_MasterConfigSynchronization+0xd2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
80061c0: 68bb ldr r3, [r7, #8]
80061c2: f023 0380 bic.w r3, r3, #128 @ 0x80
80061c6: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
80061c8: 683b ldr r3, [r7, #0]
80061ca: 689b ldr r3, [r3, #8]
80061cc: 68ba ldr r2, [r7, #8]
80061ce: 4313 orrs r3, r2
80061d0: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80061d2: 687b ldr r3, [r7, #4]
80061d4: 681b ldr r3, [r3, #0]
80061d6: 68ba ldr r2, [r7, #8]
80061d8: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
80061da: 687b ldr r3, [r7, #4]
80061dc: 2201 movs r2, #1
80061de: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
80061e2: 687b ldr r3, [r7, #4]
80061e4: 2200 movs r2, #0
80061e6: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80061ea: 2300 movs r3, #0
}
80061ec: 4618 mov r0, r3
80061ee: 3714 adds r7, #20
80061f0: 46bd mov sp, r7
80061f2: f85d 7b04 ldr.w r7, [sp], #4
80061f6: 4770 bx lr
80061f8: 40012c00 .word 0x40012c00
80061fc: 40013400 .word 0x40013400
8006200: 40000400 .word 0x40000400
8006204: 40000800 .word 0x40000800
8006208: 40014000 .word 0x40014000
0800620c <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
800620c: b480 push {r7}
800620e: b085 sub sp, #20
8006210: af00 add r7, sp, #0
8006212: 6078 str r0, [r7, #4]
8006214: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8006216: 2300 movs r3, #0
8006218: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Check input state */
__HAL_LOCK(htim);
800621a: 687b ldr r3, [r7, #4]
800621c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8006220: 2b01 cmp r3, #1
8006222: d101 bne.n 8006228 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8006224: 2302 movs r3, #2
8006226: e073 b.n 8006310 <HAL_TIMEx_ConfigBreakDeadTime+0x104>
8006228: 687b ldr r3, [r7, #4]
800622a: 2201 movs r2, #1
800622c: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8006230: 68fb ldr r3, [r7, #12]
8006232: f023 02ff bic.w r2, r3, #255 @ 0xff
8006236: 683b ldr r3, [r7, #0]
8006238: 68db ldr r3, [r3, #12]
800623a: 4313 orrs r3, r2
800623c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
800623e: 68fb ldr r3, [r7, #12]
8006240: f423 7240 bic.w r2, r3, #768 @ 0x300
8006244: 683b ldr r3, [r7, #0]
8006246: 689b ldr r3, [r3, #8]
8006248: 4313 orrs r3, r2
800624a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
800624c: 68fb ldr r3, [r7, #12]
800624e: f423 6280 bic.w r2, r3, #1024 @ 0x400
8006252: 683b ldr r3, [r7, #0]
8006254: 685b ldr r3, [r3, #4]
8006256: 4313 orrs r3, r2
8006258: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
800625a: 68fb ldr r3, [r7, #12]
800625c: f423 6200 bic.w r2, r3, #2048 @ 0x800
8006260: 683b ldr r3, [r7, #0]
8006262: 681b ldr r3, [r3, #0]
8006264: 4313 orrs r3, r2
8006266: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8006268: 68fb ldr r3, [r7, #12]
800626a: f423 5280 bic.w r2, r3, #4096 @ 0x1000
800626e: 683b ldr r3, [r7, #0]
8006270: 691b ldr r3, [r3, #16]
8006272: 4313 orrs r3, r2
8006274: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8006276: 68fb ldr r3, [r7, #12]
8006278: f423 5200 bic.w r2, r3, #8192 @ 0x2000
800627c: 683b ldr r3, [r7, #0]
800627e: 695b ldr r3, [r3, #20]
8006280: 4313 orrs r3, r2
8006282: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8006284: 68fb ldr r3, [r7, #12]
8006286: f423 4280 bic.w r2, r3, #16384 @ 0x4000
800628a: 683b ldr r3, [r7, #0]
800628c: 6b1b ldr r3, [r3, #48] @ 0x30
800628e: 4313 orrs r3, r2
8006290: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
8006292: 68fb ldr r3, [r7, #12]
8006294: f423 2270 bic.w r2, r3, #983040 @ 0xf0000
8006298: 683b ldr r3, [r7, #0]
800629a: 699b ldr r3, [r3, #24]
800629c: 041b lsls r3, r3, #16
800629e: 4313 orrs r3, r2
80062a0: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
80062a2: 68fb ldr r3, [r7, #12]
80062a4: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
80062a8: 683b ldr r3, [r7, #0]
80062aa: 69db ldr r3, [r3, #28]
80062ac: 4313 orrs r3, r2
80062ae: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
80062b0: 687b ldr r3, [r7, #4]
80062b2: 681b ldr r3, [r3, #0]
80062b4: 4a19 ldr r2, [pc, #100] @ (800631c <HAL_TIMEx_ConfigBreakDeadTime+0x110>)
80062b6: 4293 cmp r3, r2
80062b8: d004 beq.n 80062c4 <HAL_TIMEx_ConfigBreakDeadTime+0xb8>
80062ba: 687b ldr r3, [r7, #4]
80062bc: 681b ldr r3, [r3, #0]
80062be: 4a18 ldr r2, [pc, #96] @ (8006320 <HAL_TIMEx_ConfigBreakDeadTime+0x114>)
80062c0: 4293 cmp r3, r2
80062c2: d11c bne.n 80062fe <HAL_TIMEx_ConfigBreakDeadTime+0xf2>
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
80062c4: 68fb ldr r3, [r7, #12]
80062c6: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000
80062ca: 683b ldr r3, [r7, #0]
80062cc: 6a9b ldr r3, [r3, #40] @ 0x28
80062ce: 051b lsls r3, r3, #20
80062d0: 4313 orrs r3, r2
80062d2: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
80062d4: 68fb ldr r3, [r7, #12]
80062d6: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
80062da: 683b ldr r3, [r7, #0]
80062dc: 6a1b ldr r3, [r3, #32]
80062de: 4313 orrs r3, r2
80062e0: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
80062e2: 68fb ldr r3, [r7, #12]
80062e4: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
80062e8: 683b ldr r3, [r7, #0]
80062ea: 6a5b ldr r3, [r3, #36] @ 0x24
80062ec: 4313 orrs r3, r2
80062ee: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
80062f0: 68fb ldr r3, [r7, #12]
80062f2: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
80062f6: 683b ldr r3, [r7, #0]
80062f8: 6adb ldr r3, [r3, #44] @ 0x2c
80062fa: 4313 orrs r3, r2
80062fc: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
80062fe: 687b ldr r3, [r7, #4]
8006300: 681b ldr r3, [r3, #0]
8006302: 68fa ldr r2, [r7, #12]
8006304: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
8006306: 687b ldr r3, [r7, #4]
8006308: 2200 movs r2, #0
800630a: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
800630e: 2300 movs r3, #0
}
8006310: 4618 mov r0, r3
8006312: 3714 adds r7, #20
8006314: 46bd mov sp, r7
8006316: f85d 7b04 ldr.w r7, [sp], #4
800631a: 4770 bx lr
800631c: 40012c00 .word 0x40012c00
8006320: 40013400 .word 0x40013400
08006324 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8006324: b480 push {r7}
8006326: b083 sub sp, #12
8006328: af00 add r7, sp, #0
800632a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800632c: bf00 nop
800632e: 370c adds r7, #12
8006330: 46bd mov sp, r7
8006332: f85d 7b04 ldr.w r7, [sp], #4
8006336: 4770 bx lr
08006338 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8006338: b480 push {r7}
800633a: b083 sub sp, #12
800633c: af00 add r7, sp, #0
800633e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8006340: bf00 nop
8006342: 370c adds r7, #12
8006344: 46bd mov sp, r7
8006346: f85d 7b04 ldr.w r7, [sp], #4
800634a: 4770 bx lr
0800634c <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
800634c: b480 push {r7}
800634e: b083 sub sp, #12
8006350: af00 add r7, sp, #0
8006352: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8006354: bf00 nop
8006356: 370c adds r7, #12
8006358: 46bd mov sp, r7
800635a: f85d 7b04 ldr.w r7, [sp], #4
800635e: 4770 bx lr
08006360 <HAL_TIMEx_EncoderIndexCallback>:
* @brief Encoder index callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
{
8006360: b480 push {r7}
8006362: b083 sub sp, #12
8006364: af00 add r7, sp, #0
8006366: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
*/
}
8006368: bf00 nop
800636a: 370c adds r7, #12
800636c: 46bd mov sp, r7
800636e: f85d 7b04 ldr.w r7, [sp], #4
8006372: 4770 bx lr
08006374 <HAL_TIMEx_DirectionChangeCallback>:
* @brief Direction change callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
{
8006374: b480 push {r7}
8006376: b083 sub sp, #12
8006378: af00 add r7, sp, #0
800637a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
*/
}
800637c: bf00 nop
800637e: 370c adds r7, #12
8006380: 46bd mov sp, r7
8006382: f85d 7b04 ldr.w r7, [sp], #4
8006386: 4770 bx lr
08006388 <HAL_TIMEx_IndexErrorCallback>:
* @brief Index error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
{
8006388: b480 push {r7}
800638a: b083 sub sp, #12
800638c: af00 add r7, sp, #0
800638e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
*/
}
8006390: bf00 nop
8006392: 370c adds r7, #12
8006394: 46bd mov sp, r7
8006396: f85d 7b04 ldr.w r7, [sp], #4
800639a: 4770 bx lr
0800639c <HAL_TIMEx_TransitionErrorCallback>:
* @brief Transition error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
{
800639c: b480 push {r7}
800639e: b083 sub sp, #12
80063a0: af00 add r7, sp, #0
80063a2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
*/
}
80063a4: bf00 nop
80063a6: 370c adds r7, #12
80063a8: 46bd mov sp, r7
80063aa: f85d 7b04 ldr.w r7, [sp], #4
80063ae: 4770 bx lr
080063b0 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80063b0: b580 push {r7, lr}
80063b2: b082 sub sp, #8
80063b4: af00 add r7, sp, #0
80063b6: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80063b8: 687b ldr r3, [r7, #4]
80063ba: 2b00 cmp r3, #0
80063bc: d101 bne.n 80063c2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80063be: 2301 movs r3, #1
80063c0: e042 b.n 8006448 <HAL_UART_Init+0x98>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
80063c2: 687b ldr r3, [r7, #4]
80063c4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80063c8: 2b00 cmp r3, #0
80063ca: d106 bne.n 80063da <HAL_UART_Init+0x2a>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80063cc: 687b ldr r3, [r7, #4]
80063ce: 2200 movs r2, #0
80063d0: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80063d4: 6878 ldr r0, [r7, #4]
80063d6: f7fb fbb1 bl 8001b3c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80063da: 687b ldr r3, [r7, #4]
80063dc: 2224 movs r2, #36 @ 0x24
80063de: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UART_DISABLE(huart);
80063e2: 687b ldr r3, [r7, #4]
80063e4: 681b ldr r3, [r3, #0]
80063e6: 681a ldr r2, [r3, #0]
80063e8: 687b ldr r3, [r7, #4]
80063ea: 681b ldr r3, [r3, #0]
80063ec: f022 0201 bic.w r2, r2, #1
80063f0: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80063f2: 687b ldr r3, [r7, #4]
80063f4: 6a9b ldr r3, [r3, #40] @ 0x28
80063f6: 2b00 cmp r3, #0
80063f8: d002 beq.n 8006400 <HAL_UART_Init+0x50>
{
UART_AdvFeatureConfig(huart);
80063fa: 6878 ldr r0, [r7, #4]
80063fc: f000 ff26 bl 800724c <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8006400: 6878 ldr r0, [r7, #4]
8006402: f000 fc57 bl 8006cb4 <UART_SetConfig>
8006406: 4603 mov r3, r0
8006408: 2b01 cmp r3, #1
800640a: d101 bne.n 8006410 <HAL_UART_Init+0x60>
{
return HAL_ERROR;
800640c: 2301 movs r3, #1
800640e: e01b b.n 8006448 <HAL_UART_Init+0x98>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8006410: 687b ldr r3, [r7, #4]
8006412: 681b ldr r3, [r3, #0]
8006414: 685a ldr r2, [r3, #4]
8006416: 687b ldr r3, [r7, #4]
8006418: 681b ldr r3, [r3, #0]
800641a: f422 4290 bic.w r2, r2, #18432 @ 0x4800
800641e: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8006420: 687b ldr r3, [r7, #4]
8006422: 681b ldr r3, [r3, #0]
8006424: 689a ldr r2, [r3, #8]
8006426: 687b ldr r3, [r7, #4]
8006428: 681b ldr r3, [r3, #0]
800642a: f022 022a bic.w r2, r2, #42 @ 0x2a
800642e: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8006430: 687b ldr r3, [r7, #4]
8006432: 681b ldr r3, [r3, #0]
8006434: 681a ldr r2, [r3, #0]
8006436: 687b ldr r3, [r7, #4]
8006438: 681b ldr r3, [r3, #0]
800643a: f042 0201 orr.w r2, r2, #1
800643e: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8006440: 6878 ldr r0, [r7, #4]
8006442: f000 ffa5 bl 8007390 <UART_CheckIdleState>
8006446: 4603 mov r3, r0
}
8006448: 4618 mov r0, r3
800644a: 3708 adds r7, #8
800644c: 46bd mov sp, r7
800644e: bd80 pop {r7, pc}
08006450 <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8006450: b580 push {r7, lr}
8006452: b08a sub sp, #40 @ 0x28
8006454: af02 add r7, sp, #8
8006456: 60f8 str r0, [r7, #12]
8006458: 60b9 str r1, [r7, #8]
800645a: 603b str r3, [r7, #0]
800645c: 4613 mov r3, r2
800645e: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8006460: 68fb ldr r3, [r7, #12]
8006462: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006466: 2b20 cmp r3, #32
8006468: d17b bne.n 8006562 <HAL_UART_Transmit+0x112>
{
if ((pData == NULL) || (Size == 0U))
800646a: 68bb ldr r3, [r7, #8]
800646c: 2b00 cmp r3, #0
800646e: d002 beq.n 8006476 <HAL_UART_Transmit+0x26>
8006470: 88fb ldrh r3, [r7, #6]
8006472: 2b00 cmp r3, #0
8006474: d101 bne.n 800647a <HAL_UART_Transmit+0x2a>
{
return HAL_ERROR;
8006476: 2301 movs r3, #1
8006478: e074 b.n 8006564 <HAL_UART_Transmit+0x114>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
800647a: 68fb ldr r3, [r7, #12]
800647c: 2200 movs r2, #0
800647e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
huart->gState = HAL_UART_STATE_BUSY_TX;
8006482: 68fb ldr r3, [r7, #12]
8006484: 2221 movs r2, #33 @ 0x21
8006486: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800648a: f7fb fc9b bl 8001dc4 <HAL_GetTick>
800648e: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8006490: 68fb ldr r3, [r7, #12]
8006492: 88fa ldrh r2, [r7, #6]
8006494: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
huart->TxXferCount = Size;
8006498: 68fb ldr r3, [r7, #12]
800649a: 88fa ldrh r2, [r7, #6]
800649c: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80064a0: 68fb ldr r3, [r7, #12]
80064a2: 689b ldr r3, [r3, #8]
80064a4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80064a8: d108 bne.n 80064bc <HAL_UART_Transmit+0x6c>
80064aa: 68fb ldr r3, [r7, #12]
80064ac: 691b ldr r3, [r3, #16]
80064ae: 2b00 cmp r3, #0
80064b0: d104 bne.n 80064bc <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
80064b2: 2300 movs r3, #0
80064b4: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
80064b6: 68bb ldr r3, [r7, #8]
80064b8: 61bb str r3, [r7, #24]
80064ba: e003 b.n 80064c4 <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
80064bc: 68bb ldr r3, [r7, #8]
80064be: 61fb str r3, [r7, #28]
pdata16bits = NULL;
80064c0: 2300 movs r3, #0
80064c2: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
80064c4: e030 b.n 8006528 <HAL_UART_Transmit+0xd8>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
80064c6: 683b ldr r3, [r7, #0]
80064c8: 9300 str r3, [sp, #0]
80064ca: 697b ldr r3, [r7, #20]
80064cc: 2200 movs r2, #0
80064ce: 2180 movs r1, #128 @ 0x80
80064d0: 68f8 ldr r0, [r7, #12]
80064d2: f001 f807 bl 80074e4 <UART_WaitOnFlagUntilTimeout>
80064d6: 4603 mov r3, r0
80064d8: 2b00 cmp r3, #0
80064da: d005 beq.n 80064e8 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
80064dc: 68fb ldr r3, [r7, #12]
80064de: 2220 movs r2, #32
80064e0: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
80064e4: 2303 movs r3, #3
80064e6: e03d b.n 8006564 <HAL_UART_Transmit+0x114>
}
if (pdata8bits == NULL)
80064e8: 69fb ldr r3, [r7, #28]
80064ea: 2b00 cmp r3, #0
80064ec: d10b bne.n 8006506 <HAL_UART_Transmit+0xb6>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
80064ee: 69bb ldr r3, [r7, #24]
80064f0: 881b ldrh r3, [r3, #0]
80064f2: 461a mov r2, r3
80064f4: 68fb ldr r3, [r7, #12]
80064f6: 681b ldr r3, [r3, #0]
80064f8: f3c2 0208 ubfx r2, r2, #0, #9
80064fc: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
80064fe: 69bb ldr r3, [r7, #24]
8006500: 3302 adds r3, #2
8006502: 61bb str r3, [r7, #24]
8006504: e007 b.n 8006516 <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8006506: 69fb ldr r3, [r7, #28]
8006508: 781a ldrb r2, [r3, #0]
800650a: 68fb ldr r3, [r7, #12]
800650c: 681b ldr r3, [r3, #0]
800650e: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
8006510: 69fb ldr r3, [r7, #28]
8006512: 3301 adds r3, #1
8006514: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8006516: 68fb ldr r3, [r7, #12]
8006518: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
800651c: b29b uxth r3, r3
800651e: 3b01 subs r3, #1
8006520: b29a uxth r2, r3
8006522: 68fb ldr r3, [r7, #12]
8006524: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
while (huart->TxXferCount > 0U)
8006528: 68fb ldr r3, [r7, #12]
800652a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
800652e: b29b uxth r3, r3
8006530: 2b00 cmp r3, #0
8006532: d1c8 bne.n 80064c6 <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8006534: 683b ldr r3, [r7, #0]
8006536: 9300 str r3, [sp, #0]
8006538: 697b ldr r3, [r7, #20]
800653a: 2200 movs r2, #0
800653c: 2140 movs r1, #64 @ 0x40
800653e: 68f8 ldr r0, [r7, #12]
8006540: f000 ffd0 bl 80074e4 <UART_WaitOnFlagUntilTimeout>
8006544: 4603 mov r3, r0
8006546: 2b00 cmp r3, #0
8006548: d005 beq.n 8006556 <HAL_UART_Transmit+0x106>
{
huart->gState = HAL_UART_STATE_READY;
800654a: 68fb ldr r3, [r7, #12]
800654c: 2220 movs r2, #32
800654e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
8006552: 2303 movs r3, #3
8006554: e006 b.n 8006564 <HAL_UART_Transmit+0x114>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8006556: 68fb ldr r3, [r7, #12]
8006558: 2220 movs r2, #32
800655a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_OK;
800655e: 2300 movs r3, #0
8006560: e000 b.n 8006564 <HAL_UART_Transmit+0x114>
}
else
{
return HAL_BUSY;
8006562: 2302 movs r3, #2
}
}
8006564: 4618 mov r0, r3
8006566: 3720 adds r7, #32
8006568: 46bd mov sp, r7
800656a: bd80 pop {r7, pc}
0800656c <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
800656c: b580 push {r7, lr}
800656e: b08a sub sp, #40 @ 0x28
8006570: af00 add r7, sp, #0
8006572: 60f8 str r0, [r7, #12]
8006574: 60b9 str r1, [r7, #8]
8006576: 4613 mov r3, r2
8006578: 80fb strh r3, [r7, #6]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
800657a: 68fb ldr r3, [r7, #12]
800657c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8006580: 2b20 cmp r3, #32
8006582: d137 bne.n 80065f4 <HAL_UART_Receive_IT+0x88>
{
if ((pData == NULL) || (Size == 0U))
8006584: 68bb ldr r3, [r7, #8]
8006586: 2b00 cmp r3, #0
8006588: d002 beq.n 8006590 <HAL_UART_Receive_IT+0x24>
800658a: 88fb ldrh r3, [r7, #6]
800658c: 2b00 cmp r3, #0
800658e: d101 bne.n 8006594 <HAL_UART_Receive_IT+0x28>
{
return HAL_ERROR;
8006590: 2301 movs r3, #1
8006592: e030 b.n 80065f6 <HAL_UART_Receive_IT+0x8a>
}
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006594: 68fb ldr r3, [r7, #12]
8006596: 2200 movs r2, #0
8006598: 66da str r2, [r3, #108] @ 0x6c
if (!(IS_LPUART_INSTANCE(huart->Instance)))
800659a: 68fb ldr r3, [r7, #12]
800659c: 681b ldr r3, [r3, #0]
800659e: 4a18 ldr r2, [pc, #96] @ (8006600 <HAL_UART_Receive_IT+0x94>)
80065a0: 4293 cmp r3, r2
80065a2: d01f beq.n 80065e4 <HAL_UART_Receive_IT+0x78>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
80065a4: 68fb ldr r3, [r7, #12]
80065a6: 681b ldr r3, [r3, #0]
80065a8: 685b ldr r3, [r3, #4]
80065aa: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80065ae: 2b00 cmp r3, #0
80065b0: d018 beq.n 80065e4 <HAL_UART_Receive_IT+0x78>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
80065b2: 68fb ldr r3, [r7, #12]
80065b4: 681b ldr r3, [r3, #0]
80065b6: 617b str r3, [r7, #20]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80065b8: 697b ldr r3, [r7, #20]
80065ba: e853 3f00 ldrex r3, [r3]
80065be: 613b str r3, [r7, #16]
return(result);
80065c0: 693b ldr r3, [r7, #16]
80065c2: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
80065c6: 627b str r3, [r7, #36] @ 0x24
80065c8: 68fb ldr r3, [r7, #12]
80065ca: 681b ldr r3, [r3, #0]
80065cc: 461a mov r2, r3
80065ce: 6a7b ldr r3, [r7, #36] @ 0x24
80065d0: 623b str r3, [r7, #32]
80065d2: 61fa str r2, [r7, #28]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80065d4: 69f9 ldr r1, [r7, #28]
80065d6: 6a3a ldr r2, [r7, #32]
80065d8: e841 2300 strex r3, r2, [r1]
80065dc: 61bb str r3, [r7, #24]
return(result);
80065de: 69bb ldr r3, [r7, #24]
80065e0: 2b00 cmp r3, #0
80065e2: d1e6 bne.n 80065b2 <HAL_UART_Receive_IT+0x46>
}
}
return (UART_Start_Receive_IT(huart, pData, Size));
80065e4: 88fb ldrh r3, [r7, #6]
80065e6: 461a mov r2, r3
80065e8: 68b9 ldr r1, [r7, #8]
80065ea: 68f8 ldr r0, [r7, #12]
80065ec: f000 ffe8 bl 80075c0 <UART_Start_Receive_IT>
80065f0: 4603 mov r3, r0
80065f2: e000 b.n 80065f6 <HAL_UART_Receive_IT+0x8a>
}
else
{
return HAL_BUSY;
80065f4: 2302 movs r3, #2
}
}
80065f6: 4618 mov r0, r3
80065f8: 3728 adds r7, #40 @ 0x28
80065fa: 46bd mov sp, r7
80065fc: bd80 pop {r7, pc}
80065fe: bf00 nop
8006600: 40008000 .word 0x40008000
08006604 <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8006604: b580 push {r7, lr}
8006606: b0ba sub sp, #232 @ 0xe8
8006608: af00 add r7, sp, #0
800660a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
800660c: 687b ldr r3, [r7, #4]
800660e: 681b ldr r3, [r3, #0]
8006610: 69db ldr r3, [r3, #28]
8006612: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8006616: 687b ldr r3, [r7, #4]
8006618: 681b ldr r3, [r3, #0]
800661a: 681b ldr r3, [r3, #0]
800661c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8006620: 687b ldr r3, [r7, #4]
8006622: 681b ldr r3, [r3, #0]
8006624: 689b ldr r3, [r3, #8]
8006626: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
800662a: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
800662e: f640 030f movw r3, #2063 @ 0x80f
8006632: 4013 ands r3, r2
8006634: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (errorflags == 0U)
8006638: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
800663c: 2b00 cmp r3, #0
800663e: d11b bne.n 8006678 <HAL_UART_IRQHandler+0x74>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
8006640: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006644: f003 0320 and.w r3, r3, #32
8006648: 2b00 cmp r3, #0
800664a: d015 beq.n 8006678 <HAL_UART_IRQHandler+0x74>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
800664c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006650: f003 0320 and.w r3, r3, #32
8006654: 2b00 cmp r3, #0
8006656: d105 bne.n 8006664 <HAL_UART_IRQHandler+0x60>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8006658: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
800665c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8006660: 2b00 cmp r3, #0
8006662: d009 beq.n 8006678 <HAL_UART_IRQHandler+0x74>
{
if (huart->RxISR != NULL)
8006664: 687b ldr r3, [r7, #4]
8006666: 6f5b ldr r3, [r3, #116] @ 0x74
8006668: 2b00 cmp r3, #0
800666a: f000 8300 beq.w 8006c6e <HAL_UART_IRQHandler+0x66a>
{
huart->RxISR(huart);
800666e: 687b ldr r3, [r7, #4]
8006670: 6f5b ldr r3, [r3, #116] @ 0x74
8006672: 6878 ldr r0, [r7, #4]
8006674: 4798 blx r3
}
return;
8006676: e2fa b.n 8006c6e <HAL_UART_IRQHandler+0x66a>
}
}
/* If some errors occur */
if ((errorflags != 0U)
8006678: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
800667c: 2b00 cmp r3, #0
800667e: f000 8123 beq.w 80068c8 <HAL_UART_IRQHandler+0x2c4>
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
8006682: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
8006686: 4b8d ldr r3, [pc, #564] @ (80068bc <HAL_UART_IRQHandler+0x2b8>)
8006688: 4013 ands r3, r2
800668a: 2b00 cmp r3, #0
800668c: d106 bne.n 800669c <HAL_UART_IRQHandler+0x98>
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
800668e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
8006692: 4b8b ldr r3, [pc, #556] @ (80068c0 <HAL_UART_IRQHandler+0x2bc>)
8006694: 4013 ands r3, r2
8006696: 2b00 cmp r3, #0
8006698: f000 8116 beq.w 80068c8 <HAL_UART_IRQHandler+0x2c4>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
800669c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80066a0: f003 0301 and.w r3, r3, #1
80066a4: 2b00 cmp r3, #0
80066a6: d011 beq.n 80066cc <HAL_UART_IRQHandler+0xc8>
80066a8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80066ac: f403 7380 and.w r3, r3, #256 @ 0x100
80066b0: 2b00 cmp r3, #0
80066b2: d00b beq.n 80066cc <HAL_UART_IRQHandler+0xc8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
80066b4: 687b ldr r3, [r7, #4]
80066b6: 681b ldr r3, [r3, #0]
80066b8: 2201 movs r2, #1
80066ba: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
80066bc: 687b ldr r3, [r7, #4]
80066be: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80066c2: f043 0201 orr.w r2, r3, #1
80066c6: 687b ldr r3, [r7, #4]
80066c8: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80066cc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80066d0: f003 0302 and.w r3, r3, #2
80066d4: 2b00 cmp r3, #0
80066d6: d011 beq.n 80066fc <HAL_UART_IRQHandler+0xf8>
80066d8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80066dc: f003 0301 and.w r3, r3, #1
80066e0: 2b00 cmp r3, #0
80066e2: d00b beq.n 80066fc <HAL_UART_IRQHandler+0xf8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
80066e4: 687b ldr r3, [r7, #4]
80066e6: 681b ldr r3, [r3, #0]
80066e8: 2202 movs r2, #2
80066ea: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
80066ec: 687b ldr r3, [r7, #4]
80066ee: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80066f2: f043 0204 orr.w r2, r3, #4
80066f6: 687b ldr r3, [r7, #4]
80066f8: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80066fc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006700: f003 0304 and.w r3, r3, #4
8006704: 2b00 cmp r3, #0
8006706: d011 beq.n 800672c <HAL_UART_IRQHandler+0x128>
8006708: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
800670c: f003 0301 and.w r3, r3, #1
8006710: 2b00 cmp r3, #0
8006712: d00b beq.n 800672c <HAL_UART_IRQHandler+0x128>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8006714: 687b ldr r3, [r7, #4]
8006716: 681b ldr r3, [r3, #0]
8006718: 2204 movs r2, #4
800671a: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
800671c: 687b ldr r3, [r7, #4]
800671e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006722: f043 0202 orr.w r2, r3, #2
8006726: 687b ldr r3, [r7, #4]
8006728: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U)
800672c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006730: f003 0308 and.w r3, r3, #8
8006734: 2b00 cmp r3, #0
8006736: d017 beq.n 8006768 <HAL_UART_IRQHandler+0x164>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
8006738: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800673c: f003 0320 and.w r3, r3, #32
8006740: 2b00 cmp r3, #0
8006742: d105 bne.n 8006750 <HAL_UART_IRQHandler+0x14c>
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
8006744: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
8006748: 4b5c ldr r3, [pc, #368] @ (80068bc <HAL_UART_IRQHandler+0x2b8>)
800674a: 4013 ands r3, r2
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
800674c: 2b00 cmp r3, #0
800674e: d00b beq.n 8006768 <HAL_UART_IRQHandler+0x164>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8006750: 687b ldr r3, [r7, #4]
8006752: 681b ldr r3, [r3, #0]
8006754: 2208 movs r2, #8
8006756: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8006758: 687b ldr r3, [r7, #4]
800675a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800675e: f043 0208 orr.w r2, r3, #8
8006762: 687b ldr r3, [r7, #4]
8006764: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
8006768: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800676c: f403 6300 and.w r3, r3, #2048 @ 0x800
8006770: 2b00 cmp r3, #0
8006772: d012 beq.n 800679a <HAL_UART_IRQHandler+0x196>
8006774: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006778: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
800677c: 2b00 cmp r3, #0
800677e: d00c beq.n 800679a <HAL_UART_IRQHandler+0x196>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8006780: 687b ldr r3, [r7, #4]
8006782: 681b ldr r3, [r3, #0]
8006784: f44f 6200 mov.w r2, #2048 @ 0x800
8006788: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
800678a: 687b ldr r3, [r7, #4]
800678c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006790: f043 0220 orr.w r2, r3, #32
8006794: 687b ldr r3, [r7, #4]
8006796: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800679a: 687b ldr r3, [r7, #4]
800679c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80067a0: 2b00 cmp r3, #0
80067a2: f000 8266 beq.w 8006c72 <HAL_UART_IRQHandler+0x66e>
{
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
80067a6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80067aa: f003 0320 and.w r3, r3, #32
80067ae: 2b00 cmp r3, #0
80067b0: d013 beq.n 80067da <HAL_UART_IRQHandler+0x1d6>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
80067b2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80067b6: f003 0320 and.w r3, r3, #32
80067ba: 2b00 cmp r3, #0
80067bc: d105 bne.n 80067ca <HAL_UART_IRQHandler+0x1c6>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
80067be: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80067c2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80067c6: 2b00 cmp r3, #0
80067c8: d007 beq.n 80067da <HAL_UART_IRQHandler+0x1d6>
{
if (huart->RxISR != NULL)
80067ca: 687b ldr r3, [r7, #4]
80067cc: 6f5b ldr r3, [r3, #116] @ 0x74
80067ce: 2b00 cmp r3, #0
80067d0: d003 beq.n 80067da <HAL_UART_IRQHandler+0x1d6>
{
huart->RxISR(huart);
80067d2: 687b ldr r3, [r7, #4]
80067d4: 6f5b ldr r3, [r3, #116] @ 0x74
80067d6: 6878 ldr r0, [r7, #4]
80067d8: 4798 blx r3
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
80067da: 687b ldr r3, [r7, #4]
80067dc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80067e0: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
80067e4: 687b ldr r3, [r7, #4]
80067e6: 681b ldr r3, [r3, #0]
80067e8: 689b ldr r3, [r3, #8]
80067ea: f003 0340 and.w r3, r3, #64 @ 0x40
80067ee: 2b40 cmp r3, #64 @ 0x40
80067f0: d005 beq.n 80067fe <HAL_UART_IRQHandler+0x1fa>
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
80067f2: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
80067f6: f003 0328 and.w r3, r3, #40 @ 0x28
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
80067fa: 2b00 cmp r3, #0
80067fc: d054 beq.n 80068a8 <HAL_UART_IRQHandler+0x2a4>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
80067fe: 6878 ldr r0, [r7, #4]
8006800: f001 f800 bl 8007804 <UART_EndRxTransfer>
/* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006804: 687b ldr r3, [r7, #4]
8006806: 681b ldr r3, [r3, #0]
8006808: 689b ldr r3, [r3, #8]
800680a: f003 0340 and.w r3, r3, #64 @ 0x40
800680e: 2b40 cmp r3, #64 @ 0x40
8006810: d146 bne.n 80068a0 <HAL_UART_IRQHandler+0x29c>
{
/* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8006812: 687b ldr r3, [r7, #4]
8006814: 681b ldr r3, [r3, #0]
8006816: 3308 adds r3, #8
8006818: f8c7 309c str.w r3, [r7, #156] @ 0x9c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800681c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8006820: e853 3f00 ldrex r3, [r3]
8006824: f8c7 3098 str.w r3, [r7, #152] @ 0x98
return(result);
8006828: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800682c: f023 0340 bic.w r3, r3, #64 @ 0x40
8006830: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8006834: 687b ldr r3, [r7, #4]
8006836: 681b ldr r3, [r3, #0]
8006838: 3308 adds r3, #8
800683a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
800683e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
8006842: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006846: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
800684a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
800684e: e841 2300 strex r3, r2, [r1]
8006852: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return(result);
8006856: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800685a: 2b00 cmp r3, #0
800685c: d1d9 bne.n 8006812 <HAL_UART_IRQHandler+0x20e>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
800685e: 687b ldr r3, [r7, #4]
8006860: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006864: 2b00 cmp r3, #0
8006866: d017 beq.n 8006898 <HAL_UART_IRQHandler+0x294>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8006868: 687b ldr r3, [r7, #4]
800686a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800686e: 4a15 ldr r2, [pc, #84] @ (80068c4 <HAL_UART_IRQHandler+0x2c0>)
8006870: 639a str r2, [r3, #56] @ 0x38
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
8006872: 687b ldr r3, [r7, #4]
8006874: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006878: 4618 mov r0, r3
800687a: f7fd f8d5 bl 8003a28 <HAL_DMA_Abort_IT>
800687e: 4603 mov r3, r0
8006880: 2b00 cmp r3, #0
8006882: d019 beq.n 80068b8 <HAL_UART_IRQHandler+0x2b4>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
8006884: 687b ldr r3, [r7, #4]
8006886: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800688a: 6b9b ldr r3, [r3, #56] @ 0x38
800688c: 687a ldr r2, [r7, #4]
800688e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80
8006892: 4610 mov r0, r2
8006894: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8006896: e00f b.n 80068b8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006898: 6878 ldr r0, [r7, #4]
800689a: f000 f9f5 bl 8006c88 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800689e: e00b b.n 80068b8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80068a0: 6878 ldr r0, [r7, #4]
80068a2: f000 f9f1 bl 8006c88 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80068a6: e007 b.n 80068b8 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80068a8: 6878 ldr r0, [r7, #4]
80068aa: f000 f9ed bl 8006c88 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80068ae: 687b ldr r3, [r7, #4]
80068b0: 2200 movs r2, #0
80068b2: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
return;
80068b6: e1dc b.n 8006c72 <HAL_UART_IRQHandler+0x66e>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80068b8: bf00 nop
return;
80068ba: e1da b.n 8006c72 <HAL_UART_IRQHandler+0x66e>
80068bc: 10000001 .word 0x10000001
80068c0: 04000120 .word 0x04000120
80068c4: 080078d1 .word 0x080078d1
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80068c8: 687b ldr r3, [r7, #4]
80068ca: 6edb ldr r3, [r3, #108] @ 0x6c
80068cc: 2b01 cmp r3, #1
80068ce: f040 8170 bne.w 8006bb2 <HAL_UART_IRQHandler+0x5ae>
&& ((isrflags & USART_ISR_IDLE) != 0U)
80068d2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80068d6: f003 0310 and.w r3, r3, #16
80068da: 2b00 cmp r3, #0
80068dc: f000 8169 beq.w 8006bb2 <HAL_UART_IRQHandler+0x5ae>
&& ((cr1its & USART_ISR_IDLE) != 0U))
80068e0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80068e4: f003 0310 and.w r3, r3, #16
80068e8: 2b00 cmp r3, #0
80068ea: f000 8162 beq.w 8006bb2 <HAL_UART_IRQHandler+0x5ae>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
80068ee: 687b ldr r3, [r7, #4]
80068f0: 681b ldr r3, [r3, #0]
80068f2: 2210 movs r2, #16
80068f4: 621a str r2, [r3, #32]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80068f6: 687b ldr r3, [r7, #4]
80068f8: 681b ldr r3, [r3, #0]
80068fa: 689b ldr r3, [r3, #8]
80068fc: f003 0340 and.w r3, r3, #64 @ 0x40
8006900: 2b40 cmp r3, #64 @ 0x40
8006902: f040 80d8 bne.w 8006ab6 <HAL_UART_IRQHandler+0x4b2>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8006906: 687b ldr r3, [r7, #4]
8006908: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800690c: 681b ldr r3, [r3, #0]
800690e: 685b ldr r3, [r3, #4]
8006910: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
if ((nb_remaining_rx_data > 0U)
8006914: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
8006918: 2b00 cmp r3, #0
800691a: f000 80af beq.w 8006a7c <HAL_UART_IRQHandler+0x478>
&& (nb_remaining_rx_data < huart->RxXferSize))
800691e: 687b ldr r3, [r7, #4]
8006920: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8006924: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8006928: 429a cmp r2, r3
800692a: f080 80a7 bcs.w 8006a7c <HAL_UART_IRQHandler+0x478>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
800692e: 687b ldr r3, [r7, #4]
8006930: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8006934: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
8006938: 687b ldr r3, [r7, #4]
800693a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800693e: 681b ldr r3, [r3, #0]
8006940: 681b ldr r3, [r3, #0]
8006942: f003 0320 and.w r3, r3, #32
8006946: 2b00 cmp r3, #0
8006948: f040 8087 bne.w 8006a5a <HAL_UART_IRQHandler+0x456>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
800694c: 687b ldr r3, [r7, #4]
800694e: 681b ldr r3, [r3, #0]
8006950: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006954: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8006958: e853 3f00 ldrex r3, [r3]
800695c: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return(result);
8006960: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8006964: f423 7380 bic.w r3, r3, #256 @ 0x100
8006968: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
800696c: 687b ldr r3, [r7, #4]
800696e: 681b ldr r3, [r3, #0]
8006970: 461a mov r2, r3
8006972: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8006976: f8c7 3094 str.w r3, [r7, #148] @ 0x94
800697a: f8c7 2090 str.w r2, [r7, #144] @ 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800697e: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
8006982: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
8006986: e841 2300 strex r3, r2, [r1]
800698a: f8c7 308c str.w r3, [r7, #140] @ 0x8c
return(result);
800698e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8006992: 2b00 cmp r3, #0
8006994: d1da bne.n 800694c <HAL_UART_IRQHandler+0x348>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006996: 687b ldr r3, [r7, #4]
8006998: 681b ldr r3, [r3, #0]
800699a: 3308 adds r3, #8
800699c: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800699e: 6f7b ldr r3, [r7, #116] @ 0x74
80069a0: e853 3f00 ldrex r3, [r3]
80069a4: 673b str r3, [r7, #112] @ 0x70
return(result);
80069a6: 6f3b ldr r3, [r7, #112] @ 0x70
80069a8: f023 0301 bic.w r3, r3, #1
80069ac: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80069b0: 687b ldr r3, [r7, #4]
80069b2: 681b ldr r3, [r3, #0]
80069b4: 3308 adds r3, #8
80069b6: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
80069ba: f8c7 2080 str.w r2, [r7, #128] @ 0x80
80069be: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80069c0: 6ff9 ldr r1, [r7, #124] @ 0x7c
80069c2: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
80069c6: e841 2300 strex r3, r2, [r1]
80069ca: 67bb str r3, [r7, #120] @ 0x78
return(result);
80069cc: 6fbb ldr r3, [r7, #120] @ 0x78
80069ce: 2b00 cmp r3, #0
80069d0: d1e1 bne.n 8006996 <HAL_UART_IRQHandler+0x392>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80069d2: 687b ldr r3, [r7, #4]
80069d4: 681b ldr r3, [r3, #0]
80069d6: 3308 adds r3, #8
80069d8: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80069da: 6e3b ldr r3, [r7, #96] @ 0x60
80069dc: e853 3f00 ldrex r3, [r3]
80069e0: 65fb str r3, [r7, #92] @ 0x5c
return(result);
80069e2: 6dfb ldr r3, [r7, #92] @ 0x5c
80069e4: f023 0340 bic.w r3, r3, #64 @ 0x40
80069e8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
80069ec: 687b ldr r3, [r7, #4]
80069ee: 681b ldr r3, [r3, #0]
80069f0: 3308 adds r3, #8
80069f2: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
80069f6: 66fa str r2, [r7, #108] @ 0x6c
80069f8: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80069fa: 6eb9 ldr r1, [r7, #104] @ 0x68
80069fc: 6efa ldr r2, [r7, #108] @ 0x6c
80069fe: e841 2300 strex r3, r2, [r1]
8006a02: 667b str r3, [r7, #100] @ 0x64
return(result);
8006a04: 6e7b ldr r3, [r7, #100] @ 0x64
8006a06: 2b00 cmp r3, #0
8006a08: d1e3 bne.n 80069d2 <HAL_UART_IRQHandler+0x3ce>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006a0a: 687b ldr r3, [r7, #4]
8006a0c: 2220 movs r2, #32
8006a0e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006a12: 687b ldr r3, [r7, #4]
8006a14: 2200 movs r2, #0
8006a16: 66da str r2, [r3, #108] @ 0x6c
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006a18: 687b ldr r3, [r7, #4]
8006a1a: 681b ldr r3, [r3, #0]
8006a1c: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006a1e: 6cfb ldr r3, [r7, #76] @ 0x4c
8006a20: e853 3f00 ldrex r3, [r3]
8006a24: 64bb str r3, [r7, #72] @ 0x48
return(result);
8006a26: 6cbb ldr r3, [r7, #72] @ 0x48
8006a28: f023 0310 bic.w r3, r3, #16
8006a2c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8006a30: 687b ldr r3, [r7, #4]
8006a32: 681b ldr r3, [r3, #0]
8006a34: 461a mov r2, r3
8006a36: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8006a3a: 65bb str r3, [r7, #88] @ 0x58
8006a3c: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006a3e: 6d79 ldr r1, [r7, #84] @ 0x54
8006a40: 6dba ldr r2, [r7, #88] @ 0x58
8006a42: e841 2300 strex r3, r2, [r1]
8006a46: 653b str r3, [r7, #80] @ 0x50
return(result);
8006a48: 6d3b ldr r3, [r7, #80] @ 0x50
8006a4a: 2b00 cmp r3, #0
8006a4c: d1e4 bne.n 8006a18 <HAL_UART_IRQHandler+0x414>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8006a4e: 687b ldr r3, [r7, #4]
8006a50: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006a54: 4618 mov r0, r3
8006a56: f7fc ff8e bl 8003976 <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006a5a: 687b ldr r3, [r7, #4]
8006a5c: 2202 movs r2, #2
8006a5e: 671a str r2, [r3, #112] @ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8006a60: 687b ldr r3, [r7, #4]
8006a62: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
8006a66: 687b ldr r3, [r7, #4]
8006a68: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8006a6c: b29b uxth r3, r3
8006a6e: 1ad3 subs r3, r2, r3
8006a70: b29b uxth r3, r3
8006a72: 4619 mov r1, r3
8006a74: 6878 ldr r0, [r7, #4]
8006a76: f000 f911 bl 8006c9c <HAL_UARTEx_RxEventCallback>
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
}
}
return;
8006a7a: e0fc b.n 8006c76 <HAL_UART_IRQHandler+0x672>
if (nb_remaining_rx_data == huart->RxXferSize)
8006a7c: 687b ldr r3, [r7, #4]
8006a7e: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8006a82: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8006a86: 429a cmp r2, r3
8006a88: f040 80f5 bne.w 8006c76 <HAL_UART_IRQHandler+0x672>
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
8006a8c: 687b ldr r3, [r7, #4]
8006a8e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006a92: 681b ldr r3, [r3, #0]
8006a94: 681b ldr r3, [r3, #0]
8006a96: f003 0320 and.w r3, r3, #32
8006a9a: 2b20 cmp r3, #32
8006a9c: f040 80eb bne.w 8006c76 <HAL_UART_IRQHandler+0x672>
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006aa0: 687b ldr r3, [r7, #4]
8006aa2: 2202 movs r2, #2
8006aa4: 671a str r2, [r3, #112] @ 0x70
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006aa6: 687b ldr r3, [r7, #4]
8006aa8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8006aac: 4619 mov r1, r3
8006aae: 6878 ldr r0, [r7, #4]
8006ab0: f000 f8f4 bl 8006c9c <HAL_UARTEx_RxEventCallback>
return;
8006ab4: e0df b.n 8006c76 <HAL_UART_IRQHandler+0x672>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8006ab6: 687b ldr r3, [r7, #4]
8006ab8: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
8006abc: 687b ldr r3, [r7, #4]
8006abe: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8006ac2: b29b uxth r3, r3
8006ac4: 1ad3 subs r3, r2, r3
8006ac6: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
if ((huart->RxXferCount > 0U)
8006aca: 687b ldr r3, [r7, #4]
8006acc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8006ad0: b29b uxth r3, r3
8006ad2: 2b00 cmp r3, #0
8006ad4: f000 80d1 beq.w 8006c7a <HAL_UART_IRQHandler+0x676>
&& (nb_rx_data > 0U))
8006ad8: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8006adc: 2b00 cmp r3, #0
8006ade: f000 80cc beq.w 8006c7a <HAL_UART_IRQHandler+0x676>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006ae2: 687b ldr r3, [r7, #4]
8006ae4: 681b ldr r3, [r3, #0]
8006ae6: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006ae8: 6bbb ldr r3, [r7, #56] @ 0x38
8006aea: e853 3f00 ldrex r3, [r3]
8006aee: 637b str r3, [r7, #52] @ 0x34
return(result);
8006af0: 6b7b ldr r3, [r7, #52] @ 0x34
8006af2: f423 7390 bic.w r3, r3, #288 @ 0x120
8006af6: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8006afa: 687b ldr r3, [r7, #4]
8006afc: 681b ldr r3, [r3, #0]
8006afe: 461a mov r2, r3
8006b00: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
8006b04: 647b str r3, [r7, #68] @ 0x44
8006b06: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006b08: 6c39 ldr r1, [r7, #64] @ 0x40
8006b0a: 6c7a ldr r2, [r7, #68] @ 0x44
8006b0c: e841 2300 strex r3, r2, [r1]
8006b10: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8006b12: 6bfb ldr r3, [r7, #60] @ 0x3c
8006b14: 2b00 cmp r3, #0
8006b16: d1e4 bne.n 8006ae2 <HAL_UART_IRQHandler+0x4de>
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8006b18: 687b ldr r3, [r7, #4]
8006b1a: 681b ldr r3, [r3, #0]
8006b1c: 3308 adds r3, #8
8006b1e: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006b20: 6a7b ldr r3, [r7, #36] @ 0x24
8006b22: e853 3f00 ldrex r3, [r3]
8006b26: 623b str r3, [r7, #32]
return(result);
8006b28: 6a3b ldr r3, [r7, #32]
8006b2a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8006b2e: f023 0301 bic.w r3, r3, #1
8006b32: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
8006b36: 687b ldr r3, [r7, #4]
8006b38: 681b ldr r3, [r3, #0]
8006b3a: 3308 adds r3, #8
8006b3c: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
8006b40: 633a str r2, [r7, #48] @ 0x30
8006b42: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006b44: 6af9 ldr r1, [r7, #44] @ 0x2c
8006b46: 6b3a ldr r2, [r7, #48] @ 0x30
8006b48: e841 2300 strex r3, r2, [r1]
8006b4c: 62bb str r3, [r7, #40] @ 0x28
return(result);
8006b4e: 6abb ldr r3, [r7, #40] @ 0x28
8006b50: 2b00 cmp r3, #0
8006b52: d1e1 bne.n 8006b18 <HAL_UART_IRQHandler+0x514>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006b54: 687b ldr r3, [r7, #4]
8006b56: 2220 movs r2, #32
8006b58: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006b5c: 687b ldr r3, [r7, #4]
8006b5e: 2200 movs r2, #0
8006b60: 66da str r2, [r3, #108] @ 0x6c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006b62: 687b ldr r3, [r7, #4]
8006b64: 2200 movs r2, #0
8006b66: 675a str r2, [r3, #116] @ 0x74
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006b68: 687b ldr r3, [r7, #4]
8006b6a: 681b ldr r3, [r3, #0]
8006b6c: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006b6e: 693b ldr r3, [r7, #16]
8006b70: e853 3f00 ldrex r3, [r3]
8006b74: 60fb str r3, [r7, #12]
return(result);
8006b76: 68fb ldr r3, [r7, #12]
8006b78: f023 0310 bic.w r3, r3, #16
8006b7c: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8006b80: 687b ldr r3, [r7, #4]
8006b82: 681b ldr r3, [r3, #0]
8006b84: 461a mov r2, r3
8006b86: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8006b8a: 61fb str r3, [r7, #28]
8006b8c: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006b8e: 69b9 ldr r1, [r7, #24]
8006b90: 69fa ldr r2, [r7, #28]
8006b92: e841 2300 strex r3, r2, [r1]
8006b96: 617b str r3, [r7, #20]
return(result);
8006b98: 697b ldr r3, [r7, #20]
8006b9a: 2b00 cmp r3, #0
8006b9c: d1e4 bne.n 8006b68 <HAL_UART_IRQHandler+0x564>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006b9e: 687b ldr r3, [r7, #4]
8006ba0: 2202 movs r2, #2
8006ba2: 671a str r2, [r3, #112] @ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8006ba4: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8006ba8: 4619 mov r1, r3
8006baa: 6878 ldr r0, [r7, #4]
8006bac: f000 f876 bl 8006c9c <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8006bb0: e063 b.n 8006c7a <HAL_UART_IRQHandler+0x676>
}
}
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
8006bb2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006bb6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8006bba: 2b00 cmp r3, #0
8006bbc: d00e beq.n 8006bdc <HAL_UART_IRQHandler+0x5d8>
8006bbe: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006bc2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8006bc6: 2b00 cmp r3, #0
8006bc8: d008 beq.n 8006bdc <HAL_UART_IRQHandler+0x5d8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8006bca: 687b ldr r3, [r7, #4]
8006bcc: 681b ldr r3, [r3, #0]
8006bce: f44f 1280 mov.w r2, #1048576 @ 0x100000
8006bd2: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
8006bd4: 6878 ldr r0, [r7, #4]
8006bd6: f001 fbd9 bl 800838c <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006bda: e051 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
8006bdc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006be0: f003 0380 and.w r3, r3, #128 @ 0x80
8006be4: 2b00 cmp r3, #0
8006be6: d014 beq.n 8006c12 <HAL_UART_IRQHandler+0x60e>
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
8006be8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006bec: f003 0380 and.w r3, r3, #128 @ 0x80
8006bf0: 2b00 cmp r3, #0
8006bf2: d105 bne.n 8006c00 <HAL_UART_IRQHandler+0x5fc>
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
8006bf4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006bf8: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8006bfc: 2b00 cmp r3, #0
8006bfe: d008 beq.n 8006c12 <HAL_UART_IRQHandler+0x60e>
{
if (huart->TxISR != NULL)
8006c00: 687b ldr r3, [r7, #4]
8006c02: 6f9b ldr r3, [r3, #120] @ 0x78
8006c04: 2b00 cmp r3, #0
8006c06: d03a beq.n 8006c7e <HAL_UART_IRQHandler+0x67a>
{
huart->TxISR(huart);
8006c08: 687b ldr r3, [r7, #4]
8006c0a: 6f9b ldr r3, [r3, #120] @ 0x78
8006c0c: 6878 ldr r0, [r7, #4]
8006c0e: 4798 blx r3
}
return;
8006c10: e035 b.n 8006c7e <HAL_UART_IRQHandler+0x67a>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
8006c12: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006c16: f003 0340 and.w r3, r3, #64 @ 0x40
8006c1a: 2b00 cmp r3, #0
8006c1c: d009 beq.n 8006c32 <HAL_UART_IRQHandler+0x62e>
8006c1e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006c22: f003 0340 and.w r3, r3, #64 @ 0x40
8006c26: 2b00 cmp r3, #0
8006c28: d003 beq.n 8006c32 <HAL_UART_IRQHandler+0x62e>
{
UART_EndTransmit_IT(huart);
8006c2a: 6878 ldr r0, [r7, #4]
8006c2c: f000 fe62 bl 80078f4 <UART_EndTransmit_IT>
return;
8006c30: e026 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
}
/* UART TX Fifo Empty occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
8006c32: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006c36: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8006c3a: 2b00 cmp r3, #0
8006c3c: d009 beq.n 8006c52 <HAL_UART_IRQHandler+0x64e>
8006c3e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006c42: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
8006c46: 2b00 cmp r3, #0
8006c48: d003 beq.n 8006c52 <HAL_UART_IRQHandler+0x64e>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Tx Fifo Empty Callback */
huart->TxFifoEmptyCallback(huart);
#else
/* Call legacy weak Tx Fifo Empty Callback */
HAL_UARTEx_TxFifoEmptyCallback(huart);
8006c4a: 6878 ldr r0, [r7, #4]
8006c4c: f001 fbb2 bl 80083b4 <HAL_UARTEx_TxFifoEmptyCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006c50: e016 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
}
/* UART RX Fifo Full occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
8006c52: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006c56: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8006c5a: 2b00 cmp r3, #0
8006c5c: d010 beq.n 8006c80 <HAL_UART_IRQHandler+0x67c>
8006c5e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006c62: 2b00 cmp r3, #0
8006c64: da0c bge.n 8006c80 <HAL_UART_IRQHandler+0x67c>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Rx Fifo Full Callback */
huart->RxFifoFullCallback(huart);
#else
/* Call legacy weak Rx Fifo Full Callback */
HAL_UARTEx_RxFifoFullCallback(huart);
8006c66: 6878 ldr r0, [r7, #4]
8006c68: f001 fb9a bl 80083a0 <HAL_UARTEx_RxFifoFullCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006c6c: e008 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
return;
8006c6e: bf00 nop
8006c70: e006 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
return;
8006c72: bf00 nop
8006c74: e004 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
return;
8006c76: bf00 nop
8006c78: e002 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
return;
8006c7a: bf00 nop
8006c7c: e000 b.n 8006c80 <HAL_UART_IRQHandler+0x67c>
return;
8006c7e: bf00 nop
}
}
8006c80: 37e8 adds r7, #232 @ 0xe8
8006c82: 46bd mov sp, r7
8006c84: bd80 pop {r7, pc}
8006c86: bf00 nop
08006c88 <HAL_UART_ErrorCallback>:
* @brief UART error callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
8006c88: b480 push {r7}
8006c8a: b083 sub sp, #12
8006c8c: af00 add r7, sp, #0
8006c8e: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file.
*/
}
8006c90: bf00 nop
8006c92: 370c adds r7, #12
8006c94: 46bd mov sp, r7
8006c96: f85d 7b04 ldr.w r7, [sp], #4
8006c9a: 4770 bx lr
08006c9c <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8006c9c: b480 push {r7}
8006c9e: b083 sub sp, #12
8006ca0: af00 add r7, sp, #0
8006ca2: 6078 str r0, [r7, #4]
8006ca4: 460b mov r3, r1
8006ca6: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8006ca8: bf00 nop
8006caa: 370c adds r7, #12
8006cac: 46bd mov sp, r7
8006cae: f85d 7b04 ldr.w r7, [sp], #4
8006cb2: 4770 bx lr
08006cb4 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8006cb4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8006cb8: b08c sub sp, #48 @ 0x30
8006cba: af00 add r7, sp, #0
8006cbc: 6178 str r0, [r7, #20]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8006cbe: 2300 movs r3, #0
8006cc0: f887 302a strb.w r3, [r7, #42] @ 0x2a
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8006cc4: 697b ldr r3, [r7, #20]
8006cc6: 689a ldr r2, [r3, #8]
8006cc8: 697b ldr r3, [r7, #20]
8006cca: 691b ldr r3, [r3, #16]
8006ccc: 431a orrs r2, r3
8006cce: 697b ldr r3, [r7, #20]
8006cd0: 695b ldr r3, [r3, #20]
8006cd2: 431a orrs r2, r3
8006cd4: 697b ldr r3, [r7, #20]
8006cd6: 69db ldr r3, [r3, #28]
8006cd8: 4313 orrs r3, r2
8006cda: 62fb str r3, [r7, #44] @ 0x2c
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8006cdc: 697b ldr r3, [r7, #20]
8006cde: 681b ldr r3, [r3, #0]
8006ce0: 681a ldr r2, [r3, #0]
8006ce2: 4bab ldr r3, [pc, #684] @ (8006f90 <UART_SetConfig+0x2dc>)
8006ce4: 4013 ands r3, r2
8006ce6: 697a ldr r2, [r7, #20]
8006ce8: 6812 ldr r2, [r2, #0]
8006cea: 6af9 ldr r1, [r7, #44] @ 0x2c
8006cec: 430b orrs r3, r1
8006cee: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8006cf0: 697b ldr r3, [r7, #20]
8006cf2: 681b ldr r3, [r3, #0]
8006cf4: 685b ldr r3, [r3, #4]
8006cf6: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8006cfa: 697b ldr r3, [r7, #20]
8006cfc: 68da ldr r2, [r3, #12]
8006cfe: 697b ldr r3, [r7, #20]
8006d00: 681b ldr r3, [r3, #0]
8006d02: 430a orrs r2, r1
8006d04: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8006d06: 697b ldr r3, [r7, #20]
8006d08: 699b ldr r3, [r3, #24]
8006d0a: 62fb str r3, [r7, #44] @ 0x2c
if (!(UART_INSTANCE_LOWPOWER(huart)))
8006d0c: 697b ldr r3, [r7, #20]
8006d0e: 681b ldr r3, [r3, #0]
8006d10: 4aa0 ldr r2, [pc, #640] @ (8006f94 <UART_SetConfig+0x2e0>)
8006d12: 4293 cmp r3, r2
8006d14: d004 beq.n 8006d20 <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
8006d16: 697b ldr r3, [r7, #20]
8006d18: 6a1b ldr r3, [r3, #32]
8006d1a: 6afa ldr r2, [r7, #44] @ 0x2c
8006d1c: 4313 orrs r3, r2
8006d1e: 62fb str r3, [r7, #44] @ 0x2c
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8006d20: 697b ldr r3, [r7, #20]
8006d22: 681b ldr r3, [r3, #0]
8006d24: 689b ldr r3, [r3, #8]
8006d26: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000
8006d2a: f423 6330 bic.w r3, r3, #2816 @ 0xb00
8006d2e: 697a ldr r2, [r7, #20]
8006d30: 6812 ldr r2, [r2, #0]
8006d32: 6af9 ldr r1, [r7, #44] @ 0x2c
8006d34: 430b orrs r3, r1
8006d36: 6093 str r3, [r2, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8006d38: 697b ldr r3, [r7, #20]
8006d3a: 681b ldr r3, [r3, #0]
8006d3c: 6adb ldr r3, [r3, #44] @ 0x2c
8006d3e: f023 010f bic.w r1, r3, #15
8006d42: 697b ldr r3, [r7, #20]
8006d44: 6a5a ldr r2, [r3, #36] @ 0x24
8006d46: 697b ldr r3, [r7, #20]
8006d48: 681b ldr r3, [r3, #0]
8006d4a: 430a orrs r2, r1
8006d4c: 62da str r2, [r3, #44] @ 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8006d4e: 697b ldr r3, [r7, #20]
8006d50: 681b ldr r3, [r3, #0]
8006d52: 4a91 ldr r2, [pc, #580] @ (8006f98 <UART_SetConfig+0x2e4>)
8006d54: 4293 cmp r3, r2
8006d56: d125 bne.n 8006da4 <UART_SetConfig+0xf0>
8006d58: 4b90 ldr r3, [pc, #576] @ (8006f9c <UART_SetConfig+0x2e8>)
8006d5a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006d5e: f003 0303 and.w r3, r3, #3
8006d62: 2b03 cmp r3, #3
8006d64: d81a bhi.n 8006d9c <UART_SetConfig+0xe8>
8006d66: a201 add r2, pc, #4 @ (adr r2, 8006d6c <UART_SetConfig+0xb8>)
8006d68: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006d6c: 08006d7d .word 0x08006d7d
8006d70: 08006d8d .word 0x08006d8d
8006d74: 08006d85 .word 0x08006d85
8006d78: 08006d95 .word 0x08006d95
8006d7c: 2301 movs r3, #1
8006d7e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006d82: e0d6 b.n 8006f32 <UART_SetConfig+0x27e>
8006d84: 2302 movs r3, #2
8006d86: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006d8a: e0d2 b.n 8006f32 <UART_SetConfig+0x27e>
8006d8c: 2304 movs r3, #4
8006d8e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006d92: e0ce b.n 8006f32 <UART_SetConfig+0x27e>
8006d94: 2308 movs r3, #8
8006d96: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006d9a: e0ca b.n 8006f32 <UART_SetConfig+0x27e>
8006d9c: 2310 movs r3, #16
8006d9e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006da2: e0c6 b.n 8006f32 <UART_SetConfig+0x27e>
8006da4: 697b ldr r3, [r7, #20]
8006da6: 681b ldr r3, [r3, #0]
8006da8: 4a7d ldr r2, [pc, #500] @ (8006fa0 <UART_SetConfig+0x2ec>)
8006daa: 4293 cmp r3, r2
8006dac: d138 bne.n 8006e20 <UART_SetConfig+0x16c>
8006dae: 4b7b ldr r3, [pc, #492] @ (8006f9c <UART_SetConfig+0x2e8>)
8006db0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006db4: f003 030c and.w r3, r3, #12
8006db8: 2b0c cmp r3, #12
8006dba: d82d bhi.n 8006e18 <UART_SetConfig+0x164>
8006dbc: a201 add r2, pc, #4 @ (adr r2, 8006dc4 <UART_SetConfig+0x110>)
8006dbe: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006dc2: bf00 nop
8006dc4: 08006df9 .word 0x08006df9
8006dc8: 08006e19 .word 0x08006e19
8006dcc: 08006e19 .word 0x08006e19
8006dd0: 08006e19 .word 0x08006e19
8006dd4: 08006e09 .word 0x08006e09
8006dd8: 08006e19 .word 0x08006e19
8006ddc: 08006e19 .word 0x08006e19
8006de0: 08006e19 .word 0x08006e19
8006de4: 08006e01 .word 0x08006e01
8006de8: 08006e19 .word 0x08006e19
8006dec: 08006e19 .word 0x08006e19
8006df0: 08006e19 .word 0x08006e19
8006df4: 08006e11 .word 0x08006e11
8006df8: 2300 movs r3, #0
8006dfa: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006dfe: e098 b.n 8006f32 <UART_SetConfig+0x27e>
8006e00: 2302 movs r3, #2
8006e02: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e06: e094 b.n 8006f32 <UART_SetConfig+0x27e>
8006e08: 2304 movs r3, #4
8006e0a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e0e: e090 b.n 8006f32 <UART_SetConfig+0x27e>
8006e10: 2308 movs r3, #8
8006e12: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e16: e08c b.n 8006f32 <UART_SetConfig+0x27e>
8006e18: 2310 movs r3, #16
8006e1a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e1e: e088 b.n 8006f32 <UART_SetConfig+0x27e>
8006e20: 697b ldr r3, [r7, #20]
8006e22: 681b ldr r3, [r3, #0]
8006e24: 4a5f ldr r2, [pc, #380] @ (8006fa4 <UART_SetConfig+0x2f0>)
8006e26: 4293 cmp r3, r2
8006e28: d125 bne.n 8006e76 <UART_SetConfig+0x1c2>
8006e2a: 4b5c ldr r3, [pc, #368] @ (8006f9c <UART_SetConfig+0x2e8>)
8006e2c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006e30: f003 0330 and.w r3, r3, #48 @ 0x30
8006e34: 2b30 cmp r3, #48 @ 0x30
8006e36: d016 beq.n 8006e66 <UART_SetConfig+0x1b2>
8006e38: 2b30 cmp r3, #48 @ 0x30
8006e3a: d818 bhi.n 8006e6e <UART_SetConfig+0x1ba>
8006e3c: 2b20 cmp r3, #32
8006e3e: d00a beq.n 8006e56 <UART_SetConfig+0x1a2>
8006e40: 2b20 cmp r3, #32
8006e42: d814 bhi.n 8006e6e <UART_SetConfig+0x1ba>
8006e44: 2b00 cmp r3, #0
8006e46: d002 beq.n 8006e4e <UART_SetConfig+0x19a>
8006e48: 2b10 cmp r3, #16
8006e4a: d008 beq.n 8006e5e <UART_SetConfig+0x1aa>
8006e4c: e00f b.n 8006e6e <UART_SetConfig+0x1ba>
8006e4e: 2300 movs r3, #0
8006e50: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e54: e06d b.n 8006f32 <UART_SetConfig+0x27e>
8006e56: 2302 movs r3, #2
8006e58: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e5c: e069 b.n 8006f32 <UART_SetConfig+0x27e>
8006e5e: 2304 movs r3, #4
8006e60: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e64: e065 b.n 8006f32 <UART_SetConfig+0x27e>
8006e66: 2308 movs r3, #8
8006e68: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e6c: e061 b.n 8006f32 <UART_SetConfig+0x27e>
8006e6e: 2310 movs r3, #16
8006e70: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006e74: e05d b.n 8006f32 <UART_SetConfig+0x27e>
8006e76: 697b ldr r3, [r7, #20]
8006e78: 681b ldr r3, [r3, #0]
8006e7a: 4a4b ldr r2, [pc, #300] @ (8006fa8 <UART_SetConfig+0x2f4>)
8006e7c: 4293 cmp r3, r2
8006e7e: d125 bne.n 8006ecc <UART_SetConfig+0x218>
8006e80: 4b46 ldr r3, [pc, #280] @ (8006f9c <UART_SetConfig+0x2e8>)
8006e82: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006e86: f003 03c0 and.w r3, r3, #192 @ 0xc0
8006e8a: 2bc0 cmp r3, #192 @ 0xc0
8006e8c: d016 beq.n 8006ebc <UART_SetConfig+0x208>
8006e8e: 2bc0 cmp r3, #192 @ 0xc0
8006e90: d818 bhi.n 8006ec4 <UART_SetConfig+0x210>
8006e92: 2b80 cmp r3, #128 @ 0x80
8006e94: d00a beq.n 8006eac <UART_SetConfig+0x1f8>
8006e96: 2b80 cmp r3, #128 @ 0x80
8006e98: d814 bhi.n 8006ec4 <UART_SetConfig+0x210>
8006e9a: 2b00 cmp r3, #0
8006e9c: d002 beq.n 8006ea4 <UART_SetConfig+0x1f0>
8006e9e: 2b40 cmp r3, #64 @ 0x40
8006ea0: d008 beq.n 8006eb4 <UART_SetConfig+0x200>
8006ea2: e00f b.n 8006ec4 <UART_SetConfig+0x210>
8006ea4: 2300 movs r3, #0
8006ea6: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006eaa: e042 b.n 8006f32 <UART_SetConfig+0x27e>
8006eac: 2302 movs r3, #2
8006eae: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006eb2: e03e b.n 8006f32 <UART_SetConfig+0x27e>
8006eb4: 2304 movs r3, #4
8006eb6: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006eba: e03a b.n 8006f32 <UART_SetConfig+0x27e>
8006ebc: 2308 movs r3, #8
8006ebe: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006ec2: e036 b.n 8006f32 <UART_SetConfig+0x27e>
8006ec4: 2310 movs r3, #16
8006ec6: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006eca: e032 b.n 8006f32 <UART_SetConfig+0x27e>
8006ecc: 697b ldr r3, [r7, #20]
8006ece: 681b ldr r3, [r3, #0]
8006ed0: 4a30 ldr r2, [pc, #192] @ (8006f94 <UART_SetConfig+0x2e0>)
8006ed2: 4293 cmp r3, r2
8006ed4: d12a bne.n 8006f2c <UART_SetConfig+0x278>
8006ed6: 4b31 ldr r3, [pc, #196] @ (8006f9c <UART_SetConfig+0x2e8>)
8006ed8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006edc: f403 6340 and.w r3, r3, #3072 @ 0xc00
8006ee0: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8006ee4: d01a beq.n 8006f1c <UART_SetConfig+0x268>
8006ee6: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8006eea: d81b bhi.n 8006f24 <UART_SetConfig+0x270>
8006eec: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8006ef0: d00c beq.n 8006f0c <UART_SetConfig+0x258>
8006ef2: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8006ef6: d815 bhi.n 8006f24 <UART_SetConfig+0x270>
8006ef8: 2b00 cmp r3, #0
8006efa: d003 beq.n 8006f04 <UART_SetConfig+0x250>
8006efc: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8006f00: d008 beq.n 8006f14 <UART_SetConfig+0x260>
8006f02: e00f b.n 8006f24 <UART_SetConfig+0x270>
8006f04: 2300 movs r3, #0
8006f06: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f0a: e012 b.n 8006f32 <UART_SetConfig+0x27e>
8006f0c: 2302 movs r3, #2
8006f0e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f12: e00e b.n 8006f32 <UART_SetConfig+0x27e>
8006f14: 2304 movs r3, #4
8006f16: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f1a: e00a b.n 8006f32 <UART_SetConfig+0x27e>
8006f1c: 2308 movs r3, #8
8006f1e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f22: e006 b.n 8006f32 <UART_SetConfig+0x27e>
8006f24: 2310 movs r3, #16
8006f26: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006f2a: e002 b.n 8006f32 <UART_SetConfig+0x27e>
8006f2c: 2310 movs r3, #16
8006f2e: f887 302b strb.w r3, [r7, #43] @ 0x2b
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8006f32: 697b ldr r3, [r7, #20]
8006f34: 681b ldr r3, [r3, #0]
8006f36: 4a17 ldr r2, [pc, #92] @ (8006f94 <UART_SetConfig+0x2e0>)
8006f38: 4293 cmp r3, r2
8006f3a: f040 80a8 bne.w 800708e <UART_SetConfig+0x3da>
{
/* Retrieve frequency clock */
switch (clocksource)
8006f3e: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8006f42: 2b08 cmp r3, #8
8006f44: d834 bhi.n 8006fb0 <UART_SetConfig+0x2fc>
8006f46: a201 add r2, pc, #4 @ (adr r2, 8006f4c <UART_SetConfig+0x298>)
8006f48: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006f4c: 08006f71 .word 0x08006f71
8006f50: 08006fb1 .word 0x08006fb1
8006f54: 08006f79 .word 0x08006f79
8006f58: 08006fb1 .word 0x08006fb1
8006f5c: 08006f7f .word 0x08006f7f
8006f60: 08006fb1 .word 0x08006fb1
8006f64: 08006fb1 .word 0x08006fb1
8006f68: 08006fb1 .word 0x08006fb1
8006f6c: 08006f87 .word 0x08006f87
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8006f70: f7fd fccc bl 800490c <HAL_RCC_GetPCLK1Freq>
8006f74: 6278 str r0, [r7, #36] @ 0x24
break;
8006f76: e021 b.n 8006fbc <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8006f78: 4b0c ldr r3, [pc, #48] @ (8006fac <UART_SetConfig+0x2f8>)
8006f7a: 627b str r3, [r7, #36] @ 0x24
break;
8006f7c: e01e b.n 8006fbc <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8006f7e: f7fd fc57 bl 8004830 <HAL_RCC_GetSysClockFreq>
8006f82: 6278 str r0, [r7, #36] @ 0x24
break;
8006f84: e01a b.n 8006fbc <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8006f86: f44f 4300 mov.w r3, #32768 @ 0x8000
8006f8a: 627b str r3, [r7, #36] @ 0x24
break;
8006f8c: e016 b.n 8006fbc <UART_SetConfig+0x308>
8006f8e: bf00 nop
8006f90: cfff69f3 .word 0xcfff69f3
8006f94: 40008000 .word 0x40008000
8006f98: 40013800 .word 0x40013800
8006f9c: 40021000 .word 0x40021000
8006fa0: 40004400 .word 0x40004400
8006fa4: 40004800 .word 0x40004800
8006fa8: 40004c00 .word 0x40004c00
8006fac: 00f42400 .word 0x00f42400
default:
pclk = 0U;
8006fb0: 2300 movs r3, #0
8006fb2: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8006fb4: 2301 movs r3, #1
8006fb6: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
8006fba: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
8006fbc: 6a7b ldr r3, [r7, #36] @ 0x24
8006fbe: 2b00 cmp r3, #0
8006fc0: f000 812a beq.w 8007218 <UART_SetConfig+0x564>
{
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
8006fc4: 697b ldr r3, [r7, #20]
8006fc6: 6a5b ldr r3, [r3, #36] @ 0x24
8006fc8: 4a9e ldr r2, [pc, #632] @ (8007244 <UART_SetConfig+0x590>)
8006fca: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8006fce: 461a mov r2, r3
8006fd0: 6a7b ldr r3, [r7, #36] @ 0x24
8006fd2: fbb3 f3f2 udiv r3, r3, r2
8006fd6: 61bb str r3, [r7, #24]
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8006fd8: 697b ldr r3, [r7, #20]
8006fda: 685a ldr r2, [r3, #4]
8006fdc: 4613 mov r3, r2
8006fde: 005b lsls r3, r3, #1
8006fe0: 4413 add r3, r2
8006fe2: 69ba ldr r2, [r7, #24]
8006fe4: 429a cmp r2, r3
8006fe6: d305 bcc.n 8006ff4 <UART_SetConfig+0x340>
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
8006fe8: 697b ldr r3, [r7, #20]
8006fea: 685b ldr r3, [r3, #4]
8006fec: 031b lsls r3, r3, #12
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8006fee: 69ba ldr r2, [r7, #24]
8006ff0: 429a cmp r2, r3
8006ff2: d903 bls.n 8006ffc <UART_SetConfig+0x348>
{
ret = HAL_ERROR;
8006ff4: 2301 movs r3, #1
8006ff6: f887 302a strb.w r3, [r7, #42] @ 0x2a
8006ffa: e10d b.n 8007218 <UART_SetConfig+0x564>
}
else
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8006ffc: 6a7b ldr r3, [r7, #36] @ 0x24
8006ffe: 2200 movs r2, #0
8007000: 60bb str r3, [r7, #8]
8007002: 60fa str r2, [r7, #12]
8007004: 697b ldr r3, [r7, #20]
8007006: 6a5b ldr r3, [r3, #36] @ 0x24
8007008: 4a8e ldr r2, [pc, #568] @ (8007244 <UART_SetConfig+0x590>)
800700a: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
800700e: b29b uxth r3, r3
8007010: 2200 movs r2, #0
8007012: 603b str r3, [r7, #0]
8007014: 607a str r2, [r7, #4]
8007016: e9d7 2300 ldrd r2, r3, [r7]
800701a: e9d7 0102 ldrd r0, r1, [r7, #8]
800701e: f7f9 fc01 bl 8000824 <__aeabi_uldivmod>
8007022: 4602 mov r2, r0
8007024: 460b mov r3, r1
8007026: 4610 mov r0, r2
8007028: 4619 mov r1, r3
800702a: f04f 0200 mov.w r2, #0
800702e: f04f 0300 mov.w r3, #0
8007032: 020b lsls r3, r1, #8
8007034: ea43 6310 orr.w r3, r3, r0, lsr #24
8007038: 0202 lsls r2, r0, #8
800703a: 6979 ldr r1, [r7, #20]
800703c: 6849 ldr r1, [r1, #4]
800703e: 0849 lsrs r1, r1, #1
8007040: 2000 movs r0, #0
8007042: 460c mov r4, r1
8007044: 4605 mov r5, r0
8007046: eb12 0804 adds.w r8, r2, r4
800704a: eb43 0905 adc.w r9, r3, r5
800704e: 697b ldr r3, [r7, #20]
8007050: 685b ldr r3, [r3, #4]
8007052: 2200 movs r2, #0
8007054: 469a mov sl, r3
8007056: 4693 mov fp, r2
8007058: 4652 mov r2, sl
800705a: 465b mov r3, fp
800705c: 4640 mov r0, r8
800705e: 4649 mov r1, r9
8007060: f7f9 fbe0 bl 8000824 <__aeabi_uldivmod>
8007064: 4602 mov r2, r0
8007066: 460b mov r3, r1
8007068: 4613 mov r3, r2
800706a: 623b str r3, [r7, #32]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
800706c: 6a3b ldr r3, [r7, #32]
800706e: f5b3 7f40 cmp.w r3, #768 @ 0x300
8007072: d308 bcc.n 8007086 <UART_SetConfig+0x3d2>
8007074: 6a3b ldr r3, [r7, #32]
8007076: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800707a: d204 bcs.n 8007086 <UART_SetConfig+0x3d2>
{
huart->Instance->BRR = usartdiv;
800707c: 697b ldr r3, [r7, #20]
800707e: 681b ldr r3, [r3, #0]
8007080: 6a3a ldr r2, [r7, #32]
8007082: 60da str r2, [r3, #12]
8007084: e0c8 b.n 8007218 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
8007086: 2301 movs r3, #1
8007088: f887 302a strb.w r3, [r7, #42] @ 0x2a
800708c: e0c4 b.n 8007218 <UART_SetConfig+0x564>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
800708e: 697b ldr r3, [r7, #20]
8007090: 69db ldr r3, [r3, #28]
8007092: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8007096: d167 bne.n 8007168 <UART_SetConfig+0x4b4>
{
switch (clocksource)
8007098: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
800709c: 2b08 cmp r3, #8
800709e: d828 bhi.n 80070f2 <UART_SetConfig+0x43e>
80070a0: a201 add r2, pc, #4 @ (adr r2, 80070a8 <UART_SetConfig+0x3f4>)
80070a2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80070a6: bf00 nop
80070a8: 080070cd .word 0x080070cd
80070ac: 080070d5 .word 0x080070d5
80070b0: 080070dd .word 0x080070dd
80070b4: 080070f3 .word 0x080070f3
80070b8: 080070e3 .word 0x080070e3
80070bc: 080070f3 .word 0x080070f3
80070c0: 080070f3 .word 0x080070f3
80070c4: 080070f3 .word 0x080070f3
80070c8: 080070eb .word 0x080070eb
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80070cc: f7fd fc1e bl 800490c <HAL_RCC_GetPCLK1Freq>
80070d0: 6278 str r0, [r7, #36] @ 0x24
break;
80070d2: e014 b.n 80070fe <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80070d4: f7fd fc30 bl 8004938 <HAL_RCC_GetPCLK2Freq>
80070d8: 6278 str r0, [r7, #36] @ 0x24
break;
80070da: e010 b.n 80070fe <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80070dc: 4b5a ldr r3, [pc, #360] @ (8007248 <UART_SetConfig+0x594>)
80070de: 627b str r3, [r7, #36] @ 0x24
break;
80070e0: e00d b.n 80070fe <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80070e2: f7fd fba5 bl 8004830 <HAL_RCC_GetSysClockFreq>
80070e6: 6278 str r0, [r7, #36] @ 0x24
break;
80070e8: e009 b.n 80070fe <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80070ea: f44f 4300 mov.w r3, #32768 @ 0x8000
80070ee: 627b str r3, [r7, #36] @ 0x24
break;
80070f0: e005 b.n 80070fe <UART_SetConfig+0x44a>
default:
pclk = 0U;
80070f2: 2300 movs r3, #0
80070f4: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
80070f6: 2301 movs r3, #1
80070f8: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
80070fc: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
80070fe: 6a7b ldr r3, [r7, #36] @ 0x24
8007100: 2b00 cmp r3, #0
8007102: f000 8089 beq.w 8007218 <UART_SetConfig+0x564>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8007106: 697b ldr r3, [r7, #20]
8007108: 6a5b ldr r3, [r3, #36] @ 0x24
800710a: 4a4e ldr r2, [pc, #312] @ (8007244 <UART_SetConfig+0x590>)
800710c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8007110: 461a mov r2, r3
8007112: 6a7b ldr r3, [r7, #36] @ 0x24
8007114: fbb3 f3f2 udiv r3, r3, r2
8007118: 005a lsls r2, r3, #1
800711a: 697b ldr r3, [r7, #20]
800711c: 685b ldr r3, [r3, #4]
800711e: 085b lsrs r3, r3, #1
8007120: 441a add r2, r3
8007122: 697b ldr r3, [r7, #20]
8007124: 685b ldr r3, [r3, #4]
8007126: fbb2 f3f3 udiv r3, r2, r3
800712a: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800712c: 6a3b ldr r3, [r7, #32]
800712e: 2b0f cmp r3, #15
8007130: d916 bls.n 8007160 <UART_SetConfig+0x4ac>
8007132: 6a3b ldr r3, [r7, #32]
8007134: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8007138: d212 bcs.n 8007160 <UART_SetConfig+0x4ac>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
800713a: 6a3b ldr r3, [r7, #32]
800713c: b29b uxth r3, r3
800713e: f023 030f bic.w r3, r3, #15
8007142: 83fb strh r3, [r7, #30]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8007144: 6a3b ldr r3, [r7, #32]
8007146: 085b lsrs r3, r3, #1
8007148: b29b uxth r3, r3
800714a: f003 0307 and.w r3, r3, #7
800714e: b29a uxth r2, r3
8007150: 8bfb ldrh r3, [r7, #30]
8007152: 4313 orrs r3, r2
8007154: 83fb strh r3, [r7, #30]
huart->Instance->BRR = brrtemp;
8007156: 697b ldr r3, [r7, #20]
8007158: 681b ldr r3, [r3, #0]
800715a: 8bfa ldrh r2, [r7, #30]
800715c: 60da str r2, [r3, #12]
800715e: e05b b.n 8007218 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
8007160: 2301 movs r3, #1
8007162: f887 302a strb.w r3, [r7, #42] @ 0x2a
8007166: e057 b.n 8007218 <UART_SetConfig+0x564>
}
}
}
else
{
switch (clocksource)
8007168: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
800716c: 2b08 cmp r3, #8
800716e: d828 bhi.n 80071c2 <UART_SetConfig+0x50e>
8007170: a201 add r2, pc, #4 @ (adr r2, 8007178 <UART_SetConfig+0x4c4>)
8007172: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007176: bf00 nop
8007178: 0800719d .word 0x0800719d
800717c: 080071a5 .word 0x080071a5
8007180: 080071ad .word 0x080071ad
8007184: 080071c3 .word 0x080071c3
8007188: 080071b3 .word 0x080071b3
800718c: 080071c3 .word 0x080071c3
8007190: 080071c3 .word 0x080071c3
8007194: 080071c3 .word 0x080071c3
8007198: 080071bb .word 0x080071bb
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800719c: f7fd fbb6 bl 800490c <HAL_RCC_GetPCLK1Freq>
80071a0: 6278 str r0, [r7, #36] @ 0x24
break;
80071a2: e014 b.n 80071ce <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80071a4: f7fd fbc8 bl 8004938 <HAL_RCC_GetPCLK2Freq>
80071a8: 6278 str r0, [r7, #36] @ 0x24
break;
80071aa: e010 b.n 80071ce <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80071ac: 4b26 ldr r3, [pc, #152] @ (8007248 <UART_SetConfig+0x594>)
80071ae: 627b str r3, [r7, #36] @ 0x24
break;
80071b0: e00d b.n 80071ce <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80071b2: f7fd fb3d bl 8004830 <HAL_RCC_GetSysClockFreq>
80071b6: 6278 str r0, [r7, #36] @ 0x24
break;
80071b8: e009 b.n 80071ce <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80071ba: f44f 4300 mov.w r3, #32768 @ 0x8000
80071be: 627b str r3, [r7, #36] @ 0x24
break;
80071c0: e005 b.n 80071ce <UART_SetConfig+0x51a>
default:
pclk = 0U;
80071c2: 2300 movs r3, #0
80071c4: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
80071c6: 2301 movs r3, #1
80071c8: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
80071cc: bf00 nop
}
if (pclk != 0U)
80071ce: 6a7b ldr r3, [r7, #36] @ 0x24
80071d0: 2b00 cmp r3, #0
80071d2: d021 beq.n 8007218 <UART_SetConfig+0x564>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
80071d4: 697b ldr r3, [r7, #20]
80071d6: 6a5b ldr r3, [r3, #36] @ 0x24
80071d8: 4a1a ldr r2, [pc, #104] @ (8007244 <UART_SetConfig+0x590>)
80071da: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80071de: 461a mov r2, r3
80071e0: 6a7b ldr r3, [r7, #36] @ 0x24
80071e2: fbb3 f2f2 udiv r2, r3, r2
80071e6: 697b ldr r3, [r7, #20]
80071e8: 685b ldr r3, [r3, #4]
80071ea: 085b lsrs r3, r3, #1
80071ec: 441a add r2, r3
80071ee: 697b ldr r3, [r7, #20]
80071f0: 685b ldr r3, [r3, #4]
80071f2: fbb2 f3f3 udiv r3, r2, r3
80071f6: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80071f8: 6a3b ldr r3, [r7, #32]
80071fa: 2b0f cmp r3, #15
80071fc: d909 bls.n 8007212 <UART_SetConfig+0x55e>
80071fe: 6a3b ldr r3, [r7, #32]
8007200: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8007204: d205 bcs.n 8007212 <UART_SetConfig+0x55e>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8007206: 6a3b ldr r3, [r7, #32]
8007208: b29a uxth r2, r3
800720a: 697b ldr r3, [r7, #20]
800720c: 681b ldr r3, [r3, #0]
800720e: 60da str r2, [r3, #12]
8007210: e002 b.n 8007218 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
8007212: 2301 movs r3, #1
8007214: f887 302a strb.w r3, [r7, #42] @ 0x2a
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
8007218: 697b ldr r3, [r7, #20]
800721a: 2201 movs r2, #1
800721c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1;
8007220: 697b ldr r3, [r7, #20]
8007222: 2201 movs r2, #1
8007224: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
/* Clear ISR function pointers */
huart->RxISR = NULL;
8007228: 697b ldr r3, [r7, #20]
800722a: 2200 movs r2, #0
800722c: 675a str r2, [r3, #116] @ 0x74
huart->TxISR = NULL;
800722e: 697b ldr r3, [r7, #20]
8007230: 2200 movs r2, #0
8007232: 679a str r2, [r3, #120] @ 0x78
return ret;
8007234: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
}
8007238: 4618 mov r0, r3
800723a: 3730 adds r7, #48 @ 0x30
800723c: 46bd mov sp, r7
800723e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8007242: bf00 nop
8007244: 08008658 .word 0x08008658
8007248: 00f42400 .word 0x00f42400
0800724c <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
800724c: b480 push {r7}
800724e: b083 sub sp, #12
8007250: af00 add r7, sp, #0
8007252: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8007254: 687b ldr r3, [r7, #4]
8007256: 6a9b ldr r3, [r3, #40] @ 0x28
8007258: f003 0308 and.w r3, r3, #8
800725c: 2b00 cmp r3, #0
800725e: d00a beq.n 8007276 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8007260: 687b ldr r3, [r7, #4]
8007262: 681b ldr r3, [r3, #0]
8007264: 685b ldr r3, [r3, #4]
8007266: f423 4100 bic.w r1, r3, #32768 @ 0x8000
800726a: 687b ldr r3, [r7, #4]
800726c: 6b9a ldr r2, [r3, #56] @ 0x38
800726e: 687b ldr r3, [r7, #4]
8007270: 681b ldr r3, [r3, #0]
8007272: 430a orrs r2, r1
8007274: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8007276: 687b ldr r3, [r7, #4]
8007278: 6a9b ldr r3, [r3, #40] @ 0x28
800727a: f003 0301 and.w r3, r3, #1
800727e: 2b00 cmp r3, #0
8007280: d00a beq.n 8007298 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8007282: 687b ldr r3, [r7, #4]
8007284: 681b ldr r3, [r3, #0]
8007286: 685b ldr r3, [r3, #4]
8007288: f423 3100 bic.w r1, r3, #131072 @ 0x20000
800728c: 687b ldr r3, [r7, #4]
800728e: 6ada ldr r2, [r3, #44] @ 0x2c
8007290: 687b ldr r3, [r7, #4]
8007292: 681b ldr r3, [r3, #0]
8007294: 430a orrs r2, r1
8007296: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8007298: 687b ldr r3, [r7, #4]
800729a: 6a9b ldr r3, [r3, #40] @ 0x28
800729c: f003 0302 and.w r3, r3, #2
80072a0: 2b00 cmp r3, #0
80072a2: d00a beq.n 80072ba <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80072a4: 687b ldr r3, [r7, #4]
80072a6: 681b ldr r3, [r3, #0]
80072a8: 685b ldr r3, [r3, #4]
80072aa: f423 3180 bic.w r1, r3, #65536 @ 0x10000
80072ae: 687b ldr r3, [r7, #4]
80072b0: 6b1a ldr r2, [r3, #48] @ 0x30
80072b2: 687b ldr r3, [r7, #4]
80072b4: 681b ldr r3, [r3, #0]
80072b6: 430a orrs r2, r1
80072b8: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80072ba: 687b ldr r3, [r7, #4]
80072bc: 6a9b ldr r3, [r3, #40] @ 0x28
80072be: f003 0304 and.w r3, r3, #4
80072c2: 2b00 cmp r3, #0
80072c4: d00a beq.n 80072dc <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80072c6: 687b ldr r3, [r7, #4]
80072c8: 681b ldr r3, [r3, #0]
80072ca: 685b ldr r3, [r3, #4]
80072cc: f423 2180 bic.w r1, r3, #262144 @ 0x40000
80072d0: 687b ldr r3, [r7, #4]
80072d2: 6b5a ldr r2, [r3, #52] @ 0x34
80072d4: 687b ldr r3, [r7, #4]
80072d6: 681b ldr r3, [r3, #0]
80072d8: 430a orrs r2, r1
80072da: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
80072dc: 687b ldr r3, [r7, #4]
80072de: 6a9b ldr r3, [r3, #40] @ 0x28
80072e0: f003 0310 and.w r3, r3, #16
80072e4: 2b00 cmp r3, #0
80072e6: d00a beq.n 80072fe <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80072e8: 687b ldr r3, [r7, #4]
80072ea: 681b ldr r3, [r3, #0]
80072ec: 689b ldr r3, [r3, #8]
80072ee: f423 5180 bic.w r1, r3, #4096 @ 0x1000
80072f2: 687b ldr r3, [r7, #4]
80072f4: 6bda ldr r2, [r3, #60] @ 0x3c
80072f6: 687b ldr r3, [r7, #4]
80072f8: 681b ldr r3, [r3, #0]
80072fa: 430a orrs r2, r1
80072fc: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
80072fe: 687b ldr r3, [r7, #4]
8007300: 6a9b ldr r3, [r3, #40] @ 0x28
8007302: f003 0320 and.w r3, r3, #32
8007306: 2b00 cmp r3, #0
8007308: d00a beq.n 8007320 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
800730a: 687b ldr r3, [r7, #4]
800730c: 681b ldr r3, [r3, #0]
800730e: 689b ldr r3, [r3, #8]
8007310: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8007314: 687b ldr r3, [r7, #4]
8007316: 6c1a ldr r2, [r3, #64] @ 0x40
8007318: 687b ldr r3, [r7, #4]
800731a: 681b ldr r3, [r3, #0]
800731c: 430a orrs r2, r1
800731e: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8007320: 687b ldr r3, [r7, #4]
8007322: 6a9b ldr r3, [r3, #40] @ 0x28
8007324: f003 0340 and.w r3, r3, #64 @ 0x40
8007328: 2b00 cmp r3, #0
800732a: d01a beq.n 8007362 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800732c: 687b ldr r3, [r7, #4]
800732e: 681b ldr r3, [r3, #0]
8007330: 685b ldr r3, [r3, #4]
8007332: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8007336: 687b ldr r3, [r7, #4]
8007338: 6c5a ldr r2, [r3, #68] @ 0x44
800733a: 687b ldr r3, [r7, #4]
800733c: 681b ldr r3, [r3, #0]
800733e: 430a orrs r2, r1
8007340: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8007342: 687b ldr r3, [r7, #4]
8007344: 6c5b ldr r3, [r3, #68] @ 0x44
8007346: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800734a: d10a bne.n 8007362 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800734c: 687b ldr r3, [r7, #4]
800734e: 681b ldr r3, [r3, #0]
8007350: 685b ldr r3, [r3, #4]
8007352: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8007356: 687b ldr r3, [r7, #4]
8007358: 6c9a ldr r2, [r3, #72] @ 0x48
800735a: 687b ldr r3, [r7, #4]
800735c: 681b ldr r3, [r3, #0]
800735e: 430a orrs r2, r1
8007360: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8007362: 687b ldr r3, [r7, #4]
8007364: 6a9b ldr r3, [r3, #40] @ 0x28
8007366: f003 0380 and.w r3, r3, #128 @ 0x80
800736a: 2b00 cmp r3, #0
800736c: d00a beq.n 8007384 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800736e: 687b ldr r3, [r7, #4]
8007370: 681b ldr r3, [r3, #0]
8007372: 685b ldr r3, [r3, #4]
8007374: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8007378: 687b ldr r3, [r7, #4]
800737a: 6cda ldr r2, [r3, #76] @ 0x4c
800737c: 687b ldr r3, [r7, #4]
800737e: 681b ldr r3, [r3, #0]
8007380: 430a orrs r2, r1
8007382: 605a str r2, [r3, #4]
}
}
8007384: bf00 nop
8007386: 370c adds r7, #12
8007388: 46bd mov sp, r7
800738a: f85d 7b04 ldr.w r7, [sp], #4
800738e: 4770 bx lr
08007390 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8007390: b580 push {r7, lr}
8007392: b098 sub sp, #96 @ 0x60
8007394: af02 add r7, sp, #8
8007396: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007398: 687b ldr r3, [r7, #4]
800739a: 2200 movs r2, #0
800739c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80073a0: f7fa fd10 bl 8001dc4 <HAL_GetTick>
80073a4: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
80073a6: 687b ldr r3, [r7, #4]
80073a8: 681b ldr r3, [r3, #0]
80073aa: 681b ldr r3, [r3, #0]
80073ac: f003 0308 and.w r3, r3, #8
80073b0: 2b08 cmp r3, #8
80073b2: d12f bne.n 8007414 <UART_CheckIdleState+0x84>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80073b4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80073b8: 9300 str r3, [sp, #0]
80073ba: 6d7b ldr r3, [r7, #84] @ 0x54
80073bc: 2200 movs r2, #0
80073be: f44f 1100 mov.w r1, #2097152 @ 0x200000
80073c2: 6878 ldr r0, [r7, #4]
80073c4: f000 f88e bl 80074e4 <UART_WaitOnFlagUntilTimeout>
80073c8: 4603 mov r3, r0
80073ca: 2b00 cmp r3, #0
80073cc: d022 beq.n 8007414 <UART_CheckIdleState+0x84>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
80073ce: 687b ldr r3, [r7, #4]
80073d0: 681b ldr r3, [r3, #0]
80073d2: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80073d4: 6bbb ldr r3, [r7, #56] @ 0x38
80073d6: e853 3f00 ldrex r3, [r3]
80073da: 637b str r3, [r7, #52] @ 0x34
return(result);
80073dc: 6b7b ldr r3, [r7, #52] @ 0x34
80073de: f023 0380 bic.w r3, r3, #128 @ 0x80
80073e2: 653b str r3, [r7, #80] @ 0x50
80073e4: 687b ldr r3, [r7, #4]
80073e6: 681b ldr r3, [r3, #0]
80073e8: 461a mov r2, r3
80073ea: 6d3b ldr r3, [r7, #80] @ 0x50
80073ec: 647b str r3, [r7, #68] @ 0x44
80073ee: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80073f0: 6c39 ldr r1, [r7, #64] @ 0x40
80073f2: 6c7a ldr r2, [r7, #68] @ 0x44
80073f4: e841 2300 strex r3, r2, [r1]
80073f8: 63fb str r3, [r7, #60] @ 0x3c
return(result);
80073fa: 6bfb ldr r3, [r7, #60] @ 0x3c
80073fc: 2b00 cmp r3, #0
80073fe: d1e6 bne.n 80073ce <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
8007400: 687b ldr r3, [r7, #4]
8007402: 2220 movs r2, #32
8007404: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UNLOCK(huart);
8007408: 687b ldr r3, [r7, #4]
800740a: 2200 movs r2, #0
800740c: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
8007410: 2303 movs r3, #3
8007412: e063 b.n 80074dc <UART_CheckIdleState+0x14c>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8007414: 687b ldr r3, [r7, #4]
8007416: 681b ldr r3, [r3, #0]
8007418: 681b ldr r3, [r3, #0]
800741a: f003 0304 and.w r3, r3, #4
800741e: 2b04 cmp r3, #4
8007420: d149 bne.n 80074b6 <UART_CheckIdleState+0x126>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8007422: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8007426: 9300 str r3, [sp, #0]
8007428: 6d7b ldr r3, [r7, #84] @ 0x54
800742a: 2200 movs r2, #0
800742c: f44f 0180 mov.w r1, #4194304 @ 0x400000
8007430: 6878 ldr r0, [r7, #4]
8007432: f000 f857 bl 80074e4 <UART_WaitOnFlagUntilTimeout>
8007436: 4603 mov r3, r0
8007438: 2b00 cmp r3, #0
800743a: d03c beq.n 80074b6 <UART_CheckIdleState+0x126>
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
800743c: 687b ldr r3, [r7, #4]
800743e: 681b ldr r3, [r3, #0]
8007440: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007442: 6a7b ldr r3, [r7, #36] @ 0x24
8007444: e853 3f00 ldrex r3, [r3]
8007448: 623b str r3, [r7, #32]
return(result);
800744a: 6a3b ldr r3, [r7, #32]
800744c: f423 7390 bic.w r3, r3, #288 @ 0x120
8007450: 64fb str r3, [r7, #76] @ 0x4c
8007452: 687b ldr r3, [r7, #4]
8007454: 681b ldr r3, [r3, #0]
8007456: 461a mov r2, r3
8007458: 6cfb ldr r3, [r7, #76] @ 0x4c
800745a: 633b str r3, [r7, #48] @ 0x30
800745c: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800745e: 6af9 ldr r1, [r7, #44] @ 0x2c
8007460: 6b3a ldr r2, [r7, #48] @ 0x30
8007462: e841 2300 strex r3, r2, [r1]
8007466: 62bb str r3, [r7, #40] @ 0x28
return(result);
8007468: 6abb ldr r3, [r7, #40] @ 0x28
800746a: 2b00 cmp r3, #0
800746c: d1e6 bne.n 800743c <UART_CheckIdleState+0xac>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800746e: 687b ldr r3, [r7, #4]
8007470: 681b ldr r3, [r3, #0]
8007472: 3308 adds r3, #8
8007474: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007476: 693b ldr r3, [r7, #16]
8007478: e853 3f00 ldrex r3, [r3]
800747c: 60fb str r3, [r7, #12]
return(result);
800747e: 68fb ldr r3, [r7, #12]
8007480: f023 0301 bic.w r3, r3, #1
8007484: 64bb str r3, [r7, #72] @ 0x48
8007486: 687b ldr r3, [r7, #4]
8007488: 681b ldr r3, [r3, #0]
800748a: 3308 adds r3, #8
800748c: 6cba ldr r2, [r7, #72] @ 0x48
800748e: 61fa str r2, [r7, #28]
8007490: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007492: 69b9 ldr r1, [r7, #24]
8007494: 69fa ldr r2, [r7, #28]
8007496: e841 2300 strex r3, r2, [r1]
800749a: 617b str r3, [r7, #20]
return(result);
800749c: 697b ldr r3, [r7, #20]
800749e: 2b00 cmp r3, #0
80074a0: d1e5 bne.n 800746e <UART_CheckIdleState+0xde>
huart->RxState = HAL_UART_STATE_READY;
80074a2: 687b ldr r3, [r7, #4]
80074a4: 2220 movs r2, #32
80074a6: f8c3 208c str.w r2, [r3, #140] @ 0x8c
__HAL_UNLOCK(huart);
80074aa: 687b ldr r3, [r7, #4]
80074ac: 2200 movs r2, #0
80074ae: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
80074b2: 2303 movs r3, #3
80074b4: e012 b.n 80074dc <UART_CheckIdleState+0x14c>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
80074b6: 687b ldr r3, [r7, #4]
80074b8: 2220 movs r2, #32
80074ba: f8c3 2088 str.w r2, [r3, #136] @ 0x88
huart->RxState = HAL_UART_STATE_READY;
80074be: 687b ldr r3, [r7, #4]
80074c0: 2220 movs r2, #32
80074c2: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80074c6: 687b ldr r3, [r7, #4]
80074c8: 2200 movs r2, #0
80074ca: 66da str r2, [r3, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
80074cc: 687b ldr r3, [r7, #4]
80074ce: 2200 movs r2, #0
80074d0: 671a str r2, [r3, #112] @ 0x70
__HAL_UNLOCK(huart);
80074d2: 687b ldr r3, [r7, #4]
80074d4: 2200 movs r2, #0
80074d6: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
80074da: 2300 movs r3, #0
}
80074dc: 4618 mov r0, r3
80074de: 3758 adds r7, #88 @ 0x58
80074e0: 46bd mov sp, r7
80074e2: bd80 pop {r7, pc}
080074e4 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80074e4: b580 push {r7, lr}
80074e6: b084 sub sp, #16
80074e8: af00 add r7, sp, #0
80074ea: 60f8 str r0, [r7, #12]
80074ec: 60b9 str r1, [r7, #8]
80074ee: 603b str r3, [r7, #0]
80074f0: 4613 mov r3, r2
80074f2: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80074f4: e04f b.n 8007596 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80074f6: 69bb ldr r3, [r7, #24]
80074f8: f1b3 3fff cmp.w r3, #4294967295
80074fc: d04b beq.n 8007596 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80074fe: f7fa fc61 bl 8001dc4 <HAL_GetTick>
8007502: 4602 mov r2, r0
8007504: 683b ldr r3, [r7, #0]
8007506: 1ad3 subs r3, r2, r3
8007508: 69ba ldr r2, [r7, #24]
800750a: 429a cmp r2, r3
800750c: d302 bcc.n 8007514 <UART_WaitOnFlagUntilTimeout+0x30>
800750e: 69bb ldr r3, [r7, #24]
8007510: 2b00 cmp r3, #0
8007512: d101 bne.n 8007518 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8007514: 2303 movs r3, #3
8007516: e04e b.n 80075b6 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8007518: 68fb ldr r3, [r7, #12]
800751a: 681b ldr r3, [r3, #0]
800751c: 681b ldr r3, [r3, #0]
800751e: f003 0304 and.w r3, r3, #4
8007522: 2b00 cmp r3, #0
8007524: d037 beq.n 8007596 <UART_WaitOnFlagUntilTimeout+0xb2>
8007526: 68bb ldr r3, [r7, #8]
8007528: 2b80 cmp r3, #128 @ 0x80
800752a: d034 beq.n 8007596 <UART_WaitOnFlagUntilTimeout+0xb2>
800752c: 68bb ldr r3, [r7, #8]
800752e: 2b40 cmp r3, #64 @ 0x40
8007530: d031 beq.n 8007596 <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8007532: 68fb ldr r3, [r7, #12]
8007534: 681b ldr r3, [r3, #0]
8007536: 69db ldr r3, [r3, #28]
8007538: f003 0308 and.w r3, r3, #8
800753c: 2b08 cmp r3, #8
800753e: d110 bne.n 8007562 <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8007540: 68fb ldr r3, [r7, #12]
8007542: 681b ldr r3, [r3, #0]
8007544: 2208 movs r2, #8
8007546: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8007548: 68f8 ldr r0, [r7, #12]
800754a: f000 f95b bl 8007804 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
800754e: 68fb ldr r3, [r7, #12]
8007550: 2208 movs r2, #8
8007552: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007556: 68fb ldr r3, [r7, #12]
8007558: 2200 movs r2, #0
800755a: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_ERROR;
800755e: 2301 movs r3, #1
8007560: e029 b.n 80075b6 <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8007562: 68fb ldr r3, [r7, #12]
8007564: 681b ldr r3, [r3, #0]
8007566: 69db ldr r3, [r3, #28]
8007568: f403 6300 and.w r3, r3, #2048 @ 0x800
800756c: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8007570: d111 bne.n 8007596 <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8007572: 68fb ldr r3, [r7, #12]
8007574: 681b ldr r3, [r3, #0]
8007576: f44f 6200 mov.w r2, #2048 @ 0x800
800757a: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
800757c: 68f8 ldr r0, [r7, #12]
800757e: f000 f941 bl 8007804 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8007582: 68fb ldr r3, [r7, #12]
8007584: 2220 movs r2, #32
8007586: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
800758a: 68fb ldr r3, [r7, #12]
800758c: 2200 movs r2, #0
800758e: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_TIMEOUT;
8007592: 2303 movs r3, #3
8007594: e00f b.n 80075b6 <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8007596: 68fb ldr r3, [r7, #12]
8007598: 681b ldr r3, [r3, #0]
800759a: 69da ldr r2, [r3, #28]
800759c: 68bb ldr r3, [r7, #8]
800759e: 4013 ands r3, r2
80075a0: 68ba ldr r2, [r7, #8]
80075a2: 429a cmp r2, r3
80075a4: bf0c ite eq
80075a6: 2301 moveq r3, #1
80075a8: 2300 movne r3, #0
80075aa: b2db uxtb r3, r3
80075ac: 461a mov r2, r3
80075ae: 79fb ldrb r3, [r7, #7]
80075b0: 429a cmp r2, r3
80075b2: d0a0 beq.n 80074f6 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
80075b4: 2300 movs r3, #0
}
80075b6: 4618 mov r0, r3
80075b8: 3710 adds r7, #16
80075ba: 46bd mov sp, r7
80075bc: bd80 pop {r7, pc}
...
080075c0 <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
80075c0: b480 push {r7}
80075c2: b0a3 sub sp, #140 @ 0x8c
80075c4: af00 add r7, sp, #0
80075c6: 60f8 str r0, [r7, #12]
80075c8: 60b9 str r1, [r7, #8]
80075ca: 4613 mov r3, r2
80075cc: 80fb strh r3, [r7, #6]
huart->pRxBuffPtr = pData;
80075ce: 68fb ldr r3, [r7, #12]
80075d0: 68ba ldr r2, [r7, #8]
80075d2: 659a str r2, [r3, #88] @ 0x58
huart->RxXferSize = Size;
80075d4: 68fb ldr r3, [r7, #12]
80075d6: 88fa ldrh r2, [r7, #6]
80075d8: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
huart->RxXferCount = Size;
80075dc: 68fb ldr r3, [r7, #12]
80075de: 88fa ldrh r2, [r7, #6]
80075e0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
huart->RxISR = NULL;
80075e4: 68fb ldr r3, [r7, #12]
80075e6: 2200 movs r2, #0
80075e8: 675a str r2, [r3, #116] @ 0x74
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
80075ea: 68fb ldr r3, [r7, #12]
80075ec: 689b ldr r3, [r3, #8]
80075ee: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80075f2: d10e bne.n 8007612 <UART_Start_Receive_IT+0x52>
80075f4: 68fb ldr r3, [r7, #12]
80075f6: 691b ldr r3, [r3, #16]
80075f8: 2b00 cmp r3, #0
80075fa: d105 bne.n 8007608 <UART_Start_Receive_IT+0x48>
80075fc: 68fb ldr r3, [r7, #12]
80075fe: f240 12ff movw r2, #511 @ 0x1ff
8007602: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007606: e02d b.n 8007664 <UART_Start_Receive_IT+0xa4>
8007608: 68fb ldr r3, [r7, #12]
800760a: 22ff movs r2, #255 @ 0xff
800760c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007610: e028 b.n 8007664 <UART_Start_Receive_IT+0xa4>
8007612: 68fb ldr r3, [r7, #12]
8007614: 689b ldr r3, [r3, #8]
8007616: 2b00 cmp r3, #0
8007618: d10d bne.n 8007636 <UART_Start_Receive_IT+0x76>
800761a: 68fb ldr r3, [r7, #12]
800761c: 691b ldr r3, [r3, #16]
800761e: 2b00 cmp r3, #0
8007620: d104 bne.n 800762c <UART_Start_Receive_IT+0x6c>
8007622: 68fb ldr r3, [r7, #12]
8007624: 22ff movs r2, #255 @ 0xff
8007626: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
800762a: e01b b.n 8007664 <UART_Start_Receive_IT+0xa4>
800762c: 68fb ldr r3, [r7, #12]
800762e: 227f movs r2, #127 @ 0x7f
8007630: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007634: e016 b.n 8007664 <UART_Start_Receive_IT+0xa4>
8007636: 68fb ldr r3, [r7, #12]
8007638: 689b ldr r3, [r3, #8]
800763a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800763e: d10d bne.n 800765c <UART_Start_Receive_IT+0x9c>
8007640: 68fb ldr r3, [r7, #12]
8007642: 691b ldr r3, [r3, #16]
8007644: 2b00 cmp r3, #0
8007646: d104 bne.n 8007652 <UART_Start_Receive_IT+0x92>
8007648: 68fb ldr r3, [r7, #12]
800764a: 227f movs r2, #127 @ 0x7f
800764c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007650: e008 b.n 8007664 <UART_Start_Receive_IT+0xa4>
8007652: 68fb ldr r3, [r7, #12]
8007654: 223f movs r2, #63 @ 0x3f
8007656: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
800765a: e003 b.n 8007664 <UART_Start_Receive_IT+0xa4>
800765c: 68fb ldr r3, [r7, #12]
800765e: 2200 movs r2, #0
8007660: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007664: 68fb ldr r3, [r7, #12]
8007666: 2200 movs r2, #0
8007668: f8c3 2090 str.w r2, [r3, #144] @ 0x90
huart->RxState = HAL_UART_STATE_BUSY_RX;
800766c: 68fb ldr r3, [r7, #12]
800766e: 2222 movs r2, #34 @ 0x22
8007670: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
8007674: 68fb ldr r3, [r7, #12]
8007676: 681b ldr r3, [r3, #0]
8007678: 3308 adds r3, #8
800767a: 667b str r3, [r7, #100] @ 0x64
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800767c: 6e7b ldr r3, [r7, #100] @ 0x64
800767e: e853 3f00 ldrex r3, [r3]
8007682: 663b str r3, [r7, #96] @ 0x60
return(result);
8007684: 6e3b ldr r3, [r7, #96] @ 0x60
8007686: f043 0301 orr.w r3, r3, #1
800768a: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800768e: 68fb ldr r3, [r7, #12]
8007690: 681b ldr r3, [r3, #0]
8007692: 3308 adds r3, #8
8007694: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
8007698: 673a str r2, [r7, #112] @ 0x70
800769a: 66fb str r3, [r7, #108] @ 0x6c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800769c: 6ef9 ldr r1, [r7, #108] @ 0x6c
800769e: 6f3a ldr r2, [r7, #112] @ 0x70
80076a0: e841 2300 strex r3, r2, [r1]
80076a4: 66bb str r3, [r7, #104] @ 0x68
return(result);
80076a6: 6ebb ldr r3, [r7, #104] @ 0x68
80076a8: 2b00 cmp r3, #0
80076aa: d1e3 bne.n 8007674 <UART_Start_Receive_IT+0xb4>
/* Configure Rx interrupt processing */
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
80076ac: 68fb ldr r3, [r7, #12]
80076ae: 6e5b ldr r3, [r3, #100] @ 0x64
80076b0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80076b4: d14f bne.n 8007756 <UART_Start_Receive_IT+0x196>
80076b6: 68fb ldr r3, [r7, #12]
80076b8: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
80076bc: 88fa ldrh r2, [r7, #6]
80076be: 429a cmp r2, r3
80076c0: d349 bcc.n 8007756 <UART_Start_Receive_IT+0x196>
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80076c2: 68fb ldr r3, [r7, #12]
80076c4: 689b ldr r3, [r3, #8]
80076c6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80076ca: d107 bne.n 80076dc <UART_Start_Receive_IT+0x11c>
80076cc: 68fb ldr r3, [r7, #12]
80076ce: 691b ldr r3, [r3, #16]
80076d0: 2b00 cmp r3, #0
80076d2: d103 bne.n 80076dc <UART_Start_Receive_IT+0x11c>
{
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
80076d4: 68fb ldr r3, [r7, #12]
80076d6: 4a47 ldr r2, [pc, #284] @ (80077f4 <UART_Start_Receive_IT+0x234>)
80076d8: 675a str r2, [r3, #116] @ 0x74
80076da: e002 b.n 80076e2 <UART_Start_Receive_IT+0x122>
}
else
{
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
80076dc: 68fb ldr r3, [r7, #12]
80076de: 4a46 ldr r2, [pc, #280] @ (80077f8 <UART_Start_Receive_IT+0x238>)
80076e0: 675a str r2, [r3, #116] @ 0x74
}
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
80076e2: 68fb ldr r3, [r7, #12]
80076e4: 691b ldr r3, [r3, #16]
80076e6: 2b00 cmp r3, #0
80076e8: d01a beq.n 8007720 <UART_Start_Receive_IT+0x160>
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
80076ea: 68fb ldr r3, [r7, #12]
80076ec: 681b ldr r3, [r3, #0]
80076ee: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80076f0: 6d3b ldr r3, [r7, #80] @ 0x50
80076f2: e853 3f00 ldrex r3, [r3]
80076f6: 64fb str r3, [r7, #76] @ 0x4c
return(result);
80076f8: 6cfb ldr r3, [r7, #76] @ 0x4c
80076fa: f443 7380 orr.w r3, r3, #256 @ 0x100
80076fe: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8007702: 68fb ldr r3, [r7, #12]
8007704: 681b ldr r3, [r3, #0]
8007706: 461a mov r2, r3
8007708: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
800770c: 65fb str r3, [r7, #92] @ 0x5c
800770e: 65ba str r2, [r7, #88] @ 0x58
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007710: 6db9 ldr r1, [r7, #88] @ 0x58
8007712: 6dfa ldr r2, [r7, #92] @ 0x5c
8007714: e841 2300 strex r3, r2, [r1]
8007718: 657b str r3, [r7, #84] @ 0x54
return(result);
800771a: 6d7b ldr r3, [r7, #84] @ 0x54
800771c: 2b00 cmp r3, #0
800771e: d1e4 bne.n 80076ea <UART_Start_Receive_IT+0x12a>
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
8007720: 68fb ldr r3, [r7, #12]
8007722: 681b ldr r3, [r3, #0]
8007724: 3308 adds r3, #8
8007726: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007728: 6bfb ldr r3, [r7, #60] @ 0x3c
800772a: e853 3f00 ldrex r3, [r3]
800772e: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007730: 6bbb ldr r3, [r7, #56] @ 0x38
8007732: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8007736: 67fb str r3, [r7, #124] @ 0x7c
8007738: 68fb ldr r3, [r7, #12]
800773a: 681b ldr r3, [r3, #0]
800773c: 3308 adds r3, #8
800773e: 6ffa ldr r2, [r7, #124] @ 0x7c
8007740: 64ba str r2, [r7, #72] @ 0x48
8007742: 647b str r3, [r7, #68] @ 0x44
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007744: 6c79 ldr r1, [r7, #68] @ 0x44
8007746: 6cba ldr r2, [r7, #72] @ 0x48
8007748: e841 2300 strex r3, r2, [r1]
800774c: 643b str r3, [r7, #64] @ 0x40
return(result);
800774e: 6c3b ldr r3, [r7, #64] @ 0x40
8007750: 2b00 cmp r3, #0
8007752: d1e5 bne.n 8007720 <UART_Start_Receive_IT+0x160>
8007754: e046 b.n 80077e4 <UART_Start_Receive_IT+0x224>
}
else
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8007756: 68fb ldr r3, [r7, #12]
8007758: 689b ldr r3, [r3, #8]
800775a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800775e: d107 bne.n 8007770 <UART_Start_Receive_IT+0x1b0>
8007760: 68fb ldr r3, [r7, #12]
8007762: 691b ldr r3, [r3, #16]
8007764: 2b00 cmp r3, #0
8007766: d103 bne.n 8007770 <UART_Start_Receive_IT+0x1b0>
{
huart->RxISR = UART_RxISR_16BIT;
8007768: 68fb ldr r3, [r7, #12]
800776a: 4a24 ldr r2, [pc, #144] @ (80077fc <UART_Start_Receive_IT+0x23c>)
800776c: 675a str r2, [r3, #116] @ 0x74
800776e: e002 b.n 8007776 <UART_Start_Receive_IT+0x1b6>
}
else
{
huart->RxISR = UART_RxISR_8BIT;
8007770: 68fb ldr r3, [r7, #12]
8007772: 4a23 ldr r2, [pc, #140] @ (8007800 <UART_Start_Receive_IT+0x240>)
8007774: 675a str r2, [r3, #116] @ 0x74
}
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
8007776: 68fb ldr r3, [r7, #12]
8007778: 691b ldr r3, [r3, #16]
800777a: 2b00 cmp r3, #0
800777c: d019 beq.n 80077b2 <UART_Start_Receive_IT+0x1f2>
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
800777e: 68fb ldr r3, [r7, #12]
8007780: 681b ldr r3, [r3, #0]
8007782: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007784: 6abb ldr r3, [r7, #40] @ 0x28
8007786: e853 3f00 ldrex r3, [r3]
800778a: 627b str r3, [r7, #36] @ 0x24
return(result);
800778c: 6a7b ldr r3, [r7, #36] @ 0x24
800778e: f443 7390 orr.w r3, r3, #288 @ 0x120
8007792: 677b str r3, [r7, #116] @ 0x74
8007794: 68fb ldr r3, [r7, #12]
8007796: 681b ldr r3, [r3, #0]
8007798: 461a mov r2, r3
800779a: 6f7b ldr r3, [r7, #116] @ 0x74
800779c: 637b str r3, [r7, #52] @ 0x34
800779e: 633a str r2, [r7, #48] @ 0x30
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80077a0: 6b39 ldr r1, [r7, #48] @ 0x30
80077a2: 6b7a ldr r2, [r7, #52] @ 0x34
80077a4: e841 2300 strex r3, r2, [r1]
80077a8: 62fb str r3, [r7, #44] @ 0x2c
return(result);
80077aa: 6afb ldr r3, [r7, #44] @ 0x2c
80077ac: 2b00 cmp r3, #0
80077ae: d1e6 bne.n 800777e <UART_Start_Receive_IT+0x1be>
80077b0: e018 b.n 80077e4 <UART_Start_Receive_IT+0x224>
}
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
80077b2: 68fb ldr r3, [r7, #12]
80077b4: 681b ldr r3, [r3, #0]
80077b6: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80077b8: 697b ldr r3, [r7, #20]
80077ba: e853 3f00 ldrex r3, [r3]
80077be: 613b str r3, [r7, #16]
return(result);
80077c0: 693b ldr r3, [r7, #16]
80077c2: f043 0320 orr.w r3, r3, #32
80077c6: 67bb str r3, [r7, #120] @ 0x78
80077c8: 68fb ldr r3, [r7, #12]
80077ca: 681b ldr r3, [r3, #0]
80077cc: 461a mov r2, r3
80077ce: 6fbb ldr r3, [r7, #120] @ 0x78
80077d0: 623b str r3, [r7, #32]
80077d2: 61fa str r2, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80077d4: 69f9 ldr r1, [r7, #28]
80077d6: 6a3a ldr r2, [r7, #32]
80077d8: e841 2300 strex r3, r2, [r1]
80077dc: 61bb str r3, [r7, #24]
return(result);
80077de: 69bb ldr r3, [r7, #24]
80077e0: 2b00 cmp r3, #0
80077e2: d1e6 bne.n 80077b2 <UART_Start_Receive_IT+0x1f2>
}
}
return HAL_OK;
80077e4: 2300 movs r3, #0
}
80077e6: 4618 mov r0, r3
80077e8: 378c adds r7, #140 @ 0x8c
80077ea: 46bd mov sp, r7
80077ec: f85d 7b04 ldr.w r7, [sp], #4
80077f0: 4770 bx lr
80077f2: bf00 nop
80077f4: 08008021 .word 0x08008021
80077f8: 08007cbd .word 0x08007cbd
80077fc: 08007b05 .word 0x08007b05
8007800: 0800794d .word 0x0800794d
08007804 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8007804: b480 push {r7}
8007806: b095 sub sp, #84 @ 0x54
8007808: af00 add r7, sp, #0
800780a: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
800780c: 687b ldr r3, [r7, #4]
800780e: 681b ldr r3, [r3, #0]
8007810: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007812: 6b7b ldr r3, [r7, #52] @ 0x34
8007814: e853 3f00 ldrex r3, [r3]
8007818: 633b str r3, [r7, #48] @ 0x30
return(result);
800781a: 6b3b ldr r3, [r7, #48] @ 0x30
800781c: f423 7390 bic.w r3, r3, #288 @ 0x120
8007820: 64fb str r3, [r7, #76] @ 0x4c
8007822: 687b ldr r3, [r7, #4]
8007824: 681b ldr r3, [r3, #0]
8007826: 461a mov r2, r3
8007828: 6cfb ldr r3, [r7, #76] @ 0x4c
800782a: 643b str r3, [r7, #64] @ 0x40
800782c: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800782e: 6bf9 ldr r1, [r7, #60] @ 0x3c
8007830: 6c3a ldr r2, [r7, #64] @ 0x40
8007832: e841 2300 strex r3, r2, [r1]
8007836: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007838: 6bbb ldr r3, [r7, #56] @ 0x38
800783a: 2b00 cmp r3, #0
800783c: d1e6 bne.n 800780c <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
800783e: 687b ldr r3, [r7, #4]
8007840: 681b ldr r3, [r3, #0]
8007842: 3308 adds r3, #8
8007844: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007846: 6a3b ldr r3, [r7, #32]
8007848: e853 3f00 ldrex r3, [r3]
800784c: 61fb str r3, [r7, #28]
return(result);
800784e: 69fb ldr r3, [r7, #28]
8007850: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007854: f023 0301 bic.w r3, r3, #1
8007858: 64bb str r3, [r7, #72] @ 0x48
800785a: 687b ldr r3, [r7, #4]
800785c: 681b ldr r3, [r3, #0]
800785e: 3308 adds r3, #8
8007860: 6cba ldr r2, [r7, #72] @ 0x48
8007862: 62fa str r2, [r7, #44] @ 0x2c
8007864: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007866: 6ab9 ldr r1, [r7, #40] @ 0x28
8007868: 6afa ldr r2, [r7, #44] @ 0x2c
800786a: e841 2300 strex r3, r2, [r1]
800786e: 627b str r3, [r7, #36] @ 0x24
return(result);
8007870: 6a7b ldr r3, [r7, #36] @ 0x24
8007872: 2b00 cmp r3, #0
8007874: d1e3 bne.n 800783e <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007876: 687b ldr r3, [r7, #4]
8007878: 6edb ldr r3, [r3, #108] @ 0x6c
800787a: 2b01 cmp r3, #1
800787c: d118 bne.n 80078b0 <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800787e: 687b ldr r3, [r7, #4]
8007880: 681b ldr r3, [r3, #0]
8007882: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007884: 68fb ldr r3, [r7, #12]
8007886: e853 3f00 ldrex r3, [r3]
800788a: 60bb str r3, [r7, #8]
return(result);
800788c: 68bb ldr r3, [r7, #8]
800788e: f023 0310 bic.w r3, r3, #16
8007892: 647b str r3, [r7, #68] @ 0x44
8007894: 687b ldr r3, [r7, #4]
8007896: 681b ldr r3, [r3, #0]
8007898: 461a mov r2, r3
800789a: 6c7b ldr r3, [r7, #68] @ 0x44
800789c: 61bb str r3, [r7, #24]
800789e: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80078a0: 6979 ldr r1, [r7, #20]
80078a2: 69ba ldr r2, [r7, #24]
80078a4: e841 2300 strex r3, r2, [r1]
80078a8: 613b str r3, [r7, #16]
return(result);
80078aa: 693b ldr r3, [r7, #16]
80078ac: 2b00 cmp r3, #0
80078ae: d1e6 bne.n 800787e <UART_EndRxTransfer+0x7a>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80078b0: 687b ldr r3, [r7, #4]
80078b2: 2220 movs r2, #32
80078b4: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80078b8: 687b ldr r3, [r7, #4]
80078ba: 2200 movs r2, #0
80078bc: 66da str r2, [r3, #108] @ 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
80078be: 687b ldr r3, [r7, #4]
80078c0: 2200 movs r2, #0
80078c2: 675a str r2, [r3, #116] @ 0x74
}
80078c4: bf00 nop
80078c6: 3754 adds r7, #84 @ 0x54
80078c8: 46bd mov sp, r7
80078ca: f85d 7b04 ldr.w r7, [sp], #4
80078ce: 4770 bx lr
080078d0 <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
80078d0: b580 push {r7, lr}
80078d2: b084 sub sp, #16
80078d4: af00 add r7, sp, #0
80078d6: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
80078d8: 687b ldr r3, [r7, #4]
80078da: 6a9b ldr r3, [r3, #40] @ 0x28
80078dc: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
80078de: 68fb ldr r3, [r7, #12]
80078e0: 2200 movs r2, #0
80078e2: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80078e6: 68f8 ldr r0, [r7, #12]
80078e8: f7ff f9ce bl 8006c88 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80078ec: bf00 nop
80078ee: 3710 adds r7, #16
80078f0: 46bd mov sp, r7
80078f2: bd80 pop {r7, pc}
080078f4 <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
80078f4: b580 push {r7, lr}
80078f6: b088 sub sp, #32
80078f8: af00 add r7, sp, #0
80078fa: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
80078fc: 687b ldr r3, [r7, #4]
80078fe: 681b ldr r3, [r3, #0]
8007900: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007902: 68fb ldr r3, [r7, #12]
8007904: e853 3f00 ldrex r3, [r3]
8007908: 60bb str r3, [r7, #8]
return(result);
800790a: 68bb ldr r3, [r7, #8]
800790c: f023 0340 bic.w r3, r3, #64 @ 0x40
8007910: 61fb str r3, [r7, #28]
8007912: 687b ldr r3, [r7, #4]
8007914: 681b ldr r3, [r3, #0]
8007916: 461a mov r2, r3
8007918: 69fb ldr r3, [r7, #28]
800791a: 61bb str r3, [r7, #24]
800791c: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800791e: 6979 ldr r1, [r7, #20]
8007920: 69ba ldr r2, [r7, #24]
8007922: e841 2300 strex r3, r2, [r1]
8007926: 613b str r3, [r7, #16]
return(result);
8007928: 693b ldr r3, [r7, #16]
800792a: 2b00 cmp r3, #0
800792c: d1e6 bne.n 80078fc <UART_EndTransmit_IT+0x8>
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800792e: 687b ldr r3, [r7, #4]
8007930: 2220 movs r2, #32
8007932: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
8007936: 687b ldr r3, [r7, #4]
8007938: 2200 movs r2, #0
800793a: 679a str r2, [r3, #120] @ 0x78
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
800793c: 6878 ldr r0, [r7, #4]
800793e: f7f9 fea7 bl 8001690 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8007942: bf00 nop
8007944: 3720 adds r7, #32
8007946: 46bd mov sp, r7
8007948: bd80 pop {r7, pc}
...
0800794c <UART_RxISR_8BIT>:
* @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
800794c: b580 push {r7, lr}
800794e: b09c sub sp, #112 @ 0x70
8007950: af00 add r7, sp, #0
8007952: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8007954: 687b ldr r3, [r7, #4]
8007956: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
800795a: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
800795e: 687b ldr r3, [r7, #4]
8007960: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007964: 2b22 cmp r3, #34 @ 0x22
8007966: f040 80be bne.w 8007ae6 <UART_RxISR_8BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
800796a: 687b ldr r3, [r7, #4]
800796c: 681b ldr r3, [r3, #0]
800796e: 6a5b ldr r3, [r3, #36] @ 0x24
8007970: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8007974: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
8007978: b2d9 uxtb r1, r3
800797a: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
800797e: b2da uxtb r2, r3
8007980: 687b ldr r3, [r7, #4]
8007982: 6d9b ldr r3, [r3, #88] @ 0x58
8007984: 400a ands r2, r1
8007986: b2d2 uxtb r2, r2
8007988: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
800798a: 687b ldr r3, [r7, #4]
800798c: 6d9b ldr r3, [r3, #88] @ 0x58
800798e: 1c5a adds r2, r3, #1
8007990: 687b ldr r3, [r7, #4]
8007992: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007994: 687b ldr r3, [r7, #4]
8007996: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800799a: b29b uxth r3, r3
800799c: 3b01 subs r3, #1
800799e: b29a uxth r2, r3
80079a0: 687b ldr r3, [r7, #4]
80079a2: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
if (huart->RxXferCount == 0U)
80079a6: 687b ldr r3, [r7, #4]
80079a8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
80079ac: b29b uxth r3, r3
80079ae: 2b00 cmp r3, #0
80079b0: f040 80a1 bne.w 8007af6 <UART_RxISR_8BIT+0x1aa>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80079b4: 687b ldr r3, [r7, #4]
80079b6: 681b ldr r3, [r3, #0]
80079b8: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80079ba: 6cfb ldr r3, [r7, #76] @ 0x4c
80079bc: e853 3f00 ldrex r3, [r3]
80079c0: 64bb str r3, [r7, #72] @ 0x48
return(result);
80079c2: 6cbb ldr r3, [r7, #72] @ 0x48
80079c4: f423 7390 bic.w r3, r3, #288 @ 0x120
80079c8: 66bb str r3, [r7, #104] @ 0x68
80079ca: 687b ldr r3, [r7, #4]
80079cc: 681b ldr r3, [r3, #0]
80079ce: 461a mov r2, r3
80079d0: 6ebb ldr r3, [r7, #104] @ 0x68
80079d2: 65bb str r3, [r7, #88] @ 0x58
80079d4: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80079d6: 6d79 ldr r1, [r7, #84] @ 0x54
80079d8: 6dba ldr r2, [r7, #88] @ 0x58
80079da: e841 2300 strex r3, r2, [r1]
80079de: 653b str r3, [r7, #80] @ 0x50
return(result);
80079e0: 6d3b ldr r3, [r7, #80] @ 0x50
80079e2: 2b00 cmp r3, #0
80079e4: d1e6 bne.n 80079b4 <UART_RxISR_8BIT+0x68>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80079e6: 687b ldr r3, [r7, #4]
80079e8: 681b ldr r3, [r3, #0]
80079ea: 3308 adds r3, #8
80079ec: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80079ee: 6bbb ldr r3, [r7, #56] @ 0x38
80079f0: e853 3f00 ldrex r3, [r3]
80079f4: 637b str r3, [r7, #52] @ 0x34
return(result);
80079f6: 6b7b ldr r3, [r7, #52] @ 0x34
80079f8: f023 0301 bic.w r3, r3, #1
80079fc: 667b str r3, [r7, #100] @ 0x64
80079fe: 687b ldr r3, [r7, #4]
8007a00: 681b ldr r3, [r3, #0]
8007a02: 3308 adds r3, #8
8007a04: 6e7a ldr r2, [r7, #100] @ 0x64
8007a06: 647a str r2, [r7, #68] @ 0x44
8007a08: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007a0a: 6c39 ldr r1, [r7, #64] @ 0x40
8007a0c: 6c7a ldr r2, [r7, #68] @ 0x44
8007a0e: e841 2300 strex r3, r2, [r1]
8007a12: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8007a14: 6bfb ldr r3, [r7, #60] @ 0x3c
8007a16: 2b00 cmp r3, #0
8007a18: d1e5 bne.n 80079e6 <UART_RxISR_8BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007a1a: 687b ldr r3, [r7, #4]
8007a1c: 2220 movs r2, #32
8007a1e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007a22: 687b ldr r3, [r7, #4]
8007a24: 2200 movs r2, #0
8007a26: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007a28: 687b ldr r3, [r7, #4]
8007a2a: 2200 movs r2, #0
8007a2c: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007a2e: 687b ldr r3, [r7, #4]
8007a30: 681b ldr r3, [r3, #0]
8007a32: 4a33 ldr r2, [pc, #204] @ (8007b00 <UART_RxISR_8BIT+0x1b4>)
8007a34: 4293 cmp r3, r2
8007a36: d01f beq.n 8007a78 <UART_RxISR_8BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007a38: 687b ldr r3, [r7, #4]
8007a3a: 681b ldr r3, [r3, #0]
8007a3c: 685b ldr r3, [r3, #4]
8007a3e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007a42: 2b00 cmp r3, #0
8007a44: d018 beq.n 8007a78 <UART_RxISR_8BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007a46: 687b ldr r3, [r7, #4]
8007a48: 681b ldr r3, [r3, #0]
8007a4a: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007a4c: 6a7b ldr r3, [r7, #36] @ 0x24
8007a4e: e853 3f00 ldrex r3, [r3]
8007a52: 623b str r3, [r7, #32]
return(result);
8007a54: 6a3b ldr r3, [r7, #32]
8007a56: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007a5a: 663b str r3, [r7, #96] @ 0x60
8007a5c: 687b ldr r3, [r7, #4]
8007a5e: 681b ldr r3, [r3, #0]
8007a60: 461a mov r2, r3
8007a62: 6e3b ldr r3, [r7, #96] @ 0x60
8007a64: 633b str r3, [r7, #48] @ 0x30
8007a66: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007a68: 6af9 ldr r1, [r7, #44] @ 0x2c
8007a6a: 6b3a ldr r2, [r7, #48] @ 0x30
8007a6c: e841 2300 strex r3, r2, [r1]
8007a70: 62bb str r3, [r7, #40] @ 0x28
return(result);
8007a72: 6abb ldr r3, [r7, #40] @ 0x28
8007a74: 2b00 cmp r3, #0
8007a76: d1e6 bne.n 8007a46 <UART_RxISR_8BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007a78: 687b ldr r3, [r7, #4]
8007a7a: 6edb ldr r3, [r3, #108] @ 0x6c
8007a7c: 2b01 cmp r3, #1
8007a7e: d12e bne.n 8007ade <UART_RxISR_8BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007a80: 687b ldr r3, [r7, #4]
8007a82: 2200 movs r2, #0
8007a84: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007a86: 687b ldr r3, [r7, #4]
8007a88: 681b ldr r3, [r3, #0]
8007a8a: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007a8c: 693b ldr r3, [r7, #16]
8007a8e: e853 3f00 ldrex r3, [r3]
8007a92: 60fb str r3, [r7, #12]
return(result);
8007a94: 68fb ldr r3, [r7, #12]
8007a96: f023 0310 bic.w r3, r3, #16
8007a9a: 65fb str r3, [r7, #92] @ 0x5c
8007a9c: 687b ldr r3, [r7, #4]
8007a9e: 681b ldr r3, [r3, #0]
8007aa0: 461a mov r2, r3
8007aa2: 6dfb ldr r3, [r7, #92] @ 0x5c
8007aa4: 61fb str r3, [r7, #28]
8007aa6: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007aa8: 69b9 ldr r1, [r7, #24]
8007aaa: 69fa ldr r2, [r7, #28]
8007aac: e841 2300 strex r3, r2, [r1]
8007ab0: 617b str r3, [r7, #20]
return(result);
8007ab2: 697b ldr r3, [r7, #20]
8007ab4: 2b00 cmp r3, #0
8007ab6: d1e6 bne.n 8007a86 <UART_RxISR_8BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007ab8: 687b ldr r3, [r7, #4]
8007aba: 681b ldr r3, [r3, #0]
8007abc: 69db ldr r3, [r3, #28]
8007abe: f003 0310 and.w r3, r3, #16
8007ac2: 2b10 cmp r3, #16
8007ac4: d103 bne.n 8007ace <UART_RxISR_8BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007ac6: 687b ldr r3, [r7, #4]
8007ac8: 681b ldr r3, [r3, #0]
8007aca: 2210 movs r2, #16
8007acc: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007ace: 687b ldr r3, [r7, #4]
8007ad0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007ad4: 4619 mov r1, r3
8007ad6: 6878 ldr r0, [r7, #4]
8007ad8: f7ff f8e0 bl 8006c9c <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007adc: e00b b.n 8007af6 <UART_RxISR_8BIT+0x1aa>
HAL_UART_RxCpltCallback(huart);
8007ade: 6878 ldr r0, [r7, #4]
8007ae0: f7f9 fde0 bl 80016a4 <HAL_UART_RxCpltCallback>
}
8007ae4: e007 b.n 8007af6 <UART_RxISR_8BIT+0x1aa>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007ae6: 687b ldr r3, [r7, #4]
8007ae8: 681b ldr r3, [r3, #0]
8007aea: 699a ldr r2, [r3, #24]
8007aec: 687b ldr r3, [r7, #4]
8007aee: 681b ldr r3, [r3, #0]
8007af0: f042 0208 orr.w r2, r2, #8
8007af4: 619a str r2, [r3, #24]
}
8007af6: bf00 nop
8007af8: 3770 adds r7, #112 @ 0x70
8007afa: 46bd mov sp, r7
8007afc: bd80 pop {r7, pc}
8007afe: bf00 nop
8007b00: 40008000 .word 0x40008000
08007b04 <UART_RxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
8007b04: b580 push {r7, lr}
8007b06: b09c sub sp, #112 @ 0x70
8007b08: af00 add r7, sp, #0
8007b0a: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8007b0c: 687b ldr r3, [r7, #4]
8007b0e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007b12: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007b16: 687b ldr r3, [r7, #4]
8007b18: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007b1c: 2b22 cmp r3, #34 @ 0x22
8007b1e: f040 80be bne.w 8007c9e <UART_RxISR_16BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8007b22: 687b ldr r3, [r7, #4]
8007b24: 681b ldr r3, [r3, #0]
8007b26: 6a5b ldr r3, [r3, #36] @ 0x24
8007b28: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
tmp = (uint16_t *) huart->pRxBuffPtr ;
8007b2c: 687b ldr r3, [r7, #4]
8007b2e: 6d9b ldr r3, [r3, #88] @ 0x58
8007b30: 66bb str r3, [r7, #104] @ 0x68
*tmp = (uint16_t)(uhdata & uhMask);
8007b32: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c
8007b36: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
8007b3a: 4013 ands r3, r2
8007b3c: b29a uxth r2, r3
8007b3e: 6ebb ldr r3, [r7, #104] @ 0x68
8007b40: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8007b42: 687b ldr r3, [r7, #4]
8007b44: 6d9b ldr r3, [r3, #88] @ 0x58
8007b46: 1c9a adds r2, r3, #2
8007b48: 687b ldr r3, [r7, #4]
8007b4a: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007b4c: 687b ldr r3, [r7, #4]
8007b4e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007b52: b29b uxth r3, r3
8007b54: 3b01 subs r3, #1
8007b56: b29a uxth r2, r3
8007b58: 687b ldr r3, [r7, #4]
8007b5a: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
if (huart->RxXferCount == 0U)
8007b5e: 687b ldr r3, [r7, #4]
8007b60: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007b64: b29b uxth r3, r3
8007b66: 2b00 cmp r3, #0
8007b68: f040 80a1 bne.w 8007cae <UART_RxISR_16BIT+0x1aa>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8007b6c: 687b ldr r3, [r7, #4]
8007b6e: 681b ldr r3, [r3, #0]
8007b70: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007b72: 6cbb ldr r3, [r7, #72] @ 0x48
8007b74: e853 3f00 ldrex r3, [r3]
8007b78: 647b str r3, [r7, #68] @ 0x44
return(result);
8007b7a: 6c7b ldr r3, [r7, #68] @ 0x44
8007b7c: f423 7390 bic.w r3, r3, #288 @ 0x120
8007b80: 667b str r3, [r7, #100] @ 0x64
8007b82: 687b ldr r3, [r7, #4]
8007b84: 681b ldr r3, [r3, #0]
8007b86: 461a mov r2, r3
8007b88: 6e7b ldr r3, [r7, #100] @ 0x64
8007b8a: 657b str r3, [r7, #84] @ 0x54
8007b8c: 653a str r2, [r7, #80] @ 0x50
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007b8e: 6d39 ldr r1, [r7, #80] @ 0x50
8007b90: 6d7a ldr r2, [r7, #84] @ 0x54
8007b92: e841 2300 strex r3, r2, [r1]
8007b96: 64fb str r3, [r7, #76] @ 0x4c
return(result);
8007b98: 6cfb ldr r3, [r7, #76] @ 0x4c
8007b9a: 2b00 cmp r3, #0
8007b9c: d1e6 bne.n 8007b6c <UART_RxISR_16BIT+0x68>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8007b9e: 687b ldr r3, [r7, #4]
8007ba0: 681b ldr r3, [r3, #0]
8007ba2: 3308 adds r3, #8
8007ba4: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007ba6: 6b7b ldr r3, [r7, #52] @ 0x34
8007ba8: e853 3f00 ldrex r3, [r3]
8007bac: 633b str r3, [r7, #48] @ 0x30
return(result);
8007bae: 6b3b ldr r3, [r7, #48] @ 0x30
8007bb0: f023 0301 bic.w r3, r3, #1
8007bb4: 663b str r3, [r7, #96] @ 0x60
8007bb6: 687b ldr r3, [r7, #4]
8007bb8: 681b ldr r3, [r3, #0]
8007bba: 3308 adds r3, #8
8007bbc: 6e3a ldr r2, [r7, #96] @ 0x60
8007bbe: 643a str r2, [r7, #64] @ 0x40
8007bc0: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007bc2: 6bf9 ldr r1, [r7, #60] @ 0x3c
8007bc4: 6c3a ldr r2, [r7, #64] @ 0x40
8007bc6: e841 2300 strex r3, r2, [r1]
8007bca: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007bcc: 6bbb ldr r3, [r7, #56] @ 0x38
8007bce: 2b00 cmp r3, #0
8007bd0: d1e5 bne.n 8007b9e <UART_RxISR_16BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007bd2: 687b ldr r3, [r7, #4]
8007bd4: 2220 movs r2, #32
8007bd6: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007bda: 687b ldr r3, [r7, #4]
8007bdc: 2200 movs r2, #0
8007bde: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007be0: 687b ldr r3, [r7, #4]
8007be2: 2200 movs r2, #0
8007be4: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007be6: 687b ldr r3, [r7, #4]
8007be8: 681b ldr r3, [r3, #0]
8007bea: 4a33 ldr r2, [pc, #204] @ (8007cb8 <UART_RxISR_16BIT+0x1b4>)
8007bec: 4293 cmp r3, r2
8007bee: d01f beq.n 8007c30 <UART_RxISR_16BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007bf0: 687b ldr r3, [r7, #4]
8007bf2: 681b ldr r3, [r3, #0]
8007bf4: 685b ldr r3, [r3, #4]
8007bf6: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007bfa: 2b00 cmp r3, #0
8007bfc: d018 beq.n 8007c30 <UART_RxISR_16BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007bfe: 687b ldr r3, [r7, #4]
8007c00: 681b ldr r3, [r3, #0]
8007c02: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007c04: 6a3b ldr r3, [r7, #32]
8007c06: e853 3f00 ldrex r3, [r3]
8007c0a: 61fb str r3, [r7, #28]
return(result);
8007c0c: 69fb ldr r3, [r7, #28]
8007c0e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007c12: 65fb str r3, [r7, #92] @ 0x5c
8007c14: 687b ldr r3, [r7, #4]
8007c16: 681b ldr r3, [r3, #0]
8007c18: 461a mov r2, r3
8007c1a: 6dfb ldr r3, [r7, #92] @ 0x5c
8007c1c: 62fb str r3, [r7, #44] @ 0x2c
8007c1e: 62ba str r2, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007c20: 6ab9 ldr r1, [r7, #40] @ 0x28
8007c22: 6afa ldr r2, [r7, #44] @ 0x2c
8007c24: e841 2300 strex r3, r2, [r1]
8007c28: 627b str r3, [r7, #36] @ 0x24
return(result);
8007c2a: 6a7b ldr r3, [r7, #36] @ 0x24
8007c2c: 2b00 cmp r3, #0
8007c2e: d1e6 bne.n 8007bfe <UART_RxISR_16BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007c30: 687b ldr r3, [r7, #4]
8007c32: 6edb ldr r3, [r3, #108] @ 0x6c
8007c34: 2b01 cmp r3, #1
8007c36: d12e bne.n 8007c96 <UART_RxISR_16BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007c38: 687b ldr r3, [r7, #4]
8007c3a: 2200 movs r2, #0
8007c3c: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007c3e: 687b ldr r3, [r7, #4]
8007c40: 681b ldr r3, [r3, #0]
8007c42: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007c44: 68fb ldr r3, [r7, #12]
8007c46: e853 3f00 ldrex r3, [r3]
8007c4a: 60bb str r3, [r7, #8]
return(result);
8007c4c: 68bb ldr r3, [r7, #8]
8007c4e: f023 0310 bic.w r3, r3, #16
8007c52: 65bb str r3, [r7, #88] @ 0x58
8007c54: 687b ldr r3, [r7, #4]
8007c56: 681b ldr r3, [r3, #0]
8007c58: 461a mov r2, r3
8007c5a: 6dbb ldr r3, [r7, #88] @ 0x58
8007c5c: 61bb str r3, [r7, #24]
8007c5e: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007c60: 6979 ldr r1, [r7, #20]
8007c62: 69ba ldr r2, [r7, #24]
8007c64: e841 2300 strex r3, r2, [r1]
8007c68: 613b str r3, [r7, #16]
return(result);
8007c6a: 693b ldr r3, [r7, #16]
8007c6c: 2b00 cmp r3, #0
8007c6e: d1e6 bne.n 8007c3e <UART_RxISR_16BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007c70: 687b ldr r3, [r7, #4]
8007c72: 681b ldr r3, [r3, #0]
8007c74: 69db ldr r3, [r3, #28]
8007c76: f003 0310 and.w r3, r3, #16
8007c7a: 2b10 cmp r3, #16
8007c7c: d103 bne.n 8007c86 <UART_RxISR_16BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007c7e: 687b ldr r3, [r7, #4]
8007c80: 681b ldr r3, [r3, #0]
8007c82: 2210 movs r2, #16
8007c84: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007c86: 687b ldr r3, [r7, #4]
8007c88: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007c8c: 4619 mov r1, r3
8007c8e: 6878 ldr r0, [r7, #4]
8007c90: f7ff f804 bl 8006c9c <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007c94: e00b b.n 8007cae <UART_RxISR_16BIT+0x1aa>
HAL_UART_RxCpltCallback(huart);
8007c96: 6878 ldr r0, [r7, #4]
8007c98: f7f9 fd04 bl 80016a4 <HAL_UART_RxCpltCallback>
}
8007c9c: e007 b.n 8007cae <UART_RxISR_16BIT+0x1aa>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007c9e: 687b ldr r3, [r7, #4]
8007ca0: 681b ldr r3, [r3, #0]
8007ca2: 699a ldr r2, [r3, #24]
8007ca4: 687b ldr r3, [r7, #4]
8007ca6: 681b ldr r3, [r3, #0]
8007ca8: f042 0208 orr.w r2, r2, #8
8007cac: 619a str r2, [r3, #24]
}
8007cae: bf00 nop
8007cb0: 3770 adds r7, #112 @ 0x70
8007cb2: 46bd mov sp, r7
8007cb4: bd80 pop {r7, pc}
8007cb6: bf00 nop
8007cb8: 40008000 .word 0x40008000
08007cbc <UART_RxISR_8BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
8007cbc: b580 push {r7, lr}
8007cbe: b0ac sub sp, #176 @ 0xb0
8007cc0: af00 add r7, sp, #0
8007cc2: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8007cc4: 687b ldr r3, [r7, #4]
8007cc6: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007cca: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8007cce: 687b ldr r3, [r7, #4]
8007cd0: 681b ldr r3, [r3, #0]
8007cd2: 69db ldr r3, [r3, #28]
8007cd4: f8c7 30ac str.w r3, [r7, #172] @ 0xac
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8007cd8: 687b ldr r3, [r7, #4]
8007cda: 681b ldr r3, [r3, #0]
8007cdc: 681b ldr r3, [r3, #0]
8007cde: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8007ce2: 687b ldr r3, [r7, #4]
8007ce4: 681b ldr r3, [r3, #0]
8007ce6: 689b ldr r3, [r3, #8]
8007ce8: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007cec: 687b ldr r3, [r7, #4]
8007cee: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007cf2: 2b22 cmp r3, #34 @ 0x22
8007cf4: f040 8183 bne.w 8007ffe <UART_RxISR_8BIT_FIFOEN+0x342>
{
nb_rx_data = huart->NbRxDataToProcess;
8007cf8: 687b ldr r3, [r7, #4]
8007cfa: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8007cfe: f8a7 309e strh.w r3, [r7, #158] @ 0x9e
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8007d02: e126 b.n 8007f52 <UART_RxISR_8BIT_FIFOEN+0x296>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8007d04: 687b ldr r3, [r7, #4]
8007d06: 681b ldr r3, [r3, #0]
8007d08: 6a5b ldr r3, [r3, #36] @ 0x24
8007d0a: f8a7 309c strh.w r3, [r7, #156] @ 0x9c
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8007d0e: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c
8007d12: b2d9 uxtb r1, r3
8007d14: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa
8007d18: b2da uxtb r2, r3
8007d1a: 687b ldr r3, [r7, #4]
8007d1c: 6d9b ldr r3, [r3, #88] @ 0x58
8007d1e: 400a ands r2, r1
8007d20: b2d2 uxtb r2, r2
8007d22: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
8007d24: 687b ldr r3, [r7, #4]
8007d26: 6d9b ldr r3, [r3, #88] @ 0x58
8007d28: 1c5a adds r2, r3, #1
8007d2a: 687b ldr r3, [r7, #4]
8007d2c: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007d2e: 687b ldr r3, [r7, #4]
8007d30: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007d34: b29b uxth r3, r3
8007d36: 3b01 subs r3, #1
8007d38: b29a uxth r2, r3
8007d3a: 687b ldr r3, [r7, #4]
8007d3c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
isrflags = READ_REG(huart->Instance->ISR);
8007d40: 687b ldr r3, [r7, #4]
8007d42: 681b ldr r3, [r3, #0]
8007d44: 69db ldr r3, [r3, #28]
8007d46: f8c7 30ac str.w r3, [r7, #172] @ 0xac
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
8007d4a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007d4e: f003 0307 and.w r3, r3, #7
8007d52: 2b00 cmp r3, #0
8007d54: d053 beq.n 8007dfe <UART_RxISR_8BIT_FIFOEN+0x142>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8007d56: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007d5a: f003 0301 and.w r3, r3, #1
8007d5e: 2b00 cmp r3, #0
8007d60: d011 beq.n 8007d86 <UART_RxISR_8BIT_FIFOEN+0xca>
8007d62: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8007d66: f403 7380 and.w r3, r3, #256 @ 0x100
8007d6a: 2b00 cmp r3, #0
8007d6c: d00b beq.n 8007d86 <UART_RxISR_8BIT_FIFOEN+0xca>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8007d6e: 687b ldr r3, [r7, #4]
8007d70: 681b ldr r3, [r3, #0]
8007d72: 2201 movs r2, #1
8007d74: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8007d76: 687b ldr r3, [r7, #4]
8007d78: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007d7c: f043 0201 orr.w r2, r3, #1
8007d80: 687b ldr r3, [r7, #4]
8007d82: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007d86: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007d8a: f003 0302 and.w r3, r3, #2
8007d8e: 2b00 cmp r3, #0
8007d90: d011 beq.n 8007db6 <UART_RxISR_8BIT_FIFOEN+0xfa>
8007d92: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8007d96: f003 0301 and.w r3, r3, #1
8007d9a: 2b00 cmp r3, #0
8007d9c: d00b beq.n 8007db6 <UART_RxISR_8BIT_FIFOEN+0xfa>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8007d9e: 687b ldr r3, [r7, #4]
8007da0: 681b ldr r3, [r3, #0]
8007da2: 2202 movs r2, #2
8007da4: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8007da6: 687b ldr r3, [r7, #4]
8007da8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007dac: f043 0204 orr.w r2, r3, #4
8007db0: 687b ldr r3, [r7, #4]
8007db2: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007db6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007dba: f003 0304 and.w r3, r3, #4
8007dbe: 2b00 cmp r3, #0
8007dc0: d011 beq.n 8007de6 <UART_RxISR_8BIT_FIFOEN+0x12a>
8007dc2: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8007dc6: f003 0301 and.w r3, r3, #1
8007dca: 2b00 cmp r3, #0
8007dcc: d00b beq.n 8007de6 <UART_RxISR_8BIT_FIFOEN+0x12a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8007dce: 687b ldr r3, [r7, #4]
8007dd0: 681b ldr r3, [r3, #0]
8007dd2: 2204 movs r2, #4
8007dd4: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8007dd6: 687b ldr r3, [r7, #4]
8007dd8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007ddc: f043 0202 orr.w r2, r3, #2
8007de0: 687b ldr r3, [r7, #4]
8007de2: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8007de6: 687b ldr r3, [r7, #4]
8007de8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007dec: 2b00 cmp r3, #0
8007dee: d006 beq.n 8007dfe <UART_RxISR_8BIT_FIFOEN+0x142>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8007df0: 6878 ldr r0, [r7, #4]
8007df2: f7fe ff49 bl 8006c88 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007df6: 687b ldr r3, [r7, #4]
8007df8: 2200 movs r2, #0
8007dfa: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
if (huart->RxXferCount == 0U)
8007dfe: 687b ldr r3, [r7, #4]
8007e00: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007e04: b29b uxth r3, r3
8007e06: 2b00 cmp r3, #0
8007e08: f040 80a3 bne.w 8007f52 <UART_RxISR_8BIT_FIFOEN+0x296>
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8007e0c: 687b ldr r3, [r7, #4]
8007e0e: 681b ldr r3, [r3, #0]
8007e10: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007e12: 6f3b ldr r3, [r7, #112] @ 0x70
8007e14: e853 3f00 ldrex r3, [r3]
8007e18: 66fb str r3, [r7, #108] @ 0x6c
return(result);
8007e1a: 6efb ldr r3, [r7, #108] @ 0x6c
8007e1c: f423 7380 bic.w r3, r3, #256 @ 0x100
8007e20: f8c7 3098 str.w r3, [r7, #152] @ 0x98
8007e24: 687b ldr r3, [r7, #4]
8007e26: 681b ldr r3, [r3, #0]
8007e28: 461a mov r2, r3
8007e2a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8007e2e: 67fb str r3, [r7, #124] @ 0x7c
8007e30: 67ba str r2, [r7, #120] @ 0x78
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007e32: 6fb9 ldr r1, [r7, #120] @ 0x78
8007e34: 6ffa ldr r2, [r7, #124] @ 0x7c
8007e36: e841 2300 strex r3, r2, [r1]
8007e3a: 677b str r3, [r7, #116] @ 0x74
return(result);
8007e3c: 6f7b ldr r3, [r7, #116] @ 0x74
8007e3e: 2b00 cmp r3, #0
8007e40: d1e4 bne.n 8007e0c <UART_RxISR_8BIT_FIFOEN+0x150>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8007e42: 687b ldr r3, [r7, #4]
8007e44: 681b ldr r3, [r3, #0]
8007e46: 3308 adds r3, #8
8007e48: 65fb str r3, [r7, #92] @ 0x5c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007e4a: 6dfb ldr r3, [r7, #92] @ 0x5c
8007e4c: e853 3f00 ldrex r3, [r3]
8007e50: 65bb str r3, [r7, #88] @ 0x58
return(result);
8007e52: 6dbb ldr r3, [r7, #88] @ 0x58
8007e54: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007e58: f023 0301 bic.w r3, r3, #1
8007e5c: f8c7 3094 str.w r3, [r7, #148] @ 0x94
8007e60: 687b ldr r3, [r7, #4]
8007e62: 681b ldr r3, [r3, #0]
8007e64: 3308 adds r3, #8
8007e66: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
8007e6a: 66ba str r2, [r7, #104] @ 0x68
8007e6c: 667b str r3, [r7, #100] @ 0x64
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007e6e: 6e79 ldr r1, [r7, #100] @ 0x64
8007e70: 6eba ldr r2, [r7, #104] @ 0x68
8007e72: e841 2300 strex r3, r2, [r1]
8007e76: 663b str r3, [r7, #96] @ 0x60
return(result);
8007e78: 6e3b ldr r3, [r7, #96] @ 0x60
8007e7a: 2b00 cmp r3, #0
8007e7c: d1e1 bne.n 8007e42 <UART_RxISR_8BIT_FIFOEN+0x186>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007e7e: 687b ldr r3, [r7, #4]
8007e80: 2220 movs r2, #32
8007e82: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007e86: 687b ldr r3, [r7, #4]
8007e88: 2200 movs r2, #0
8007e8a: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007e8c: 687b ldr r3, [r7, #4]
8007e8e: 2200 movs r2, #0
8007e90: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007e92: 687b ldr r3, [r7, #4]
8007e94: 681b ldr r3, [r3, #0]
8007e96: 4a60 ldr r2, [pc, #384] @ (8008018 <UART_RxISR_8BIT_FIFOEN+0x35c>)
8007e98: 4293 cmp r3, r2
8007e9a: d021 beq.n 8007ee0 <UART_RxISR_8BIT_FIFOEN+0x224>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007e9c: 687b ldr r3, [r7, #4]
8007e9e: 681b ldr r3, [r3, #0]
8007ea0: 685b ldr r3, [r3, #4]
8007ea2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007ea6: 2b00 cmp r3, #0
8007ea8: d01a beq.n 8007ee0 <UART_RxISR_8BIT_FIFOEN+0x224>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007eaa: 687b ldr r3, [r7, #4]
8007eac: 681b ldr r3, [r3, #0]
8007eae: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007eb0: 6cbb ldr r3, [r7, #72] @ 0x48
8007eb2: e853 3f00 ldrex r3, [r3]
8007eb6: 647b str r3, [r7, #68] @ 0x44
return(result);
8007eb8: 6c7b ldr r3, [r7, #68] @ 0x44
8007eba: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007ebe: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8007ec2: 687b ldr r3, [r7, #4]
8007ec4: 681b ldr r3, [r3, #0]
8007ec6: 461a mov r2, r3
8007ec8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8007ecc: 657b str r3, [r7, #84] @ 0x54
8007ece: 653a str r2, [r7, #80] @ 0x50
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007ed0: 6d39 ldr r1, [r7, #80] @ 0x50
8007ed2: 6d7a ldr r2, [r7, #84] @ 0x54
8007ed4: e841 2300 strex r3, r2, [r1]
8007ed8: 64fb str r3, [r7, #76] @ 0x4c
return(result);
8007eda: 6cfb ldr r3, [r7, #76] @ 0x4c
8007edc: 2b00 cmp r3, #0
8007ede: d1e4 bne.n 8007eaa <UART_RxISR_8BIT_FIFOEN+0x1ee>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007ee0: 687b ldr r3, [r7, #4]
8007ee2: 6edb ldr r3, [r3, #108] @ 0x6c
8007ee4: 2b01 cmp r3, #1
8007ee6: d130 bne.n 8007f4a <UART_RxISR_8BIT_FIFOEN+0x28e>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007ee8: 687b ldr r3, [r7, #4]
8007eea: 2200 movs r2, #0
8007eec: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007eee: 687b ldr r3, [r7, #4]
8007ef0: 681b ldr r3, [r3, #0]
8007ef2: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007ef4: 6b7b ldr r3, [r7, #52] @ 0x34
8007ef6: e853 3f00 ldrex r3, [r3]
8007efa: 633b str r3, [r7, #48] @ 0x30
return(result);
8007efc: 6b3b ldr r3, [r7, #48] @ 0x30
8007efe: f023 0310 bic.w r3, r3, #16
8007f02: f8c7 308c str.w r3, [r7, #140] @ 0x8c
8007f06: 687b ldr r3, [r7, #4]
8007f08: 681b ldr r3, [r3, #0]
8007f0a: 461a mov r2, r3
8007f0c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8007f10: 643b str r3, [r7, #64] @ 0x40
8007f12: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007f14: 6bf9 ldr r1, [r7, #60] @ 0x3c
8007f16: 6c3a ldr r2, [r7, #64] @ 0x40
8007f18: e841 2300 strex r3, r2, [r1]
8007f1c: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007f1e: 6bbb ldr r3, [r7, #56] @ 0x38
8007f20: 2b00 cmp r3, #0
8007f22: d1e4 bne.n 8007eee <UART_RxISR_8BIT_FIFOEN+0x232>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007f24: 687b ldr r3, [r7, #4]
8007f26: 681b ldr r3, [r3, #0]
8007f28: 69db ldr r3, [r3, #28]
8007f2a: f003 0310 and.w r3, r3, #16
8007f2e: 2b10 cmp r3, #16
8007f30: d103 bne.n 8007f3a <UART_RxISR_8BIT_FIFOEN+0x27e>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007f32: 687b ldr r3, [r7, #4]
8007f34: 681b ldr r3, [r3, #0]
8007f36: 2210 movs r2, #16
8007f38: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007f3a: 687b ldr r3, [r7, #4]
8007f3c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007f40: 4619 mov r1, r3
8007f42: 6878 ldr r0, [r7, #4]
8007f44: f7fe feaa bl 8006c9c <HAL_UARTEx_RxEventCallback>
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
break;
8007f48: e00e b.n 8007f68 <UART_RxISR_8BIT_FIFOEN+0x2ac>
HAL_UART_RxCpltCallback(huart);
8007f4a: 6878 ldr r0, [r7, #4]
8007f4c: f7f9 fbaa bl 80016a4 <HAL_UART_RxCpltCallback>
break;
8007f50: e00a b.n 8007f68 <UART_RxISR_8BIT_FIFOEN+0x2ac>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8007f52: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e
8007f56: 2b00 cmp r3, #0
8007f58: d006 beq.n 8007f68 <UART_RxISR_8BIT_FIFOEN+0x2ac>
8007f5a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007f5e: f003 0320 and.w r3, r3, #32
8007f62: 2b00 cmp r3, #0
8007f64: f47f aece bne.w 8007d04 <UART_RxISR_8BIT_FIFOEN+0x48>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8007f68: 687b ldr r3, [r7, #4]
8007f6a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007f6e: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
8007f72: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
8007f76: 2b00 cmp r3, #0
8007f78: d049 beq.n 800800e <UART_RxISR_8BIT_FIFOEN+0x352>
8007f7a: 687b ldr r3, [r7, #4]
8007f7c: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8007f80: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a
8007f84: 429a cmp r2, r3
8007f86: d242 bcs.n 800800e <UART_RxISR_8BIT_FIFOEN+0x352>
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
8007f88: 687b ldr r3, [r7, #4]
8007f8a: 681b ldr r3, [r3, #0]
8007f8c: 3308 adds r3, #8
8007f8e: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007f90: 6a3b ldr r3, [r7, #32]
8007f92: e853 3f00 ldrex r3, [r3]
8007f96: 61fb str r3, [r7, #28]
return(result);
8007f98: 69fb ldr r3, [r7, #28]
8007f9a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007f9e: f8c7 3084 str.w r3, [r7, #132] @ 0x84
8007fa2: 687b ldr r3, [r7, #4]
8007fa4: 681b ldr r3, [r3, #0]
8007fa6: 3308 adds r3, #8
8007fa8: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
8007fac: 62fa str r2, [r7, #44] @ 0x2c
8007fae: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007fb0: 6ab9 ldr r1, [r7, #40] @ 0x28
8007fb2: 6afa ldr r2, [r7, #44] @ 0x2c
8007fb4: e841 2300 strex r3, r2, [r1]
8007fb8: 627b str r3, [r7, #36] @ 0x24
return(result);
8007fba: 6a7b ldr r3, [r7, #36] @ 0x24
8007fbc: 2b00 cmp r3, #0
8007fbe: d1e3 bne.n 8007f88 <UART_RxISR_8BIT_FIFOEN+0x2cc>
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_8BIT;
8007fc0: 687b ldr r3, [r7, #4]
8007fc2: 4a16 ldr r2, [pc, #88] @ (800801c <UART_RxISR_8BIT_FIFOEN+0x360>)
8007fc4: 675a str r2, [r3, #116] @ 0x74
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8007fc6: 687b ldr r3, [r7, #4]
8007fc8: 681b ldr r3, [r3, #0]
8007fca: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007fcc: 68fb ldr r3, [r7, #12]
8007fce: e853 3f00 ldrex r3, [r3]
8007fd2: 60bb str r3, [r7, #8]
return(result);
8007fd4: 68bb ldr r3, [r7, #8]
8007fd6: f043 0320 orr.w r3, r3, #32
8007fda: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8007fde: 687b ldr r3, [r7, #4]
8007fe0: 681b ldr r3, [r3, #0]
8007fe2: 461a mov r2, r3
8007fe4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8007fe8: 61bb str r3, [r7, #24]
8007fea: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007fec: 6979 ldr r1, [r7, #20]
8007fee: 69ba ldr r2, [r7, #24]
8007ff0: e841 2300 strex r3, r2, [r1]
8007ff4: 613b str r3, [r7, #16]
return(result);
8007ff6: 693b ldr r3, [r7, #16]
8007ff8: 2b00 cmp r3, #0
8007ffa: d1e4 bne.n 8007fc6 <UART_RxISR_8BIT_FIFOEN+0x30a>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007ffc: e007 b.n 800800e <UART_RxISR_8BIT_FIFOEN+0x352>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007ffe: 687b ldr r3, [r7, #4]
8008000: 681b ldr r3, [r3, #0]
8008002: 699a ldr r2, [r3, #24]
8008004: 687b ldr r3, [r7, #4]
8008006: 681b ldr r3, [r3, #0]
8008008: f042 0208 orr.w r2, r2, #8
800800c: 619a str r2, [r3, #24]
}
800800e: bf00 nop
8008010: 37b0 adds r7, #176 @ 0xb0
8008012: 46bd mov sp, r7
8008014: bd80 pop {r7, pc}
8008016: bf00 nop
8008018: 40008000 .word 0x40008000
800801c: 0800794d .word 0x0800794d
08008020 <UART_RxISR_16BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
8008020: b580 push {r7, lr}
8008022: b0ae sub sp, #184 @ 0xb8
8008024: af00 add r7, sp, #0
8008026: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8008028: 687b ldr r3, [r7, #4]
800802a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
800802e: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8008032: 687b ldr r3, [r7, #4]
8008034: 681b ldr r3, [r3, #0]
8008036: 69db ldr r3, [r3, #28]
8008038: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
800803c: 687b ldr r3, [r7, #4]
800803e: 681b ldr r3, [r3, #0]
8008040: 681b ldr r3, [r3, #0]
8008042: f8c7 30ac str.w r3, [r7, #172] @ 0xac
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8008046: 687b ldr r3, [r7, #4]
8008048: 681b ldr r3, [r3, #0]
800804a: 689b ldr r3, [r3, #8]
800804c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8008050: 687b ldr r3, [r7, #4]
8008052: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8008056: 2b22 cmp r3, #34 @ 0x22
8008058: f040 8187 bne.w 800836a <UART_RxISR_16BIT_FIFOEN+0x34a>
{
nb_rx_data = huart->NbRxDataToProcess;
800805c: 687b ldr r3, [r7, #4]
800805e: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8008062: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8008066: e12a b.n 80082be <UART_RxISR_16BIT_FIFOEN+0x29e>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8008068: 687b ldr r3, [r7, #4]
800806a: 681b ldr r3, [r3, #0]
800806c: 6a5b ldr r3, [r3, #36] @ 0x24
800806e: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4
tmp = (uint16_t *) huart->pRxBuffPtr ;
8008072: 687b ldr r3, [r7, #4]
8008074: 6d9b ldr r3, [r3, #88] @ 0x58
8008076: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
*tmp = (uint16_t)(uhdata & uhMask);
800807a: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4
800807e: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2
8008082: 4013 ands r3, r2
8008084: b29a uxth r2, r3
8008086: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
800808a: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
800808c: 687b ldr r3, [r7, #4]
800808e: 6d9b ldr r3, [r3, #88] @ 0x58
8008090: 1c9a adds r2, r3, #2
8008092: 687b ldr r3, [r7, #4]
8008094: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8008096: 687b ldr r3, [r7, #4]
8008098: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800809c: b29b uxth r3, r3
800809e: 3b01 subs r3, #1
80080a0: b29a uxth r2, r3
80080a2: 687b ldr r3, [r7, #4]
80080a4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
isrflags = READ_REG(huart->Instance->ISR);
80080a8: 687b ldr r3, [r7, #4]
80080aa: 681b ldr r3, [r3, #0]
80080ac: 69db ldr r3, [r3, #28]
80080ae: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
80080b2: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80080b6: f003 0307 and.w r3, r3, #7
80080ba: 2b00 cmp r3, #0
80080bc: d053 beq.n 8008166 <UART_RxISR_16BIT_FIFOEN+0x146>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
80080be: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80080c2: f003 0301 and.w r3, r3, #1
80080c6: 2b00 cmp r3, #0
80080c8: d011 beq.n 80080ee <UART_RxISR_16BIT_FIFOEN+0xce>
80080ca: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
80080ce: f403 7380 and.w r3, r3, #256 @ 0x100
80080d2: 2b00 cmp r3, #0
80080d4: d00b beq.n 80080ee <UART_RxISR_16BIT_FIFOEN+0xce>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
80080d6: 687b ldr r3, [r7, #4]
80080d8: 681b ldr r3, [r3, #0]
80080da: 2201 movs r2, #1
80080dc: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
80080de: 687b ldr r3, [r7, #4]
80080e0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80080e4: f043 0201 orr.w r2, r3, #1
80080e8: 687b ldr r3, [r7, #4]
80080ea: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80080ee: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80080f2: f003 0302 and.w r3, r3, #2
80080f6: 2b00 cmp r3, #0
80080f8: d011 beq.n 800811e <UART_RxISR_16BIT_FIFOEN+0xfe>
80080fa: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
80080fe: f003 0301 and.w r3, r3, #1
8008102: 2b00 cmp r3, #0
8008104: d00b beq.n 800811e <UART_RxISR_16BIT_FIFOEN+0xfe>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8008106: 687b ldr r3, [r7, #4]
8008108: 681b ldr r3, [r3, #0]
800810a: 2202 movs r2, #2
800810c: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
800810e: 687b ldr r3, [r7, #4]
8008110: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8008114: f043 0204 orr.w r2, r3, #4
8008118: 687b ldr r3, [r7, #4]
800811a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
800811e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8008122: f003 0304 and.w r3, r3, #4
8008126: 2b00 cmp r3, #0
8008128: d011 beq.n 800814e <UART_RxISR_16BIT_FIFOEN+0x12e>
800812a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800812e: f003 0301 and.w r3, r3, #1
8008132: 2b00 cmp r3, #0
8008134: d00b beq.n 800814e <UART_RxISR_16BIT_FIFOEN+0x12e>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8008136: 687b ldr r3, [r7, #4]
8008138: 681b ldr r3, [r3, #0]
800813a: 2204 movs r2, #4
800813c: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
800813e: 687b ldr r3, [r7, #4]
8008140: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8008144: f043 0202 orr.w r2, r3, #2
8008148: 687b ldr r3, [r7, #4]
800814a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800814e: 687b ldr r3, [r7, #4]
8008150: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8008154: 2b00 cmp r3, #0
8008156: d006 beq.n 8008166 <UART_RxISR_16BIT_FIFOEN+0x146>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8008158: 6878 ldr r0, [r7, #4]
800815a: f7fe fd95 bl 8006c88 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800815e: 687b ldr r3, [r7, #4]
8008160: 2200 movs r2, #0
8008162: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
if (huart->RxXferCount == 0U)
8008166: 687b ldr r3, [r7, #4]
8008168: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800816c: b29b uxth r3, r3
800816e: 2b00 cmp r3, #0
8008170: f040 80a5 bne.w 80082be <UART_RxISR_16BIT_FIFOEN+0x29e>
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8008174: 687b ldr r3, [r7, #4]
8008176: 681b ldr r3, [r3, #0]
8008178: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800817a: 6f7b ldr r3, [r7, #116] @ 0x74
800817c: e853 3f00 ldrex r3, [r3]
8008180: 673b str r3, [r7, #112] @ 0x70
return(result);
8008182: 6f3b ldr r3, [r7, #112] @ 0x70
8008184: f423 7380 bic.w r3, r3, #256 @ 0x100
8008188: f8c7 309c str.w r3, [r7, #156] @ 0x9c
800818c: 687b ldr r3, [r7, #4]
800818e: 681b ldr r3, [r3, #0]
8008190: 461a mov r2, r3
8008192: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8008196: f8c7 3080 str.w r3, [r7, #128] @ 0x80
800819a: 67fa str r2, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800819c: 6ff9 ldr r1, [r7, #124] @ 0x7c
800819e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
80081a2: e841 2300 strex r3, r2, [r1]
80081a6: 67bb str r3, [r7, #120] @ 0x78
return(result);
80081a8: 6fbb ldr r3, [r7, #120] @ 0x78
80081aa: 2b00 cmp r3, #0
80081ac: d1e2 bne.n 8008174 <UART_RxISR_16BIT_FIFOEN+0x154>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80081ae: 687b ldr r3, [r7, #4]
80081b0: 681b ldr r3, [r3, #0]
80081b2: 3308 adds r3, #8
80081b4: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80081b6: 6e3b ldr r3, [r7, #96] @ 0x60
80081b8: e853 3f00 ldrex r3, [r3]
80081bc: 65fb str r3, [r7, #92] @ 0x5c
return(result);
80081be: 6dfb ldr r3, [r7, #92] @ 0x5c
80081c0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80081c4: f023 0301 bic.w r3, r3, #1
80081c8: f8c7 3098 str.w r3, [r7, #152] @ 0x98
80081cc: 687b ldr r3, [r7, #4]
80081ce: 681b ldr r3, [r3, #0]
80081d0: 3308 adds r3, #8
80081d2: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98
80081d6: 66fa str r2, [r7, #108] @ 0x6c
80081d8: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80081da: 6eb9 ldr r1, [r7, #104] @ 0x68
80081dc: 6efa ldr r2, [r7, #108] @ 0x6c
80081de: e841 2300 strex r3, r2, [r1]
80081e2: 667b str r3, [r7, #100] @ 0x64
return(result);
80081e4: 6e7b ldr r3, [r7, #100] @ 0x64
80081e6: 2b00 cmp r3, #0
80081e8: d1e1 bne.n 80081ae <UART_RxISR_16BIT_FIFOEN+0x18e>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80081ea: 687b ldr r3, [r7, #4]
80081ec: 2220 movs r2, #32
80081ee: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
80081f2: 687b ldr r3, [r7, #4]
80081f4: 2200 movs r2, #0
80081f6: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
80081f8: 687b ldr r3, [r7, #4]
80081fa: 2200 movs r2, #0
80081fc: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
80081fe: 687b ldr r3, [r7, #4]
8008200: 681b ldr r3, [r3, #0]
8008202: 4a60 ldr r2, [pc, #384] @ (8008384 <UART_RxISR_16BIT_FIFOEN+0x364>)
8008204: 4293 cmp r3, r2
8008206: d021 beq.n 800824c <UART_RxISR_16BIT_FIFOEN+0x22c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8008208: 687b ldr r3, [r7, #4]
800820a: 681b ldr r3, [r3, #0]
800820c: 685b ldr r3, [r3, #4]
800820e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8008212: 2b00 cmp r3, #0
8008214: d01a beq.n 800824c <UART_RxISR_16BIT_FIFOEN+0x22c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8008216: 687b ldr r3, [r7, #4]
8008218: 681b ldr r3, [r3, #0]
800821a: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800821c: 6cfb ldr r3, [r7, #76] @ 0x4c
800821e: e853 3f00 ldrex r3, [r3]
8008222: 64bb str r3, [r7, #72] @ 0x48
return(result);
8008224: 6cbb ldr r3, [r7, #72] @ 0x48
8008226: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
800822a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
800822e: 687b ldr r3, [r7, #4]
8008230: 681b ldr r3, [r3, #0]
8008232: 461a mov r2, r3
8008234: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
8008238: 65bb str r3, [r7, #88] @ 0x58
800823a: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800823c: 6d79 ldr r1, [r7, #84] @ 0x54
800823e: 6dba ldr r2, [r7, #88] @ 0x58
8008240: e841 2300 strex r3, r2, [r1]
8008244: 653b str r3, [r7, #80] @ 0x50
return(result);
8008246: 6d3b ldr r3, [r7, #80] @ 0x50
8008248: 2b00 cmp r3, #0
800824a: d1e4 bne.n 8008216 <UART_RxISR_16BIT_FIFOEN+0x1f6>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800824c: 687b ldr r3, [r7, #4]
800824e: 6edb ldr r3, [r3, #108] @ 0x6c
8008250: 2b01 cmp r3, #1
8008252: d130 bne.n 80082b6 <UART_RxISR_16BIT_FIFOEN+0x296>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8008254: 687b ldr r3, [r7, #4]
8008256: 2200 movs r2, #0
8008258: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800825a: 687b ldr r3, [r7, #4]
800825c: 681b ldr r3, [r3, #0]
800825e: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8008260: 6bbb ldr r3, [r7, #56] @ 0x38
8008262: e853 3f00 ldrex r3, [r3]
8008266: 637b str r3, [r7, #52] @ 0x34
return(result);
8008268: 6b7b ldr r3, [r7, #52] @ 0x34
800826a: f023 0310 bic.w r3, r3, #16
800826e: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8008272: 687b ldr r3, [r7, #4]
8008274: 681b ldr r3, [r3, #0]
8008276: 461a mov r2, r3
8008278: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
800827c: 647b str r3, [r7, #68] @ 0x44
800827e: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8008280: 6c39 ldr r1, [r7, #64] @ 0x40
8008282: 6c7a ldr r2, [r7, #68] @ 0x44
8008284: e841 2300 strex r3, r2, [r1]
8008288: 63fb str r3, [r7, #60] @ 0x3c
return(result);
800828a: 6bfb ldr r3, [r7, #60] @ 0x3c
800828c: 2b00 cmp r3, #0
800828e: d1e4 bne.n 800825a <UART_RxISR_16BIT_FIFOEN+0x23a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8008290: 687b ldr r3, [r7, #4]
8008292: 681b ldr r3, [r3, #0]
8008294: 69db ldr r3, [r3, #28]
8008296: f003 0310 and.w r3, r3, #16
800829a: 2b10 cmp r3, #16
800829c: d103 bne.n 80082a6 <UART_RxISR_16BIT_FIFOEN+0x286>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800829e: 687b ldr r3, [r7, #4]
80082a0: 681b ldr r3, [r3, #0]
80082a2: 2210 movs r2, #16
80082a4: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80082a6: 687b ldr r3, [r7, #4]
80082a8: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
80082ac: 4619 mov r1, r3
80082ae: 6878 ldr r0, [r7, #4]
80082b0: f7fe fcf4 bl 8006c9c <HAL_UARTEx_RxEventCallback>
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
break;
80082b4: e00e b.n 80082d4 <UART_RxISR_16BIT_FIFOEN+0x2b4>
HAL_UART_RxCpltCallback(huart);
80082b6: 6878 ldr r0, [r7, #4]
80082b8: f7f9 f9f4 bl 80016a4 <HAL_UART_RxCpltCallback>
break;
80082bc: e00a b.n 80082d4 <UART_RxISR_16BIT_FIFOEN+0x2b4>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
80082be: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6
80082c2: 2b00 cmp r3, #0
80082c4: d006 beq.n 80082d4 <UART_RxISR_16BIT_FIFOEN+0x2b4>
80082c6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80082ca: f003 0320 and.w r3, r3, #32
80082ce: 2b00 cmp r3, #0
80082d0: f47f aeca bne.w 8008068 <UART_RxISR_16BIT_FIFOEN+0x48>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
80082d4: 687b ldr r3, [r7, #4]
80082d6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
80082da: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
80082de: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
80082e2: 2b00 cmp r3, #0
80082e4: d049 beq.n 800837a <UART_RxISR_16BIT_FIFOEN+0x35a>
80082e6: 687b ldr r3, [r7, #4]
80082e8: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
80082ec: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e
80082f0: 429a cmp r2, r3
80082f2: d242 bcs.n 800837a <UART_RxISR_16BIT_FIFOEN+0x35a>
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
80082f4: 687b ldr r3, [r7, #4]
80082f6: 681b ldr r3, [r3, #0]
80082f8: 3308 adds r3, #8
80082fa: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80082fc: 6a7b ldr r3, [r7, #36] @ 0x24
80082fe: e853 3f00 ldrex r3, [r3]
8008302: 623b str r3, [r7, #32]
return(result);
8008304: 6a3b ldr r3, [r7, #32]
8008306: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800830a: f8c7 3088 str.w r3, [r7, #136] @ 0x88
800830e: 687b ldr r3, [r7, #4]
8008310: 681b ldr r3, [r3, #0]
8008312: 3308 adds r3, #8
8008314: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88
8008318: 633a str r2, [r7, #48] @ 0x30
800831a: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800831c: 6af9 ldr r1, [r7, #44] @ 0x2c
800831e: 6b3a ldr r2, [r7, #48] @ 0x30
8008320: e841 2300 strex r3, r2, [r1]
8008324: 62bb str r3, [r7, #40] @ 0x28
return(result);
8008326: 6abb ldr r3, [r7, #40] @ 0x28
8008328: 2b00 cmp r3, #0
800832a: d1e3 bne.n 80082f4 <UART_RxISR_16BIT_FIFOEN+0x2d4>
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_16BIT;
800832c: 687b ldr r3, [r7, #4]
800832e: 4a16 ldr r2, [pc, #88] @ (8008388 <UART_RxISR_16BIT_FIFOEN+0x368>)
8008330: 675a str r2, [r3, #116] @ 0x74
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8008332: 687b ldr r3, [r7, #4]
8008334: 681b ldr r3, [r3, #0]
8008336: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8008338: 693b ldr r3, [r7, #16]
800833a: e853 3f00 ldrex r3, [r3]
800833e: 60fb str r3, [r7, #12]
return(result);
8008340: 68fb ldr r3, [r7, #12]
8008342: f043 0320 orr.w r3, r3, #32
8008346: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800834a: 687b ldr r3, [r7, #4]
800834c: 681b ldr r3, [r3, #0]
800834e: 461a mov r2, r3
8008350: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8008354: 61fb str r3, [r7, #28]
8008356: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8008358: 69b9 ldr r1, [r7, #24]
800835a: 69fa ldr r2, [r7, #28]
800835c: e841 2300 strex r3, r2, [r1]
8008360: 617b str r3, [r7, #20]
return(result);
8008362: 697b ldr r3, [r7, #20]
8008364: 2b00 cmp r3, #0
8008366: d1e4 bne.n 8008332 <UART_RxISR_16BIT_FIFOEN+0x312>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8008368: e007 b.n 800837a <UART_RxISR_16BIT_FIFOEN+0x35a>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
800836a: 687b ldr r3, [r7, #4]
800836c: 681b ldr r3, [r3, #0]
800836e: 699a ldr r2, [r3, #24]
8008370: 687b ldr r3, [r7, #4]
8008372: 681b ldr r3, [r3, #0]
8008374: f042 0208 orr.w r2, r2, #8
8008378: 619a str r2, [r3, #24]
}
800837a: bf00 nop
800837c: 37b8 adds r7, #184 @ 0xb8
800837e: 46bd mov sp, r7
8008380: bd80 pop {r7, pc}
8008382: bf00 nop
8008384: 40008000 .word 0x40008000
8008388: 08007b05 .word 0x08007b05
0800838c <HAL_UARTEx_WakeupCallback>:
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
800838c: b480 push {r7}
800838e: b083 sub sp, #12
8008390: af00 add r7, sp, #0
8008392: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8008394: bf00 nop
8008396: 370c adds r7, #12
8008398: 46bd mov sp, r7
800839a: f85d 7b04 ldr.w r7, [sp], #4
800839e: 4770 bx lr
080083a0 <HAL_UARTEx_RxFifoFullCallback>:
* @brief UART RX Fifo full callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
80083a0: b480 push {r7}
80083a2: b083 sub sp, #12
80083a4: af00 add r7, sp, #0
80083a6: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
*/
}
80083a8: bf00 nop
80083aa: 370c adds r7, #12
80083ac: 46bd mov sp, r7
80083ae: f85d 7b04 ldr.w r7, [sp], #4
80083b2: 4770 bx lr
080083b4 <HAL_UARTEx_TxFifoEmptyCallback>:
* @brief UART TX Fifo empty callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
80083b4: b480 push {r7}
80083b6: b083 sub sp, #12
80083b8: af00 add r7, sp, #0
80083ba: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
80083bc: bf00 nop
80083be: 370c adds r7, #12
80083c0: 46bd mov sp, r7
80083c2: f85d 7b04 ldr.w r7, [sp], #4
80083c6: 4770 bx lr
080083c8 <HAL_UARTEx_DisableFifoMode>:
* @brief Disable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
80083c8: b480 push {r7}
80083ca: b085 sub sp, #20
80083cc: af00 add r7, sp, #0
80083ce: 6078 str r0, [r7, #4]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
80083d0: 687b ldr r3, [r7, #4]
80083d2: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
80083d6: 2b01 cmp r3, #1
80083d8: d101 bne.n 80083de <HAL_UARTEx_DisableFifoMode+0x16>
80083da: 2302 movs r3, #2
80083dc: e027 b.n 800842e <HAL_UARTEx_DisableFifoMode+0x66>
80083de: 687b ldr r3, [r7, #4]
80083e0: 2201 movs r2, #1
80083e2: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
80083e6: 687b ldr r3, [r7, #4]
80083e8: 2224 movs r2, #36 @ 0x24
80083ea: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
80083ee: 687b ldr r3, [r7, #4]
80083f0: 681b ldr r3, [r3, #0]
80083f2: 681b ldr r3, [r3, #0]
80083f4: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
80083f6: 687b ldr r3, [r7, #4]
80083f8: 681b ldr r3, [r3, #0]
80083fa: 681a ldr r2, [r3, #0]
80083fc: 687b ldr r3, [r7, #4]
80083fe: 681b ldr r3, [r3, #0]
8008400: f022 0201 bic.w r2, r2, #1
8008404: 601a str r2, [r3, #0]
/* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
8008406: 68fb ldr r3, [r7, #12]
8008408: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
800840c: 60fb str r3, [r7, #12]
huart->FifoMode = UART_FIFOMODE_DISABLE;
800840e: 687b ldr r3, [r7, #4]
8008410: 2200 movs r2, #0
8008412: 665a str r2, [r3, #100] @ 0x64
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8008414: 687b ldr r3, [r7, #4]
8008416: 681b ldr r3, [r3, #0]
8008418: 68fa ldr r2, [r7, #12]
800841a: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
800841c: 687b ldr r3, [r7, #4]
800841e: 2220 movs r2, #32
8008420: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
8008424: 687b ldr r3, [r7, #4]
8008426: 2200 movs r2, #0
8008428: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
800842c: 2300 movs r3, #0
}
800842e: 4618 mov r0, r3
8008430: 3714 adds r7, #20
8008432: 46bd mov sp, r7
8008434: f85d 7b04 ldr.w r7, [sp], #4
8008438: 4770 bx lr
0800843a <HAL_UARTEx_SetTxFifoThreshold>:
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
800843a: b580 push {r7, lr}
800843c: b084 sub sp, #16
800843e: af00 add r7, sp, #0
8008440: 6078 str r0, [r7, #4]
8008442: 6039 str r1, [r7, #0]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8008444: 687b ldr r3, [r7, #4]
8008446: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
800844a: 2b01 cmp r3, #1
800844c: d101 bne.n 8008452 <HAL_UARTEx_SetTxFifoThreshold+0x18>
800844e: 2302 movs r3, #2
8008450: e02d b.n 80084ae <HAL_UARTEx_SetTxFifoThreshold+0x74>
8008452: 687b ldr r3, [r7, #4]
8008454: 2201 movs r2, #1
8008456: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
800845a: 687b ldr r3, [r7, #4]
800845c: 2224 movs r2, #36 @ 0x24
800845e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8008462: 687b ldr r3, [r7, #4]
8008464: 681b ldr r3, [r3, #0]
8008466: 681b ldr r3, [r3, #0]
8008468: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
800846a: 687b ldr r3, [r7, #4]
800846c: 681b ldr r3, [r3, #0]
800846e: 681a ldr r2, [r3, #0]
8008470: 687b ldr r3, [r7, #4]
8008472: 681b ldr r3, [r3, #0]
8008474: f022 0201 bic.w r2, r2, #1
8008478: 601a str r2, [r3, #0]
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
800847a: 687b ldr r3, [r7, #4]
800847c: 681b ldr r3, [r3, #0]
800847e: 689b ldr r3, [r3, #8]
8008480: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000
8008484: 687b ldr r3, [r7, #4]
8008486: 681b ldr r3, [r3, #0]
8008488: 683a ldr r2, [r7, #0]
800848a: 430a orrs r2, r1
800848c: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
800848e: 6878 ldr r0, [r7, #4]
8008490: f000 f850 bl 8008534 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8008494: 687b ldr r3, [r7, #4]
8008496: 681b ldr r3, [r3, #0]
8008498: 68fa ldr r2, [r7, #12]
800849a: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
800849c: 687b ldr r3, [r7, #4]
800849e: 2220 movs r2, #32
80084a0: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
80084a4: 687b ldr r3, [r7, #4]
80084a6: 2200 movs r2, #0
80084a8: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
80084ac: 2300 movs r3, #0
}
80084ae: 4618 mov r0, r3
80084b0: 3710 adds r7, #16
80084b2: 46bd mov sp, r7
80084b4: bd80 pop {r7, pc}
080084b6 <HAL_UARTEx_SetRxFifoThreshold>:
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
80084b6: b580 push {r7, lr}
80084b8: b084 sub sp, #16
80084ba: af00 add r7, sp, #0
80084bc: 6078 str r0, [r7, #4]
80084be: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
80084c0: 687b ldr r3, [r7, #4]
80084c2: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
80084c6: 2b01 cmp r3, #1
80084c8: d101 bne.n 80084ce <HAL_UARTEx_SetRxFifoThreshold+0x18>
80084ca: 2302 movs r3, #2
80084cc: e02d b.n 800852a <HAL_UARTEx_SetRxFifoThreshold+0x74>
80084ce: 687b ldr r3, [r7, #4]
80084d0: 2201 movs r2, #1
80084d2: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
80084d6: 687b ldr r3, [r7, #4]
80084d8: 2224 movs r2, #36 @ 0x24
80084da: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
80084de: 687b ldr r3, [r7, #4]
80084e0: 681b ldr r3, [r3, #0]
80084e2: 681b ldr r3, [r3, #0]
80084e4: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
80084e6: 687b ldr r3, [r7, #4]
80084e8: 681b ldr r3, [r3, #0]
80084ea: 681a ldr r2, [r3, #0]
80084ec: 687b ldr r3, [r7, #4]
80084ee: 681b ldr r3, [r3, #0]
80084f0: f022 0201 bic.w r2, r2, #1
80084f4: 601a str r2, [r3, #0]
/* Update RX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
80084f6: 687b ldr r3, [r7, #4]
80084f8: 681b ldr r3, [r3, #0]
80084fa: 689b ldr r3, [r3, #8]
80084fc: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000
8008500: 687b ldr r3, [r7, #4]
8008502: 681b ldr r3, [r3, #0]
8008504: 683a ldr r2, [r7, #0]
8008506: 430a orrs r2, r1
8008508: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
800850a: 6878 ldr r0, [r7, #4]
800850c: f000 f812 bl 8008534 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8008510: 687b ldr r3, [r7, #4]
8008512: 681b ldr r3, [r3, #0]
8008514: 68fa ldr r2, [r7, #12]
8008516: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8008518: 687b ldr r3, [r7, #4]
800851a: 2220 movs r2, #32
800851c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
8008520: 687b ldr r3, [r7, #4]
8008522: 2200 movs r2, #0
8008524: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8008528: 2300 movs r3, #0
}
800852a: 4618 mov r0, r3
800852c: 3710 adds r7, #16
800852e: 46bd mov sp, r7
8008530: bd80 pop {r7, pc}
...
08008534 <UARTEx_SetNbDataToProcess>:
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
8008534: b480 push {r7}
8008536: b085 sub sp, #20
8008538: af00 add r7, sp, #0
800853a: 6078 str r0, [r7, #4]
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
800853c: 687b ldr r3, [r7, #4]
800853e: 6e5b ldr r3, [r3, #100] @ 0x64
8008540: 2b00 cmp r3, #0
8008542: d108 bne.n 8008556 <UARTEx_SetNbDataToProcess+0x22>
{
huart->NbTxDataToProcess = 1U;
8008544: 687b ldr r3, [r7, #4]
8008546: 2201 movs r2, #1
8008548: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1U;
800854c: 687b ldr r3, [r7, #4]
800854e: 2201 movs r2, #1
8008550: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
8008554: e031 b.n 80085ba <UARTEx_SetNbDataToProcess+0x86>
rx_fifo_depth = RX_FIFO_DEPTH;
8008556: 2308 movs r3, #8
8008558: 73fb strb r3, [r7, #15]
tx_fifo_depth = TX_FIFO_DEPTH;
800855a: 2308 movs r3, #8
800855c: 73bb strb r3, [r7, #14]
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
800855e: 687b ldr r3, [r7, #4]
8008560: 681b ldr r3, [r3, #0]
8008562: 689b ldr r3, [r3, #8]
8008564: 0e5b lsrs r3, r3, #25
8008566: b2db uxtb r3, r3
8008568: f003 0307 and.w r3, r3, #7
800856c: 737b strb r3, [r7, #13]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
800856e: 687b ldr r3, [r7, #4]
8008570: 681b ldr r3, [r3, #0]
8008572: 689b ldr r3, [r3, #8]
8008574: 0f5b lsrs r3, r3, #29
8008576: b2db uxtb r3, r3
8008578: f003 0307 and.w r3, r3, #7
800857c: 733b strb r3, [r7, #12]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
800857e: 7bbb ldrb r3, [r7, #14]
8008580: 7b3a ldrb r2, [r7, #12]
8008582: 4911 ldr r1, [pc, #68] @ (80085c8 <UARTEx_SetNbDataToProcess+0x94>)
8008584: 5c8a ldrb r2, [r1, r2]
8008586: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[tx_fifo_threshold];
800858a: 7b3a ldrb r2, [r7, #12]
800858c: 490f ldr r1, [pc, #60] @ (80085cc <UARTEx_SetNbDataToProcess+0x98>)
800858e: 5c8a ldrb r2, [r1, r2]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8008590: fb93 f3f2 sdiv r3, r3, r2
8008594: b29a uxth r2, r3
8008596: 687b ldr r3, [r7, #4]
8008598: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
800859c: 7bfb ldrb r3, [r7, #15]
800859e: 7b7a ldrb r2, [r7, #13]
80085a0: 4909 ldr r1, [pc, #36] @ (80085c8 <UARTEx_SetNbDataToProcess+0x94>)
80085a2: 5c8a ldrb r2, [r1, r2]
80085a4: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[rx_fifo_threshold];
80085a8: 7b7a ldrb r2, [r7, #13]
80085aa: 4908 ldr r1, [pc, #32] @ (80085cc <UARTEx_SetNbDataToProcess+0x98>)
80085ac: 5c8a ldrb r2, [r1, r2]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
80085ae: fb93 f3f2 sdiv r3, r3, r2
80085b2: b29a uxth r2, r3
80085b4: 687b ldr r3, [r7, #4]
80085b6: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
}
80085ba: bf00 nop
80085bc: 3714 adds r7, #20
80085be: 46bd mov sp, r7
80085c0: f85d 7b04 ldr.w r7, [sp], #4
80085c4: 4770 bx lr
80085c6: bf00 nop
80085c8: 08008670 .word 0x08008670
80085cc: 08008678 .word 0x08008678
080085d0 <memset>:
80085d0: 4402 add r2, r0
80085d2: 4603 mov r3, r0
80085d4: 4293 cmp r3, r2
80085d6: d100 bne.n 80085da <memset+0xa>
80085d8: 4770 bx lr
80085da: f803 1b01 strb.w r1, [r3], #1
80085de: e7f9 b.n 80085d4 <memset+0x4>
080085e0 <__libc_init_array>:
80085e0: b570 push {r4, r5, r6, lr}
80085e2: 4d0d ldr r5, [pc, #52] @ (8008618 <__libc_init_array+0x38>)
80085e4: 4c0d ldr r4, [pc, #52] @ (800861c <__libc_init_array+0x3c>)
80085e6: 1b64 subs r4, r4, r5
80085e8: 10a4 asrs r4, r4, #2
80085ea: 2600 movs r6, #0
80085ec: 42a6 cmp r6, r4
80085ee: d109 bne.n 8008604 <__libc_init_array+0x24>
80085f0: 4d0b ldr r5, [pc, #44] @ (8008620 <__libc_init_array+0x40>)
80085f2: 4c0c ldr r4, [pc, #48] @ (8008624 <__libc_init_array+0x44>)
80085f4: f000 f818 bl 8008628 <_init>
80085f8: 1b64 subs r4, r4, r5
80085fa: 10a4 asrs r4, r4, #2
80085fc: 2600 movs r6, #0
80085fe: 42a6 cmp r6, r4
8008600: d105 bne.n 800860e <__libc_init_array+0x2e>
8008602: bd70 pop {r4, r5, r6, pc}
8008604: f855 3b04 ldr.w r3, [r5], #4
8008608: 4798 blx r3
800860a: 3601 adds r6, #1
800860c: e7ee b.n 80085ec <__libc_init_array+0xc>
800860e: f855 3b04 ldr.w r3, [r5], #4
8008612: 4798 blx r3
8008614: 3601 adds r6, #1
8008616: e7f2 b.n 80085fe <__libc_init_array+0x1e>
8008618: 08008688 .word 0x08008688
800861c: 08008688 .word 0x08008688
8008620: 08008688 .word 0x08008688
8008624: 0800868c .word 0x0800868c
08008628 <_init>:
8008628: b5f8 push {r3, r4, r5, r6, r7, lr}
800862a: bf00 nop
800862c: bcf8 pop {r3, r4, r5, r6, r7}
800862e: bc08 pop {r3}
8008630: 469e mov lr, r3
8008632: 4770 bx lr
08008634 <_fini>:
8008634: b5f8 push {r3, r4, r5, r6, r7, lr}
8008636: bf00 nop
8008638: bcf8 pop {r3, r4, r5, r6, r7}
800863a: bc08 pop {r3}
800863c: 469e mov lr, r3
800863e: 4770 bx lr
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