113 lines
20 KiB
HTML
113 lines
20 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 1299–1328</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert h2 { color: #e65100; margin-top: 0; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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table { border-collapse: collapse; width: 100%; }
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th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 5 of 30 display load sessions (17%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>1302</td><td>20260415_151649</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.014 V</td></tr><tr><td>1306</td><td>20260415_151816</td><td>dat</td><td style='color:red'>0.9 ns</td><td>0.0 ns</td><td>1.016 V</td></tr><tr><td>1309</td><td>20260415_151921</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.3 ns</td><td>1.014 V</td></tr><tr><td>1315</td><td>20260415_152132</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.5 ns</td><td>1.015 V</td></tr><tr><td>1324</td><td>20260415_152447</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.5 ns</td><td>1.016 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>1299</td><td>20260415_151544</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1300</td><td>20260415_151606</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1301</td><td>20260415_151628</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1302</td><td>20260415_151649</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1303</td><td>20260415_151711</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1304</td><td>20260415_151732</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1305</td><td>20260415_151754</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1306</td><td>20260415_151816</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1307</td><td>20260415_151838</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1308</td><td>20260415_151900</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1309</td><td>20260415_151921</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1310</td><td>20260415_151943</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1311</td><td>20260415_152005</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1312</td><td>20260415_152027</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1313</td><td>20260415_152049</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1314</td><td>20260415_152110</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1315</td><td>20260415_152132</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1316</td><td>20260415_152154</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1317</td><td>20260415_152216</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1318</td><td>20260415_152237</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1319</td><td>20260415_152259</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1320</td><td>20260415_152320</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1321</td><td>20260415_152342</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1322</td><td>20260415_152404</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1323</td><td>20260415_152425</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1324</td><td>20260415_152447</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1325</td><td>20260415_152509</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1326</td><td>20260415_152531</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1327</td><td>20260415_152553</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1328</td><td>20260415_152614</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-15 15:31:13 |
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<strong>Scope:</strong> Captures 1299–1328 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis Report</p>
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<p>## Batch: Captures 1299–1328 (30 pipeline load/unload cycles)</p>
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<ul><li></li></ul>
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<p>## 1. Consistent Spec Concerns</p>
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<p>### A. Register Timing — Universal, Every Capture<br>All 30 captures show identical register values (`Round Best` mode) with <strong>5 D-PHY v1.1 violations</strong>:</p>
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<p>| Parameter | Measured | Spec Min | Deficit | Severity |<br>|-----------|----------|----------|---------|----------|<br>| THS_EXIT | 92.6 ns | 100.0 ns | −7.4 ns | <strong>HIGH</strong> — affects LP→HS exit handshake |<br>| TCLK_PREPARE | 37.0 ns | 38.0 ns | −1.0 ns | <strong>CRITICAL</strong> — clock SoT preamble too short |<br>| TCLK_TRAIL | 55.6 ns | 60.0 ns | −4.4 ns | MODERATE — affects HS→LP teardown |<br>| TCLK_PREPARE+TCLK_ZERO | 296.3 ns | 300.0 ns | −3.7 ns | <strong>CRITICAL</strong> — clock lane init sequence truncated |<br>| THS_PREPARE+THS_ZERO | 166.7 ns | 168.2 ns | −1.5 ns | <strong>CRITICAL</strong> — data lane SoT sequence truncated |</p>
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<p><strong>Key insight:</strong> The TCLK_PREPARE and THS_PREPARE+THS_ZERO violations directly shorten the SoT preamble the SN65DSI83 must detect. Combined with THS_EXIT being short, the receiver has a <strong>compressed detection window</strong> on every single startup. The system works most of the time because the SN65DSI83 has some internal tolerance, but the margins are razor-thin.</p>
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<p>### B. LP-Exit Duration — Universal Violation<br><strong>Every capture with LP data</strong> (28 of 30) shows LP exit → HS of <strong>0–4 ns</strong> against a spec minimum of <strong>50 ns</strong>. This is not a measurement artifact — it confirms the PHY is driving LP-01/LP-00 states for effectively zero time at the scope's resolution, consistent with the truncated TCLK_PREPARE and THS_PREPARE+THS_ZERO register values.</p>
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<p>### C. LP-11 Voltage — Marginal but Passing<br>LP-11 consistently measures <strong>1.014–1.016 V</strong> (spec 1.0–1.45 V). This is only <strong>14–16 mV above the lower spec limit</strong> on a 1.8 V VDDIO rail. With VDDIO measured at ~1.766 V, the LP-11 level is <strong>56.4% of VDDIO</strong> rather than the expected ~VDDIO. This suggests the LP drivers have significant series impedance or the probe loading/termination at the SN65DSI83 input is pulling the LP level down. While technically in-spec, this reduces the SN65DSI83's LP-11 detect margin.</p>
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<p>### D. HS Amplitude — Clock Lane Asymmetry<br>Clock differential: consistently <strong>+195 / −137 mV</strong> (common mode +29 mV). The positive swing is 42% larger than negative, indicating a <strong>systematic offset in the clock lane driver or termination</strong>. The mean amplitude (~166 mV) is within spec but only 26 mV above the 140 mV floor. Multiple captures show <strong>20–124 settled samples below 140 mV</strong>, confirming the clock eye is clipping the spec floor on some transitions.</p>
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<p>Data lane amplitude (~187–195 mV) is better centered but also shows sub-140 mV samples in many captures.</p>
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<ul><li></li></ul>
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<p>## 2. Trends Across Captures</p>
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<p>### A. No Drift — System Is Stationary<br>| Parameter | Range Across 30 Captures | Trend |<br>|-----------|--------------------------|-------|<br>| CLK Vdiff amplitude | 166.1–166.9 mV | Flat (< 1 mV variation) |<br>| DAT Vdiff amplitude | 186.5–223.9 mV | Capture-dependent (see §3) |<br>| CLK jitter p-p | 145.8–169.9 ps | No trend |<br>| CLK jitter RMS | 51.8–56.7 ps | No trend |<br>| LP-11 voltage | 1.014–1.016 V | Flat |<br>| 1.8 V mean | 1.764–1.771 V | Flat |<br>| 1.8 V droop | 7.2–18.3 mV | No trend |<br>| Register values | Identical all captures | No change |</p>
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<p><strong>Conclusion:</strong> There is no progressive degradation. The problem is purely a <strong>startup race condition</strong>, consistent with the reported bistable behaviour.</p>
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<p>### B. LP-Low Plateau — Bimodal Distribution<br>The LP-low plateau measurement shows a striking bimodal pattern:</p>
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<p>| LP-low Plateau | Count | Sessions | Flicker? |<br>|----------------|-------|----------|----------|<br>| <strong>342–348 ns</strong> | 16 | Good + some marginal | Mostly no |<br>| <strong>108 ns</strong> | 6 | Mixed | No (in these captures) |<br>| <strong>0–1 ns</strong> | 5 | <strong>1302, 1306, 1309, 1315, 1324</strong> | <strong>YES — all flicker</strong> |<br>| Error/missing | 2 | 1303, 1322 | Unknown |</p>
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<p>This is the <strong>smoking gun</strong>: when the LP-low plateau collapses to 0–1 ns, the SN65DSI83 cannot detect the SoT entry sequence and the bridge fails to lock. The 342 ns plateau corresponds to approximately <strong>18.5 byte-clock periods</strong> — consistent with the programmed THS_PREPARE + THS_ZERO = 9 bc on the data lane (the scope measures both the low-going prepare and zero states as one contiguous low region, and the clock lane's TCLK_PREPARE + TCLK_ZERO = 16 bc adds to this window). When the PHY's internal state machine occasionally <strong>skips or truncates the LP-01→LP-00 sequence</strong>, the plateau vanishes entirely.</p>
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<ul><li></li></ul>
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<p>## 3. Anomalies</p>
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<p>### A. Flicker Captures — LP-Low Plateau Absent<br><strong>Captures 1302, 1306, 1309, 1315, 1324</strong> (all confirmed flicker):<br>- LP-low plateau: <strong>0 ns</strong> (1302, 1309, 1315, 1324) or <strong>1 ns</strong> (1306)<br>- HS amplitude (single-ended): <strong>24–34 mV</strong> — dramatically lower than the ~104–120 mV seen in good sessions<br>- This low HS amplitude in flicker captures indicates the data lane <strong>never properly entered HS mode</strong> — the SoT handshake failed, and what the scope captures as "HS" is likely residual coupling or a partially driven state</p>
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<p>### B. Data Lane "Only Negative Swings" Warning<br>Many captures (both good and bad) report `Only negative swings in capture window` on DAT0 sig/proto channels. This is a <strong>probe/trigger alignment issue</strong>: the oscilloscope capture window happened to land on a data pattern that is predominantly one polarity. It does not indicate a fault, but it means the reported amplitude is a lower bound. This is benign.</p>
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<p>### C. Data Lane Amplitude Bimodality in Proto Captures<br>Several captures show DAT0 proto amplitudes of <strong>222–224 mV</strong> with an asymmetric swing (+200/−247 mV, CM = −23 mV):<br>- Captures 1301, 1304, 1322 (all non-flicker)<br>- These coincide with slightly lower clock frequencies (~213.4 MHz vs. nominal 216 MHz)<br>- This may represent a different data pattern in the capture window or a transient PLL settling artefact at startup. Not directly correlated with flicker.</p>
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<p>### D. Processing Errors<br>- <strong>Capture 1303</strong> and <strong>1322</strong>: `[lp_dat] ERROR: index 200000 is out of bounds` — the LP waveform processing script hit the end of the capture buffer, likely because the LP→HS transition occurred at the very edge of the acquisition window. These two captures could not be assessed for LP timing. Recommendation: increase capture record length or adjust trigger position.</p>
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<p>### E. DAT0 sig = 0.0 mV<br>Captures <strong>1304, 1305, 1317</strong>: `No HS signal detected` on DAT0 sig channel. The high-res capture window missed the data lane HS content entirely (either blanking interval or trigger misalignment). Not a hardware fault — the proto and LP captures from the same sessions are normal.</p>
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<ul><li></li></ul>
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<p>## 4. Supply Correlation Analysis</p>
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<p>### A. 1.8 V Supply vs. LP Anomalies</p>
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<p>| Capture | Flicker? | LP-low (ns) | V_mean (V) | V_min (V) | Droop (mV) | Ripple RMS (mV) |<br>|---------|----------|-------------|------------|-----------|------------|-----------------|<br>| 1302 | <strong>YES</strong> | 0 | 1.7656 | 1.7560 | 9.6 | 5.61 |<br>| 1306 | <strong>YES</strong> | 1 | 1.7665 | 1.7560 | 10.6 | 5.80 |<br>| 1309 | <strong>YES</strong> | 0 | 1.7655 | 1.7560 | 9.5 | 5.41 |<br>| 1315 | <strong>YES</strong> | 0 | 1.7667 | 1.7560 | 10.7 | 5.86 |<br>| 1324 | <strong>YES</strong> | 0 | 1.7656 | 1.7560 | 9.6 | 5.53 |<br>| <strong>Good avg</strong> | No | 108–348 | 1.766 | 1.756 | 10.5 | 5.70 |</p>
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<p><strong>Conclusion: No supply correlation.</strong> The flicker captures show identical supply characteristics to good captures:<br>- Mean voltage: indistinguishable (~1.766 V in both)<br>- Minimum voltage: identical (1.756 V)<br>- Droop: 9.5–10.7 mV for flicker vs. 7.2–18.3 mV for all captures — flicker sessions are actually in the *lower* droop range<br>- Ripple RMS: 5.41–5.86 mV — squarely in the middle of the full population</p>
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<p><strong>The 1.8 V supply is not the root cause.</strong> The supply is well within spec (1.71–1.89 V) at all times and shows no correlation with SoT failures.</p>
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<ul><li></li></ul>
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<p>## 5. WARNING/ERROR Explanation</p>
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<p>| Warning/Error | Likely Cause | Action |<br>|---------------|-------------|--------|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>PHY timing registers too short</strong> — THS_EXIT=5bc, THS_PREPARE+THS_ZERO=9bc produce SoT states near the minimum; PHY internal jitter occasionally eliminates them entirely | <strong>Switch to Round Up register values</strong> |<br>| `FLICKER SUSPECT: LP-low plateau absent or < 50 ns` | SoT LP-01→LP-00 states skipped or truncated below scope resolution; SN65DSI83 cannot detect Start-of-Transmission | <strong>Root cause — register fix required</strong> |<br>| `Only negative swings in capture window` | Scope triggered on a data symbol that happened to be low for the entire capture window; amplitude underestimated | Benign — no action needed. Increase capture length if accurate amplitude stats are required |<br>| `No HS signal detected — line may be in LP state or idle` | High-res capture window landed in blanking interval or LP state | Adjust trigger delay for sig captures; not a hardware fault |<br>| `CLK lane is in continuous HS mode — LP states not expected on CLK` | Normal — Samsung DSIM uses continuous clock mode; CLK lane doesn't return to LP-11 between frames | Expected behaviour, no action |<br>| `101/113/... settled samples below 140 mV` | Clock amplitude of 166 mV has only 26 mV margin above 140 mV floor; transitions and ISI dip below threshold | Monitor — not immediately actionable but indicates the PHY is near its low-amplitude limit |<br>| `index 200000 is out of bounds` | Processing script ran past end of LP capture buffer | Increase scope record length or adjust trigger position to ensure SoT transition is fully captured |</p>
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<ul><li></li></ul>
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<p>## 6. Actionable Recommendations</p>
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<p>### IMMEDIATE — Register Fix (PRIMARY FIX)</p>
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<p><strong>Switch from `Round Best` to `Round Up` PHY timing values:</strong></p>
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<p>```<br># From device tree or driver override:<br>DSIM_PHYTIMING (0xb4): 0x00000306 (was 0x00000305)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04 (was 0x020e0a03)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706 (was 0x00030605)<br>```</p>
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<p>Field-by-field changes:</p>
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<p>| Field | Old (bc) | New (bc) | Old (ns) | New (ns) | Spec Min | Effect |<br>|-------|----------|----------|----------|----------|----------|--------|<br>| THS_EXIT | 5 | <strong>6</strong> | 92.6 | 111.1 | 100.0 | Now compliant |<br>| TCLK_PREPARE | 2 | <strong>3</strong> | 37.0 | 55.6 | 38.0 | Now compliant, +50% margin |<br>| TCLK_ZERO | 14 | <strong>15</strong> | 259.3 | 277.8 | (combined) | — |<br>| TCLK_PREPARE+ZERO | 16 | <strong>18</strong> | 296.3 | 333.3 | 300.0 | Now compliant, +11% margin |<br>| TCLK_TRAIL | 3 | <strong>4</strong> | 55.6 | 74.1 | 60.0 | Now compliant |<br>| THS_ZERO | 6 | <strong>7</strong> | 111.1 | 129.6 | (combined) | — |<br>| THS_PREPARE+ZERO | 9 | <strong>10</strong> | 166.7 | 185.2 | 168.2 | Now compliant, +10% margin |<br>| THS_TRAIL | 5 | <strong>6</strong> | 92.6 | 111.1 | 69.3 | Extra margin |</p>
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<p><strong>Implementation path — samsung-dsim driver:</strong></p>
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<p>The samsung-dsim (sec-dsim) driver computes these values in `samsung_dsim_set_phy_timing()`. The rounding mode is typically controlled by the `samsung,phy-timing` property or an internal calculation. Options:</p>
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<ol><li><strong>Preferred:</strong> Patch the driver's timing calculation to use ceiling (round-up) instead of round-to-nearest for all parameters. This is a one-line change in the rounding function.</li><li><strong>Alternative:</strong> Override the timing registers directly via device tree `samsung,phy-timing = <0x00000306 0x030f0a04 0x00030706>;` if the driver supports it.</li><li><strong>Fallback:</strong> Write the registers directly from userspace after boot via `memtool` / `devmem2` as a validation step, then commit the change to the driver.</li></ol>
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<p>### SECONDARY — LP-11 Voltage Investigation</p>
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<p>The LP-11 level of 1.014–1.016 V (56% of VDDIO) is unusually low. While in-spec, it suggests:<br>- Check for <strong>excessive series resistance</strong> in the LP driver path (SOM trace, connector, cable to SN65DSI83)<br>- Verify the SN65DSI83 input termination matches the design — its LP input impedance may be loading the line excessively<br>- Confirm MIPI_DPHY_CON register (if accessible) is set for correct LP driver impedance</p>
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<p>### TERTIARY — Clock Lane Amplitude Asymmetry</p>
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<p>The +195/−137 mV asymmetry (CM offset +29 mV) on the clock lane suggests:<br>- Slight termination mismatch between CLK_P and CLK_N at the receiver<br>- Or a systematic PHY driver offset<br>- While not causing flicker, it reduces the clock eye margin. <strong>Check 100Ω differential termination</strong> at the SN65DSI83 CLK input and verify PCB trace matching.</p>
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<p>### MONITORING</p>
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<p>After applying the</p>
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<p class="tokens">Tokens: 45440 in / 4096 out</p>
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</body>
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</html>
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