116 lines
19 KiB
HTML
116 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0303–0332</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 1 of 30 display load sessions (3%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0312</td><td>20260413_105141</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.1 ns</td><td>1.016 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0303</td><td>20260413_104826</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0304</td><td>20260413_104847</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0305</td><td>20260413_104909</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260413_104931</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260413_104952</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260413_105014</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260413_105036</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260413_105058</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260413_105119</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260413_105141</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260413_105203</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260413_105225</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260413_105247</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260413_105309</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260413_105331</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260413_105352</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260413_105414</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260413_105435</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260413_105457</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260413_105519</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260413_105541</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260413_105602</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260413_105624</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260413_105646</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260413_105708</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260413_105729</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260413_105751</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260413_105813</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260413_105834</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260413_105856</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-13 11:03:38 |
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<strong>Scope:</strong> Captures 0303–0332 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0303–0332 (30 sessions)</p>
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<ul><li></li></ul>
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<p>## 1. Consistent Spec Concerns</p>
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<p>### A. PHY Timing Registers — 5 D-PHY v1.1 Violations (ALL 30 captures, 100%)</p>
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<p>Every single capture shows identical register values (`Round Best` mode), confirming the driver is not applying the `Round Up` corrections:</p>
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<p>| Parameter | Programmed | Actual | Spec Min | Deficit |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc → 92.6 ns | — | 100.0 ns | <strong>−7.4 ns</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc → 37.0 ns | — | 38.0 ns | <strong>−1.0 ns</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc → 55.6 ns | — | 60.0 ns | <strong>−4.4 ns</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc → 296.3 ns | — | 300.0 ns | <strong>−3.7 ns</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc → 166.7 ns | — | 168.2 ns | <strong>−1.5 ns</strong> |</p>
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<p><strong>These are not marginal — they are hard violations.</strong> The SN65DSI83 must detect the SoT sequence within D-PHY spec windows. When the PHY's TCLK_PREPARE is 1 ns short of the 38 ns floor and THS_PREPARE+THS_ZERO is 1.5 ns below the combined minimum, the bridge's internal state machine has almost no margin to recognize the HS entry.</p>
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<p>### B. LP Exit Duration — Systematically Violated</p>
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<p>| Metric | Good captures (5/30) | Typical captures (22/30) | Flicker capture 0312 |<br>|---|---|---|---|<br>| LP exit → HS | <strong>348 ns</strong> ✓ | <strong>1–4 ns</strong> ✗ | <strong>0 ns</strong> ✗ |<br>| LP-low plateau | 342–343 ns | 108–343 ns | <strong>0 ns</strong> ✗ |</p>
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<ul><li><strong>26 of 30 captures</strong> (87%) show LP exit durations of 1–4 ns — far below the 50 ns D-PHY minimum. This means the LP-01 → LP-00 state sequence required by the SoT protocol is either absent or completed in under one oscilloscope sample.</li><li>Only 5 captures (0305, 0316, 0326, 0328, 0329, 0332) show compliant 348 ns LP exit durations. <strong>These are the captures where the measurement resolved the full LP-01/LP-00 sequence.</strong></li><li>The fact that most "good" sessions also show ~2–4 ns LP exit suggests the measurement resolution may not always capture LP-01/LP-00 properly, <strong>but</strong> the flicker event (0312) shows LP-low = 0 ns, meaning the SoT sequence was genuinely absent or catastrophically compressed.</li></ul>
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<p>### C. HS Differential Amplitude — Clock Lane Marginal</p>
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<ul><li><strong>Clock lane Vdiff</strong>: 164.2–166.9 mV — nominally above the 140 mV floor but with <strong>28–230 settled samples below 140 mV</strong> in every proto capture. The negative half-swing is consistently ~30 mV weaker than the positive half (typ. +194 mV / −137 mV), producing a <strong>+28 mV common-mode offset</strong>.</li><li><strong>Data lane Vdiff</strong>: 178–223 mV median — healthy, but <strong>up to 12,596 settled samples below 140 mV</strong> (capture 0326). This is ISI/transition-related undershoot.</li></ul>
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<p>### D. LP-11 Voltage — Consistent but Low</p>
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<ul><li>LP-11 = <strong>1.014–1.016 V</strong> across all captures. The D-PHY spec requires ≥ 1.0 V (for 1.2 V VDDIO) but at 1.8 V VDDIO the expected LP-high is ~1.2 V. The <strong>1.015 V measured value</strong> is suspiciously low — only 15 mV above the absolute floor. This suggests either the LP driver pull-up impedance is too high, the 1.8 V rail is being divided down, or there is excessive loading on the LP lines (SN65DSI83 input + routing parasitics).</li></ul>
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<ul><li></li></ul>
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<p>## 2. Trends Over 30 Captures</p>
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<p>### No Drift Detected — The System is Stationary</p>
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<p>| Parameter | Min | Max | σ | Trend |<br>|---|---|---|---|---|<br>| CLK Vdiff | 165.0 mV | 166.9 mV | < 0.5 mV | Flat |<br>| CLK jitter p-p | 147.3 ps | 171.8 ps | ~6 ps | Flat (noise) |<br>| CLK rise time | 164.3 ps | 166.0 ps | < 1 ps | Flat |<br>| CLK frequency | 213.4–219.2 MHz | — | ~1.5 MHz | Measurement window variance only |<br>| 1.8 V mean | 1.764–1.770 V | — | ~2 mV | Flat |<br>| 1.8 V droop | 8.1–16.1 mV | — | ~2 mV | Flat |<br>| LP-11 voltage | 1.014–1.016 V | — | < 1 mV | Flat |<br>| LP-11 duration | 1.73 µs | 1.73 µs | 0 | Constant |</p>
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<p><strong>Conclusion: This is not a degradation or drift problem.</strong> The failure mode is purely stochastic at the SoT moment — consistent with a timing-margin race condition.</p>
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<ul><li></li></ul>
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<p>## 3. Anomalies</p>
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<p>### 🔴 CRITICAL — Capture 0312: Confirmed Flicker Event<br>- <strong>LP-low plateau = 0 ns</strong> — the SoT LP-01 → LP-00 sequence was entirely absent<br>- <strong>LP exit → HS = 0 ns</strong> — the data lane jumped directly from LP-11 to HS with no intermediate states<br>- <strong>HS single-ended amplitude = 32 mV</strong> (vs ~108 mV typical) — the bridge never locked to HS, so HS data was essentially absent/garbage on that first burst<br>- <strong>LP-11 voltage = 1.016 V</strong> — marginally *higher* than average (not lower), ruling out supply droop as the trigger<br>- <strong>1.8 V supply: mean 1.769 V, droop 9.1 mV</strong> — actually *better* than average, ruling out supply sag</p>
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<p><strong>Root cause of this specific event:</strong> The PHY transitioned from LP-11 directly to HS without executing the LP-01 → LP-00 SoT sequence. The SN65DSI83 never saw SoT, never entered HS receive mode, and remained stuck. This is a <strong>PHY state machine race condition</strong> exacerbated by the 5 timing violations.</p>
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<p>### 🟡 Capture 0307: DAT0 Proto Shows 0 mV<br>- Data lane proto amplitude = 0.0 mV — "No HS signal detected"<br>- This is likely a <strong>trigger/capture timing issue</strong> where the proto window landed during an LP or blanking period, not a genuine signal absence (sig capture shows 193.7 mV, LP shows valid HS burst). <strong>Not a flicker event but a measurement artifact.</strong></p>
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<p>### 🟡 Recurring: "Only negative swings in capture window"<br>- 27 of 30 dat sig captures show only negative swings. This is a <strong>probe/trigger alignment artifact</strong> — the high-res window consistently lands on the same phase of the data pattern. The amplitude is still correctly measured from the negative excursion. <strong>Not a signal integrity concern.</strong></p>
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<p>### 🟡 LP-low Plateau Bimodal Distribution<br>- <strong>~342–343 ns</strong> (majority): Full LP-00 plateau resolved<br>- <strong>~108 ns</strong> (captures 0307, 0313, 0314, 0325, 0330): Shortened — possibly the measurement caught LP-01 but missed part of LP-00, or the PHY genuinely shortened the low period<br>- <strong>0 ns</strong> (capture 0312): Complete SoT failure → flicker</p>
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<p>This 342 → 108 → 0 ns distribution suggests the SoT LP-low duration has <strong>significant jitter</strong> — it's not always 342 ns. The 108 ns captures may represent borderline events where the bridge barely locked.</p>
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<ul><li></li></ul>
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<p>## 4. Supply Correlation Analysis</p>
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<p>| Capture | LP-low (ns) | LP exit (ns) | Flicker? | 1.8V Mean (V) | Droop (mV) | Ripple RMS (mV) |<br>|---|---|---|---|---|---|---|<br>| 0312 (flicker) | <strong>0</strong> | <strong>0</strong> | <strong>YES</strong> | 1.7691 | 9.1 | 5.46 |<br>| 0305 (good LP) | 343 | 348 | no | 1.7658 | 13.8 | 5.86 |<br>| 0316 (good LP) | 343 | 348 | no | 1.7641 | 16.1 | 5.84 |<br>| 0322 (bad LP) | 343 | 4 | no | 1.7641 | 16.1 | 5.73 |</p>
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<p><strong>No correlation between supply droop/ripple and SoT failures.</strong> The flicker capture (0312) had the <strong>best</strong> supply conditions in the batch (highest mean, lowest droop). Captures with the highest droop (16.1 mV in 0316, 0322) showed no flicker.</p>
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<p><strong>The 1.8 V supply is not the root cause.</strong> The supply is healthy at 1.764–1.770 V with < 17 mV droop — well within the 1.71–1.89 V spec.</p>
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<ul><li></li></ul>
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<p>## 5. Warning/Error Explanation</p>
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<p>| Warning | Frequency | Likely Cause | Action |<br>|---|---|---|---|<br>| "LP exit duration N ns below spec min 50 ns" | 25/30 (83%) | <strong>PHY timing registers underprogram THS_PREPARE+THS_ZERO and TCLK_PREPARE</strong> — the SoT sequence is too fast for the scope (and bridge) to resolve individual LP-01/LP-00 states | Switch to `Round Up` registers |<br>| "CLK lane in continuous HS mode" | 30/30 (100%) | <strong>Expected</strong> — DSI video mode drives CLK continuously; LP-11/SoT only occurs on data lanes | No action needed |<br>| "Only negative swings in capture window" | 27/30 (90%) | High-res sig window triggers on consistent data phase; asymmetric capture | Consider random trigger offset; <strong>not a signal problem</strong> |<br>| "N settled samples below 140 mV" | 30/30 (100%) | ISI/transition undershoot during bit transitions; clock lane asymmetric swing | Monitor; acceptable if median is above 140 mV |<br>| "No HS signal detected" (0307 proto/dat) | 1/30 (3%) | Proto window landed during blanking/LP interval | Retrigger or extend window; <strong>measurement artifact</strong> |<br>| "FLICKER SUSPECT: LP-low plateau absent" (0312) | 1/30 (3%) | <strong>Genuine SoT failure — PHY skipped LP-01/LP-00</strong> | <strong>Root cause of flicker; fix registers</strong> |</p>
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<ul><li></li></ul>
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<p>## 6. Actionable Recommendations</p>
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<p>### 🔴 IMMEDIATE — Switch to 'Round Up' PHY Timing (Primary Fix)</p>
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<p>Patch the samsung-dsim / sec-dsim driver to program `Round Up` values:</p>
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<p>```<br>DSIM_PHYTIMING (0xb4): 0x00000306 → THS_EXIT=6 (111.1 ns ✓)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04 → TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4<br>DSIM_PHYTIMING2 (0xbc): 0x00030706 → THS_ZERO=7, THS_TRAIL=6<br>```</p>
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<p>This eliminates all 5 D-PHY violations. Specifically:<br>- <strong>TCLK_PREPARE</strong> 37→55.6 ns: +18.6 ns margin above 38 ns floor<br>- <strong>THS_PREPARE+THS_ZERO</strong> 166.7→185.2 ns: +17 ns margin above 168.2 ns floor<br>- <strong>TCLK_PREPARE+TCLK_ZERO</strong> 296.3→333.3 ns: +33 ns margin above 300 ns floor<br>- <strong>THS_EXIT</strong> 92.6→111.1 ns: +11 ns margin above 100 ns floor<br>- <strong>TCLK_TRAIL</strong> 55.6→74.1 ns: +14 ns margin above 60 ns floor</p>
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<p>The extra byte-clock per parameter costs ~18.5 ns of SoT overhead per frame entry — negligible at 60 Hz.</p>
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<p><strong>Implementation:</strong> In the driver's `samsung_dsim_set_phy_timing()` or equivalent, change the rounding mode from truncation to ceiling for all timing parameters. Alternatively, apply direct register overrides via device-tree `phy-timing` properties if supported.</p>
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<p>### 🟡 SECONDARY — Investigate LP-11 Voltage (1.015 V)</p>
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<p>At 1.8 V VDDIO, LP-high should be ~1.2 V (VDDIO × 0.67 typ). The measured 1.015 V is 15% low. Check:<br>1. <strong>Series resistance</strong> in LP path (PCB trace, protection resistors, ESD diodes)<br>2. <strong>SN65DSI83 LP input current</strong> loading — the DSI83 LP-mode input impedance may be lower than expected<br>3. <strong>VDDIO actual voltage</strong> at the PHY pad (not just at the regulator) — 1.766 V at the regulator minus PCB IR drop</p>
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<p>While 1.015 V is technically compliant, it leaves zero margin and may contribute to the bridge's inability to cleanly detect LP state transitions.</p>
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<p>### 🟢 OPTIONAL — Clock Lane Amplitude Asymmetry</p>
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<p>The consistent +194/−137 mV asymmetry (28 mV common-mode offset) on CLK suggests a slight impedance mismatch between CLK+ and CLK−. Check:<br>1. Differential pair trace length matching (< 5 mil skew)<br>2. AC coupling capacitors (if present) for value tolerance<br>3. SN65DSI83 CLK input termination</p>
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<p>This is not causing flicker but degrades noise margin.</p>
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<ul><li></li></ul>
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<p>## 7. Summary</p>
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<p><strong>The system is running with 5 D-PHY v1.1 timing violations caused by the `Round Best` register programming mode, which truncates timing parameters to the nearest byte-clock below spec minimums.</strong> The most critical violations — THS_PREPARE+THS_ZERO (1.5 ns short) and TCLK_PREPARE (1.0 ns short) — compress the SoT handshake window to the point where the SN65DSI83 bridge's SoT detector has essentially zero margin. On ~3% of pipeline startups, the PHY's SoT state machine races past LP-01/LP-00 so quickly (or skips them entirely, as in capture 0312) that the bridge fails to enter HS receive mode, producing permanent flicker for that session.</p>
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<p><strong>Switching to the `Round Up` register values (PHYTIMING=0x306, PHYTIMING1=0x030f0a04, PHYTIMING2=0x00030706) will eliminate all 5 violations with comfortable margin and is expected to resolve the intermittent flicker completely.</strong> The 1.8 V supply is healthy and not a contributing factor. No hardware changes are required — this is a software-only fix in the DSIM PHY timing configuration.</p>
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<p class="tokens">Tokens: 45578 in / 4027 out</p>
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