120 lines
19 KiB
HTML
120 lines
19 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0469–0498</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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p { line-height: 1.6; }
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ol, ul { line-height: 1.8; padding-left: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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.flicker-alert h2 { color: #e65100; margin-top: 0; }
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.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
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.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
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.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
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table { border-collapse: collapse; width: 100%; }
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th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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@media print { body { margin: 20px; } }
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</style>
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</head>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 3 of 30 display load sessions (10%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0475</td><td>20260415_095344</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.0 ns</td><td>1.015 V</td></tr><tr><td>0488</td><td>20260415_095826</td><td>dat</td><td style='color:red'>0.3 ns</td><td>1.8 ns</td><td>1.015 V</td></tr><tr><td>0492</td><td>20260415_095953</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.6 ns</td><td>1.015 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0469</td><td>20260415_095133</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0470</td><td>20260415_095154</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0471</td><td>20260415_095217</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0472</td><td>20260415_095239</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0473</td><td>20260415_095300</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0474</td><td>20260415_095322</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0475</td><td>20260415_095344</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0476</td><td>20260415_095406</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0477</td><td>20260415_095427</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0478</td><td>20260415_095449</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0479</td><td>20260415_095511</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0480</td><td>20260415_095532</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0481</td><td>20260415_095554</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0482</td><td>20260415_095616</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0483</td><td>20260415_095637</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0484</td><td>20260415_095659</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0485</td><td>20260415_095721</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0486</td><td>20260415_095743</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0487</td><td>20260415_095804</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0488</td><td>20260415_095826</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0489</td><td>20260415_095848</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0490</td><td>20260415_095910</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0491</td><td>20260415_095931</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0492</td><td>20260415_095953</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0493</td><td>20260415_100015</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0494</td><td>20260415_100036</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0495</td><td>20260415_100058</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0496</td><td>20260415_100120</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0497</td><td>20260415_100142</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0498</td><td>20260415_100204</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-15 10:06:53 |
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<strong>Scope:</strong> Captures 0469–0498 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0469–0498</p>
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<p>## 1. Executive Summary</p>
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<p><strong>The system is running with 'Round Best' PHY timing registers that violate D-PHY v1.1 in 5 fields. Every single capture (30/30) shows identical non-compliant register values. The SoT sequence is marginal: LP-low plateaux are bimodal (either ~343 ns or ~108 ns or 0 ns), and the three confirmed flicker events (0475, 0488, 0492) all have LP-low plateau = 0 ns — meaning the data lane SoT LP-01→LP-00 sequence is entirely absent. The root cause is the too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns min) combined with a too-short TCLK_PREPARE (37.0 ns vs 38.0 ns min), which leaves zero timing margin for the SN65DSI83 to detect the SoT. Switching to the 'Round Up' register set eliminates all 5 violations and should eliminate flicker.</strong></p>
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<ul><li></li></ul>
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<p>## 2. Consistent Spec Concerns</p>
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<p>### 2.1 Register Violations (100% of captures — STATIC, every capture identical)</p>
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<p>| Field | Value | Actual | Spec Min | Deficit | Impact |<br>|-------|-------|--------|----------|---------|--------|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> | Insufficient HS→LP exit time; bridge may not recognise LP return |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> | Clock SoT prepare phase too short; clock lane PLL may not lock |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> | Clock trail too short; bridge may lose clock before data trail completes |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> | Clock lane SoT init sequence too short |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> | <strong>Critical: Data lane SoT sequence is 1.5 ns below spec</strong> |</p>
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<p>The THS_PREPARE+THS_ZERO violation is the <strong>smoking gun</strong>. At 1.5 ns below spec, the SN65DSI83's internal SoT detector is right at its detection threshold. On most startups, the bridge barely catches it (State A). On ~10% of startups, PVT variation or supply noise pushes the effective timing below the bridge's internal detection window → SoT is missed → bridge never locks → permanent flicker (State B).</p>
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<p>### 2.2 LP-11 Voltage</p>
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<ul><li>All captures: <strong>1.014–1.016 V</strong> (spec 1.0–1.45 V) ✓</li><li>Consistent, no drift, but <strong>low in the spec range</strong> (56% of min). This is borderline — the LP-11 high level should be closer to VDDIO (1.8 V). The 1.015 V value suggests the LP drivers are sourcing through significant resistance (likely the 200 Ω series resistors in the LP path), or the bridge's LP termination is loading the line. This reduces noise margin for LP state detection.</li></ul>
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<p>### 2.3 HS Amplitude</p>
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<ul><li><strong>CLK lane</strong>: 163.7–166.6 mV differential — consistently within spec (140–270 mV) but <strong>low</strong> (only 18–19% above the 140 mV floor).</li><li><strong>DAT0 lane</strong>: 186.1–200.0 mV differential — healthier, ~33% above floor.</li><li><strong>Below-140 mV samples</strong>: Present in every capture (7–2052 samples). This indicates ISI/crosstalk dips during transitions. Not the flicker cause but reduces eye margin.</li></ul>
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<p>### 2.4 Clock Common Mode Offset</p>
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<ul><li>All captures show <strong>+27 to +32 mV common mode</strong> on the CLK lane (spec is ±25 mV from VCM nom). This is marginal and indicates slight driver asymmetry on the clock P/N pair.</li></ul>
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<ul><li></li></ul>
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<p>## 3. LP Timing Analysis — The Flicker Mechanism</p>
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<p>### 3.1 LP-Low Plateau Distribution (30 captures)</p>
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<p>| LP-low plateau | Count | LP exit→HS | Flicker? |<br>|----------------|-------|------------|----------|<br>| <strong>~343 ns</strong> | 13 | ~348 ns | <strong>0/13 (0%)</strong> |<br>| <strong>~108 ns</strong> | 8 | 1–4 ns | <strong>0/8 (0%)</strong> |<br>| <strong>0 ns</strong> | <strong>3</strong> | 2–4 ns | <strong>3/3 (100%)</strong> |<br>| Mixed (343 + valid exit) | 6 | 3–113 ns | 0/6 (0%) |</p>
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<p><strong>Key finding</strong>: The LP-low plateau has three discrete values — it is quantised, not continuously distributed. This proves the variation is <strong>digital</strong> (byte-clock quantisation in the DSIM PHY state machine), not analog (noise-induced). The LP→HS SoT sequence duration depends on exactly when the DSIM's internal state machine transitions, which has a ±1 byte-clock (±18.5 ns) jitter relative to the scope trigger.</p>
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<p>### 3.2 Flicker Correlation</p>
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<p>All three flicker captures share:<br>- <strong>LP-low plateau = 0 ns</strong> (SoT LP-01/LP-00 states completely absent)<br>- <strong>LP exit→HS = 1.8–3.6 ns</strong> (effectively instantaneous — no LP→HS transition)<br>- The data lane jumps directly from LP-11 to HS with no intervening LP-01→LP-00 sequence</p>
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<p>This means the <strong>DSIM PHY is occasionally skipping the data lane SoT entry sequence entirely</strong>. The SN65DSI83 requires LP-11 → LP-01 → LP-00 → HS-0 to detect SoT (per D-PHY spec §5.7.1). When this sequence is absent, the bridge cannot synchronise to the HS data stream.</p>
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<p>### 3.3 Root Cause Chain</p>
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<ol><li><strong>THS_PREPARE+THS_ZERO = 166.7 ns</strong> (1.5 ns below 168.2 ns spec min)</li><li>The Samsung DSIM PHY implements this as 9 byte-clocks. Due to internal clock domain crossing between the LP and HS clock domains, the actual LP→HS transition can vary by ±1 byte-clock.</li><li>When the timing falls short by 1 byte-clock (−18.5 ns), the effective THS_PREPARE+THS_ZERO drops to <strong>~148 ns</strong> — well below spec.</li><li>In the worst case, the LP-01/LP-00 states are so brief that they are entirely swallowed by the HS ramp-up, producing LP-low plateau = 0 ns.</li><li>The SN65DSI83 never sees the SoT → never enters HS receive mode → never locks → flicker forever.</li></ol>
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<ul><li></li></ul>
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<p>## 4. Supply Rail Correlation</p>
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<p>### 4.1 1.8 V Supply Statistics</p>
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<p>| Metric | Min | Max | Mean | Spec |<br>|--------|-----|-----|------|------|<br>| Mean voltage | 1.7626 V | 1.7694 V | 1.7649 V | 1.71–1.89 V ✓ |<br>| Min voltage | <strong>1.6920 V</strong> | 1.7360 V | — | 1.71 V min ✗ |<br>| Droop depth | 28.3 mV | <strong>73.4 mV</strong> | 41.6 mV | — |<br>| Ripple RMS | 10.08 mV | 13.03 mV | 11.0 mV | — |</p>
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<p>### 4.2 Sub-spec Supply Events</p>
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<p>5 captures droop below 1.71 V: <strong>0472</strong> (1.696 V), <strong>0478</strong> (1.708 V), <strong>0479</strong> (1.700 V), <strong>0489</strong> (1.692 V), <strong>0492</strong> (1.696 V), <strong>0497</strong> (1.692 V).</p>
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<p>### 4.3 Supply–Flicker Correlation</p>
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<p>| Flicker capture | Min V | Droop | Flicker? |<br>|-----------------|-------|-------|----------|<br>| 0475 | 1.728 V | 34.6 mV | ✓ FLICKER |<br>| 0488 | 1.728 V | 37.8 mV | ✓ FLICKER |<br>| 0492 | <strong>1.696 V</strong> | 69.1 mV | ✓ FLICKER |</p>
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<p><strong>Mixed correlation</strong>: Two of three flicker events (0475, 0488) have <strong>normal</strong> supply conditions (droop < 40 mV, above 1.71 V). Only 0492 has a significant droop. Conversely, several non-flicker captures (0472, 0479, 0489, 0497) have worse droops (65–73 mV) without flicker.</p>
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<p><strong>Conclusion</strong>: Supply droop is <strong>not the primary flicker cause</strong>. The flicker occurs even with clean supply. However, large droops (>60 mV) are a secondary concern:<br>- They reduce LP driver headroom (LP-11 is already at 1.015 V with 1.765 V supply; a 73 mV droop could momentarily reduce LP drive below 1.0 V threshold)<br>- They may exacerbate the DSIM PHY's internal timing uncertainty during the LP→HS transition</p>
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<ul><li></li></ul>
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<p>## 5. Warning/Error Explanation</p>
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<p>| Warning | Count | Cause | Action |<br>|---------|-------|-------|--------|<br>| `sig/dat: No HS signal detected` | 3 captures | Scope triggered during LP or inter-frame gap; DAT0 was idle | Benign — scope timing artifact |<br>| `sig/dat: Only negative swings` | 22 captures | Capture window caught only one polarity of differential data | Benign — data pattern / trigger alignment |<br>| `CLK lane in continuous HS mode` | 30/30 | Expected: DSI clock runs continuously, no LP states on CLK | Normal operation |<br>| `LP exit duration < 50 ns` | 21/30 | <strong>THS_PREPARE is at the edge of spec</strong> — the LP→HS transition happens faster than the scope's LP-state detection algorithm can measure the discrete LP-01/LP-00 steps | The "LP exit" metric measures the time from first LP-11 departure to first HS activity; when THS_PREPARE+THS_ZERO is marginal, the LP-01→LP-00 duration is too short to resolve |<br>| `Supply below 1.71 V` | 6/30 | Transient droop during LP→HS current surge (4 lanes + clock transitioning simultaneously) | Add decoupling — see recommendations |<br>| `Settled samples below 140 mV` | 30/30 on CLK, most on DAT | ISI / transition dips in HS signalling | Low-margin but not root cause; trace impedance and termination review recommended |</p>
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<ul><li></li></ul>
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<p>## 6. Trend Analysis</p>
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<p>### No Degradation Over Time<br>- HS amplitudes, jitter, rise times, LP-11 voltage, and supply mean are <strong>rock-stable</strong> across all 30 captures (captured over ~53 minutes).<br>- No thermal drift, no aging, no progressive degradation.<br>- The flicker events (0475, 0488, 0492) are randomly distributed in time, consistent with a <strong>stochastic digital timing race</strong> rather than an analog drift.</p>
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<p>### Bimodal HS Amplitude on DAT0 (Single-Ended LP Capture)<br>- HS amplitude in LP captures alternates between <strong>~108–120 mV</strong> and <strong>~11–36 mV</strong> (single-ended p-p/2).<br>- The low values (11–36 mV) likely correspond to captures where the scope caught the HS-0 (LP-to-HS transition ramp) rather than settled HS data, or the DAT0 line is carrying a long run of identical symbols. This is a measurement artifact, not a signal quality issue.</p>
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<ul><li></li></ul>
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<p>## 7. Actionable Recommendations</p>
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<p>### 7.1 CRITICAL — Switch to 'Round Up' Register Set (Software Fix)</p>
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<p><strong>Change the samsung-dsim driver to use the 'Round Up' timing calculation.</strong> This is the single most impactful fix and requires no hardware change.</p>
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<p>```<br>PHYTIMING (0xb4): 0x00000305 → 0x00000306 (+1 bc on THS_EXIT)<br>PHYTIMING1 (0xb8): 0x020e0a03 → 0x030f0a04 (+1 bc on TCLK_PREPARE, +1 bc on TCLK_ZERO, +1 bc on TCLK_TRAIL)<br>PHYTIMING2 (0xbc): 0x00030605 → 0x00030706 (+1 bc on THS_ZERO, +1 bc on THS_TRAIL)<br>```</p>
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<p>This eliminates all 5 D-PHY violations:<br>- THS_PREPARE+THS_ZERO: 166.7 → <strong>185.2 ns</strong> (10% margin over 168.2 ns spec)<br>- TCLK_PREPARE: 37.0 → <strong>55.6 ns</strong> (46% margin over 38 ns spec)<br>- TCLK_PREPARE+TCLK_ZERO: 296.3 → <strong>333.3 ns</strong> (11% margin over 300 ns spec)<br>- THS_EXIT: 92.6 → <strong>111.1 ns</strong> (11% margin over 100 ns spec)<br>- TCLK_TRAIL: 55.6 → <strong>74.1 ns</strong> (23% margin over 60 ns spec)</p>
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<p><strong>Implementation</strong>: In the `samsung-dsim` (or `sec-dsim`) driver, the timing calculation function computes byte-clock counts from D-PHY formulas then applies either `round()` or `ceil()`. Change to `ceil()` for all timing parameters, or hard-code the 'Round Up' values via device tree overrides if available.</p>
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<p>### 7.2 HIGH — Improve 1.8 V VDDIO Decoupling</p>
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<ul><li>Add <strong>1 µF + 100 nF MLCC</strong> as close as physically possible to the i.MX 8M Mini MIPI PHY VDDIO pins (balls).</li><li>The 73 mV worst-case droop (4.1% of 1.8 V) with ~11 mV RMS ripple indicates the existing decoupling cannot handle the 4-lane simultaneous LP→HS current surge (~80 mA transient for 4 data + 1 clock lane).</li><li>While not the primary flicker cause, sub-1.71 V excursions violate the VDDIO spec and reduce margins on all LP and HS thresholds.</li></ul>
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<p>### 7.3 MEDIUM — Investigate LP-11 Voltage</p>
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<ul><li>LP-11 at 1.015 V with VDDIO = 1.765 V means <strong>785 mV</strong> dropped across the LP output stage and series resistors. The D-PHY spec allows LP-11 down to 1.0 V, so this is technically compliant, but:</li><li>The SN65DSI83 LP receiver thresholds are referenced to its own VDDIO, so the actual noise margin depends on the bridge's input threshold.</li><li>Check that the 200 Ω LP series resistors (if present) are not excessively loading the LP output.</li><li>Verify the bridge's LP termination resistance matches expectations.</li></ul>
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<p>### 7.4 LOW — HS Amplitude Margin</p>
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<ul><li>CLK at 165 mV is only 18% above the 140 mV floor. While sufficient under nominal conditions, it leaves little margin for connector aging, temperature, or cable degradation.</li><li>If the design uses a flex cable or connector between the SOM and the SN65DSI83, verify impedance matching (100 Ω differential) and minimise stub lengths.</li></ul>
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<ul><li></li></ul>
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<p>## 8. Overall Signal Health & Flicker Risk</p>
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<ul><li>The HS signal quality is adequate but low-margin</li></ul>
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<p class="tokens">Tokens: 45813 in / 4096 out</p>
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</body>
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</html>
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