114 lines
18 KiB
HTML
114 lines
18 KiB
HTML
<!DOCTYPE html>
|
||
<html lang="en">
|
||
<head>
|
||
<meta charset="UTF-8">
|
||
<title>MIPI Analysis — Captures 0305–0334</title>
|
||
<style>
|
||
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
|
||
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
|
||
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
|
||
p { line-height: 1.6; }
|
||
ol, ul { line-height: 1.8; padding-left: 24px; }
|
||
li { margin: 4px 0; }
|
||
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
|
||
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
|
||
padding: 16px 20px; margin-bottom: 28px; }
|
||
.flicker-alert h2 { color: #e65100; margin-top: 0; }
|
||
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
|
||
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
|
||
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
|
||
table { border-collapse: collapse; width: 100%; }
|
||
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
|
||
td { border: 1px solid #ddd; padding: 5px 10px; }
|
||
@media print { body { margin: 20px; } }
|
||
</style>
|
||
</head>
|
||
<body>
|
||
<h1>MIPI D-PHY Analysis Report</h1>
|
||
|
||
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
|
||
padding:16px 20px;margin-bottom:28px;">
|
||
<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 3 of 30 display load sessions (10%) flickered</h2>
|
||
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
|
||
pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
|
||
missed the SoT sequence and dropped a frame.<br>
|
||
LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
|
||
for the SN65DSI83 bridge to detect start-of-transmission.</p>
|
||
<table>
|
||
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
|
||
<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
|
||
<tr><td>0313</td><td>20260410_123438</td><td>dat</td><td style='color:red'>1.4 ns</td><td>0.1 ns</td><td>1.015 V</td></tr><tr><td>0320</td><td>20260410_123710</td><td>dat</td><td style='color:red'>0.2 ns</td><td>1.9 ns</td><td>1.017 V</td></tr><tr><td>0325</td><td>20260410_123858</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.5 ns</td><td>1.015 V</td></tr>
|
||
</table>
|
||
</div>
|
||
|
||
<details style="margin-bottom:24px;">
|
||
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
|
||
DSI Register Snapshots (30 captures)
|
||
</summary>
|
||
<div style="overflow-x:auto;margin-top:8px;">
|
||
<table>
|
||
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
|
||
<tr><td>0305</td><td>20260410_123145</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260410_123206</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260410_123228</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260410_123250</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260410_123312</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260410_123333</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260410_123355</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260410_123417</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260410_123438</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260410_123500</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260410_123521</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260410_123543</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260410_123604</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260410_123626</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260410_123648</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260410_123710</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260410_123731</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260410_123753</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260410_123815</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260410_123836</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260410_123858</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260410_123920</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260410_123941</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260410_124003</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260410_124024</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260410_124046</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260410_124108</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260410_124130</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0333</td><td>20260410_124151</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0334</td><td>20260410_124213</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
|
||
</table>
|
||
</div>
|
||
</details>
|
||
<p class="meta">
|
||
<strong>Generated:</strong> 2026-04-10 12:46:56 |
|
||
<strong>Scope:</strong> Captures 0305–0334 |
|
||
<strong>Model:</strong> claude-opus-4-6
|
||
</p>
|
||
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0305–0334</p>
|
||
<p>## 1. Root Cause Identification</p>
|
||
<p>### The Primary Problem: Register Mismatch — Driver Not Applying Target Timing</p>
|
||
<p><strong>This is the single most important finding.</strong> Every capture shows the same register values:</p>
|
||
<p>| Register | Actual (all captures) | Target (spec-compliant) | Delta |<br>|---|---|---|---|<br>| PHYTIMING (0xb4) | `0x00000305` | `0x00000306` | THS_EXIT: 5→93 ns vs 6→111 ns |<br>| PHYTIMING1 (0xb8) | `0x020e0a03` | `0x03110A04` | TCLK_PREPARE: 2→37 ns vs 3→56 ns; <strong>TCLK_ZERO: 14→259 ns vs 17→315 ns</strong>; TCLK_TRAIL: 3→56 ns vs 4→74 ns |<br>| PHYTIMING2 (0xbc) | `0x00030605` | `0x00040A03` | <strong>THS_PREPARE: 5→93 ns vs 3→56 ns</strong>; <strong>THS_ZERO: 6→111 ns vs 10→185 ns</strong>; THS_TRAIL: 3→56 ns vs 4→74 ns |</p>
|
||
<p><strong>Critical field-level decode of actual register 0xbc = `0x00030605`:</strong></p>
|
||
<p>| Field | Actual | Duration | D-PHY v1.1 Spec | Status |<br>|---|---|---|---|---|<br>| THS_PREPARE | 5 | 92.6 ns | 40+4×UI=49.3 ns … 85+6×UI=98.9 ns | ✓ but at upper edge |<br>| THS_ZERO | 6 | 111.1 ns | <strong>THS_ZERO + THS_PREPARE ≥ 145+10×UI = 168.2 ns</strong> → need THS_ZERO ≥ ~4.1 → 5 min | Marginal ✓ (combined = 203.7 ns ≥ 168.2 ns) |<br>| THS_TRAIL | 3 | 55.6 ns | max(n×8×UI, 60+n×4×UI) = 60+4×2.315 = <strong>69.3 ns</strong> | <strong>✗ VIOLATION</strong> |</p>
|
||
<p><strong>Critical field-level decode of actual register 0xb8 = `0x020e0a03`:</strong></p>
|
||
<p>| Field | Actual | Duration | Spec | Status |<br>|---|---|---|---|---|<br>| TCLK_PREPARE | 2 | 37.0 ns | 38 ns … 95 ns | <strong>✗ VIOLATION (37 < 38 ns)</strong> |<br>| TCLK_ZERO | 14 (0x0e) | 259.3 ns | TCLK_PREPARE + TCLK_ZERO ≥ 300 ns | <strong>✗ VIOLATION (296.3 < 300 ns)</strong> |<br>| TCLK_POST | 10 (0x0a) | 185.2 ns | 60 + 52×UI = 180.4 ns | ✓ barely |<br>| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | <strong>✗ VIOLATION (55.6 < 60 ns)</strong> |</p>
|
||
<p>### Summary of Timing Violations in Running Registers</p>
|
||
<p>| Parameter | Required | Actual | Margin | Verdict |<br>|---|---|---|---|---|<br>| TCLK_PREPARE | ≥ 38 ns | 37.0 ns | <strong>−1 ns</strong> | <strong>FAIL</strong> |<br>| TCLK_PREPARE + TCLK_ZERO | ≥ 300 ns | 296.3 ns | <strong>−3.7 ns</strong> | <strong>FAIL</strong> |<br>| TCLK_TRAIL | ≥ 60 ns | 55.6 ns | <strong>−4.4 ns</strong> | <strong>FAIL</strong> |<br>| THS_TRAIL | ≥ 69.3 ns | 55.6 ns | <strong>−13.7 ns</strong> | <strong>FAIL</strong> |<br>| THS_EXIT | ≥ 100 ns | 92.6 ns | <strong>−7.4 ns</strong> | <strong>FAIL</strong> |<br>| TLPX | ≥ 50 ns | 55.6 ns | +5.6 ns | ✓ marginal |</p>
|
||
<p><strong>Five timing parameters are out of spec.</strong> The samsung-dsim driver is computing or applying incorrect values. The target values (which you've verified as compliant) are not reaching the hardware.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 2. LP SoT Sequence Analysis — The Flicker Mechanism</p>
|
||
<p>### LP-Low Plateau Distribution (all captures with valid LP data)</p>
|
||
<p>| LP-low plateau | Captures | Flicker? |<br>|---|---|---|<br>| ~342–343 ns | 0305, 0306, 0310, 0312, 0316, 0317, 0319, 0321, 0322, 0323, 0324, 0329, 0332, 0333, 0334 | All NO |<br>| ~108 ns | 0308 (69 ns), 0311, 0315, 0326, 0327, 0328 | All NO |<br>| <strong>0–1.4 ns</strong> | <strong>0313 (1 ns), 0320 (0 ns), 0325 (0 ns)</strong> | <strong>ALL YES</strong> |</p>
|
||
<p><strong>The correlation is absolute:</strong> Flicker occurs if and only if the LP-low plateau is effectively absent (< ~2 ns). The SN65DSI83 requires a well-formed LP-11 → LP-01 → LP-00 → HS-0 SoT entry sequence on the data lanes. When the LP-low states are compressed to zero, the bridge cannot detect the SoT, fails to lock to the HS data stream, and remains stuck for the entire session.</p>
|
||
<p>### Why LP-Low Disappears Intermittently</p>
|
||
<p>The LP exit → HS measurement is universally 0–4 ns across <strong>all</strong> captures (good and bad), meaning the LP-01 transition state is always extremely brief. This is consistent with the TLPX register value of 3 byte-clocks (55.6 ns) — marginally above the 50 ns spec minimum — combined with the fact that TCLK_PREPARE, THS_PREPARE, and THS_EXIT are all either at or below spec limits.</p>
|
||
<p>The key observation is that the LP-low plateau shows a <strong>trimodal distribution</strong>: ~343 ns, ~108 ns, or ~0 ns. This suggests:</p>
|
||
<ol><li>The PHY state machine has a race condition at the LP→HS transition</li><li>The combination of marginal/violated timing parameters creates a window where the PHY occasionally skips the LP-00 hold state entirely</li><li>The ~343 ns cases likely represent a full nominal hold; ~108 ns represents one byte-clock step shorter (≈6 byte-clocks vs ~18.5 byte-clocks); 0 ns represents complete state skip</li></ol>
|
||
<p>The THS_TRAIL violation (55.6 ns vs required 69.3 ns) and THS_EXIT violation (92.6 ns vs required 100 ns) are particularly relevant: if the PHY's internal LP state machine uses these timers to sequence the LP-01→LP-00→HS-0 entry, short timers increase the probability that on any given startup, the state machine races through or skips the low states.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 3. HS Signal Health</p>
|
||
<p>### Consistent Concerns</p>
|
||
<p>| Parameter | Typical Value | Spec | Assessment |<br>|---|---|---|---|<br>| CLK Vdiff | 166.2–167.2 mV | 140–270 mV | ✓ but only <strong>19% above floor</strong> — very low margin |<br>| DAT Vdiff | 186–197 mV | 140–270 mV | ✓ acceptable |<br>| CLK common mode | +28–32 mV | ±25 mV recommended | Slightly high, minor |<br>| CLK asymmetry | +196/−136 mV | Should be symmetric | <strong>60 mV offset — significant</strong> |<br>| DAT below-140mV samples | 29–16234 per capture | 0 | <strong>Persistent spec violation</strong> |<br>| CLK below-140mV samples | 40–274 per capture | 0 | <strong>Persistent spec violation</strong> |</p>
|
||
<p>The clock amplitude of ~167 mV is only 27 mV above the 140 mV absolute minimum. The persistent sub-140 mV excursions are transition-region violations (ISI/ringing during edge transitions), not a settled-level problem, but they represent genuine eye-closure events.</p>
|
||
<p><strong>Clock asymmetry</strong> (+196/−136 mV, ~60 mV offset) indicates either a DC offset in the PHY output driver or an impedance mismatch on the CLK+ vs CLK− traces. This doesn't directly cause flicker but reduces noise margin.</p>
|
||
<p>### No Significant Trends Over Time</p>
|
||
<p>| Parameter | Capture 0305 | Capture 0334 | Trend |<br>|---|---|---|---|<br>| CLK Vdiff | 166.5 mV | 166.2 mV | Flat |<br>| DAT Vdiff | 187.2 mV | 186.4 mV | Flat |<br>| CLK jitter RMS | 54.6 ps | 53.8 ps | Flat |<br>| LP-11 voltage | 1.015 V | 1.014 V | Flat |<br>| 1.8V mean | 1.7663 V | 1.7670 V | Flat |</p>
|
||
<p>No thermal drift, aging, or progressive degradation detected across this batch.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 4. Supply Rail Correlation</p>
|
||
<p>### 1.8V Supply Statistics</p>
|
||
<p>| Metric | Range | Spec |<br>|---|---|---|<br>| Mean | 1.7655–1.7724 V | 1.71–1.89 V ✓ but 34–45 mV below nominal |<br>| Min | 1.6960–1.7440 V | ≥ 1.71 V |<br>| Droop | 24.5–69.7 mV | — |</p>
|
||
<p>Two captures breach the 1.71 V floor: <strong>0305</strong> (1.700 V, 66 mV droop) and <strong>0314</strong> (1.696 V, 70 mV droop).</p>
|
||
<p>### Supply vs Flicker Correlation</p>
|
||
<p>| Capture | Flicker? | LP-low | Droop (mV) | Min V |<br>|---|---|---|---|---|<br>| <strong>0313</strong> | <strong>YES</strong> | 1 ns | 35.4 | 1.732 V |<br>| <strong>0320</strong> | <strong>YES</strong> | 0 ns | 55.3 | 1.712 V |<br>| <strong>0325</strong> | <strong>YES</strong> | 0 ns | 38.2 | 1.728 V |<br>| 0305 | no | 343 ns | <strong>66.3</strong> | <strong>1.700 V</strong> |<br>| 0314 | no (no LP data) | — | <strong>69.7</strong> | <strong>1.696 V</strong> |<br>| 0329 | no | 343 ns | 50.0 | 1.716 V |</p>
|
||
<p><strong>No correlation between supply droop and flicker.</strong> Capture 0313 (flicker) has only 35 mV droop, while 0305 and 0314 (no flicker) have the worst droops at 66–70 mV. The flicker mechanism is not supply-droop-driven. However, the supply violations are a separate concern that should be addressed.</p>
|
||
<ul><li></li></ul>
|
||
<p>## 5. Warning/Error Explanations</p>
|
||
<p>| Warning/Error | Frequency | Most Likely Cause | Action |<br>|---|---|---|---|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>100% of LP captures</strong> | Register TLPX=3 (55.6 ns) is marginal; actual LP-01 state is being measured at single-ended level with limited bandwidth — the 0–4 ns measurement likely reflects the fast single-ended slew between LP-11 and LP-00, not a true timing violation at the protocol level. But the LP-01→LP-00 transition is clearly being squeezed. | Increase TLPX to 4 (74 ns) in target registers |<br>| `LP-low plateau absent or < 50 ns` (FLICKER) | 3/30 (10%) | PHY state machine race — LP-00 hold state skipped due to marginal/violated timing register values | <strong>Apply correct registers (see §6)</strong> |<br>| `Only negative swings in capture window` | ~60% of sig/dat | Oscilloscope trigger or probe captured during a run of consecutive '0' bits (or blanking with HS-0 idle) | Non-actionable — adjust trigger or increase capture window for sig captures |<br>| `index 200000 out of bounds` | 5 captures | LP data array too short — likely the SoT transition occurred outside the trigger window or the capture didn't include the LP→HS edge | Adjust trigger delay or increase pre-trigger buffer |<br>| `CLK lane continuous HS mode — LP states not expected` | 100% | Expected — DSI clock lane runs in continuous HS mode (non-burst) at this configuration | Non-actionable, correct behavior |<br>| `Supply droops below 1.71 V` | 2/30 (7%) | Insufficient bulk + HF decoupling on VDDIO near PHY, combined with LP→HS transient current draw (~tens of mA step) | Add 10 µF + 100 nF ceramic caps close to MIPI PHY VDDIO pins |<br>| `No HS signal detected` (sig/dat) | 2 captures (0325, 0328, 0332) | Scope captured during blanking interval or LP state on data lane — no HS activity in window | Non-actionable artifact |<br>| `Settled samples below 140 mV` | 100% of proto captures | ISI-induced eye closure during transitions and during low-amplitude data patterns; clock amplitude is marginal at 167 mV | Monitor; consider trace impedance tuning if layout revision is possible |</p>
|
||
<ul><li></li></ul>
|
||
<p>## 6. Actionable Recommendations</p>
|
||
<p>### CRITICAL — Fix #1: Force Correct PHY Timing Registers</p>
|
||
<p>The samsung-dsim driver is not applying your target values. The actual registers show shorter timings that violate D-PHY spec in 5 parameters. <strong>This is the root cause of the intermittent flicker.</strong></p>
|
||
<p><strong>Option A — Device Tree override (preferred, no driver patch):</strong><br>In the DSIM node of the device tree, check if `samsung,phy-timing` properties exist. The `sec-dsim` / `samsung-dsim` driver in some BSP versions computes timings from the bit rate using internal formulas that may undercount at 432 Mbit/s. If the DT accepts explicit timing overrides:</p>
|
||
<p>```dts<br>&mipi_dsi {<br> samsung,phy-timing = <0x00000306 0x03110A04 0x00040A03>;<br> /* Or individual fields if supported by your BSP version */<br>};<br>```</p>
|
||
<p><strong>Option B — Direct register poke (validation only):</strong><br>```bash<br># After pipeline load but before enable:<br>memtool mw -l 0x32e100b4=0x00000306<br>memtool mw -l 0x32e100b8=0x03110A04<br>memtool mw -l 0x32e100bc=0x00040A03<br>```</p>
|
||
<p><strong>Option C — Driver patch:</strong><br>In `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` depending on BSP), find the `samsung_dsim_set_phy_timing()` function and either:<br>- Override the computed values with hardcoded values for your bit rate, or<br>- Fix the computation formula (the standard formula uses `ceil((ns_value / byte_clk_period) - 1)` which at 432 Mbit/s rounds down for several parameters)</p>
|
||
<p><strong>Expected effect:</strong> Increasing THS_ZERO from 6→10, THS_TRAIL from 3→4, TCLK_PREPARE from 2→3, TCLK_ZERO from 14→17, and TCLK_TRAIL from 3→4 will bring all parameters into spec. More importantly, the longer THS_ZERO/THS_PREPARE timing combination gives the PHY state machine more time to properly sequence LP</p>
|
||
<p class="tokens">Tokens: 32742 in / 4096 out</p>
|
||
</body>
|
||
</html>
|