155 lines
20 KiB
HTML
155 lines
20 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Interactive Flicker Test — 2026-04-16 10:28:00</title>
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<style>
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body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
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padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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h2 { color: #1a3a5c; margin-top: 32px; }
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h3 { color: #333; }
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.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
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.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
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padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
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.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
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border-radius: 6px; font-size: 1.05em; font-weight: bold; }
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.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
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.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
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.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
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table { border-collapse: collapse; width: 100%; margin-top: 8px; }
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th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
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td { border: 1px solid #ddd; padding: 5px 10px; }
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tr:nth-child(even) { background: #fafafa; }
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pre { margin: 0; }
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</style>
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</head>
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<body>
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<h1>MIPI Interactive Flicker Test Report</h1>
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<p class="meta">
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Generated: 2026-04-16 10:28:00 |
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Model: claude-opus-4-6
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</p>
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<div class="stop-box">
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<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
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</div>
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<div>
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<div class="stat s-confirmed">0 confirmed flicker(s)</div>
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<div class="stat s-false">16 false alarm(s)</div>
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<div class="stat s-claude-no">0 Claude said no</div>
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</div>
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<h2>D-PHY Configuration</h2>
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<p>
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Pixel clock: <strong>72.0 MHz</strong> |
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Bit rate: <strong>432.0 Mbit/s per lane</strong> |
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Byte clock: <strong>54.000 MHz</strong>
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(18.519 ns/byte) |
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UI: <strong>2.315 ns</strong>
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</p>
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<table>
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<tr>
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<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
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<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
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</tr>
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<tr><td><code>lpx</code></td><td>≥ 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
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<tr><td><code>hs_prepare</code></td><td>49.3 – 98.9</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
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<tr><td><code>hs_zero</code></td><td>≥ 112.6</td><td>6</td><td>7</td><td>+0</td><td><strong>7</strong></td><td>129.63</td><td>✓</td></tr>
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<tr><td><code>hs_trail</code></td><td>≥ 69.3</td><td>4</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>✓</td></tr>
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<tr><td><code>hs_exit</code></td><td>≥ 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>✓</td></tr>
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<tr><td><code>clk_prepare</code></td><td>38.0 – 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>✓</td></tr>
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<tr><td><code>clk_zero</code></td><td>≥ 244.4</td><td>13</td><td>14</td><td>+0</td><td><strong>14</strong></td><td>259.26</td><td>✓</td></tr>
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<tr><td><code>clk_post</code></td><td>≥ 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>✓</td></tr>
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<tr><td><code>clk_trail</code></td><td>≥ 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>✓</td></tr>
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</table>
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<p style="color:#2e7d32">✓ All D-PHY v1.1 Table 14 constraints satisfied.</p>
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<h3>Samsung DSIM Registers</h3>
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<table>
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<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
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<tr>
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<td>PHY_TIMING</td><td><code>0xb4</code></td>
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<td><code>0x00000306</code></td>
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<td>lpx=3 hs_exit=6</td>
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</tr>
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<tr>
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<td>PHY_TIMING1</td><td><code>0xb8</code></td>
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<td><code>0x030e0a04</code></td>
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<td>clk_prepare=3 clk_zero=14
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clk_post=10 clk_trail=4</td>
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</tr>
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<tr>
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<td>PHY_TIMING2</td><td><code>0xbc</code></td>
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<td><code>0x00030704</code></td>
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<td>hs_prepare=3 hs_zero=7
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hs_trail=4</td>
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</tr>
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</table>
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<h3>u-boot Commands</h3>
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<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
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white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
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#
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# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
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# PHY_TIMING1 (0xb8) = 0x030e0a04 clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
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# PHY_TIMING2 (0xbc) = 0x00030704 hs_prepare=3 hs_zero=7 hs_trail=4
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# Enable Round-Up rounding (dsi-tweak bit 2)
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setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"
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saveenv
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boot</pre>
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<h2>Event Log</h2>
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<table>
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<tr>
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<th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th>
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<th>Claude: flicker?</th><th>Outcome</th>
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</tr>
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<tr><td>0002</td><td>20260416_091714</td><td>dat</td><td style="color:red">0.3 ns</td><td>1.4 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0029</td><td>20260416_092745</td><td>dat</td><td style="color:red">0.3 ns</td><td>1.8 ns</td><td>1.017 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0041</td><td>20260416_093239</td><td>dat</td><td style="color:red">0.3 ns</td><td>1.9 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0052</td><td>20260416_093705</td><td>dat</td><td style="color:red">0.3 ns</td><td>2.6 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0091</td><td>20260416_095213</td><td>dat</td><td style="color:red">0.2 ns</td><td>1.9 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0093</td><td>20260416_095313</td><td>dat</td><td style="color:red">0.2 ns</td><td>0.6 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0095</td><td>20260416_095412</td><td>dat</td><td style="color:red">0.3 ns</td><td>1.3 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0105</td><td>20260416_095814</td><td>dat</td><td style="color:red">0.9 ns</td><td>0.8 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0124</td><td>20260416_100542</td><td>dat</td><td style="color:red">0.3 ns</td><td>3.5 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0135</td><td>20260416_101007</td><td>dat</td><td style="color:red">23.1 ns</td><td>1.2 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0139</td><td>20260416_101154</td><td>dat</td><td style="color:red">0.2 ns</td><td>0.1 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0144</td><td>20260416_101402</td><td>dat</td><td style="color:red">0.2 ns</td><td>0.1 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0145</td><td>20260416_101439</td><td>dat</td><td style="color:red">0.2 ns</td><td>3.6 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0160</td><td>20260416_102036</td><td>dat</td><td style="color:red">39.8 ns</td><td>0.1 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0170</td><td>20260416_102440</td><td>dat</td><td style="color:red">0.3 ns</td><td>0.8 ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr><tr><td>0176</td><td>20260416_102713</td><td>dat</td><td style="color:red">0.9 ns</td><td>0.1 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">✓ FALSE ALARM</span></td></tr>
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</table>
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<h2>Claude Assessments</h2><h3>Capture 0002 [20260416_091714] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at effectively 0 ns (reported 0.3 ns) is drastically below the SN65DSI83's required ≥ 50 ns minimum for SoT detection. The LP exit-to-HS transition of only 1 ns confirms that the LP-01/LP-00 preamble states are essentially absent, meaning the bridge has no opportunity to recognize the start-of-transmission sequence. With these timing values, the SN65DSI83 will almost certainly miss the HS entry, resulting in a lost or corrupted video frame and visible display flicker.</pre><h3>Capture 0029 [20260416_092745] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau of 0.3 ns is essentially absent—two orders of magnitude below the SN65DSI83's required ≥ 50 ns minimum for SoT detection. The LP exit-to-HS transition of only 2 ns (also far below the 50 ns spec) confirms that the LP-01/LP-00 preamble states were either skipped or collapsed into a sub-UI glitch, making it impossible for the bridge's LP receiver to recognize the start-of-transmission. Additionally, the HS single-ended amplitude of 31 mV is anomalously low, suggesting the bridge likely failed to lock onto the HS data burst entirely, which would produce a dropped or corrupted frame and visible flicker.</pre><h3>Capture 0041 [20260416_093239] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau is measured at effectively 0 ns (flagged as 0.3 ns by the pre-processor), far below the SN65DSI83's 50 ns minimum requirement for SoT detection. The LP exit-to-HS transition of only 2 ns confirms that the LP-01/LP-00 preamble states were essentially skipped, meaning the bridge had no opportunity to recognize the start-of-transmission. With the HS amplitude also anomalously low at 32 mV (suggesting the bridge may not have properly locked onto the HS data), this capture is a clear flicker event where the SN65DSI83 missed the SoT and failed to decode the subsequent HS burst.</pre><h3>Capture 0052 [20260416_093705] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at 0.3 ns is effectively absent — it is over two orders of magnitude below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection. The total LP exit-to-HS transition of only 3 ns (versus the ≥ 50 ns spec) confirms that the LP-01/LP-00 preamble states were essentially skipped, meaning the bridge almost certainly failed to recognize the start-of-transmission. This is a textbook flicker-inducing condition: without a properly timed SoT sequence, the SN65DSI83 cannot synchronize to the incoming HS burst, resulting in a missed or corrupted video frame and visible display flicker.</pre><h3>Capture 0091 [20260416_095213] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at 0.2 ns is essentially absent — nearly three orders of magnitude below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection. The LP exit-to-HS transition of only 2 ns (vs. the 50 ns spec minimum) confirms that the LP-01/LP-00 preamble states were either skipped or collapsed to sub-UI durations, meaning the bridge almost certainly missed the start-of-transmission. With the SoT undetected, the bridge would fail to deserialize the subsequent HS burst (~5012 ns), resulting in a dropped or corrupted video line and visible flicker on the display.</pre><h3>Capture 0093 [20260416_095313] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at effectively 0 ns (reported 0.2 ns) is vastly below the 50 ns minimum required by the SN65DSI83 to detect the Start-of-Transmission sequence. The LP exit-to-HS transition of only 1 ns (vs. the ≥50 ns spec) confirms that the LP-01/LP-00 preamble states were essentially absent, meaning the bridge had no opportunity to recognize the SoT entry. With the receiver unable to lock onto the HS burst, this capture almost certainly resulted in a missed packet and visible display flicker.</pre><h3>Capture 0095 [20260416_095412] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau is measured at effectively 0 ns (reported as 0.3 ns by the flag, 0 ns in the full summary), which is drastically below the SN65DSI83's required ≥ 50 ns minimum for SoT detection. The LP exit-to-HS transition of only 1–1.3 ns confirms that the LP-01/LP-00 preamble states are essentially absent, meaning the bridge has no opportunity to recognize the start-of-transmission sequence. Additionally, the HS single-ended amplitude of only 26 mV is abnormally low (typical is ~100–200 mV), further suggesting the bridge would fail to lock onto the HS data, compounding the flicker risk. This capture is a textbook flicker event: the transmitter is skipping or compressing the LP-to-HS entry sequence far below what the SN65DSI83 requires.</pre><h3>Capture 0105 [20260416_095814] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at only ~1 ns, which is drastically below the SN65DSI83's required ≥50 ns minimum for reliable SoT detection — falling short by nearly two orders of magnitude. The LP exit-to-HS transition of just 1 ns confirms that the LP-01/LP-00 preamble states were essentially absent or collapsed into a sub-UI glitch, making it impossible for the bridge's LP receiver to recognize the start-of-transmission sequence. With the bridge unable to synchronize to the incoming HS burst, the corresponding video data would be lost, producing visible flicker on the display.</pre><h3>Capture 0124 [20260416_100542] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at effectively 0 ns (reported as 0.3 ns by the pre-processor, 0 ns in the full summary) is drastically below the 50 ns minimum required by the SN65DSI83 to detect the Start-of-Transmission sequence. The LP exit-to-HS transition of only 4 ns confirms that the LP-01/LP-00 preamble states were essentially skipped, giving the bridge no opportunity to recognize the SoT and synchronize to the incoming HS burst. With the receiver unable to lock onto the data, this capture almost certainly resulted in a missed frame and visible display flicker.</pre><h3>Capture 0135 [20260416_101007] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau of 23.1 ns is less than half the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of only 1.2 ns is drastically below the 50 ns spec minimum, indicating the LP-01/LP-00 preamble states were essentially skipped. With these timing violations, the bridge almost certainly failed to recognize the start-of-transmission, causing it to miss the subsequent HS burst entirely. This is a textbook flicker-inducing condition for the SN65DSI83, which is known to be strict about LP timing compliance.</pre><h3>Capture 0139 [20260416_101154] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau is measured at effectively 0 ns (reported as 0.2 ns by the flag, 0 ns in the full summary), far below the 50 ns minimum required by the SN65DSI83 to detect the Start-of-Transmission sequence. The LP exit-to-HS transition time of 0 ns confirms that the LP-01/LP-00 preamble states are essentially absent, meaning the bridge has no opportunity to recognize the SoT and synchronize to the incoming HS data burst. Despite the LP-11 voltage being within spec (1.015 V) and a valid HS burst being present, the missing LP-low plateau will cause the SN65DSI83 to miss this HS packet, resulting in visible display flicker.</pre><h3>Capture 0144 [20260416_101402] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau is measured at effectively 0 ns (reported as 0.2 ns by the pre-processor, 0 ns in the full summary), far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection. The LP exit-to-HS transition time is also 0 ns, indicating the LP-01/LP-00 preamble states are essentially absent — the transmitter appears to jump from LP-11 directly into HS mode without dwelling in the required low states. Without a valid SoT preamble the bridge cannot synchronize to the incoming HS burst, which will cause it to miss the video packet and produce visible flicker on the display.</pre><h3>Capture 0145 [20260416_101439] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau is effectively absent at 0.2 ns (rounded to 0 ns in the full summary), which is drastically below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection. The LP exit-to-HS transition of only 3.6–4 ns confirms that the LP-01/LP-00 preamble states were either skipped or collapsed to sub-UI durations, far too brief for the bridge's LP receiver to recognize the start-of-transmission sequence. With the bridge unable to synchronize to the incoming HS burst, this capture almost certainly represents a missed SoT event resulting in visible display flicker.</pre><h3>Capture 0160 [20260416_102036] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau of 39.8 ns is clearly below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, falling short by over 10 ns (approximately 20% under spec). Additionally, the LP exit → HS transition time of 0.1 ns is essentially instantaneous, indicating the LP-01/LP-00 preamble states were either absent or too brief for the bridge's input comparators to properly recognize the start-of-transmission sequence. These two violations together — a truncated LP-low plateau and a missing LP exit interval — make it highly likely the SN65DSI83 failed to detect this SoT, resulting in a dropped or corrupted HS burst and visible display flicker.</pre><h3>Capture 0170 [20260416_102440] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at 0.3 ns is effectively absent and falls catastrophically short of the SN65DSI83's required ≥ 50 ns minimum for SoT detection. The LP exit-to-HS transition of only 1 ns (versus the 50 ns spec minimum) confirms that the LP-01/LP-00 preamble states were essentially skipped, meaning the bridge had no opportunity to recognize the start-of-transmission. With these timing violations — roughly two orders of magnitude below specification — the SN65DSI83 would almost certainly miss the SoT, fail to synchronize to the incoming HS burst, and produce a visible flicker event on the display.</pre><h3>Capture 0176 [20260416_102713] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
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The LP-low plateau measured at only 0.9 ns is drastically below the SN65DSI83's required ≥ 50 ns minimum for SoT detection — it is essentially absent at less than 2% of the required duration. The LP exit-to-HS transition time of 0 ns further confirms that the LP-01/LP-00 preamble states were either skipped or too brief to be resolved, meaning the bridge almost certainly failed to recognize the start-of-transmission. With the LP→HS entry sequence this severely truncated, the SN65DSI83 would miss the HS sync, causing a dropped or corrupted video line/frame and resulting in visible flicker.</pre>
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</body>
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</html>
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