MIPI Interactive Flicker Test Report

Generated: 2026-04-17 09:29:53 | Model: claude-opus-4-6

Stop reason: Test interrupted by operator (Ctrl+C)

0 confirmed flicker(s)

2 false alarm(s)

6 Claude said no

D-PHY Configuration

Pixel clock: 72.0 MHz | Bit rate: 432.0 Mbit/s per lane | Byte clock: 54.000 MHz (18.519 ns/byte) | UI: 2.315 ns

Field	Spec (ns)	Rnd Best	Rnd Up	Extra	Final	Actual (ns)	Status
`lpx`	≥ 50.0	3	3	+0	3	55.56	✓
`hs_prepare`	49.3 – 98.9	3	3	+0	3	55.56	✓
`hs_zero`	≥ 112.6	6	7	+0	7	129.63	✓
`hs_trail`	≥ 69.3	4	4	+0	4	74.07	✓
`hs_exit`	≥ 100.0	5	6	+0	6	111.11	✓
`clk_prepare`	38.0 – 95.0	2	3	+0	3	55.56	✓
`clk_zero`	≥ 244.4	13	14	+0	14	259.26	✓
`clk_post`	≥ 180.4	10	10	+0	10	185.19	✓
`clk_trail`	≥ 60.0	3	4	+0	4	74.07	✓

✓ All D-PHY v1.1 Table 14 constraints satisfied.

Samsung DSIM Registers

Register	Address	Value	Field breakdown
PHY_TIMING	`0xb4`	`0x00000306`	lpx=3 hs_exit=6
PHY_TIMING1	`0xb8`	`0x030e0a04`	clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
PHY_TIMING2	`0xbc`	`0x00030704`	hs_prepare=3 hs_zero=7 hs_trail=4

u-boot Commands

# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04   clk_prepare=3  clk_zero=14  clk_post=10  clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704   hs_prepare=3  hs_zero=7  hs_trail=4

# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"

saveenv
boot

Event Log

Capture	Timestamp	Channel	LP-low plateau	LP exit→HS	LP-11 voltage	Claude: flicker?	Outcome
0001	20260417_084455	dat	107.8 ns	112.9 ns	1.016 V	NO	Claude said NO — user not asked
0005	20260417_084634	dat	53.2 ns	58.3 ns	1.016 V	NO	Claude said NO — user not asked
0023	20260417_085336	dat	342.4 ns	347.7 ns	1.016 V	NO	Claude said NO — user not asked
0029	20260417_085602	dat	342.6 ns	347.8 ns	1.015 V	NO	Claude said NO — user not asked
0033	20260417_085742	dat	342.5 ns	347.5 ns	1.016 V	NO	Claude said NO — user not asked
0079	20260417_091529	dat	12.2 ns	0.6 ns	1.015 V	YES	✓ FALSE ALARM
0082	20260417_091657	dat	6.8 ns	0.0 ns	1.016 V	YES	✓ FALSE ALARM
0085	20260417_091825	dat	342.5 ns	347.8 ns	1.016 V	NO	Claude said NO — user not asked

Claude Assessments

Capture 0079 [20260417_091529] — FALSE ALARM

YES

The LP-low plateau of 12.2 ns is far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, at only ~24% of the threshold. The LP exit-to-HS transition of just 0.6–1 ns confirms the LP-01/LP-00 preamble states were essentially skipped, giving the bridge no meaningful window to recognize the start-of-transmission. Despite the HS amplitude (116 mV) and LP-11 voltage (1.015 V) being within normal ranges—indicating the PHY is electrically healthy—the critically truncated LP-low plateau means the SN65DSI83 almost certainly missed this SoT entry, resulting in a lost or corrupted video frame and visible flicker.

Capture 0082 [20260417_091657] — FALSE ALARM

YES

The LP-low plateau of 6.8 ns is dramatically below the SN65DSI83's 50 ns minimum requirement for SoT detection — it is only ~14% of the needed duration. The LP exit-to-HS transition time of 0 ns further confirms that the LP-01/LP-00 preamble states were essentially absent or too brief to be resolved, meaning the bridge almost certainly missed the start-of-transmission. The slightly elevated HS amplitude of 131 mV (above the normal 105–122 mV range) suggests the transmitter may have entered HS mode abruptly without proper state progression, consistent with a truncated entry sequence that would cause the SN65DSI83 to lose frame sync and produce visible flicker.