MIPI D-PHY Analysis Report

Generated: 2026-04-15 10:06:53  |  Scope: Captures 0469–0498  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0469–0498

## 1. Executive Summary

The system is running with 'Round Best' PHY timing registers that violate D-PHY v1.1 in 5 fields. Every single capture (30/30) shows identical non-compliant register values. The SoT sequence is marginal: LP-low plateaux are bimodal (either ~343 ns or ~108 ns or 0 ns), and the three confirmed flicker events (0475, 0488, 0492) all have LP-low plateau = 0 ns — meaning the data lane SoT LP-01→LP-00 sequence is entirely absent. The root cause is the too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns min) combined with a too-short TCLK_PREPARE (37.0 ns vs 38.0 ns min), which leaves zero timing margin for the SN65DSI83 to detect the SoT. Switching to the 'Round Up' register set eliminates all 5 violations and should eliminate flicker.

## 2. Consistent Spec Concerns

### 2.1 Register Violations (100% of captures — STATIC, every capture identical)

| Field | Value | Actual | Spec Min | Deficit | Impact |
|-------|-------|--------|----------|---------|--------|
| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns | Insufficient HS→LP exit time; bridge may not recognise LP return |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns | Clock SoT prepare phase too short; clock lane PLL may not lock |
| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns | Clock trail too short; bridge may lose clock before data trail completes |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns | Clock lane SoT init sequence too short |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns | Critical: Data lane SoT sequence is 1.5 ns below spec |

The THS_PREPARE+THS_ZERO violation is the smoking gun. At 1.5 ns below spec, the SN65DSI83's internal SoT detector is right at its detection threshold. On most startups, the bridge barely catches it (State A). On ~10% of startups, PVT variation or supply noise pushes the effective timing below the bridge's internal detection window → SoT is missed → bridge never locks → permanent flicker (State B).

### 2.2 LP-11 Voltage

• All captures: 1.014–1.016 V (spec 1.0–1.45 V) ✓
• Consistent, no drift, but low in the spec range (56% of min). This is borderline — the LP-11 high level should be closer to VDDIO (1.8 V). The 1.015 V value suggests the LP drivers are sourcing through significant resistance (likely the 200 Ω series resistors in the LP path), or the bridge's LP termination is loading the line. This reduces noise margin for LP state detection.

### 2.3 HS Amplitude

• CLK lane: 163.7–166.6 mV differential — consistently within spec (140–270 mV) but low (only 18–19% above the 140 mV floor).
• DAT0 lane: 186.1–200.0 mV differential — healthier, ~33% above floor.
• Below-140 mV samples: Present in every capture (7–2052 samples). This indicates ISI/crosstalk dips during transitions. Not the flicker cause but reduces eye margin.

### 2.4 Clock Common Mode Offset

• All captures show +27 to +32 mV common mode on the CLK lane (spec is ±25 mV from VCM nom). This is marginal and indicates slight driver asymmetry on the clock P/N pair.

## 3. LP Timing Analysis — The Flicker Mechanism

### 3.1 LP-Low Plateau Distribution (30 captures)

| LP-low plateau | Count | LP exit→HS | Flicker? |
|----------------|-------|------------|----------|
| ~343 ns | 13 | ~348 ns | 0/13 (0%) |
| ~108 ns | 8 | 1–4 ns | 0/8 (0%) |
| 0 ns | 3 | 2–4 ns | 3/3 (100%) |
| Mixed (343 + valid exit) | 6 | 3–113 ns | 0/6 (0%) |

Key finding: The LP-low plateau has three discrete values — it is quantised, not continuously distributed. This proves the variation is digital (byte-clock quantisation in the DSIM PHY state machine), not analog (noise-induced). The LP→HS SoT sequence duration depends on exactly when the DSIM's internal state machine transitions, which has a ±1 byte-clock (±18.5 ns) jitter relative to the scope trigger.

### 3.2 Flicker Correlation

All three flicker captures share:
- LP-low plateau = 0 ns (SoT LP-01/LP-00 states completely absent)
- LP exit→HS = 1.8–3.6 ns (effectively instantaneous — no LP→HS transition)
- The data lane jumps directly from LP-11 to HS with no intervening LP-01→LP-00 sequence

This means the DSIM PHY is occasionally skipping the data lane SoT entry sequence entirely. The SN65DSI83 requires LP-11 → LP-01 → LP-00 → HS-0 to detect SoT (per D-PHY spec §5.7.1). When this sequence is absent, the bridge cannot synchronise to the HS data stream.

### 3.3 Root Cause Chain

1. THS_PREPARE+THS_ZERO = 166.7 ns (1.5 ns below 168.2 ns spec min)
2. The Samsung DSIM PHY implements this as 9 byte-clocks. Due to internal clock domain crossing between the LP and HS clock domains, the actual LP→HS transition can vary by ±1 byte-clock.
3. When the timing falls short by 1 byte-clock (−18.5 ns), the effective THS_PREPARE+THS_ZERO drops to ~148 ns — well below spec.
4. In the worst case, the LP-01/LP-00 states are so brief that they are entirely swallowed by the HS ramp-up, producing LP-low plateau = 0 ns.
5. The SN65DSI83 never sees the SoT → never enters HS receive mode → never locks → flicker forever.

## 4. Supply Rail Correlation

### 4.1 1.8 V Supply Statistics

| Metric | Min | Max | Mean | Spec |
|--------|-----|-----|------|------|
| Mean voltage | 1.7626 V | 1.7694 V | 1.7649 V | 1.71–1.89 V ✓ |
| Min voltage | 1.6920 V | 1.7360 V | — | 1.71 V min ✗ |
| Droop depth | 28.3 mV | 73.4 mV | 41.6 mV | — |
| Ripple RMS | 10.08 mV | 13.03 mV | 11.0 mV | — |

### 4.2 Sub-spec Supply Events

5 captures droop below 1.71 V: 0472 (1.696 V), 0478 (1.708 V), 0479 (1.700 V), 0489 (1.692 V), 0492 (1.696 V), 0497 (1.692 V).

### 4.3 Supply–Flicker Correlation

| Flicker capture | Min V | Droop | Flicker? |
|-----------------|-------|-------|----------|
| 0475 | 1.728 V | 34.6 mV | ✓ FLICKER |
| 0488 | 1.728 V | 37.8 mV | ✓ FLICKER |
| 0492 | 1.696 V | 69.1 mV | ✓ FLICKER |

Mixed correlation: Two of three flicker events (0475, 0488) have normal supply conditions (droop < 40 mV, above 1.71 V). Only 0492 has a significant droop. Conversely, several non-flicker captures (0472, 0479, 0489, 0497) have worse droops (65–73 mV) without flicker.

Conclusion: Supply droop is not the primary flicker cause. The flicker occurs even with clean supply. However, large droops (>60 mV) are a secondary concern:
- They reduce LP driver headroom (LP-11 is already at 1.015 V with 1.765 V supply; a 73 mV droop could momentarily reduce LP drive below 1.0 V threshold)
- They may exacerbate the DSIM PHY's internal timing uncertainty during the LP→HS transition

## 5. Warning/Error Explanation

| Warning | Count | Cause | Action |
|---------|-------|-------|--------|
| `sig/dat: No HS signal detected` | 3 captures | Scope triggered during LP or inter-frame gap; DAT0 was idle | Benign — scope timing artifact |
| `sig/dat: Only negative swings` | 22 captures | Capture window caught only one polarity of differential data | Benign — data pattern / trigger alignment |
| `CLK lane in continuous HS mode` | 30/30 | Expected: DSI clock runs continuously, no LP states on CLK | Normal operation |
| `LP exit duration < 50 ns` | 21/30 | THS_PREPARE is at the edge of spec — the LP→HS transition happens faster than the scope's LP-state detection algorithm can measure the discrete LP-01/LP-00 steps | The "LP exit" metric measures the time from first LP-11 departure to first HS activity; when THS_PREPARE+THS_ZERO is marginal, the LP-01→LP-00 duration is too short to resolve |
| `Supply below 1.71 V` | 6/30 | Transient droop during LP→HS current surge (4 lanes + clock transitioning simultaneously) | Add decoupling — see recommendations |
| `Settled samples below 140 mV` | 30/30 on CLK, most on DAT | ISI / transition dips in HS signalling | Low-margin but not root cause; trace impedance and termination review recommended |

## 6. Trend Analysis

### No Degradation Over Time
- HS amplitudes, jitter, rise times, LP-11 voltage, and supply mean are rock-stable across all 30 captures (captured over ~53 minutes).
- No thermal drift, no aging, no progressive degradation.
- The flicker events (0475, 0488, 0492) are randomly distributed in time, consistent with a stochastic digital timing race rather than an analog drift.

### Bimodal HS Amplitude on DAT0 (Single-Ended LP Capture)
- HS amplitude in LP captures alternates between ~108–120 mV and ~11–36 mV (single-ended p-p/2).
- The low values (11–36 mV) likely correspond to captures where the scope caught the HS-0 (LP-to-HS transition ramp) rather than settled HS data, or the DAT0 line is carrying a long run of identical symbols. This is a measurement artifact, not a signal quality issue.

## 7. Actionable Recommendations

### 7.1 CRITICAL — Switch to 'Round Up' Register Set (Software Fix)

Change the samsung-dsim driver to use the 'Round Up' timing calculation. This is the single most impactful fix and requires no hardware change.

```
PHYTIMING (0xb4): 0x00000305 → 0x00000306 (+1 bc on THS_EXIT)
PHYTIMING1 (0xb8): 0x020e0a03 → 0x030f0a04 (+1 bc on TCLK_PREPARE, +1 bc on TCLK_ZERO, +1 bc on TCLK_TRAIL)
PHYTIMING2 (0xbc): 0x00030605 → 0x00030706 (+1 bc on THS_ZERO, +1 bc on THS_TRAIL)
```

This eliminates all 5 D-PHY violations:
- THS_PREPARE+THS_ZERO: 166.7 → 185.2 ns (10% margin over 168.2 ns spec)
- TCLK_PREPARE: 37.0 → 55.6 ns (46% margin over 38 ns spec)
- TCLK_PREPARE+TCLK_ZERO: 296.3 → 333.3 ns (11% margin over 300 ns spec)
- THS_EXIT: 92.6 → 111.1 ns (11% margin over 100 ns spec)
- TCLK_TRAIL: 55.6 → 74.1 ns (23% margin over 60 ns spec)

Implementation: In the `samsung-dsim` (or `sec-dsim`) driver, the timing calculation function computes byte-clock counts from D-PHY formulas then applies either `round()` or `ceil()`. Change to `ceil()` for all timing parameters, or hard-code the 'Round Up' values via device tree overrides if available.

### 7.2 HIGH — Improve 1.8 V VDDIO Decoupling

• Add 1 µF + 100 nF MLCC as close as physically possible to the i.MX 8M Mini MIPI PHY VDDIO pins (balls).
• The 73 mV worst-case droop (4.1% of 1.8 V) with ~11 mV RMS ripple indicates the existing decoupling cannot handle the 4-lane simultaneous LP→HS current surge (~80 mA transient for 4 data + 1 clock lane).
• While not the primary flicker cause, sub-1.71 V excursions violate the VDDIO spec and reduce margins on all LP and HS thresholds.

### 7.3 MEDIUM — Investigate LP-11 Voltage

• LP-11 at 1.015 V with VDDIO = 1.765 V means 785 mV dropped across the LP output stage and series resistors. The D-PHY spec allows LP-11 down to 1.0 V, so this is technically compliant, but:
• The SN65DSI83 LP receiver thresholds are referenced to its own VDDIO, so the actual noise margin depends on the bridge's input threshold.
• Check that the 200 Ω LP series resistors (if present) are not excessively loading the LP output.
• Verify the bridge's LP termination resistance matches expectations.

### 7.4 LOW — HS Amplitude Margin

• CLK at 165 mV is only 18% above the 140 mV floor. While sufficient under nominal conditions, it leaves little margin for connector aging, temperature, or cable degradation.
• If the design uses a flex cable or connector between the SOM and the SN65DSI83, verify impedance matching (100 Ω differential) and minimise stub lengths.

## 8. Overall Signal Health & Flicker Risk

• The HS signal quality is adequate but low-margin

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