MIPI D-PHY Analysis Report

Generated: 2026-04-13 11:03:38  |  Scope: Captures 0303–0332  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0303–0332 (30 sessions)

## 1. Consistent Spec Concerns

### A. PHY Timing Registers — 5 D-PHY v1.1 Violations (ALL 30 captures, 100%)

Every single capture shows identical register values (`Round Best` mode), confirming the driver is not applying the `Round Up` corrections:

| Parameter | Programmed | Actual | Spec Min | Deficit |
|---|---|---|---|---|
| THS_EXIT | 5 bc → 92.6 ns | — | 100.0 ns | −7.4 ns |
| TCLK_PREPARE | 2 bc → 37.0 ns | — | 38.0 ns | −1.0 ns |
| TCLK_TRAIL | 3 bc → 55.6 ns | — | 60.0 ns | −4.4 ns |
| TCLK_PREPARE+TCLK_ZERO | 16 bc → 296.3 ns | — | 300.0 ns | −3.7 ns |
| THS_PREPARE+THS_ZERO | 9 bc → 166.7 ns | — | 168.2 ns | −1.5 ns |

These are not marginal — they are hard violations. The SN65DSI83 must detect the SoT sequence within D-PHY spec windows. When the PHY's TCLK_PREPARE is 1 ns short of the 38 ns floor and THS_PREPARE+THS_ZERO is 1.5 ns below the combined minimum, the bridge's internal state machine has almost no margin to recognize the HS entry.

### B. LP Exit Duration — Systematically Violated

| Metric | Good captures (5/30) | Typical captures (22/30) | Flicker capture 0312 |
|---|---|---|---|
| LP exit → HS | 348 ns ✓ | 1–4 ns ✗ | 0 ns ✗ |
| LP-low plateau | 342–343 ns | 108–343 ns | 0 ns ✗ |

• 26 of 30 captures (87%) show LP exit durations of 1–4 ns — far below the 50 ns D-PHY minimum. This means the LP-01 → LP-00 state sequence required by the SoT protocol is either absent or completed in under one oscilloscope sample.
• Only 5 captures (0305, 0316, 0326, 0328, 0329, 0332) show compliant 348 ns LP exit durations. These are the captures where the measurement resolved the full LP-01/LP-00 sequence.
• The fact that most "good" sessions also show ~2–4 ns LP exit suggests the measurement resolution may not always capture LP-01/LP-00 properly, but the flicker event (0312) shows LP-low = 0 ns, meaning the SoT sequence was genuinely absent or catastrophically compressed.

### C. HS Differential Amplitude — Clock Lane Marginal

• Clock lane Vdiff: 164.2–166.9 mV — nominally above the 140 mV floor but with 28–230 settled samples below 140 mV in every proto capture. The negative half-swing is consistently ~30 mV weaker than the positive half (typ. +194 mV / −137 mV), producing a +28 mV common-mode offset.
• Data lane Vdiff: 178–223 mV median — healthy, but up to 12,596 settled samples below 140 mV (capture 0326). This is ISI/transition-related undershoot.

### D. LP-11 Voltage — Consistent but Low

• LP-11 = 1.014–1.016 V across all captures. The D-PHY spec requires ≥ 1.0 V (for 1.2 V VDDIO) but at 1.8 V VDDIO the expected LP-high is ~1.2 V. The 1.015 V measured value is suspiciously low — only 15 mV above the absolute floor. This suggests either the LP driver pull-up impedance is too high, the 1.8 V rail is being divided down, or there is excessive loading on the LP lines (SN65DSI83 input + routing parasitics).

## 2. Trends Over 30 Captures

### No Drift Detected — The System is Stationary

| Parameter | Min | Max | σ | Trend |
|---|---|---|---|---|
| CLK Vdiff | 165.0 mV | 166.9 mV | < 0.5 mV | Flat |
| CLK jitter p-p | 147.3 ps | 171.8 ps | ~6 ps | Flat (noise) |
| CLK rise time | 164.3 ps | 166.0 ps | < 1 ps | Flat |
| CLK frequency | 213.4–219.2 MHz | — | ~1.5 MHz | Measurement window variance only |
| 1.8 V mean | 1.764–1.770 V | — | ~2 mV | Flat |
| 1.8 V droop | 8.1–16.1 mV | — | ~2 mV | Flat |
| LP-11 voltage | 1.014–1.016 V | — | < 1 mV | Flat |
| LP-11 duration | 1.73 µs | 1.73 µs | 0 | Constant |

Conclusion: This is not a degradation or drift problem. The failure mode is purely stochastic at the SoT moment — consistent with a timing-margin race condition.

## 3. Anomalies

### 🔴 CRITICAL — Capture 0312: Confirmed Flicker Event
- LP-low plateau = 0 ns — the SoT LP-01 → LP-00 sequence was entirely absent
- LP exit → HS = 0 ns — the data lane jumped directly from LP-11 to HS with no intermediate states
- HS single-ended amplitude = 32 mV (vs ~108 mV typical) — the bridge never locked to HS, so HS data was essentially absent/garbage on that first burst
- LP-11 voltage = 1.016 V — marginally *higher* than average (not lower), ruling out supply droop as the trigger
- 1.8 V supply: mean 1.769 V, droop 9.1 mV — actually *better* than average, ruling out supply sag

Root cause of this specific event: The PHY transitioned from LP-11 directly to HS without executing the LP-01 → LP-00 SoT sequence. The SN65DSI83 never saw SoT, never entered HS receive mode, and remained stuck. This is a PHY state machine race condition exacerbated by the 5 timing violations.

### 🟡 Capture 0307: DAT0 Proto Shows 0 mV
- Data lane proto amplitude = 0.0 mV — "No HS signal detected"
- This is likely a trigger/capture timing issue where the proto window landed during an LP or blanking period, not a genuine signal absence (sig capture shows 193.7 mV, LP shows valid HS burst). Not a flicker event but a measurement artifact.

### 🟡 Recurring: "Only negative swings in capture window"
- 27 of 30 dat sig captures show only negative swings. This is a probe/trigger alignment artifact — the high-res window consistently lands on the same phase of the data pattern. The amplitude is still correctly measured from the negative excursion. Not a signal integrity concern.

### 🟡 LP-low Plateau Bimodal Distribution
- ~342–343 ns (majority): Full LP-00 plateau resolved
- ~108 ns (captures 0307, 0313, 0314, 0325, 0330): Shortened — possibly the measurement caught LP-01 but missed part of LP-00, or the PHY genuinely shortened the low period
- 0 ns (capture 0312): Complete SoT failure → flicker

This 342 → 108 → 0 ns distribution suggests the SoT LP-low duration has significant jitter — it's not always 342 ns. The 108 ns captures may represent borderline events where the bridge barely locked.

## 4. Supply Correlation Analysis

| Capture | LP-low (ns) | LP exit (ns) | Flicker? | 1.8V Mean (V) | Droop (mV) | Ripple RMS (mV) |
|---|---|---|---|---|---|---|
| 0312 (flicker) | 0 | 0 | YES | 1.7691 | 9.1 | 5.46 |
| 0305 (good LP) | 343 | 348 | no | 1.7658 | 13.8 | 5.86 |
| 0316 (good LP) | 343 | 348 | no | 1.7641 | 16.1 | 5.84 |
| 0322 (bad LP) | 343 | 4 | no | 1.7641 | 16.1 | 5.73 |

No correlation between supply droop/ripple and SoT failures. The flicker capture (0312) had the best supply conditions in the batch (highest mean, lowest droop). Captures with the highest droop (16.1 mV in 0316, 0322) showed no flicker.

The 1.8 V supply is not the root cause. The supply is healthy at 1.764–1.770 V with < 17 mV droop — well within the 1.71–1.89 V spec.

## 5. Warning/Error Explanation

| Warning | Frequency | Likely Cause | Action |
|---|---|---|---|
| "LP exit duration N ns below spec min 50 ns" | 25/30 (83%) | PHY timing registers underprogram THS_PREPARE+THS_ZERO and TCLK_PREPARE — the SoT sequence is too fast for the scope (and bridge) to resolve individual LP-01/LP-00 states | Switch to `Round Up` registers |
| "CLK lane in continuous HS mode" | 30/30 (100%) | Expected — DSI video mode drives CLK continuously; LP-11/SoT only occurs on data lanes | No action needed |
| "Only negative swings in capture window" | 27/30 (90%) | High-res sig window triggers on consistent data phase; asymmetric capture | Consider random trigger offset; not a signal problem |
| "N settled samples below 140 mV" | 30/30 (100%) | ISI/transition undershoot during bit transitions; clock lane asymmetric swing | Monitor; acceptable if median is above 140 mV |
| "No HS signal detected" (0307 proto/dat) | 1/30 (3%) | Proto window landed during blanking/LP interval | Retrigger or extend window; measurement artifact |
| "FLICKER SUSPECT: LP-low plateau absent" (0312) | 1/30 (3%) | Genuine SoT failure — PHY skipped LP-01/LP-00 | Root cause of flicker; fix registers |

## 6. Actionable Recommendations

### 🔴 IMMEDIATE — Switch to 'Round Up' PHY Timing (Primary Fix)

Patch the samsung-dsim / sec-dsim driver to program `Round Up` values:

```
DSIM_PHYTIMING (0xb4): 0x00000306 → THS_EXIT=6 (111.1 ns ✓)
DSIM_PHYTIMING1 (0xb8): 0x030f0a04 → TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4
DSIM_PHYTIMING2 (0xbc): 0x00030706 → THS_ZERO=7, THS_TRAIL=6
```

This eliminates all 5 D-PHY violations. Specifically:
- TCLK_PREPARE 37→55.6 ns: +18.6 ns margin above 38 ns floor
- THS_PREPARE+THS_ZERO 166.7→185.2 ns: +17 ns margin above 168.2 ns floor
- TCLK_PREPARE+TCLK_ZERO 296.3→333.3 ns: +33 ns margin above 300 ns floor
- THS_EXIT 92.6→111.1 ns: +11 ns margin above 100 ns floor
- TCLK_TRAIL 55.6→74.1 ns: +14 ns margin above 60 ns floor

The extra byte-clock per parameter costs ~18.5 ns of SoT overhead per frame entry — negligible at 60 Hz.

Implementation: In the driver's `samsung_dsim_set_phy_timing()` or equivalent, change the rounding mode from truncation to ceiling for all timing parameters. Alternatively, apply direct register overrides via device-tree `phy-timing` properties if supported.

### 🟡 SECONDARY — Investigate LP-11 Voltage (1.015 V)

At 1.8 V VDDIO, LP-high should be ~1.2 V (VDDIO × 0.67 typ). The measured 1.015 V is 15% low. Check:
1. Series resistance in LP path (PCB trace, protection resistors, ESD diodes)
2. SN65DSI83 LP input current loading — the DSI83 LP-mode input impedance may be lower than expected
3. VDDIO actual voltage at the PHY pad (not just at the regulator) — 1.766 V at the regulator minus PCB IR drop

While 1.015 V is technically compliant, it leaves zero margin and may contribute to the bridge's inability to cleanly detect LP state transitions.

### 🟢 OPTIONAL — Clock Lane Amplitude Asymmetry

The consistent +194/−137 mV asymmetry (28 mV common-mode offset) on CLK suggests a slight impedance mismatch between CLK+ and CLK−. Check:
1. Differential pair trace length matching (< 5 mil skew)
2. AC coupling capacitors (if present) for value tolerance
3. SN65DSI83 CLK input termination

This is not causing flicker but degrades noise margin.

## 7. Summary

The system is running with 5 D-PHY v1.1 timing violations caused by the `Round Best` register programming mode, which truncates timing parameters to the nearest byte-clock below spec minimums. The most critical violations — THS_PREPARE+THS_ZERO (1.5 ns short) and TCLK_PREPARE (1.0 ns short) — compress the SoT handshake window to the point where the SN65DSI83 bridge's SoT detector has essentially zero margin. On ~3% of pipeline startups, the PHY's SoT state machine races past LP-01/LP-00 so quickly (or skips them entirely, as in capture 0312) that the bridge fails to enter HS receive mode, producing permanent flicker for that session.

Switching to the `Round Up` register values (PHYTIMING=0x306, PHYTIMING1=0x030f0a04, PHYTIMING2=0x00030706) will eliminate all 5 violations with comfortable margin and is expected to resolve the intermittent flicker completely. The 1.8 V supply is healthy and not a contributing factor. No hardware changes are required — this is a software-only fix in the DSIM PHY timing configuration.

Tokens: 45578 in / 4027 out