MIPI D-PHY Analysis Report

Generated: 2026-04-13 09:59:11  |  Scope: Captures 0137–0166  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166

## 1. Consistent Spec Concerns

### Register Timing Violations (100% of captures — systemic)
Every single capture shows the 'Round Best' register set with identical 5 D-PHY v1.1 violations:

| Parameter | Programmed | Actual | Spec Min | Shortfall |
|-----------|-----------|--------|----------|-----------|
| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns |
| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns |

Critical insight: The THS_PREPARE+THS_ZERO violation (1.5 ns short) directly controls the data-lane SoT sequence. This is the interval during which the receiver must detect the HS-0 state and synchronise to the incoming data. Being 1.5 ns short means the SN65DSI83 has ~1% less time to complete bit-sync. Combined with the TCLK_PREPARE+TCLK_ZERO shortfall (3.7 ns), the clock lane's HS entry is also marginal — the receiver may not have a stable clock reference when data arrives.

### LP Exit Duration (Pervasive)
24 of 29 captures with LP data report LP exit → HS durations of 0–4 ns (spec ≥ 50 ns). This is not a measurement artefact — it reflects the PHY skipping or severely truncating the LP-01 → LP-00 states on the data lane. The programmed THS_PREPARE+THS_ZERO budget is too short to guarantee the LP-00 state is held long enough for the bridge's LP receiver to register it.

Only 5 captures show compliant LP exit (108–348 ns): 0137, 0139, 0148, 0159, 0166.

### LP-11 Voltage
LP-11 voltage is consistently 1.013–1.016 V across all captures (spec 1.0–1.45 V). This is at the absolute floor of the D-PHY spec (VOH ≥ VIH_LP = ~1.0 V). The 1.8 V VDDIO is ~1.765 V (2% below nominal) and the LP drivers are delivering only 56% of VDDIO. This leaves no noise margin — any additional drop could cause LP-11 to be misread.

### HS Amplitude
- CLK lane: Stable at 165–167 mV differential — passes spec (140–270 mV) but with only ~26 mV margin above the 140 mV floor.
- DAT0 lane: 186–224 mV nominal, but persistent sub-140 mV samples in every capture (16 to 9742 samples). This indicates ISI-induced eye closure during data transitions.
- CLK common mode offset: Consistently +28–31 mV (positive skew), indicating slight impedance imbalance on CLK±.

### Single-Ended HS Amplitude (LP capture)
Bimodal: captures show either ~106–118 mV or ~16–32 mV single-ended HS amplitude. The low-amplitude group likely represents captures where the scope triggered on a blanking interval or the data lane was in LP-idle between video lines.

## 2. Trends Over Captures

| Parameter | Range | Trend |
|-----------|-------|-------|
| CLK Vdiff | 165.6–166.8 mV | Rock stable — no drift |
| DAT0 Vdiff | 186.5–223.6 mV | Occasional jumps (0140, 0153, 0161 show ~224 mV) — likely different data patterns |
| CLK jitter p-p | 141.7–177.4 ps | No trend — random variation |
| CLK jitter RMS | 52.2–56.6 ps | Stable |
| LP-11 voltage | 1.013–1.016 V | No drift — thermally stable |
| 1.8 V mean | 1.7644–1.7705 V | Stable |
| 1.8 V droop | 8.4–17.4 mV | No trend, occasional spikes (0137: 13.3, 0144: 17.4, 0154: 13.7, 0163: 13.6, 0165: 13.7) |
| LP-low plateau | 0–343 ns | Trimodal: 0 ns, ~108 ns, ~343 ns |
| DAT0 sub-140mV count | 16–9742 | High variance; spikes in 0141 (3347), 0143 (6189), 0151 (3815), 0166 (9742) |

No progressive degradation. The system is thermally and electrically stable during a session. The variation is entirely in the SoT-moment behaviour, consistent with the bistable flicker description.

## 3. Anomalies

### FLICKER EVENT — Capture 0164
- LP-low plateau = 0 ns — the LP-01/LP-00 SoT states are completely absent
- LP exit → HS = 2 ns (spec ≥ 50 ns)
- LP-11 voltage = 1.015 V (normal)
- 1.8 V supply: mean 1.7665 V, droop 10.5 mV, ripple 6.01 mV — nothing abnormal
- Register values: identical 'Round Best' violations as all other captures

This confirms the root cause is timing, not supply: the SN65DSI83 never saw the LP-00 state, so it could not detect SoT and never locked to the HS data stream.

### DAT0 sig Capture Anomalies
- 0138, 0146, 0152, 0154, 0158, 0165: sig/dat shows 0.0 mV — "No HS signal detected." These captures caught the data lane during an LP-idle or blanking gap. This is a trigger timing issue, not a signal problem.
- 0141 sig/dat: 324.8 mV differential — exceeds spec max 270 mV. This is likely an overshoot/ringing event captured during a transition. The CLK lane in the same capture is normal (166.8 mV), confirming the data lane has a reflection or impedance discontinuity that occasionally produces overshoot.

### DAT0 "Only Negative Swings"
Nearly every sig/dat capture shows only negative Vdiff with zero positive swing. This means the scope capture window consistently catches the same bit pattern (likely repeated zeros or sync bytes). The amplitude is likely underestimated by ~2×; true differential amplitude is probably ~390 mV, well within spec. However, the capture methodology should be verified — the sig trigger may need adjustment to catch both polarities.

### LP-Low Plateau Trimodal Distribution
| LP-low (ns) | Captures | Interpretation |
|-------------|----------|----------------|
| 0 | 0164 (flicker) | SoT completely missing — bridge fails to lock |
| ~108 | 0139, 0143, 0148, 0155, 0159 | Marginal — ~2 TLPX, borderline for SN65DSI83 |
| ~343 | All others | ~6 TLPX — this is the "normal" case |

The ~108 ns group didn't flicker in this batch but represents a secondary risk tier. The quantisation into three discrete values suggests the PHY state machine has a timing race: it either completes the full LP-01→LP-00 sequence (~343 ns), partially completes it (~108 ns), or skips it entirely (0 ns / flicker).

### Capture 0145 — LP Data Processing Error
`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP capture buffer was exactly full, causing an off-by-one indexing error in post-processing. No LP data for this capture. This is a script bug, not a signal issue.

## 4. Supply Correlation Analysis

| Metric | Flicker Capture (0164) | Non-Flicker Mean (n=28) | Correlation |
|--------|----------------------|------------------------|-------------|
| 1.8 V mean | 1.7665 V | 1.7658 V | None |
| 1.8 V min | 1.7560 V | 1.7556 V | None |
| Droop depth | 10.5 mV | 10.6 mV | None |
| Ripple RMS | 6.01 mV | 5.76 mV | None |

No supply correlation whatsoever. The 1.8 V rail is well within spec (1.71–1.89 V) in all captures, droop is modest (< 18 mV), and the flicker capture has completely average supply behaviour. The LP-11 voltage at 1.015 V in the flicker capture is indistinguishable from non-flicker captures. Supply is definitively ruled out as a contributing factor.

## 5. WARNING/ERROR Explanation

| Warning | Cause | Action |
|---------|-------|--------|
| "CLK lane is in continuous HS mode — LP states not expected on CLK" | Normal — DSIM runs CLK in continuous HS mode per SN65DSI83 requirement | None needed |
| "LP exit duration N ns below spec min 50 ns" | THS_PREPARE+THS_ZERO too short (166.7 ns vs 168.2 ns spec); PHY truncates LP-00 state non-deterministically | Switch to 'Round Up' registers |
| "Only negative swings in capture window" | Repetitive bit pattern in short sig capture window | Widen sig capture window or trigger on random data |
| "No HS signal detected — line may be in LP state or idle" | Trigger caught blanking interval | Add trigger holdoff or qualify trigger on active video |
| "N settled samples below 140 mV" | ISI eye closure during transitions; amplitude near spec floor | Normal for 432 Mbit/s with this trace geometry |
| "Vdiff 325 mV above spec max 270 mV" (0141) | Impedance mismatch causing overshoot on data lane | Check DAT0± trace impedance, termination, via stubs |
| "index 200000 out of bounds" (0145) | Off-by-one bug in LP analysis script | Fix: use `< len(array)` not `<= len(array)` |

## 6. Actionable Recommendations

### PRIMARY FIX (Critical — eliminates root cause)
Switch from 'Round Best' to 'Round Up' PHY timing registers:

```
# In device tree or driver override:
DSIM_PHYTIMING (0xb4) = 0x00000306 # THS_EXIT=6 → 111.1 ns ✓
DSIM_PHYTIMING1 (0xb8) = 0x030f0a04 # TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4 ✓
DSIM_PHYTIMING2 (0xbc) = 0x00030706 # THS_ZERO=7, THS_TRAIL=6 ✓
```

This eliminates all 5 D-PHY violations. The key change is THS_PREPARE+THS_ZERO = 10 bc (185.2 ns) vs the current 9 bc (166.7 ns) — an extra 18.5 ns for the bridge to detect LP-00 and synchronise. This directly addresses the non-deterministic SoT failure.

Implementation path: In the `samsung-dsim` driver (`drivers/gpu/drm/bridge/samsung-dsim.c`), the timing calculation function `samsung_dsim_set_phy_ctrl()` uses a rounding mode. The default rounds to the nearest byte-clock ('Round Best'). Override this to always round up:
- Patch the driver to use `DIV_ROUND_UP` instead of `DIV_ROUND_CLOSEST` for all timing parameters, OR
- Apply the register values directly via device tree `phy-timing` properties if supported by your BSP.

### SECONDARY (Recommended — improves margin)
1. Investigate LP-11 voltage: 1.015 V is technically compliant but dangerously low. Check if the VDDIO_MIPI domain has a series resistance or if LP pull-ups are undersized. The SN65DSI83 datasheet specifies VIH_LP ≥ 1.0 V, so 1.015 V gives only 15 mV of noise margin. If possible, ensure VDDIO is at 1.80 V nominal (currently 1.766 V — check LDO/DCDC output voltage setting and load regulation).

1. Investigate DAT0 impedance: The 324.8 mV overshoot in Capture 0141 and the consistent CLK common-mode offset (+29 mV) suggest minor impedance discontinuities. Review:
2. DAT0± trace impedance (target 100Ω differential)
3. Via stubs at connector transitions
4. SN65DSI83 input termination (internal 100Ω)

1. Increase CLK amplitude margin: CLK Vdiff at 166 mV with sub-140 mV samples means the eye is marginal. If the i.MX 8M Mini DPHY allows TX emphasis or amplitude adjustment (DSIM_PLLCTRL or analog trim registers), increase CLK drive strength by one step.

### TERTIARY (Measurement improvement)
4. Fix the LP analysis script off-by-one error (Capture 0145).
5. Adjust sig/dat trigger to capture both positive and negative differential swings for accurate amplitude measurement.
6. Consider a longer proto capture window to reduce the variability in sub-140 mV sample counts.

## 7. Summary

The system is running non-compliant D-PHY timing ('Round Best' mode) with 5 spec violations that create a narrow, non-deterministic SoT failure window. The flicker event (Capture 0164, LP-low = 0 ns) is a direct consequence: the programmed THS_PREPARE+THS_ZERO is 1.5 ns short of spec, causing the LP-00 state to be occasionally skipped entirely, which prevents the SN65DSI83 from detecting Start-of-Transmission and locking to HS data. Supply rail, temperature, and HS signal quality are all stable and uncorrelated with the failure.

Switching to the 'Round Up' register set (0x00000306 / 0x030f0a04 / 0x00030706) will make all timing parameters D-PHY v1.1 compliant and is expected to eliminate the intermittent flicker. This is a software-only change with no hardware modification required. The 3% flicker rate at current timing margins should drop to 0% with the added ~18.5 ns of THS_ZERO headroom.

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