MIPI D-PHY Analysis Report

Generated: 2026-04-09 15:49:15  |  Scope: Captures 0635–0664  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0635–0664

## 1. Register Mismatch: The Primary Root Cause

### Actual vs. Target Register Values

| Register | Target | Actual (all captures) | Impact |
|---|---|---|---|
| PHYTIMING (0xb4) | `0x00000306` | `0x00000305` | THS_EXIT=5 → 92.6 ns (spec ≥100 ns) ✗ |
| PHYTIMING1 (0xb8) | `0x03110A04` | `0x020e0a03` | TCLK_PREPARE=2 → 37 ns (spec 38–95 ns) ✗, TCLK_ZERO=14 → 259 ns (spec ≥300 ns) ✗, TCLK_TRAIL=3 → 55.6 ns (spec ≥60 ns) ✗ |
| PHYTIMING2 (0xbc) | `0x00040A03` | `0x00030605` | THS_PREPARE=5 → 92.6 ns (spec 40+4×UI = 49.3–99.3 ns) ✓ but high, THS_ZERO=6 → 111 ns (spec ≥145+10×UI = 168.1 ns) ✗, THS_TRAIL=3 → 55.6 ns (spec max(8×UI, 60ns+4×UI) = 69.3 ns) ✗ |

Every single capture shows the wrong register values. The driver is not applying the target timing. This is the systematic root cause of all LP/SoT violations.

### Critical Decoded Field Comparison

| Field | Target (byte-clk) | Actual (byte-clk) | Target (ns) | Actual (ns) | Spec Min (ns) | Verdict |
|---|---|---|---|---|---|---|
| TLPX | 3 | 3 | 55.6 | 55.6 | 50 | ✓ |
| THS_EXIT | 6 | 5 | 111 | 92.6 | 100 | ✗ FAIL |
| TCLK_PREPARE | 3 | 2 | 55.6 | 37.0 | 38 | ✗ FAIL |
| TCLK_ZERO | 17 | 14 | 315 | 259 | 300 | ✗ FAIL |
| TCLK_POST | 10 | 10 | 185 | 185 | 180 | ✓ (marginal) |
| TCLK_TRAIL | 4 | 3 | 74 | 55.6 | 60 | ✗ FAIL |
| THS_PREPARE | 3 | 5 | 55.6 | 92.6 | 49.3 | ✓ (but over-programmed) |
| THS_ZERO | 10 | 6 | 185 | 111 | 168.1 | ✗ FAIL |
| THS_TRAIL | 4 | 3 | 55.6 | 55.6 | 69.3 | ✗ FAIL |

Six of nine timing parameters violate the MIPI D-PHY v1.1 specification. The registers are static across all 30 captures — the driver is consistently programming wrong values, likely because the samsung-dsim driver is computing timings from a formula rather than using the device-tree overrides you intended.

## 2. LP→HS SoT Analysis: Two Distinct Populations

### LP-Low Plateau Distribution

| LP-low plateau | Count | LP exit→HS | HS amplitude (SE) | Interpretation |
|---|---|---|---|---|
| ~343 ns | 11 captures | 2–348 ns | 17–122 mV | Normal SoT — LP-01→LP-00 sequence present |
| ~108 ns | 13 captures | 0–113 ns | 20–42 mV | Truncated SoT — LP states compressed |
| 1 ns | 1 capture (0646) | 0 ns | 122 mV | SoT absent — FLICKER |
| Not detected | 3 captures (0636, 0652, 0660) | — | — | Trigger/capture missed transition entirely |

Key observation: There is a clear bimodal distribution — ~343 ns vs ~108 ns. The flicker capture (0646) represents the extreme tail where the LP-low state is essentially absent (1 ns). This is a race condition, not a supply problem.

### Correlation with HS Amplitude

The 108 ns group consistently shows very low HS amplitude (20–42 mV single-ended, i.e. ~40–84 mV differential) during the first HS burst, well below the 140 mV minimum. This suggests:
- The 108 ns captures are catching DAT0 during or near a blanking interval where the line is in LP-idle or low-power, and the scope sees only the HS ramp-up/ramp-down transient.
- The 343 ns captures with high HS amplitude (106–122 mV SE ≈ 212–244 mV differential) are capturing active video data.

The difference between the two populations is which exact byte-clock edge the SoT lands on relative to the PHY state machine — this is the non-deterministic element.

## 3. Why Capture 0646 Flickered

Capture 0646 is the extreme case of the 108 ns population pushed to its limit:
- LP-low plateau: 1 ns — essentially zero. The LP-01→LP-00 SoT entry states are completely absent.
- LP exit→HS: 0 ns — the data lane jumps directly from LP-11 to HS differential signalling.
- HS amplitude: 122 mV SE (244 mV diff) — strong signal, so the PHY *did* enter HS mode.
- 14,588 proto/dat samples below 140 mV — massively elevated, confirming the bridge saw corrupted/unsynchronized HS data.

The SN65DSI83 requires a valid LP-11 → LP-01 → LP-00 → HS-0 entry sequence (per MIPI D-PHY spec, Section 5.1). When this sequence is absent:
1. The bridge's clock-data training fails.
2. It cannot lock onto the HS byte boundary.
3. All subsequent video data is interpreted as garbage.
4. The bridge stays stuck in this state for the entire session because the CLK lane is in continuous HS mode (never returns to LP to re-attempt SoT).

### Why it's non-deterministic

The too-short THS_ZERO (111 ns actual vs 168 ns required) and THS_PREPARE (already at the high end) create a window where the combined THS_PREPARE+THS_ZERO duration (204 ns actual vs 217 ns minimum) is violated. The PHY state machine exit from LP depends on:
1. Phase alignment between the byte clock and the LP state counter
2. PLL lock timing at startup
3. Internal flip-flop metastability in the LP-to-HS crossover logic

With only ~204 ns total vs ~217 ns required, the margin is negative 13 ns. Most of the time the PHY "gets away with it" because internal delays pad the timing. Occasionally (3% of startups), the timing lands in the metastable window and the LP-01/LP-00 states are completely skipped.

## 4. Supply Correlation Assessment

| Parameter | Range across all captures | Correlation with flicker? |
|---|---|---|
| Mean 1.8 V | 1.7633–1.7688 V | No — all within spec, no trend |
| Min voltage | 1.7480–1.7600 V | No — 0646 min=1.7520 V, identical to non-flicker captures |
| Droop depth | 7.6–16.1 mV | No — 0646 droop=11.6 mV, median of the distribution |
| Ripple RMS | 4.99–5.95 mV | No — 0646 ripple=5.45 mV, average |

Conclusion: The 1.8 V supply is NOT the cause. Droop and ripple show no correlation with LP timing violations or flicker events. The supply is stable and well within spec. The LP-11 voltage (1.012–1.016 V) is at the very bottom of the 1.0–1.45 V spec window — consistent with a 1.8 V rail that's 2% low — but this is not causing the SoT failure.

## 5. Explanation of Warnings and Errors

| Warning/Error | Count | Likely Cause | Action |
|---|---|---|---|
| LP exit duration 0–4 ns below 50 ns | 23/27 LP captures | THS_ZERO and TCLK_ZERO under-programmed — LP-01/LP-00 states are too brief for the scope to resolve at its sample rate, or the PHY genuinely skips them | Fix registers (primary action) |
| CLK lane in continuous HS mode | All captures | Expected — samsung-dsim runs CLK in continuous HS for video mode panels. Not an error. | Informational only |
| Only negative swings in capture window | ~20 captures | Scope triggered on a specific data pattern; differential probe captured only one polarity of HS transitions in the narrow sig window. Common for short bursts. | Not a hardware issue — capture artifact |
| No HS signal on dat (sig) | 3 captures (0636, 0641, 0648) | Sig capture window missed the HS burst — timing jitter in trigger vs data phase | Not a hardware issue |
| index 200000 out of bounds | 2 captures (0636, 0652) | LP capture buffer exactly full — trigger timing placed the SoT at the buffer boundary | Increase capture depth or adjust trigger position |
| Samples below 140 mV (proto/dat) | All captures | ISI and transition regions in HS data naturally dip below 140 mV. The 10,000+ counts in captures 0646, 0647, 0652, 0655 suggest data-dependent jitter or pattern sensitivity at these margins | Addressed by fixing THS_ZERO to give the receiver more setup time |
| LP-11 → LP-low → HS not detected (0660) | 1 capture | Trigger fired but no LP transition in the capture window — missed the SoT event entirely | Not a hardware issue — adjust trigger |
| Capture 0649: LP-11 duration 4.99 µs (vs 1.73 µs typical) | 1 capture | Longer LP-11 idle period before first SoT — likely a software timing variation in display pipeline startup | Informational — no impact |

## 6. Actionable Recommendations

### CRITICAL — Fix Immediately

1. Apply correct PHY timing registers.

The samsung-dsim driver is computing its own timings and ignoring your target values. You must force the correct values:

```
PHYTIMING (0xb4): 0x00000306 → TLPX=3, THS_EXIT=6
PHYTIMING1 (0xb8): 0x03110A04 → TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4
PHYTIMING2 (0xbc): 0x00040A03 → THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3
```

Options to force this:
- Option A (preferred): Patch the `samsung_dsim_set_phy_timing()` function in `drivers/gpu/drm/bridge/samsung-dsim.c` to use hardcoded values for your bit rate. The driver currently calculates timings using a formula that does not account for the minimum spec values at 432 Mbit/s.
- Option B: Add a post-init register write via `devmem2` or a custom script after `modprobe` — fragile but validates the fix.
- Option C: Modify the device tree `phy-timing` properties if your driver version supports them (check for `samsung,phy-timing` bindings).

2. Increase THS_ZERO further for margin.

Even the target value of 10 (185 ns) only gives 17 ns margin over the 168 ns minimum. Consider THS_ZERO=12 (222 ns) for robust margin against PVT variation:
```
PHYTIMING2 (0xbc): 0x00040C03 → THS_ZERO=12
```

3. Increase TCLK_ZERO for margin.

Target of 17 (315 ns) over 300 ns minimum gives only 15 ns margin. Consider TCLK_ZERO=19 (352 ns):
```
PHYTIMING1 (0xb8): 0x03130A04 → TCLK_ZERO=19
```

### IMPORTANT — Verify After Fix

4. Verify register values are applied.

After every pipeline load, read back registers with `memtool md -l 0x32e100b4+0x0c` and confirm they match target values. The current data proves they don't — 100% of 30 captures show wrong values.

5. Re-run the 30-cycle flicker test with correct registers and confirm:
- LP-low plateau consistently ≥200 ns
- LP exit→HS consistently ≥50 ns
- No bimodal distribution (should be a single population near ~340 ns)
- Zero flicker events

### MONITORING — Track These Metrics

6. The LP-11 voltage of 1.015 V is at the spec floor (1.0 V).

While not causing the flicker, this leaves zero margin. The LP-11 voltage is set by the VDDIO supply (1.765 V) and the PHY's internal LP driver, which divides VDDIO roughly in half plus series resistance. If VDDIO drifts lower (temperature, load transients), LP-11 could go below 1.0 V. Consider:
- Verifying VDDIO regulation target is exactly 1.8 V (currently 2% low at 1.764 V)
- Checking if the SOM has a VDDIO trim resistor that can be adjusted

7. The HS clock common mode offset of +13–15 mV is within spec (±25 mV) but consistently positive. This indicates a slight impedance mismatch on CLK+ vs CLK−. Check:
- Trace length matching between CLK+ and CLK− (target ≤2 mil difference)
- AC coupling capacitor tolerance matching

## 7. Summary

The intermittent flicker is caused by incorrect DSIM PHY timing register values. All 30 captures show `PHYTIMING1=0x020e0a03` and `PHYTIMING2=0x00030605` instead of the target values, resulting in six out of nine D-PHY timing parameters violating the MIPI spec. The most critical violations — THS_ZERO at 111 ns (spec ≥168 ns) and TCLK_ZERO at 259 ns (spec ≥300 ns) — create a negative timing margin that causes the LP→HS SoT entry sequence to be non-deterministically truncated or skipped entirely. When the SoT is completely absent (as in capture 0646, LP-low=1 ns), the SN65DSI83 cannot lock onto the HS data stream and the display flickers for the entire session.

The fix is straightforward: force the correct register values into the samsung-dsim driver. The supply rail, HS signal quality, and board-level signal integrity are all acceptable and are not contributing to the failure. Once correct timings are programmed, the 3% flicker rate should drop to zero.

Tokens: 33025 in / 4080 out