MIPI D-PHY Analysis Report

Generated: 2026-04-10 11:42:18  |  Scope: Captures 0138–0167  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0138–0167

## 1. CRITICAL FINDING: Register Mismatch Is the Root Cause

### Actual vs. Target Register Values

| Register | Target | Actual (all captures) | Impact |
|---|---|---|---|
| PHYTIMING (0xb4) | 0x00000306 | 0x00000305 | THS_EXIT=5 → 92.6 ns (spec ≥100 ns) ✗ VIOLATION |
| PHYTIMING1 (0xb8) | 0x03110A04 | 0x020e0a03 | TCLK_PREPARE=2 → 37 ns (spec 38–95 ns) ✗ VIOLATION; TCLK_ZERO=14 → 259 ns (spec ≥300 ns) ✗ VIOLATION; TCLK_TRAIL=3 → 55.6 ns (spec ≥60 ns) ✗ VIOLATION |
| PHYTIMING2 (0xbc) | 0x00040A03 | 0x00030605 | THS_PREPARE=5 → 92.6 ns (spec 40+4×UI=49 ns to 85+6×UI=99 ns) ✗ BORDERLINE/VIOLATION at 93 ns; THS_ZERO=6 → 111 ns (spec ≥ 145+10×UI=168 ns) ✗ VIOLATION; THS_TRAIL=3 → 55.6 ns (spec ≥ max(8×UI, 60+4×UI)=69.3 ns) ✗ VIOLATION |

Every single DSIM PHY timing register is wrong. The driver is not applying the target values. All 30 captures show the identical incorrect values, confirming this is a persistent configuration bug — not a transient failure.

### Decoded Timing Violations (actual register values)

| Parameter | Field Value | Actual Duration | D-PHY v1.1 Min | Status |
|---|---|---|---|---|
| TLPX | 3 | 55.6 ns | 50 ns | ✓ marginal |
| THS_EXIT | 5 | 92.6 ns | 100 ns | ✗ SHORT by 7.4 ns |
| TCLK_PREPARE | 2 | 37.0 ns | 38 ns | ✗ SHORT by 1 ns |
| TCLK_ZERO | 14 (0x0e) | 259 ns | 300 ns | ✗ SHORT by 41 ns |
| TCLK_POST | 10 (0x0a) | 185 ns | ~180 ns | ✓ barely |
| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | ✗ SHORT by 4.4 ns |
| THS_PREPARE | 5 | 92.6 ns | 49–99 ns | ✓ but high-side |
| THS_ZERO | 6 | 111 ns | 168 ns | ✗ SHORT by 57 ns |
| THS_TRAIL | 3 | 55.6 ns | 69.3 ns | ✗ SHORT by 13.7 ns |

Six of nine timing parameters violate D-PHY v1.1 spec. The most damaging are:

• THS_ZERO = 111 ns vs. 168 ns required: The data lane HS-Zero state is 34% too short. This is the interval where the receiver must detect the HS-0 level before the SoT (sync byte 0xB8). When it's too short, the SN65DSI83's CDR has insufficient time to lock before data arrives.
• TCLK_ZERO = 259 ns vs. 300 ns required: The clock lane HS-Zero is 14% too short, reducing the receiver's window to acquire clock lock.
• THS_EXIT = 92.6 ns vs. 100 ns required: Exit from HS back to LP is too fast for receivers to reliably detect the transition.

## 2. LP-Low Plateau Analysis: The Flicker Mechanism

### Distribution of LP-low plateau durations across all captures

| LP-low Plateau | Count | Flicker? | Captures |
|---|---|---|---|
| 0 ns (absent) | 4 | YES — all 4 | 0143, 0148, 0152, 0164 |
| ~108 ns | 4 | No | 0139, 0155, 0158, 0160, 0162 |
| ~342–348 ns | 20 | No | Remainder |
| Missing data | 1 | Unknown | 0141 (processing error) |

Perfect correlation: Every flicker event corresponds to LP-low plateau = 0 ns. Every non-flicker event has LP-low ≥ 108 ns. There are no exceptions.

The LP-low plateau represents the combined duration of the LP-01 → LP-00 sequence that constitutes the data lane SoT entry. When THS_ZERO is programmed at only 111 ns (vs. 168 ns required), the PHY's internal state machine has almost no timing margin. Under normal conditions, the silicon *happens* to produce a recognizable LP-00 state of ~342 ns — well above spec. But intermittently (~13% of startups), a race condition within the PHY causes the LP-01/LP-00 states to be completely swallowed, producing a direct LP-11 → HS transition with no detectable SoT sequence.

Why it's non-deterministic: The Samsung DSIM PHY's internal PLL lock time and lane synchronization have cycle-to-cycle jitter. With the programmed THS_ZERO 34% below spec, the internal sequencer's timing margin is negative. Most of the time the PLL locks fast enough that the sequencer still outputs the LP states; occasionally it doesn't, and the SoT is corrupted.

The "LP exit → HS" metric (1–4 ns across all captures, including non-flicker ones) confirms that the LP-01 state itself is never being held for the required TLPX ≥ 50 ns — even on "good" startups, the LP-01 pulse is undetectably brief. What saves non-flicker sessions is the ~342 ns LP-00 plateau, which gives the SN65DSI83 enough time to detect the HS entry. When even that disappears (flicker cases), the bridge never acquires sync.

## 3. HS Signal Quality

### Consistent observations across all 30 captures:

| Parameter | CLK | DAT0 | Assessment |
|---|---|---|---|
| Vdiff amplitude | 165.6–169.1 mV | 177–224 mV | Marginal-low on CLK (spec 140–270 mV, only 26 mV above floor) |
| Common mode | +26.6 to +32.0 mV | −98 to +5 mV | CLK offset ✓; DAT asymmetric |
| Rise time 20–80% | 163.6–165.4 ps | 143.8–219.4 ps | ✓ within spec |
| Jitter p-p | 145–177 ps | — | ✓ acceptable |
| Samples below 140 mV | 21–153 per capture | 18–7280 per capture | ✗ Persistent sub-spec excursions |

Clock amplitude is running at ~167 mV — only 19% above the 140 mV floor. This provides essentially no margin against supply droop, temperature variation, or aging. The persistent sub-140 mV samples on both clock and data indicate ISI/reflection-induced amplitude dips that regularly breach the minimum.

DAT0 asymmetry: Most sig/dat captures show only negative differential swings (Vdiff pos = 0.0 mV), indicating a probe/measurement artifact (likely single-ended measurement of one line only, or trigger position capturing only one data phase). However, proto/dat captures with both polarities show a consistent ~7–10 mV asymmetry between positive and negative swings, suggesting slight impedance mismatch or common-mode offset on the data lane.

## 4. 1.8 V Supply Rail Correlation

### Supply droop statistics:

| Droop Category | Count | Flicker events in category |
|---|---|---|
| < 30 mV (healthy) | 7 | 2 flicker (0143: 31 mV, 0148: 30.7 mV, 0164: 28.4 mV) |
| 30–50 mV (marginal) | 8 | 1 flicker (0152: 55.6 mV) |
| 50–68 mV (poor, some below 1.71 V) | 12 | 0 flicker |
| Below 1.71 V spec minimum | 5 | 0 flicker |

No correlation between supply droop and flicker. Three of four flicker events occurred at modest droop (<32 mV), while the deepest droops (66–68 mV, Vmin = 1.700 V) produced no flicker. This confirms the flicker is not supply-induced — it's a timing/sequencing issue.

However, the supply health is independently concerning:
- 5 captures dropped below the 1.71 V MIPI VDDIO minimum (0142: 1.700 V, 0147: 1.704 V, 0150: 1.700 V, 0151: 1.700 V, 0166: 1.708 V)
- Mean droop is ~43 mV; worst case is 67.7 mV
- This indicates insufficient bulk/MLCC decoupling near the MIPI PHY VDDIO pin

## 5. Warning/Error Explanations

| Warning | Cause | Action |
|---|---|---|
| "CLK lane is in continuous HS mode" | Normal for video-mode DSI — CLK runs continuously HS; no LP→HS expected on CLK | None needed |
| "Only negative swings in capture window" | sig/dat probe capturing during a single data symbol (long run of zeros/ones), or single-ended probe on one line only | Verify differential probe connection; not a device fault |
| "No HS signal detected" (sig/dat 0162, 0163; proto/dat 0155) | Trigger caught blanking interval (HFP/HBP) where DAT0 is in LP; CLK continues HS | Trigger refinement; not a device fault |
| "LP exit duration X ns below spec min 50 ns" | Register misconfiguration: THS_PREPARE (92.6 ns) is correct but the LP-01 state is too brief because the PHY sequencer races through it with the underspecified THS_ZERO | Fix registers |
| "index 200000 is out of bounds" (Capture 0141) | Buffer overrun in LP analysis script; the LP→HS edge was at or beyond the end of the capture window | Re-capture with wider window or earlier trigger |
| "Supply droops below 1.71 V" | Insufficient decoupling or trace resistance on VDDIO | Add MLCC capacitance |
| "Settled samples below 140 mV" | ISI/reflection causing Vdiff dips below 140 mV floor during HS toggling | Improve termination/routing; increase PHY drive strength if available |

## 6. Actionable Recommendations

### PRIORITY 1 — Fix PHY Timing Registers (ROOT CAUSE OF FLICKER)

The samsung-dsim (sec-dsim) driver is computing or writing incorrect values. Apply the target values via device-tree override or driver patch:

```
/* Device tree or driver patch */
DSIM_PHYTIMING = 0x00000306 /* TLPX=3, THS_EXIT=6 */
DSIM_PHYTIMING1 = 0x03110A04 /* TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4 */
DSIM_PHYTIMING2 = 0x00040A03 /* THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3 */
```

Specific fixes and expected impact:

| Field | Current → Target | Duration Change | Why It Matters |
|---|---|---|---|
| THS_ZERO | 6 → 10 | 111 → 185 ns | Gives receiver 74 ns more to detect HS-0 before sync byte. Primary flicker fix. |
| TCLK_ZERO | 14 → 17 | 259 → 315 ns | Allows proper clock CDR acquisition. Eliminates clock lock failures. |
| THS_EXIT | 5 → 6 | 92.6 → 111 ns | Meets 100 ns minimum. Prevents LP re-entry confusion. |
| TCLK_PREPARE | 2 → 3 | 37 → 55.6 ns | Meets 38 ns minimum with margin. |
| TCLK_TRAIL | 3 → 4 | 55.6 → 74 ns | Meets 60 ns minimum with margin. |
| THS_TRAIL | 3 → 4 | 55.6 → 74 ns | Meets 69.3 ns minimum with margin. |
| THS_PREPARE | 5 → 3 | 92.6 → 55.6 ns | Moves from 93 ns (borderline over 99 ns max) to comfortable mid-range. |

Verification: After applying, read back registers with `memtool md -l 0x32e100b4+0x0c` and confirm the target values. Run 100+ pipeline load/unload cycles to verify zero flicker.

Driver investigation: The samsung-dsim driver's `samsung_dsim_set_phy_timing()` function computes timing from the HS clock rate. At 432 Mbit/s the formula may be rounding down. Check:
- `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` in NXP BSP)
- The timing computation uses integer division that truncates; for low bitrates like 432 Mbps, every byte-clock unit matters
- Consider whether the NXP BSP has a known erratum or patch for this

### PRIORITY 2 — Improve 1.8 V VDDIO Decoupling

Although not correlated with flicker, the supply is out-of-spec:

1. Add 2×4.7 µF + 2×100 nF MLCC as close as possible to the MIPI PHY VDDIO pins on the SOM carrier board
2. Check VDDIO trace impedance — the 67 mV droop at LP→HS transition (4 lanes switching simultaneously) suggests >100 mΩ path resistance
3. Target: droop < 30 mV, Vmin > 1.71 V under all conditions

### PRIORITY 3 — Clock Amplitude Margin

CLK differential amplitude at ~167 mV is only 19% above the 140 mV minimum:

1. Check for excessive series resistance in AC coupling capacitors (use 0402 or 0201 with low ESR)
2. Verify 100 Ω differential termination at receiver (SN65DSI83 has internal, but external may be present and wrong value)
3. If the i.MX 8M Mini DPHY has programmable drive strength, increase by one step
4. Reduce trace length / improve impedance matching to eliminate the sub-140 mV ISI dips

### PRIORITY 4 — Add Software Retry as Belt-and-Suspenders

Even after fixing registers, add a startup verification loop:

```c
/* After DSI pipeline enable, read SN65DSI83 status register 0x0A */
/* Bit 0 = PLL lock. If not locked within 50ms, unload and reload pipeline */
for (retries = 0

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