MIPI D-PHY Analysis Report

Generated: 2026-04-15 14:26:26  |  Scope: Captures 1133–1162  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 1133–1162

## 1. Executive Summary

The system is running with 'Round Best' PHY timing registers that produce 5 D-PHY v1.1 spec violations on every single capture. The SoT sequence on the data lane is critically degraded: LP-low plateau is absent (0 ns) on all 4 confirmed flicker events, and the LP-11→HS exit time is universally 0–4 ns (spec ≥ 50 ns) across both good and bad sessions. The difference between State A (good) and State B (flicker) is whether the SN65DSI83 receiver happens to sample the truncated/missing LP-01→LP-00 SoT preamble in time — a race condition caused by timing fields programmed below D-PHY minimums.

## 2. Consistent Spec Concerns

### 2.1 Register Timing Violations (100% of captures)

Every single capture shows identical register values — the 'Round Best' mode is active throughout:

| Parameter | Programmed | Actual | D-PHY v1.1 Spec | Deficit |
|-----------|-----------|--------|-----------------|---------|
| THS_EXIT | 5 bc | 92.6 ns | ≥ 100.0 ns | −7.4 ns |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0–95.0 ns | −1.0 ns |
| TCLK_TRAIL | 3 bc | 55.6 ns | ≥ 60.0 ns | −4.4 ns |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | ≥ 300.0 ns | −3.7 ns |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | ≥ 168.2 ns | −1.5 ns |

The THS_PREPARE+THS_ZERO violation (−1.5 ns) is the smoking gun. This combined parameter defines the data-lane SoT sequence duration — specifically, how long the receiver sees the HS-zero state before the first valid data bit. At 166.7 ns vs. the 168.2 ns minimum, the SN65DSI83's LP-HS state machine has less than one UI (2.315 ns) of margin to recognise the SoT. Analog process/voltage/temperature variation inside the bridge's receiver comparators will occasionally cause it to miss the SoT entirely — exactly matching the observed bistable behaviour.

### 2.2 LP-11→HS Exit Timing (Universal Violation)

| Metric | Flicker captures (1133, 1149, 1151, 1152) | Non-flicker captures | Spec |
|--------|-------------------------------------------|---------------------|------|
| LP exit → HS | 2–3 ns | 0–4 ns (majority 2–4 ns) | ≥ 50 ns |
| LP-low plateau | 0 ns | 108–343 ns | ≥ TLPX (50 ns) |

Critical finding: The LP exit duration is below spec in every capture (flicker and non-flicker alike), typically 2–4 ns vs. the 50 ns minimum. This means the LP-11→LP-01→LP-00→HS-0 state machine is running too fast for the scope to resolve the intermediate states — the PHY is essentially slamming from LP-11 directly into HS with no discernible LP-00 dwell.

The differentiator for flicker is whether the LP-low plateau is detected at all:
- Flicker events (4/30): LP-low = 0 ns — the LP-00 state is completely absent
- Good sessions: LP-low = 108–343 ns — some LP-00 dwell is present, enough for the bridge

This is consistent with THS_PREPARE+THS_ZERO being 1.5 ns short: the PHY occasionally collapses the LP-00 state entirely when internal PLL/divider phase alignment happens to truncate it by that extra fraction of a byte clock.

### 2.3 LP-11 Voltage

LP-11 = 1.015–1.016 V across all captures. Spec range is 1.0–1.45 V (derived from VDDIO × 55%–80%). At VDDIO = 1.765 V, the expected LP-high range is 0.97–1.41 V, so 1.015 V is within spec but in the lower quartile. This is not the failure mechanism but offers minimal noise margin for LP-state detection at the receiver.

### 2.4 HS Amplitude

• CLK lane: 164.6–169.0 mV differential — consistently within spec (140–270 mV) but at the low end
• DAT lane: 177.8–199.2 mV differential — healthy
• Below-140 mV samples: Present on every capture (CLK: 18–106 samples; DAT: 7–3846 samples). These are transition-region excursions and ISI-related dips. The DAT lane shows significantly more sub-140 mV samples, indicating worse signal integrity on the data path (likely longer trace, worse impedance match, or coupling).

## 3. Trend Analysis Across 30 Captures

### 3.1 No Temporal Drift
- CLK amplitude: 166.0–166.5 mV — rock-steady, no degradation
- CLK frequency: 213.1–219.2 MHz — variation is capture-window aliasing, nominal 216 MHz
- Jitter: 140–167 ps p-p, 52.6–55.9 ps RMS — stable, within typical bounds
- Rise times: 139.9–174.1 ps (20–80%) — consistent
- 1.8 V supply: Mean 1.7635–1.7695 V, ripple RMS 5.14–5.94 mV — stable
- LP-11 voltage: 1.015–1.016 V — no drift

Conclusion: There is no progressive degradation. The failure mode is purely stochastic at each pipeline-load event.

### 3.2 LP-Low Plateau Distribution

| LP-low plateau (ns) | Count | Flicker? |
|---------------------|-------|----------|
| 0 | 4 | YES (all 4 flicker events) |
| 108 | 7 | No |
| 342–343 | 15 | No |
| N/A (capture error) | 1 (cap 1143) | Unknown |

The plateau quantises into three clusters (0, ~108, ~342 ns), suggesting the PHY's internal state machine aligns the LP-00 dwell to byte-clock boundaries. When the phase alignment is unfavourable, the dwell collapses to zero — the SoT preamble vanishes entirely.

## 4. Supply Correlation Analysis

### 4.1 Droop vs. Flicker

| Capture | Flicker? | LP-low (ns) | 1.8V droop (mV) | 1.8V min (V) |
|---------|----------|-------------|-----------------|--------------|
| 1133 | YES | 0 | 16.9 | 1.748 |
| 1134 | No | 342 | 9.7 | 1.756 |
| 1135 | No | 342 | 9.6 | 1.756 |
| 1149 | YES | 0 | 9.0 | 1.756 |
| 1151 | YES | 0 | 16.6 | 1.748 |
| 1152 | YES | 0 | 9.4 | 1.756 |
| 1157 | No | 343 | 13.2 | 1.752 |
| 1158 | No | 108 | 15.5 | 1.748 |

Mixed correlation. Captures 1133 and 1151 (flicker) show the deepest droops (16.9/16.6 mV, min 1.748 V), but captures 1149 and 1152 (also flicker) show normal droop (9.0/9.4 mV). Conversely, capture 1158 (no flicker) has 15.5 mV droop.

Conclusion: Supply droop is a contributing factor but not the primary cause. The deeper droops (to 1.748 V) reduce the LP driver swing and PHY PLL stability during the LP→HS transition, which further compresses the already-too-short SoT timing. However, flicker also occurs at normal supply levels, confirming the root cause is the register-level timing violation, not supply.

## 5. Anomaly & Warning Explanations

### 5.1 "Only negative swings in capture window" (≈60% of sig/dat captures)
Cause: The oscilloscope trigger captured a window aligned to a run of identical data bits (e.g., all-zero payload region). In DDR MIPI, a constant '0' pattern produces only negative differential swings. This is a capture-window artifact, not a signal defect. The amplitude from these captures (~194 mV) is consistent with full-swing measurements from balanced captures.

Action: No concern. Could refine trigger to capture more diverse bit patterns if balanced amplitude measurement is needed.

### 5.2 "No HS signal detected" on sig/dat (Captures 1136, 1141, 1144, 1147)
Cause: The high-resolution trigger on DAT0 captured a blanking interval or LP idle period between HS bursts. The DAT lane is in LP state during vertical blanking; the narrow capture window occasionally falls in this gap.

Action: No concern for signal health assessment — the proto captures from the same sessions confirm valid HS operation.

### 5.3 "CLK lane is in continuous HS mode" on lp/clk (all captures)
Cause: Expected behaviour. The Samsung DSIM PHY operates the clock lane in continuous HS mode (not non-continuous clock mode). The clock lane entered HS before the data lane's LP capture window and stays there. LP states on the clock lane are only visible during the very first pipeline startup, which occurs before the scope's trigger on data-lane LP activity.

Action: No concern. This is correct DSI Video Mode operation.

### 5.4 "[lp_dat] ERROR: index 200000 is out of bounds" (Capture 1143)
Cause: The LP analysis script's edge-detection algorithm attempted to access beyond the capture buffer boundary. Most likely, the LP→HS transition occurred at the very end of the capture window, and the algorithm's look-ahead overran. This is a software bug in the analysis tool, not a signal issue.

Action: Extend the capture window by 10% or add bounds checking in the LP analysis script. The LP data for this capture is not available for flicker analysis — it should be repeated.

### 5.5 DAT lane sub-140 mV sample counts vary wildly (7–3846)
Cause: Data-dependent ISI (inter-symbol interference). Long runs of alternating bits produce clean eye openings; long runs of same-bit produce DC-wander and pre-/post-cursor ISI that momentarily drops the differential swing below 140 mV. Captures with higher counts happened to contain more worst-case bit patterns.

Action: The maximum count (3846 in capture 1140) suggests the DAT lane's SI is marginal. Check trace impedance matching and consider adding 100 Ω differential termination at the SN65DSI83 input if not already present.

## 6. Actionable Recommendations

### 6.1 CRITICAL — Switch to 'Round Up' Register Values

This is the single most important fix. Apply the fully D-PHY v1.1 compliant timing:

```
# Write 'Round Up' values via memtool or device tree overlay:
DSIM_PHYTIMING (0x32e100b4) = 0x00000306 # THS_EXIT=6 → 111.1 ns ✓
DSIM_PHYTIMING1 (0x32e100b8) = 0x030f0a04 # TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4 ✓
DSIM_PHYTIMING2 (0x32e100bc) = 0x00030706 # THS_ZERO=7, THS_TRAIL=6 ✓
```

Specific impact on the failure mechanism:
- THS_PREPARE+THS_ZERO increases from 166.7 ns → 185.2 ns (+18.5 ns, 10% margin over spec)
- TCLK_PREPARE+TCLK_ZERO increases from 296.3 ns → 333.3 ns (+33 ns, 11% margin)
- THS_EXIT increases from 92.6 ns → 111.1 ns (11% margin)

This eliminates the race condition at SoT by giving the SN65DSI83 receiver substantially more time to detect the LP-00 state and synchronise to the HS preamble.

Implementation: In the samsung-dsim / sec-dsim driver, the timing calculation is done in `samsung_dsim_set_phy_timing()`. The 'Round Best' mode truncates fractional byte-clock results downward; switching to ceiling (round-up) ensures all timings meet or exceed spec minimums. This is typically a one-line change in the driver's rounding mode or can be forced via device tree properties if supported by the BSP.

### 6.2 HIGH — Verify the Fix Eliminates LP-Low Plateau Collapse

After applying Round Up registers, repeat the 30-cycle load/unload test and verify:
- LP-low plateau ≥ 50 ns on every capture
- LP exit → HS ≥ 50 ns on every capture
- Zero flicker events across ≥ 100 pipeline-load cycles

### 6.3 MEDIUM — Investigate LP-11 Voltage (1.015 V)

LP-11 at 1.015 V with VDDIO = 1.765 V gives LP-high = 57.5% of VDDIO — barely above the 55% threshold. The LP driver's output impedance combined with the 1.016 V level suggests possible over-termination or an impedance mismatch pulling the LP level down.

Check:
- SN65DSI83 input termination — the bridge has internal 200 Ω LP termination; verify no external termination resistors are double-loading the LP driver
- Trace length on LP lines — should be ≤ 100 mm for 432 Mbit/s

### 6.4 MEDIUM — CLK Lane Differential Asymmetry

The CLK lane consistently shows asymmetric swings: +195 mV / −137 mV (common mode offset ≈ +29 mV). While the total differential amplitude (166 mV) is within spec, the positive/negative asymmetry suggests a DC offset in the CLK driver or unequal termination on CLK+ vs CLK−.

Check:
- AC-coupling capacitor values on CLK+ and CLK− (should be matched within 1%)
- PCB trace length matching between CLK+ and CLK− (should be within 0.1 mm)

### 6.5 LOW — DAT Lane Sub-140 mV Excursions

While not causing the flicker, the DAT lane's occasional high sub-140 mV sample counts (up to 3846) indicate marginal eye opening during worst-case data patterns. After fixing the SoT timing:
- Monitor for bit errors on long-running sessions
- If issues persist, consider reducing DAT lane trace stub lengths or adding matched termination

## 7. Overall Signal Health & Flicker Risk Summary

The HS signal quality is adequate — amplitudes, rise times, jitter, and supply rail are all within acceptable bounds and show no degradation trend. The flicker is entirely caused by the 'Round Best' PHY timing mode, which programs 5 register fields below D-PHY v

Tokens: 45873 in / 4096 out