MIPI Interactive Flicker Test Report

Generated: 2026-04-16 15:37:29  |  Model: claude-opus-4-6

D-PHY Configuration

Pixel clock: 72.0 MHz  |  Bit rate: 432.0 Mbit/s per lane  |  Byte clock: 54.000 MHz (18.519 ns/byte)  |  UI: 2.315 ns

✓ All D-PHY v1.1 Table 14 constraints satisfied.

Samsung DSIM Registers

u-boot Commands

# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04   clk_prepare=3  clk_zero=14  clk_post=10  clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704   hs_prepare=3  hs_zero=7  hs_trail=4

# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"

saveenv
boot

Event Log

Claude Assessments

Capture 0079 [20260416_123835] — FALSE ALARM

YES

The LP-low plateau measured at 49.6–50 ns is right at the absolute edge of the SN65DSI83's 50 ns minimum detection threshold, and the pre-processor flag reports 49.6 ns which falls below spec. More critically, the LP exit → HS transition duration of only 1–1.2 ns is drastically below the 50 ns minimum, indicating the LP-01/LP-00 preamble states are essentially absent or compressed beyond what the bridge can reliably sample. With the SoT entry sequence this severely truncated, the SN65DSI83 would very likely miss the start-of-transmission, causing it to lose synchronization on this HS burst and produce visible flicker.

Capture 0110 [20260416_125738] — FALSE ALARM

YES

The LP-low plateau of 46.6–47 ns is below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, falling short by approximately 3–3.4 ns. Additionally, the LP exit-to-HS transition time of only 2.9–3 ns is drastically below the 50 ns spec minimum, confirming that the LP-01/LP-00 preamble states are too brief for the bridge's LP receiver to properly recognize the start-of-transmission sequence. With both critical timing parameters violated, the SN65DSI83 will almost certainly miss this SoT event, resulting in a lost HS burst and visible display flicker.

Capture 0158 [20260416_131640] — FALSE ALARM

YES

The LP-low plateau of 27.2 ns is well below the SN65DSI83's required 50 ns minimum for reliable SoT detection. Additionally, the LP exit-to-HS transition time of only 2.4 ns is far too brief (spec ≥ 50 ns), meaning the LP-01/LP-00 states were essentially absent or unresolvable by the bridge's receiver. The HS amplitude of 37 mV is also critically low—below the 50 mV threshold indicating a near-absent or severely attenuated HS burst—which strongly suggests the bridge failed to lock onto the data stream. All three anomalies together make it virtually certain the SN65DSI83 missed this SoT, resulting in a dropped frame and visible flicker.

Capture 0206 [20260416_133554] — FALSE ALARM

YES

The LP-low plateau of 44.6 ns is below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition time of only 1.8–2 ns is drastically shorter than the 50 ns spec minimum, meaning the LP-01/LP-00 preamble states are essentially absent from the bridge's perspective. With both timing parameters failing spec by significant margins, the SN65DSI83 will almost certainly miss this SoT entry, causing it to lose synchronization on this HS burst and produce a visible flicker event. The HS amplitude at 122 mV and LP-11 voltage at 1.015 V are within normal bounds, confirming the root cause is purely the truncated LP-low preamble timing rather than a signal amplitude issue.

Capture 0261 [20260416_135714] — FALSE ALARM

YES

The LP-low plateau of 49.3 ns is below the SN65DSI83's required 50 ns minimum for reliable SoT detection, and the LP exit-to-HS transition of only ~1 ns confirms the LP-01/LP-00 preamble states were essentially absent or far too brief (spec ≥ 50 ns). Additionally, the HS amplitude of ~30 mV is dramatically below the normal 105–122 mV range and falls below the 50 mV "absent" threshold, indicating the bridge almost certainly failed to lock onto the HS data burst. Taken together — a marginal/sub-spec LP-low plateau, a virtually nonexistent LP exit duration, and an abnormally low HS amplitude — this capture strongly indicates a missed SoT event that would produce visible flicker.

Capture 0293 [20260416_141016] — FALSE ALARM

YES

The LP-low plateau of 25.6–26 ns is roughly half the 50 ns minimum required by the SN65DSI83 to reliably detect the Start-of-Transmission sequence, and the LP-exit-to-HS transition of only 1.9–2 ns confirms the LP-01/LP-00 states were far too brief for the bridge's input comparators to register. Additionally, the HS amplitude of ~44 mV is well below the normal 105–122 mV range and sits under the 50 mV threshold, indicating the bridge almost certainly did not lock onto the HS data burst even if it had detected the SoT. Together, a failed SoT detection combined with sub-threshold HS signaling makes it virtually certain this capture corresponds to a missed video line or frame, producing visible flicker.

Capture 0338 [20260416_142759] — FALSE ALARM

YES

The LP-low plateau is reported as `None` (absent), meaning the DAT0 lane never presented a valid LP-01/LP-00 preamble long enough to be measured — far below the SN65DSI83's required ≥ 50 ns detection threshold. Additionally, the HS amplitude of only 3.1 mV is essentially absent (normal range 105–122 mV, with < 50 mV classified as absent), confirming the bridge never locked onto a valid HS burst. Together, the missing SoT preamble and negligible HS swing mean the SN65DSI83 could not detect start-of-transmission, virtually guaranteeing a missed frame and visible flicker.