MIPI D-PHY Analysis Report

Generated: 2026-04-15 12:16:31  |  Scope: Captures 0801–0830  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0801–0830

## 1. Executive Summary

The system is running with non-compliant D-PHY timing registers (5 spec violations) that create a narrow but real window for SoT failure. The 3 confirmed flicker events (0819, 0821, 0830) all share a unique signature: LP-low plateau = 0 ns, meaning the LP-01/LP-00 SoT states were completely skipped. The root cause is the samsung-dsim driver's "Round Best" timing calculation mode, which produces sub-spec THS_PREPARE+THS_ZERO and TCLK_PREPARE+TCLK_ZERO values. The SN65DSI83 bridge occasionally fails to detect the truncated SoT and never recovers within that session. Switching to "Round Up" register values eliminates all 5 violations and should eliminate flicker.

## 2. Consistent Spec Concerns

### 2.1 Register Timing — 5 Persistent D-PHY v1.1 Violations (ALL 30 captures)

Every single capture shows identical register values — the PHY timing is static and non-compliant:

| Parameter | Programmed | Actual | Spec Min | Deficit | Severity |
|---|---|---|---|---|---|
| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns | Medium — affects HS→LP→HS turnaround |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns | Critical — clock SoT setup |
| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns | Medium — clock lane EoT |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns | Critical — clock HS-init total |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns | Critical — data lane HS-init total |

The deficits are tiny (1–7 ns) but they are systematic and always present. They don't cause failure alone — they reduce the SN65DSI83's timing margin to near-zero, making the system vulnerable to any jitter or race condition at the SoT instant.

### 2.2 LP-Exit Duration — Universally Below Spec

| Metric | Good sessions | Flicker sessions |
|---|---|---|
| LP exit → HS | 1–4 ns (spec ≥ 50 ns) | 2–3 ns (spec ≥ 50 ns) |
| LP-low plateau | 108–343 ns | 0 ns |

All 30 captures show LP-exit durations of 1–4 ns, far below the 50 ns D-PHY minimum. This is a measurement of the actual LP-01→LP-00 intermediate state duration on the wire. The PHY is transitioning through the SoT LP states so rapidly that the oscilloscope (at its capture resolution) cannot distinguish them — they appear as a near-instantaneous drop from LP-11 to HS common mode.

However, the critical differentiator is the LP-low plateau:
- Non-flicker captures: 108–343 ns plateau (the LP-00 state is held long enough for the bridge)
- Flicker captures (0819, 0821, 0830): 0 ns plateau (LP-00 never appears on the wire)

### 2.3 HS Amplitude — Marginal but In-Spec

| Lane | Typical Vdiff | Spec Range | Concern |
|---|---|---|---|
| CLK | 164.2–166.3 mV | 140–270 mV | Consistently near low end; every capture has samples below 140 mV |
| DAT0 | 175.7–223.4 mV | 140–270 mV | Higher but variable; many sub-140 mV samples |

The CLK lane amplitude is systematically within 25 mV of the 140 mV floor. Combined with jitter (150–183 ps p-p), individual transitions dip below threshold. This doesn't cause flicker on its own but further degrades the bridge's ability to lock onto a marginal SoT.

### 2.4 CLK Lane Common Mode Offset

CLK consistently shows +28 to +30 mV common-mode offset (positive). DAT0 shows −5 to −7 mV typically. This ~35 mV differential CM offset is within spec (±25 mV per line, ±50 mV lane-to-lane) but on the high side and could affect the SN65DSI83's internal common-mode rejection during the critical SoT detection window.

### 2.5 LP-11 Voltage — Consistent but Low

All captures show LP-11 = 1.014–1.016 V against a 1.8 V VDDIO. The spec requires LP-11 to be ≥ VIH(LP) ≈ 880 mV (0.55 × 1.6 V with 200 mV hysteresis), so 1.015 V is in-spec. However, this is 56% of VDDIO, which is below the typical 70–80% expected. This suggests:
- Significant resistive drop in the LP driver path, or
- The LP-11 voltage is reduced by the 1.8 V supply being at 1.764 V (1.015/1.764 = 57.5%)

This is not a direct flicker cause but is worth noting as a contributing factor to the bridge's reduced noise margin for LP state detection.

## 3. Trends Over Captures

### 3.1 No Amplitude or Jitter Drift
CLK Vdiff is remarkably stable: 164.2–166.3 mV across all 30 captures (< 2 mV variation). Jitter ranges 148–183 ps p-p with no upward trend. There is no thermal drift or degradation over the 10-minute capture window.

### 3.2 LP-Low Plateau Shows Three Distinct Populations

| Plateau Duration | Count | Flicker? |
|---|---|---|
| 342–343 ns | 14 captures | No |
| 108 ns | 10 captures | No |
| 0 ns | 3 captures (0819, 0821, 0830) | YES |

The 343 ns and 108 ns populations both produce stable displays. The bimodal distribution (343 vs 108) suggests the PHY has two internal timing paths — possibly related to whether the HS clock PLL is already locked from a prior cycle or initializing fresh. The 0 ns population is the pathological case.

### 3.3 Supply Droop — Slight Correlation with Flicker

| Captures | Mean Droop | Mean Ripple RMS |
|---|---|---|
| Non-flicker (27) | 9.4 mV | 5.60 mV |
| Flicker (3: 0819,0821,0830) | 11.8 mV | 5.60 mV |

Capture 0821 (flicker) has the largest single droop in the batch: 17.0 mV (V_min = 1.748 V). However, non-flicker capture 0822 has nearly identical droop (14.6 mV, V_min = 1.748 V). The correlation is weak — supply droop is not the primary cause, though the 0821 droop is the worst-case and may have contributed to that specific event.

### 3.4 HS Burst Duration — Consistent
All captures show a single HS burst of ~5,020–5,077 ns. This is consistent with a single video line at the observed configuration. No anomalous burst counts or durations.

## 4. Anomaly Analysis

### 4.1 Flicker Events — Complete SoT Omission

Captures 0819, 0821, 0830 all show LP-low plateau = 0 ns. This means:
- The LP-11 → LP-01 → LP-00 → HS-0 sequence was not executed or was so fast it was indistinguishable from a direct LP-11 → HS transition
- The SN65DSI83 requires a minimum LP-00 hold time to recognize the SoT sequence (TI specifies compliance with D-PHY v1.1, implying ≥ THS_PREPARE min = 40ns + 4×UI ≈ 49 ns)
- With 0 ns LP-00, the bridge treats the first HS burst as noise and never achieves lane synchronization

Root cause mechanism: The Samsung DSIM PHY has THS_PREPARE+THS_ZERO programmed 1.5 ns below spec minimum. On most initializations, the analog PHY adds enough internal delay to produce a detectable LP-00 plateau (108–343 ns). On ~10% of initializations, PVT (process/voltage/temperature) variation within the PHY causes the LP-00 state machine to skip or truncate the LP-00 hold, producing the 0 ns plateau. This is classic metastability behavior in a timing-marginal digital state machine.

### 4.2 Missing or Partial DAT0 HS in sig Captures

Captures 0805, 0807 show `sig/dat Vdiff = 0.0 mV` ("No HS signal detected"). This is a scope triggering artifact — the sig capture window is very short (high-resolution mode) and occasionally misses the HS burst. These captures are NOT flicker events (both show 108–343 ns LP-low plateaux and no confirmed flicker).

Similarly, many `sig/dat` captures show "Only negative swings" — this indicates the sig trigger caught a run of identical data bits (e.g., all-zero pixel data). This is expected and benign.

### 4.3 proto/dat Capture 0821 — No HS Signal

Capture 0821 (confirmed flicker) shows `proto/dat Vdiff = 0.0 mV`. This is consistent with the flicker mechanism: the bridge failed to lock, so the DSIM controller may have entered a degraded state where DAT0 was not transmitting valid HS data during the proto capture window. The CLK lane continued running (proto/clk is normal), confirming the clock lane is in continuous HS mode regardless of data lane SoT failure.

### 4.4 CLK Lane LP — Expected Behavior

All captures show "CLK LP→HS sequence NOT DETECTED" on the CLK lane. This is correct and expected: the DSIM controller runs the clock lane in continuous HS mode (no LP states on CLK after initial startup). The LP captures on CLK confirm the clock never leaves HS during normal operation.

## 5. Supply Correlation Analysis

### 5.1 1.8 V Supply — Within Spec but Sagged

| Metric | Range | Spec | Assessment |
|---|---|---|---|
| Mean voltage | 1.7625–1.7657 V | 1.71–1.89 V | ✓ but 2% below nominal |
| Min voltage | 1.7480–1.7560 V | ≥ 1.71 V | ✓ but only 38–46 mV above spec floor |
| Droop depth | 7.3–17.0 mV | — | Max 17 mV at flicker event 0821 |
| Ripple RMS | 5.44–5.84 mV | — | Consistent, no trend |

The supply is healthy but running 36 mV below nominal (1.764 vs 1.800 V). This is within tolerance but means:
- LP driver output is reduced (explaining the 1.015 V LP-11 ≈ 57.5% of VDDIO)
- PHY internal logic has less VDD margin for state machine transitions

### 5.2 Supply vs. LP-Low Plateau Correlation

| LP-low plateau | V_min range | Droop range |
|---|---|---|
| 343 ns | 1.752–1.756 V | 7.3–12.1 mV |
| 108 ns | 1.748–1.756 V | 7.9–16.5 mV |
| 0 ns (flicker) | 1.748–1.756 V | 8.8–17.0 mV |

There is a slight trend toward higher droop in the 0 ns / flicker group, but the overlap is too large to conclude causation. The supply is not the trigger — it is, at most, a contributing factor that reduces the noise margin of the already-marginal PHY timing.

## 6. Warning/Error Explanation

| Warning | Captures | Most Likely Cause | Action |
|---|---|---|---|
| "LP exit duration X ns below spec min 50 ns" | 25/30 | THS_PREPARE+THS_ZERO is 1.5 ns below spec; PHY state machine exits LP states too quickly | Fix register timing |
| "settled samples below 140 mV" (CLK) | 30/30 | CLK amplitude ~165 mV with ISI/jitter; transitions through 140 mV threshold | Increase PHY drive strength if adjustable; otherwise acceptable |
| "settled samples below 140 mV" (DAT) | 28/30 | Data-dependent ISI causes amplitude variation | Same as above |
| "Only negative swings" (sig/dat) | ~20/30 | Short capture window caught monotone data pattern | Benign — scope trigger artifact |
| "No HS signal detected" (sig/dat) | 2/30 | Scope trigger missed HS burst in narrow window | Benign — increase sig capture window |
| "FLICKER SUSPECT: LP-low plateau absent" | 3/30 | PHY skipped LP-00 hold state entirely | Root cause — fix timing registers |
| "CLK lane in continuous HS mode" | 30/30 | Expected: DSIM runs CLK in continuous HS | No action needed |
| "No HS signal detected" (proto/dat 0821) | 1/30 | Bridge failed to lock → DSIM data lane in degraded state | Consequence of flicker, not cause |

## 7. Actionable Recommendations

### 7.1 PRIMARY FIX — Switch to "Round Up" PHY Timing (Critical, Immediate)

Patch the samsung-dsim / sec-dsim driver to use ceiling-rounded timing values. Target register writes:

```
DSIM_PHYTIMING (0x32e100b4) = 0x00000306 (was 0x00000305)
TLPX=3 (55.6ns ✓), THS_EXIT=6 (111.1ns ✓)

DSIM_PHYTIMING1 (0x32e100b8) = 0x030f0a04 (was 0x020e0a03)
TCLK_PREPARE=3 (55.6ns ✓), TCLK_ZERO=15 (PREP+ZERO=333ns ✓),
TCLK_POST=10 (185ns ✓), TCLK_TRAIL=4 (74.1ns ✓)

DSIM_PHYTIMING2 (0x32e100bc) = 0x00030706 (was 0x00030605)
THS_PREPARE=3 (55.6ns ✓), THS_ZERO=7 (PREP+ZERO=185.2ns ✓),
THS_TRAIL=6 (111.1ns ✓)
```

This eliminates all 5 D-PHY violations with zero cost (adds 1–2 byte-clock cycles to SoT/EoT sequences, imperceptible to throughput at 432 Mbit/s).

Implementation options (in order of preference):

1. Kernel driver patch: Modify the `samsung_dsim_set_phy_timing()` function to use `DIV_ROUND_UP()` instead of integer division for all timing parameters

Tokens: 45807 in / 4096 out