MIPI D-PHY Analysis Report

Generated: 2026-04-15 07:57:44  |  Scope: Captures 0137–0166  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166

## 1. Consistent Spec Concerns

### Register-Level Timing Violations (100% of captures)
Every single capture shows identical register values — the system is running 'Round Best' mode with 5 D-PHY v1.1 violations:

| Parameter | Programmed | Actual | Spec Min | Shortfall |
|-----------|-----------|--------|----------|-----------|
| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns |
| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns |

These are not marginal — they are hardcoded violations. The byte-clock granularity (18.518 ns) means every field is either clearly below spec or clearly above; there is no jitter-induced ambiguity in the register domain.

### LP-Exit Timing (Universal Violation)
Every capture with valid LP data (28 of 28) shows LP exit → HS duration of 0–4 ns against a spec minimum of 50 ns. This is a systematic hardware/driver issue, not a measurement artefact. The LP-01 and LP-00 SoT entry states are being driven for sub-nanosecond durations at the single-ended measurement resolution.

### LP-11 Voltage
All captures: 1.013–1.016 V against spec 1.0–1.45 V. Technically passing, but sitting at the extreme low end — only 13–16 mV above the 1.0 V floor. This is consistent with the 1.8 V supply being at 1.765 V (low side of nominal) and the PHY LP driver having significant drop. A marginal LP-11 voltage reduces the SN65DSI83's noise margin for detecting the LP-11 → LP-01 → LP-00 transition.

### HS Amplitude
- CLK lane: 161–173 mV differential — consistently passes 140 mV minimum but only by ~25 mV. Negative swing systematically weaker (+193 mV / −138 mV asymmetry → ~28 mV common-mode offset).
- DAT0 lane: 177–199 mV when properly captured — adequate but numerous sub-140 mV samples in proto captures (25–5098 per capture), indicating ISI/pattern-dependent amplitude dips.

### Clock Frequency
Mostly 215.6–216.2 MHz as expected. Occasional readings of 213.0–213.4 MHz and 218.1–219.1 MHz are within proto measurement window artefacts (windowing/gating), not real frequency excursions.

## 2. Trends Across Captures

### LP-Low Plateau Duration — The Critical Discriminator

| LP-Low Plateau | Count | Captures | Flicker? |
|---------------|-------|----------|----------|
| 0 ns | 2 | 0137★, 0147★ | YES — both flicker events |
| 108 ns | 5 | 0142, 0153, 0158, 0160, 0166 | No |
| 342–343 ns | 19 | All others | No |
| 348 ns (LP exit also ≥ 348 ns) | 4 | 0143, 0144, 0150, 0156, 0161 | No |
| Error/missing | 2 | 0148, 0162 | Unknown |

Key finding: The LP-low plateau is tristable — it lands at ~0, ~108, or ~343 ns. The flicker events correspond exclusively to the 0 ns case, where the LP-01/LP-00 states are completely absent. The 108 ns captures are a partial SoT (approximately 6 byte-clocks — coincidentally close to THS_PREPARE+THS_ZERO = 9 bc) and are borderline but do not flicker in this batch. The 343 ns captures show a healthy SoT sequence.

This tristability is the smoking gun: the PHY's internal SoT state machine has a race condition. The programmed THS_PREPARE+THS_ZERO (166.7 ns, 1.5 ns below spec) and TCLK_PREPARE+TCLK_ZERO (296.3 ns, 3.7 ns below spec) are below the minimum required for the receiver to detect the SoT sequence. When internal PLL/clock alignment at startup happens to compress these states further (or the state machine skips them entirely), the bridge never detects SoT.

### HS Amplitude — No Drift
CLK and DAT0 amplitudes are rock-stable across all 30 captures. No thermal or aging drift.

### Jitter — Stable
CLK jitter: 142–172 ps p-p, 50–53 ps RMS. No trend. Well within typical D-PHY budgets.

### 1.8 V Supply — Stable, No Correlation
Mean: 1.764–1.766 V. Droop: 8.5–14.1 mV. Ripple RMS: 5.3–5.9 mV. All within spec.

## 3. Anomalies

### A. Two Flicker Events (Captures 0137, 0147)
- LP-low plateau = 0 ns — LP-01/LP-00 states completely absent
- LP exit → HS = 1–2 ns (essentially instantaneous)
- HS amplitude in LP capture window: 25–30 mV single-ended (vs. 106–119 mV in non-flicker captures)
- This ultra-low HS amplitude confirms the bridge never locked — it is seeing HS transitions but has not synchronised because SoT was never received

### B. Intermediate LP-Low (~108 ns) Captures (0142, 0153, 0158, 0160, 0166)
- LP-low is present but shortened by ~3× compared to normal (~343 ns)
- HS amplitude in LP window: 16–35 mV (same low range as flicker captures)
- These are near-misses — the SoT sequence exists but is abbreviated. The bridge manages to lock, but barely. With a less tolerant bridge or slightly different timing, these would flicker too.

### C. LP Data Processing Errors (Captures 0148, 0162)
`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP transition occurred at or beyond the capture window edge. These represent captures where the trigger timing placed the SoT at the buffer boundary. Not a hardware fault; increase capture depth or adjust trigger delay.

### D. DAT0 "Only Negative Swings" (Majority of sig/dat captures)
Approximately 70% of sig/dat captures show only negative-going differential transitions. This is a capture window alignment issue — the high-res window is short enough that it may only contain one data phase. Not a real signal fault, but it means the positive-swing amplitude is not being validated for most captures. Recommend widening the sig capture window or using edge-triggered dual-window acquisition.

### E. DAT0 sig = 0.0 mV (Captures 0138, 0140, 0150, 0151, 0158, 0164)
The data line was in LP idle or between bursts during the high-res capture. Again a trigger alignment issue.

## 4. Supply Correlation Analysis

| Metric | Flicker (0137, 0147) | No-Flicker (avg of rest) | Correlation? |
|--------|---------------------|-------------------------|-------------|
| V_mean | 1.7656, 1.7655 V | 1.7652 V | None |
| V_min | 1.756, 1.756 V | 1.754 V | None |
| Droop | 9.6, 9.5 mV | 10.1 mV | None |
| Ripple RMS | 5.59, 5.49 mV | 5.59 mV | None |

Conclusion: The 1.8 V supply is not the root cause. Droop and ripple are identical in flicker and non-flicker sessions. The supply is healthy and not contributing to the SoT failure.

The slightly low LP-11 voltage (1.015 V) is a constant across all captures and therefore cannot explain the intermittent behaviour. However, it does reduce the SN65DSI83's detection margin, making the system more sensitive to the SoT timing violations.

## 5. WARNING/ERROR Explanation

| Warning | Cause | Action |
|---------|-------|--------|
| `LP exit duration N ns below spec min 50 ns` | PHY is not holding LP-01/LP-00 states for the required TLPX duration. The samsung-dsim PHY programmes TLPX=3 bc (55.6 ns) but the actual LP-low state exits in 0–4 ns. This means the LP driver is being overridden by the HS driver prematurely — a PHY state machine race. | Switch to 'Round Up' register values |
| `FLICKER SUSPECT: LP-low plateau absent` | SoT LP-01→LP-00 sequence completely skipped | Root cause — see §6 |
| `Only negative swings in capture window` | Sig capture window too short / trigger phase alignment | Widen sig window or add trigger holdoff jitter |
| `No HS signal detected` | Sig capture window hit LP gap between bursts | Same as above |
| `N settled samples below 140 mV` | ISI-induced amplitude dips during data transitions | Expected at 432 Mbit/s with PCB trace losses; not a primary concern but monitor |
| `index 200000 out of bounds` | LP transition at capture buffer edge | Increase LP capture depth to 250k+ samples |
| `CLK lane in continuous HS mode` | Normal — continuous clock mode; CLK LP→HS happens once at startup and is not re-triggered per frame | Expected behaviour |

## 6. Actionable Recommendations

### CRITICAL — Fix #1: Switch to 'Round Up' PHY Timing Registers

This is the single change most likely to eliminate flicker. Patch the samsung-dsim driver (or device tree) to use:

```
PHYTIMING (0xb4): 0x00000306 (THS_EXIT=6 → 111.1 ns ✓)
PHYTIMING1 (0xb8): 0x030f0a04 (TCLK_PREPARE=3→55.6ns ✓, TCLK_ZERO=15, TCLK_TRAIL=4→74.1ns ✓)
PHYTIMING2 (0xbc): 0x00030706 (THS_ZERO=7, THS_TRAIL=6→111.1ns ✓)
```

This eliminates all 5 D-PHY violations and gives:
- TCLK_PREPARE+TCLK_ZERO = 333 ns (33 ns margin over 300 ns spec)
- THS_PREPARE+THS_ZERO = 185 ns (17 ns margin over 168 ns spec)

The additional margin will eliminate the race condition that causes the tristable LP-low plateau (0/108/343 ns) by ensuring the PHY state machine always completes the full SoT sequence before the HS driver engages.

Implementation: In the samsung-dsim (sec-dsim) driver, the timing calculation function (`samsung_dsim_set_phy_timing()` or equivalent) uses a rounding mode when converting continuous D-PHY timing formulae to integer byte-clock counts. Change the rounding from `floor()` / truncation to `ceil()` for all timing parameters. Alternatively, force the register values directly via a device-tree override or platform data hook.

### IMPORTANT — Fix #2: Investigate LP-11 Voltage

LP-11 at 1.015 V (with VDDIO = 1.765 V) implies a 750 mV drop across the LP driver. This is excessive for a CMOS push-pull driver. Check:
1. Series resistance in the LP-mode path (ESD protection, connector, filter)
2. Whether a pull-up/pull-down network is loading the LP lines
3. SN65DSI83 input bias current (should be < 10 µA; if a pull-down exists on the bridge side, it will drag LP-11 low)

Even though 1.015 V passes spec, increasing it to ~1.3 V would give the bridge 300 mV more noise margin for SoT detection.

### MODERATE — Fix #3: Add SoT Lock Verification + Retry

Since the failure mode is bistable (SoT succeeds or fails, never changes mid-session), add a software check after pipeline startup:
1. Read SN65DSI83 register 0x0A (PLL lock / sync status) within 100 ms of pipeline load
2. If not locked, unload and reload the pipeline (takes < 200 ms)
3. Limit retries to 3 (with Round Up timing, retries should never be needed)

This provides defence-in-depth even if the timing fix reduces but doesn't fully eliminate the race.

### MINOR — Fix #4: Measurement Infrastructure

1. LP capture depth: Increase from 200k to 300k samples to avoid buffer edge errors
2. Sig trigger: Add ±5 ns random holdoff to sample both data phases
3. Proto window: Ensure capture contains both positive and negative data swings (the "only negative swings" artefact affects amplitude validation)

## 7. Summary

The system has a non-deterministic SoT failure caused by 5 D-PHY timing violations in the 'Round Best' register configuration, combined with a marginal LP-11 voltage of 1.015 V. The PHY's internal state machine occasionally skips or truncates the LP-01/LP-00 SoT entry sequence (LP-low plateau = 0 ns in ~7% of startups), preventing the SN65DSI83 bridge from detecting start-of-transmission and locking. The 1.8 V supply is clean and not a contributing factor.

Switching to the 'Round Up' register values (0x00000306 / 0x030f0a04 / 0x00030706) will bring all timing parameters into D-PHY v1.1 compliance with comfortable margin and is expected to eliminate the flicker. This is a software-only fix requiring a driver patch to the samsung-dsim PHY timing calculation, and should be validated by re-running the 30-capture batch to confirm 0% flicker rate and 0% occurrence of LP-low plateau < 300 ns.

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