Updates
This commit is contained in:
david rice
122
reports/20260413_131240_analysis.html
Normal file
122
reports/20260413_131240_analysis.html
Normal file
@@ -0,0 +1,122 @@
|
||||
<!DOCTYPE html>
|
||||
<html lang="en">
|
||||
<head>
|
||||
<meta charset="UTF-8">
|
||||
<title>MIPI Analysis — Captures 0635–0664</title>
|
||||
<style>
|
||||
body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
|
||||
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
|
||||
.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
|
||||
p { line-height: 1.6; }
|
||||
ol, ul { line-height: 1.8; padding-left: 24px; }
|
||||
li { margin: 4px 0; }
|
||||
.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
|
||||
.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
|
||||
padding: 16px 20px; margin-bottom: 28px; }
|
||||
.flicker-alert h2 { color: #e65100; margin-top: 0; }
|
||||
.flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
|
||||
.flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
|
||||
.flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
|
||||
table { border-collapse: collapse; width: 100%; }
|
||||
th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
|
||||
td { border: 1px solid #ddd; padding: 5px 10px; }
|
||||
@media print { body { margin: 20px; } }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<h1>MIPI D-PHY Analysis Report</h1>
|
||||
|
||||
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
|
||||
padding:16px 20px;margin-bottom:28px;">
|
||||
<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 3 of 30 display load sessions (10%) flickered</h2>
|
||||
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
|
||||
pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
|
||||
missed the SoT sequence and dropped a frame.<br>
|
||||
LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
|
||||
for the SN65DSI83 bridge to detect start-of-transmission.</p>
|
||||
<table>
|
||||
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
|
||||
<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
|
||||
<tr><td>0648</td><td>20260413_130204</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>0659</td><td>20260413_130603</td><td>dat</td><td style='color:red'>0.4 ns</td><td>3.5 ns</td><td>1.016 V</td></tr><tr><td>0664</td><td>20260413_130751</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.8 ns</td><td>1.016 V</td></tr>
|
||||
</table>
|
||||
</div>
|
||||
|
||||
<details style="margin-bottom:24px;">
|
||||
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
|
||||
DSI Register Snapshots (30 captures)
|
||||
</summary>
|
||||
<div style="overflow-x:auto;margin-top:8px;">
|
||||
<table>
|
||||
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
|
||||
<tr><td>0635</td><td>20260413_125723</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0636</td><td>20260413_125744</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0637</td><td>20260413_125806</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0638</td><td>20260413_125828</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0639</td><td>20260413_125849</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0640</td><td>20260413_125911</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0641</td><td>20260413_125933</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0642</td><td>20260413_125954</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0643</td><td>20260413_130016</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0644</td><td>20260413_130038</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0645</td><td>20260413_130059</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0646</td><td>20260413_130121</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0647</td><td>20260413_130142</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0648</td><td>20260413_130204</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0649</td><td>20260413_130226</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0650</td><td>20260413_130248</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0651</td><td>20260413_130309</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0652</td><td>20260413_130331</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0653</td><td>20260413_130353</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0654</td><td>20260413_130414</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0655</td><td>20260413_130436</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0656</td><td>20260413_130458</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0657</td><td>20260413_130519</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0658</td><td>20260413_130541</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0659</td><td>20260413_130603</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0660</td><td>20260413_130624</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0661</td><td>20260413_130646</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0662</td><td>20260413_130708</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0663</td><td>20260413_130729</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0664</td><td>20260413_130751</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
|
||||
</table>
|
||||
</div>
|
||||
</details>
|
||||
<p class="meta">
|
||||
<strong>Generated:</strong> 2026-04-13 13:12:40 |
|
||||
<strong>Scope:</strong> Captures 0635–0664 |
|
||||
<strong>Model:</strong> claude-opus-4-6
|
||||
</p>
|
||||
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0635–0664 (30 sessions, 3 flicker events)</p>
|
||||
<ul><li></li></ul>
|
||||
<p>## 1. Consistent Spec Concerns</p>
|
||||
<p>### A. PHY Timing Registers — 5 D-PHY v1.1 Violations (Every Capture, Unchanged)</p>
|
||||
<p>All 30 captures show identical register values — the system is running <strong>'Round Best' mode</strong> with 5 timing violations:</p>
|
||||
<p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns (7.4%)</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns (2.6%)</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns (7.3%)</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns (1.2%)</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns (0.9%)</strong> |</p>
|
||||
<p><strong>Key insight</strong>: Every violation is a shortfall of 1–7 ns — exactly the kind of margin the SN65DSI83 may or may not tolerate depending on its internal sampling phase at the moment of SoT detection. This explains the <strong>bistable, non-deterministic</strong> flicker behaviour perfectly: the timing is close enough to work ~90% of the time, but the bridge's SoT detector has a probabilistic window of acceptance when margins are this thin.</p>
|
||||
<p>### B. LP Exit Duration — Universally Violated</p>
|
||||
<p><strong>Every single capture</strong> shows LP exit → HS of 0–4 ns against a spec minimum of 50 ns. This is not a measurement artifact — it is a systematic violation:</p>
|
||||
<p>| LP exit (ns) | Captures |<br>|---|---|<br>| 0 ns | 0656 |<br>| 1 ns | 0647 |<br>| 2 ns | 0648★, 0649 |<br>| 3 ns | 0638, 0639, 0643, 0645, 0646, 0651, 0652, 0654, 0658, 0660, 0664★ |<br>| 4 ns | 0635, 0636, 0637, 0640, 0642, 0648★, 0650, 0653, 0659★ |<br>| 113 ns | 0644, 0657 |<br>| 348 ns | 0641, 0661, 0662, 0663 |</p>
|
||||
<p>★ = confirmed flicker event</p>
|
||||
<p><strong>Critical observation</strong>: The LP-01→LP-00 transition states are either absent (<4 ns, too fast for the bridge to detect) or properly formed (~108–348 ns). The 0–4 ns measurements indicate the PHY is <strong>skipping the LP-01/LP-00 states entirely</strong> on most startups, jumping directly from LP-11 to HS. The captures with 113 ns or 348 ns show the PHY occasionally executing the full SoT sequence correctly.</p>
|
||||
<p>### C. LP-Low Plateau — Bimodal Distribution Correlating with Flicker</p>
|
||||
<p>| LP-low plateau | Count | Flicker? |<br>|---|---|---|<br>| <strong>0 ns</strong> | 3 | <strong>ALL 3 flicker events</strong> (0648, 0659, 0664) |<br>| ~108 ns | 7 | No flicker |<br>| ~342–343 ns | 18 | No flicker |<br>| Error/missing | 1 (0655) | Unknown |</p>
|
||||
<p><strong>This is the smoking gun</strong>: LP-low = 0 ns means the SoT sequence (LP-11→LP-01→LP-00→HS-0→HS data) was completely absent or truncated. The SN65DSI83 never saw a valid Start-of-Transmission and failed to synchronize. <strong>100% correlation between LP-low = 0 and flicker.</strong></p>
|
||||
<p>The bimodal LP-low distribution (108 ns vs 342 ns) in non-flicker captures likely reflects whether the scope triggered on the first or second LP-low region in the SoT/EoT/SoT sequence, but both are long enough for the bridge to detect.</p>
|
||||
<p>### D. HS Amplitude — Marginal with Persistent Below-Spec Samples</p>
|
||||
<ul><li><strong>CLK lane</strong>: 164.5–166.9 mV mean differential — within spec (140–270 mV) but <strong>low</strong>. Every capture has 18–214 settled samples below 140 mV.</li><li><strong>DAT0 lane</strong>: 185.7–222.6 mV mean — better, but with <strong>253–16,593 below-140 mV samples</strong> per capture in proto windows.</li><li><strong>Clock lane asymmetry</strong>: Consistently +194 / −137 mV (common mode +28 mV), indicating a ~30 mV offset. This is within the ±25% Vdiff imbalance allowed but at the edge.</li></ul>
|
||||
<p>### E. LP-11 Voltage — Low but In-Spec</p>
|
||||
<p>LP-11 consistently reads 1.015–1.017 V against a spec range of 1.0–1.45 V. This is <strong>at the bottom of the range</strong> and only 15–17 mV above the minimum. At 1.8 V VDDIO, LP-11 should ideally be near 1.2 V. The low LP-11 voltage suggests either:<br>- Resistive loading on the LP lines (SN65DSI83 input bias or PCB leakage)<br>- VDDIO-referenced LP driver with a voltage divider effect<br>- The LP driver output impedance is high relative to the load</p>
|
||||
<p>While technically passing, this leaves minimal noise margin for the bridge's LP state detector.</p>
|
||||
<ul><li></li></ul>
|
||||
<p>## 2. Trends Across Captures</p>
|
||||
<p>### A. No Significant Drift<br>- <strong>HS amplitude</strong>: CLK ±1.5 mV, DAT0 ±8 mV — stable<br>- <strong>Jitter</strong>: 136–177 ps p-p, 51–55 ps RMS — stable, no drift<br>- <strong>Clock frequency</strong>: 212.76–218.99 MHz — mostly 215.7–216.3 with occasional outliers (212.76, 213.04, 213.30 in captures 0646/0651/0654/0663; 218.99 in 0655/0663). The low-frequency outliers may be measurement artifacts from the scope's frequency estimation with slightly different trigger windows.<br>- <strong>LP-11 voltage</strong>: 1.015–1.017 V — rock stable<br>- <strong>1.8 V supply</strong>: 1.7637–1.7695 V mean — no drift</p>
|
||||
<p>### B. DAT0 Below-140-mV Count Varies Widely<br>Range: 13 to 16,593 samples across captures. This variation is <strong>data-dependent</strong> (the pattern being transmitted changes the ratio of transitions to settled bits), not a degradation trend.</p>
|
||||
<ul><li></li></ul>
|
||||
<p>## 3. Anomalies Flagged</p>
|
||||
<p>### A. Three Confirmed Flicker Events (LP-low = 0 ns)</p>
|
||||
<p>| Capture | LP exit | LP-low | Flicker |<br>|---|---|---|---|<br>| <strong>0648</strong> | 2 ns | <strong>0 ns</strong> | ✓ |<br>| <strong>0659</strong> | 4 ns | <strong>0 ns</strong> | ✓ |<br>| <strong>0664</strong> | 3 ns | <strong>0 ns</strong> | ✓ |</p>
|
||||
<p>All three show the same signature: the data lane jumped from LP-11 directly to HS without executing the LP-01→LP-00 SoT sequence. The SN65DSI83 never received a valid SoT and could not lock its HS receiver, resulting in persistent flicker.</p>
|
||||
<p>### B. DAT0 sig Capture Shows 0 mV in 4 Captures (0635, 0638, 0640, 0646, 0664★)<br>The high-res sig capture on DAT0 shows "No HS signal detected" in several captures. This is a <strong>trigger timing artifact</strong> — the sig window (~10 ns) captured during an LP or blanking gap rather than during HS data. Not a hardware concern.</p>
|
||||
<p>### C. DAT0 "Only Negative Swings" Warning (Most sig/dat Captures)<br>The sig window captured during a data pattern that happened to have consecutive identical bits (HS-0 to HS-0 transitions) or caught only one polarity. Again a <strong>trigger timing artifact</strong>, not a hardware issue.</p>
|
||||
<p>### D. Capture 0655 — LP Data Processing Error<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP capture buffer was exactly full, likely because the trigger point was at the very end of the acquisition window. This is a <strong>capture/processing artifact</strong>, not a hardware failure. Recommend extending the LP capture buffer or adjusting trigger position.</p>
|
||||
<p>### E. CLK Lane in Continuous HS — Expected<br>The CLK lane shows "LP→HS sequence NOT DETECTED" in all captures. This is <strong>correct behaviour</strong> for the Samsung DSIM IP, which places the clock lane in continuous HS mode and only performs LP→HS transitions on data lanes.</p>
|
||||
<ul><li></li></ul>
|
||||
<p>## 4. Supply Correlation Analysis</p>
|
||||
<p>### A. 1.8 V Supply — No Correlation with Flicker</p>
|
||||
<p>| Metric | Flicker (0648, 0659, 0664) | Non-flicker (27 captures) |<br>|---|---|---|<br>| Mean voltage | 1.7643–1.7654 V | 1.7637–1.7695 V |<br>| Min voltage | 1.7560 V | 1.7520–1.7600 V |<br>| Droop | 8.3–9.5 mV | 7.8–12.8 mV |<br>| Ripple RMS | 5.45–5.55 mV | 5.19–5.85 mV |</p>
|
||||
<p><strong>No correlation exists.</strong> The flicker events have average-to-good supply metrics. The worst droop (12.8 mV in 0642, 12.2 mV in 0645) and worst ripple (5.85 mV in 0662) all occurred in <strong>non-flicker</strong> sessions. This conclusively rules out supply-induced SoT failure.</p>
|
||||
<p>### B. Supply Health Overall<br>- Mean 1.765 V is 35 mV below nominal 1.8 V — acceptable but leaving only 55 mV margin to 1.71 V lower limit<br>- All captures maintain min voltage ≥ 1.752 V — healthy<br>- Droop and ripple are well within spec</p>
|
||||
<ul><li></li></ul>
|
||||
<p>## 5. WARNING/ERROR Explanations</p>
|
||||
<p>| Warning/Error | Cause | Action |<br>|---|---|---|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>PHY skipping LP-01/LP-00 states</strong> due to insufficient THS_PREPARE+THS_ZERO timing programmed in registers. The Samsung DSIM PHY's SoT state machine runs the LP-01→LP-00 states for a duration derived from THS_PREPARE, and with only 2–3 bc programmed (37–56 ns), the LP-low states may be too brief for the scope to resolve, or the PHY may skip them entirely when internal timing jitter causes the state machine to advance before the LP lines settle. | <strong>Switch to 'Round Up' register values</strong> |<br>| `LP-low plateau absent or < 50 ns` — FLICKER SUSPECT | SoT sequence was completely missing. The PHY transitioned from LP-11 directly to HS-0 without the required LP-01→LP-00 intermediate states. | Root cause is register timing; fix registers |<br>| `No HS signal detected — line may be in LP state or idle` (sig/dat) | Trigger caught a blanking/LP period rather than active HS data. Normal for video mode DSI where data lanes go LP between lines/frames. | Ignore — adjust trigger if sig captures needed |<br>| `Only negative swings in capture window` | Short capture window caught a run of identical bits. Data-pattern dependent. | Ignore — no hardware concern |<br>| `X settled samples below 140 mV` (CLK and DAT) | Clock amplitude is at lower end of spec; data transitions create brief low-amplitude moments. Mostly ISI (inter-symbol interference) at transitions. | Monitor; consider PCB impedance review if count increases |<br>| `index 200000 out of bounds` (Capture 0655 lp_dat) | Processing script hit end-of-buffer — trigger too late in acquisition window | Extend buffer or add bounds checking |</p>
|
||||
<ul><li></li></ul>
|
||||
<p>## 6. Actionable Recommendations</p>
|
||||
<p>### PRIORITY 1 — CRITICAL (Fix Immediately): Switch to 'Round Up' PHY Timing</p>
|
||||
<p>Modify the samsung-dsim driver timing calculation or apply a device-tree override to program <strong>'Round Up' register values</strong>:</p>
|
||||
<p>```<br>DSIM_PHYTIMING (0xb4): 0x00000306 (THS_EXIT=6)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04 (TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706 (THS_ZERO=7, THS_TRAIL=6)<br>```</p>
|
||||
<p>This eliminates all 5 D-PHY violations and adds 11–37 ns of margin to each parameter. The additional 1 byte-clock (18.5 ns) per parameter has <strong>zero impact</strong> on bandwidth or display performance at 432 Mbit/s.</p>
|
||||
<p><strong>Implementation path</strong>: The samsung-dsim driver (drivers/gpu/drm/bridge/samsung-dsim.c) computes these values in `samsung_dsim_set_phy_timing()`. The "Round Best" mode uses `DIV_ROUND_CLOSEST` for the byte-clock conversion; change to `DIV_ROUND_UP` (ceiling), or apply hardcoded overrides via a platform-specific timing table. This is a <strong>one-line change</strong> in the rounding function.</p>
|
||||
<p>### PRIORITY 2 — HIGH: Validate LP SoT Sequence After Register Fix</p>
|
||||
<p>After applying Round Up timings, re-run the same 30-session capture batch and verify:<br>- LP-low plateau ≥ 50 ns in <strong>all</strong> sessions (currently 0 ns in 10% = flicker rate)<br>- LP exit → HS ≥ 50 ns<br>- No flicker events</p>
|
||||
<p>The expectation is that increasing THS_PREPARE+THS_ZERO from 9 bc to 10 bc (166.7 → 185.2 ns) will give the PHY state machine sufficient time to reliably execute the LP-01→LP-00 sequence, eliminating the probabilistic skip.</p>
|
||||
<p>### PRIORITY 3 — MEDIUM: Investigate LP-11 Voltage</p>
|
||||
<p>LP-11 at 1.015–1.017 V (only 1.5% above the 1.0 V minimum) is abnormally low for a 1.8 V VDDIO system. Check:<br>1. LP termination resistance on the SN65DSI83 input — per datasheet, the SN65DSI83 has internal 200 kΩ pull-ups; if external pull-ups/pull-downs are present, they may be loading the line<br>2. Series resistance in the LP path — excessive via/trace resistance could create a divider<br>3. VDDIO at the PHY pad — confirm 1.8 V is reaching the i.MX 8M Mini MIPI PHY supply pin, not just the bulk decoupling point</p>
|
||||
<p>While this is not the flicker root cause, it reduces noise margin and could contribute to problems at lower VDDIO or higher temperatures.</p>
|
||||
<p>### PRIORITY 4 — LOW: Monitor CLK Lane Amplitude</p>
|
||||
<p>CLK lane differential amplitude at 165 mV (only 25 mV / 18% above the 140 mV minimum) with persistent below-spec samples suggests:<br>1. Slightly high trace impedance or length mismatch on CLK P/N<br>2. PCB impedance above the 100Ω differential target<br>3. Verify CLK lane termination at the SN65DSI83 — a missing or incorrect termination resistor would reduce amplitude</p>
|
||||
<p>This is not causing flicker but is a long-term reliability concern as components age and impedance drifts.</p>
|
||||
<p>### PRIORITY 5 — LOW: Capture Script Improvements<br>- Add bounds checking for LP buffer</p>
|
||||
<p class="tokens">Tokens: 45745 in / 4096 out</p>
|
||||
</body>
|
||||
</html>
|
||||
Reference in New Issue
Block a user